JP4862395B2 - Information processing apparatus and information processing apparatus control method - Google Patents

Description

  The present invention relates to an information processing apparatus and an information processing apparatus for transferring received data from the outside to a storage means by DMA (Direct Memory Access) transfer and storing the data, and executing predetermined processing on the received data stored in the storage means It relates to a control method.

  Information processing apparatuses that execute predetermined processing on data received through communication with external apparatuses include printers, facsimiles, multifunction peripherals, and the like.

  In this type of information processing apparatus, it has been proposed to DMA-transfer received data directly to storage means such as a RAM (Random Access Memory) without using a CPU (Central Processing Unit).

  In addition, in this type of information processing apparatus, there is also a model that adopts a function of setting an operation state to a power saving mode that reduces the supply of power to each part when the state of non-operation continues for a predetermined period or longer. In the power saving mode, for example, power supply to the CPU is stopped, and normal power is supplied to an I / O port or the like that performs communication with an external device.

  Here, in order to further reduce the power consumption in the power saving mode, it is preferable to reduce the power supplied to a RAM such as a DRAM (Dynamic Random Access Memory).

  However, if the data supplied from the I / O port is DMA-transferred to the RAM when the power supplied to the RAM is reduced, not only the data cannot be stored in the RAM but also the CPU hangs up.

  As a technique that can be applied to this problem, it has been proposed that a device controlled by a host computer enters a sleep mode at its own judgment and can return from the sleep mode by a reset signal from the host computer. (For example, refer to Patent Document 1).

That is, in Patent Document 1, the host computer and the device are usually configured to exchange data via an interface processing unit that performs interface processing on signals exchanged between the host computer and the device. However, when the device is in the sleep mode by the state control unit, the host computer supplies the reset signal directly to the device state control unit without going through the interface processing unit, and returns the device to the normal state. The data is supplied through the interface processing unit.
JP 2002-318646 A

  However, in the technique described in Patent Document 1, the hardware configuration is changed so that the host computer and the device state control unit can communicate with each other without using the interface processing unit, and the device is in the normal state before the DMA transfer. There was a problem that it was necessary to have a function to return to.

  In other words, if the hardware configuration does not have a function to return the device to the normal state before DMA transfer, the power supplied to the RAM cannot be reduced in order not to miss the received data. .

  The present invention has been made to solve the above-described problems, and provides an information processing apparatus and a control method for the information processing apparatus that can reduce power consumption in the power saving mode regardless of the hardware configuration. Is the purpose.

  In order to solve the above-mentioned problems, the invention of claim 1 is an operation state control for shifting to a power saving mode for controlling power supply and reducing power consumption when a predetermined condition is satisfied with respect to the normal mode. A main storage means for temporarily storing at least received data inputted from the outside for a predetermined process is an information processing apparatus targeted for a power saving mode, and received from the external apparatus DMA transfer means for DMA-transferring data to the main storage means, and an interrupt signal generation for generating an interrupt signal for instructing the main storage means to return to the normal mode when the received data is acquired by the DMA transfer means Based on the interrupt signal generated by the interrupt signal generating means and the interrupt signal generating means, the main memory means is returned to the normal mode by returning the operating state from the power saving mode. And includes a data receiving time of the recovery control means to de, a.

In order to solve the above-mentioned problem, the invention of claim 1 controls the supply of power when a state in which a predetermined process is not executed for data received from an external device continues for a predetermined period or more in the normal mode. An information processing apparatus including an operation state control unit that shifts to a power saving mode for reducing power consumption, and a main storage unit that temporarily stores data received from the outside for a predetermined process is a target of the power saving mode The received data storage means includes auxiliary storage means in which power supply is not reduced even in the power saving mode, and received data storage means for receiving data from the external device and storing the received data. When the received data stored in the memory reaches a predetermined capacity, a notification means for notifying that the predetermined capacity has been reached, and receiving the notification from the notification means. And, an interrupt signal indicating a return to the normal mode of the main memory means when a predetermined signal to said auxiliary storage means the notification as a trigger to the DMA transfer, and DMA transfer of the predetermined signal has been completed DMA transfer means for generating and transmitting the interrupt signal; receiving the interrupt signal; using the interrupt signal as a trigger to return the operating state of the main memory means from the power saving mode to the normal mode; and the main memory means And a data reception return control means for transmitting a return signal indicating the return to the normal mode , wherein the DMA transfer means receives the return signal and is stored in the received data storage means using the return signal as a trigger. the received data that have DMA transfer to the main memory unit.

  In other words, when data is received from an external device while operating in the power saving mode, an interrupt signal is transmitted to execute the process of returning from the power saving mode. Therefore, the main memory is used regardless of the hardware configuration. The received data can be DMA transferred after the power supplied to the means is restored. Thereby, even if the power supplied to the main storage means that is the DMA transfer destination of the received data in the power saving mode is reduced, there is no possibility that the control system hangs up by receiving data from the external device. Power consumption in the power saving mode can be reduced.

  As the main storage means, a storage medium capable of high-capacity and high-speed processing is usually used. Therefore, reducing the power consumption of the main storage means in the power saving mode reduces the overall power consumption of the apparatus. It is effective.

In addition, as in the invention described in claim 2, the present invention further comprises read-only storage means in which a program related to the return processing from the power saving mode to the normal mode is stored in advance, and the data reception return control After receiving the interrupt signal, the means restores the operating state of the main storage means from the power saving mode using the program stored in advance in the read-only storage means, and sets the main storage means to the normal mode. You can also

As the read-only storage means, ROM (Read Only Memory) is desirable.

Furthermore, according to the present invention, the predetermined signal may be a request signal for a write request to the auxiliary storage unit.

In such a configuration, by using a request signal for a write request that is normally used for DMA transfer, power consumption in the power saving mode can be reduced regardless of the hardware configuration.

  As the auxiliary storage means, it is preferable to apply a storage medium with a small capacity and low speed processing compared to the main storage means.

On the other hand, in order to solve the above problem, the invention according to claim 4 provides power supply when a state in which a predetermined process is not executed for data received from an external device continues for a predetermined period or more in the normal mode. An operation state control unit that shifts to a power saving mode to control and reduce power consumption and a data reception return control unit that returns the power saving mode to the normal mode triggered by reception of an interrupt signal are received from the outside. Main storage means for temporarily storing data for predetermined processing; auxiliary storage means; notification means for receiving data from the external device; received data storage means for storing the received data; A storage unit and a DMA transfer unit that DMA-transfers data or signals to the auxiliary storage unit, and the main storage unit is a target of a power saving mode. A control method for an information processing device, wherein the power supply of the auxiliary storage means is maintained even in the power saving mode, data is received from the external device, and the received data is stored in the received data storage means. When the storage of the received data reaches a predetermined capacity, the notification unit notifies the DMA transfer unit to that effect, and the DMA transfer unit uses the notification as a trigger to the auxiliary storage unit. When the DMA transfer of the predetermined signal is completed and the DMA transfer of the predetermined signal is completed, the DMA transfer unit generates an interrupt signal instructing the return of the main storage unit to the normal mode, and the DMA transfer unit The generated interrupt signal is transmitted to the data reception return control means, and the data reception return control means uses the interrupt signal as a trigger to operate the main memory means. The state is returned from the power saving mode to the normal mode, and a return signal indicating that the main storage means has returned to the normal mode is transmitted to the DMA transfer means, and the DMA transfer means receives the return signal. The received data stored in the received data storage means is DMA-transferred to the main storage means using the return signal as a trigger.

According to the invention of claim 4 , it comprises an operation state control means for shifting to a power saving mode for controlling power supply and reducing power consumption when a predetermined condition is satisfied with respect to the normal mode. When the main storage means for temporarily storing received data input from the outside for a predetermined process is the target of the power saving mode, the received data is received from the external device in the power saving mode. Generating an interrupt signal instructing the return of the main storage means to the normal mode, returning the operating state from the power saving mode based on the interrupt signal, setting the main storage means to the normal mode, and setting the received data to the normal mode. Since DMA transfer is performed to the main storage means, power consumption in the power saving mode can be reduced regardless of the hardware configuration.

In other words, when data is received from an external device while operating in the power saving mode, an interrupt signal is transmitted to execute the process of returning from the power saving mode. Therefore, the main memory is used regardless of the hardware configuration. The received data can be DMA transferred after the power supplied to the means is restored.

Thereby, even if the power supplied to the main storage means that is the DMA transfer destination of the received data in the power saving mode is reduced, there is no possibility that the control system hangs up by receiving data from the external device. Power consumption in the power saving mode can be reduced.

Further, the present invention provides a control method for an information processing apparatus, further comprising read-only storage means in which a program relating to a process for returning from the power saving mode to the normal mode is stored in advance as in the invention described in claim 5 When the data reception return control means uses the interrupt signal as a trigger to return the operation state of the main storage means from the power saving mode to the normal mode, the read-only storage means stores the data stored in advance. A program may be used.

According to the invention of claim 5 , the main storage means can be returned from the power saving mode to the normal mode by the power saving mode return processing program stored in advance in the read-only storage means.

Furthermore, the present invention is, as in the invention of claim 6, wherein the predetermined signal may be a request signal of the write request to the secondary storage means.

According to the sixth aspect of the present invention, it is possible to reduce the power consumption in the power saving mode regardless of the hardware configuration by using the request signal for the write request that is normally used in the DMA transfer.

  As described above, the present invention comprises an operation state control means for controlling the supply of power and reducing the power consumption when a predetermined condition is satisfied with respect to the normal mode, and at least from the outside. When the main storage means for temporarily storing the input received data for a predetermined process is the target of the power saving mode, the received data is received from the external device in the power saving mode. An interrupt signal for instructing the return of the main storage means to the normal mode is generated, the operation state is returned from the power saving mode based on the interrupt signal, the main storage means is set to the normal mode, and the received data is stored in the main memory. Because DMA (Direct Memory Access) transfer to the means, power consumption in the power saving mode can be reduced regardless of the hardware configuration. It has an excellent effect.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, FIG. 1 is a schematic diagram illustrating a configuration of an information processing apparatus 10 according to the present embodiment. Hereinafter, a schematic configuration of the information processing apparatus 10 will be described.

  As shown in the figure, the information processing apparatus 10 is connected to an external personal computer (external PC) 12 via a communication medium.

  Note that as a communication medium, in addition to a cable for performing wired communication, infrared rays, radio waves, and the like for performing wireless communication represented by Bluetooth (Infrared Data Association) standards and the like can be applied.

  The information processing apparatus 10 includes a CPU (Central Processing Unit) 22 that controls the operation of the entire apparatus, a RAM (Random Access Memory) 24 as a main memory in the information processing apparatus 10, a RAM controller 26, a bus bridge 20, The CPU 22, the RAM controller 26, and the bus 30 are connected to each other via the bus bridge 20.

  The RAM 24 is connected to the RAM controller 26, and the RAM controller 26 controls access to the RAM 24, power supply, and the like.

  The bus bridge 20 connects a plurality of buses provided in the information processing apparatus 10 such as a bus (not shown in the figure) to which the CPU 22 and the RAM controller 26 are connected, a bus 30, and the like. Mediates communications.

  On the other hand, the bus 30 includes an SRAM (Static RAM) 32 mainly used for a cache memory, a ROM (Read Only Memory) 34 in which various processing programs and tables for executing information processing are stored, and an ASIC. (Application Specific Integrated Circuit) 36 is connected to each other.

  The ASIC 36 is a circuit for controlling input / output of data to the information processing apparatus 10, and includes a DMA controller 42 and an I / O controller 44, and the I / O controller 44 is connected to the DMA controller 42. Has been.

  The I / O controller 44 further includes a first-in first-out buffer (FIFO) 46 for receiving and temporarily storing input data and outputting the data in the stored order. ing.

  Data input from the external PC 12 via an interface (not shown) is input to the I / O controller 44 of the ASIC 36 and is temporarily stored and accumulated in the FIFO 46 sequentially.

  The FIFO 46 outputs a FIFO alarm to the DMA controller 42 when the accumulated data capacity reaches a predetermined capacity.

  The data storage capacity for outputting the FIFO alarm can be set in advance as appropriate.

  When a FIFO alarm is input from the FIFO 46, the DMA controller 42 sequentially reads out the data stored in the FIFO 46 and transfers it to the RAM 24 via the bus 30, the bus bridge 20 and the RAM controller 26. When the DMA transfer to the RAM 24 is completed, the DMA controller 42 outputs a DMA transfer completion signal indicating that to the CPU 22.

  Here, in the information processing apparatus 10, when the state where each part does not operate continues for a predetermined period or longer in the information processing apparatus 10, the operation state is set to the power saving mode for reducing the power supplied to each part.

  In this power saving mode, the power supplied to the CPU 22 is cut off, and the power supplied to the bus bridge 20 and the RAM controller 26 is reduced. Along with this, the power supplied to the RAM 24 is also reduced, and the RAM 24 is operated in a self-refresh mode in which refresh is executed at predetermined intervals in order to maintain the stored data.

  On the other hand, in the power saving mode, each part connected to the bus 30 is supplied with the same amount of power as usual, so that even if the operation state of the information processing apparatus 10 is in the power saving mode, the external PC 12 It is configured to be able to communicate with.

  In this embodiment, in order to avoid access to the RAM 24 operating in the self-refresh mode, an interrupt signal is output to the CPU 22 before the DMA transfer by the DMA controller 42 is performed. .

  That is, when the DMA controller 42 receives a FIFO alarm when the operation state of the information processing apparatus 10 is the power saving mode, the DMA controller 42 first transfers predetermined data to the SRAM 32 by DMA. By executing DMA transfer to the SRAM 32, a DMA transfer completion signal is output to the CPU 22.

  During operation in the power saving mode, the CPU 22 executes an interrupt handler stored in the ROM 34 based on the DMA transfer completion signal, and issues an instruction (return signal) to return the power amount supplied to each part as usual. Output and return from power saving mode.

  When the return signal from the CPU 22 is input, the DMA controller 42 starts execution of DMA transfer of received data to the RAM 24.

  Hereinafter, the operation of the present embodiment will be described.

  FIG. 2 shows a flow of power saving data reception processing executed by the ASIC 36 when the operation state of the information processing apparatus 10 is the power saving mode. Hereinafter, the power saving data receiving process according to the present embodiment will be described with reference to FIG.

  Note that when the CPU 22 sets the operation state of the information processing apparatus 10 to the power saving mode, the CPU 22 transmits information indicating that fact to all parts regardless of whether or not the supplied power is reduced. In this case, the operating state of the information processing apparatus 10 can be grasped.

  First, in step 200, reception of data from the outside is waited, and in the next step 202, the received data is sequentially stored in the FIFO 46. The reception data is accumulated by temporarily storing the data in the FIFO 46.

  In the next step 204, the process waits until the storage capacity of the received data in the FIFO 46 reaches a predetermined amount. If the determination is affirmative, the process proceeds to step 205. In step 205, the I / O controller 42 outputs a FIFO alarm to the DMA controller 42, and then the process proceeds to step 206.

  In step 206, DMA transfer of predetermined data to the SRAM 32 is executed, and then the process proceeds to step 208 to wait for completion of transfer of all data.

  In this embodiment, the predetermined data to be DMA transferred to the SRAM 32 is empty data, and the DMA controller 42 transmits only a request signal for a write request to the SRAM 32.

  In the next step 210, a DMA transfer completion signal is transmitted as an interrupt signal to the CPU 22, and then the process proceeds to step 212 to wait for reception of a return signal from the CPU 22.

  In the next step 214, it is determined that the RAM 24 can be accessed, and the data received from the outside is DMA-transferred to the RAM 24.

  In the next step 216, the completion of the transfer of the received data to the RAM 24 is waited. In the next step 218, a DAM transfer completion signal is output to the CPU 22, and then the power saving data receiving process is terminated.

  FIG. 3 shows the flow of processing of the power saving mode return processing program executed by the CPU 22 every predetermined period when the operation state is set to the power saving mode. Hereinafter, the power saving mode return process according to the present embodiment will be described with reference to FIG. The power saving mode return processing program is stored in the ROM 34 or the like.

  First, in step 250, it is determined whether or not a DMA transfer completion signal has been received. If the determination is affirmative, the process proceeds to step 252 where the interrupt handler stored in the ROM 34 is read and executed. Accordingly, a return signal is output to each part to return the operation state of the information processing apparatus 10 from the power saving mode, and then the power saving mode return processing is ended.

  If the determination in step 250 is negative, it is determined that the operating state is not yet returned from the power saving mode at this point, and the power saving mode return process is terminated.

  As described above in detail, according to the present embodiment, received data indicating a signal received from the external PC 12 is DMA-transferred and stored in the RAM 24, and predetermined processing is performed on the received data stored in the RAM 24. When executing, when a state in which a predetermined process is not executed continues for a predetermined period or longer, the operation state is set to a power saving mode for reducing at least the power supplied to the RAM 24, and when a signal from the external PC 12 is received, Since an interrupt signal is generated before DMA transfer of received data and the operation state is restored from the power saving mode based on the interrupt signal, power consumption in the power saving mode can be reduced regardless of the hardware configuration. it can.

  Further, according to the present embodiment, in order to generate the interrupt signal, the DMA of the predetermined data for the SRAM 32 whose power supply is not reduced even in the power saving mode before the DMA transfer of the received data to the RAM 24 is performed. Since the transfer is executed and the DMA transfer completion signal of the predetermined data is used as the interrupt signal, the interrupt signal can be generated without changing the hardware configuration.

  Furthermore, according to the present embodiment, so-called empty transfer is performed in which only the request signal is transferred as predetermined data to be DMA-transferred to the SRAM 32, so that the interrupt signal can be easily changed without changing the hardware configuration. Can be generated.

  Furthermore, in the present embodiment, an interrupt handler is stored in advance in the ROM 34 in which power supply is not reduced even in the power saving mode, and the operating state is restored from the power saving mode by executing the interrupt handler. Regardless of the hardware configuration, each part (particularly the RAM 24) of the information processing apparatus 10 can be reliably restored from the power saving mode.

  The interrupt handler includes processing for transmitting an instruction to restore the power supplied to the RAM 24 to the RAM controller 26 connected to the CPU 22 via the bus bridge 20.

  Although the present embodiment has been described with respect to an embodiment in which empty transfer is performed to the SRAM 32, the present invention is not limited to this.

For example, a part of the received data actually transmitted from the external PC 12 is transferred, and when the received data is subjected to predetermined processing, the received data transferred to the SRAM 32 and the RAM 24 are joined together. The received data may be processed.
(Second Embodiment)
In the first embodiment, in the data receiving process in the power saving mode, the operation state of the information processing apparatus 10 is restored by performing the DMA transfer to the SRAM 32 before the DMA transfer of the received data to the RAM 24. In the second embodiment, a mode in which the operation state of the information processing apparatus 10 is restored by directly transmitting a FIFO alarm based on data reception to the CPU 22 will be described.

  Note that the configuration of the information processing apparatus 10 according to the second embodiment is the same as the configuration of the information processing apparatus 10 according to the first embodiment. The illustration and description in are omitted.

  FIG. 4 shows a flow of power saving data reception processing according to the second embodiment. Hereinafter, the power saving data reception process according to the second embodiment will be described with reference to FIG.

  Note that when the CPU 22 sets the operation state of the information processing apparatus 10 to the power saving mode, the CPU 22 transmits information indicating that fact to all parts regardless of whether or not the supplied power is reduced. In this case, the operating state of the information processing apparatus 10 can be grasped.

  First, in step 300, the reception of data from the outside is waited, and in the next step 302, the received data is sequentially stored in the FIFO 46. The reception data is accumulated by temporarily storing the data in the FIFO 46.

  In the next step 304, the process waits until the storage capacity of the received data in the FIFO 46 reaches a predetermined amount. If the determination is affirmative, the process proceeds to step 306.

  In step 306, the FIFO alarm output from the I / O controller 42 is output as an interrupt signal to the CPU 22, and then the process proceeds to step 308 to wait for reception of a return signal from the CPU 22.

  In the next step 310, it is determined that the RAM 24 can be accessed, and the data received from the outside is DMA transferred to the RAM 24.

  In the next step 312, the completion of transfer of received data to the RAM 24 is waited. In the next step 314, a DAM transfer completion signal is output to the CPU 22, and then the power saving data receiving process is terminated.

  FIG. 5 shows the flow of processing of the power saving mode return processing program executed by the CPU 22 every predetermined period when the operation state is set to the power saving mode. Hereinafter, the power saving mode return processing according to the second embodiment will be described with reference to FIG. The power saving mode return processing program is stored in the ROM 34 or the like.

  First, in step 350, it is determined whether or not the FIFO alarm transmitted by the ASIC 36 has been received. If the determination is affirmative, the process proceeds to step 352, and the interrupt handler stored in the ROM 34 is read. By executing, a return signal is output to each part, the operation state of the information processing apparatus 10 is returned from the power saving mode, and then the power saving mode return process is terminated.

  If the determination in step 350 is negative, it is determined that the operating state is not yet returned from the power saving mode at this point, and the power saving mode return process is terminated.

As described above in detail, according to the second embodiment, when the capacity of the received signal exceeds a predetermined amount in the I / O controller, a FIFO alarm indicating the fact is interrupted. Since the signal is transmitted to the CPU 22 as a signal, the operation state of the information processing apparatus 10 can be returned from the power saving mode without performing special processing such as DMA transfer to the SRAM 32.
(Third embodiment)
In each of the above-described embodiments, the mode of returning from the power saving mode based on the signal transmitted from the ASIC 36 has been described. However, in the third embodiment, it is determined whether it is the timing for the CPU 22 to return. A mode of returning from the power mode will be described.

  The configuration of the information processing apparatus 10 according to the third embodiment is the same as the configuration of the information processing apparatus 10 according to the first embodiment. The illustration and description in are omitted.

  FIG. 6 shows a flow of power saving data reception processing according to the third embodiment. Hereinafter, the power saving data receiving process according to the third embodiment will be described with reference to FIG.

  Note that when the CPU 22 sets the operation state of the information processing apparatus 10 to the power saving mode, the CPU 22 transmits information indicating that fact to all parts regardless of whether or not the supplied power is reduced. In this case, the operating state of the information processing apparatus 10 can be grasped.

  First, in step 400, the reception of data from the outside is waited, and in the next step 402, the received data is sequentially stored in the FIFO 46. The reception data is accumulated by temporarily storing the data in the FIFO 46.

  In the next step 404, the process waits until the storage capacity of the received data in the FIFO 46 reaches a predetermined amount. If the determination is affirmative, the process proceeds to step 406.

  In step 306, it is determined whether or not a return signal from the CPU 22 has been received. If the determination is negative, the process proceeds to step 408 to transmit a data retransmission request to the external PC 12, and thereafter Return to step 406 again.

  On the other hand, if an affirmative determination is made in step 406, it is determined that access to the RAM 24 is possible, the process proceeds to step 410, DMA transfer of data received from the outside to the RAM 24 is started, and the next step Move to 412.

  In step 412, the completion of transfer of received data to the RAM 24 is waited. In the next step 414, a DAM transfer completion signal is output to the CPU 22, and then the power saving data receiving process is terminated.

  FIG. 7 shows a flow of processing of the power saving mode return processing program executed by the CPU 22 every predetermined period when the operation state is set to the power saving mode. Hereinafter, the power saving mode return processing according to the third embodiment will be described with reference to FIG. The power saving mode return processing program is stored in the ROM 34 or the like.

  The power saving mode return processing program is usually included in a processing program executed by the CPU 22 every predetermined period (for example, 50 msec) by a system timer (not shown) in the CPU in the power saving mode.

  First, in step 450, the status of the ASIC 36 is checked. In the next step 452, it is determined whether or not the ASIC 36 has received data from the external PC 12. If the determination is affirmative, the process proceeds to step 454. Then, by reading out and executing the interrupt handler stored in the ROM 34, a return signal is output to each part to return the operation state of the information processing apparatus 10 from the power saving mode, and then the power saving mode return processing is terminated. To do.

  On the other hand, if a negative determination is made in step 452, it is determined that the operating state is not yet returned from the power saving mode at this point, and the power saving mode return process is terminated.

  As described above in detail, according to the third embodiment, received data indicating a signal received from the external PC 12 is DMA-transferred and stored in the RAM 24, and the received data stored in the RAM 24 is predetermined. When executing the above process, if the state in which the predetermined process is not executed continues for a predetermined period or longer, the operation state is set to the power saving mode for reducing power supplied to at least the RAM 24, and data is received from the external PC 12 in the power saving mode. In this case, the reception of the data is temporarily stopped by the I / O controller 44, and the presence or absence of the signal received from the external PC 12 is determined by the CPU 22 every predetermined period, and it is determined that the signal is received from the external PC 12. If the operation state is restored from the power saving mode and data reception by the I / O controller 44 is resumed , Because to perform the DMA transfer of the received data to RAM24 by the DMA controller 42, regardless of the hardware configuration, it is possible to reduce the power consumption in the power saving mode.

  Here, in the third embodiment, it has been described that the reception of data is temporarily stopped. However, as another embodiment, the time for which the storage capacity of the FIFO 46 is executed by the CPU 22 to execute the power saving mode return process is described. By increasing the data received within the interval (corresponding to the “predetermined period” above) to a capacity that can be stored, the means for stopping data reception can be omitted.

  In each of the above embodiments, the interrupt handler is stored in the ROM 34 and the operation state is returned from the power saving mode by executing the interrupt handler. However, the present invention is limited to this. It is not a thing.

  For example, an SRAM 32 or the like that is connected to the ASIC 36 and can be appropriately stored in a portion where power is not reduced even in the power saving mode.

  In addition, if the configuration of the information processing apparatus 10 is a configuration that can return from the power saving mode without using an interrupt handler, the interrupt handler need not be stored.

  Furthermore, the configuration (see FIG. 1) of the information processing apparatus 10 according to each of the above embodiments is an example, and can be changed as appropriate without departing from the spirit of the present invention.

  The processing flow according to each of the above embodiments (see FIGS. 2 to 7) is also an example, and can be changed as appropriate without departing from the spirit of the present invention.

It is the schematic which shows the structure of the information processing apparatus which concerns on embodiment. It is a flowchart which shows the flow of the power saving data reception process which concerns on 1st Embodiment. It is a flowchart which shows the flow of a process of the power saving mode return process program which concerns on 1st Embodiment. It is a flowchart which shows the flow of the power saving data reception process which concerns on 2nd Embodiment. It is a flowchart which shows the flow of a process of the power saving mode return process program which concerns on 2nd Embodiment. It is a flowchart which shows the flow of the power saving data reception process which concerns on 3rd Embodiment. It is a flowchart which shows the flow of a process of the power saving mode return process program which concerns on 3rd Embodiment.

Explanation of symbols

10 Information processing device 12 External PC (External device)
20 bus bridge 22 CPU (operation state control means)
24 RAM (main storage means)
26 RAM controller 30 bus 32 SRAM (auxiliary storage means)
34 ROM (storage means)
36 ASIC (interrupt signal generation means, reception restart means)
42 DMA controller 44 I / O controller 46 First-in first-out memory for reception: FIFO

Claims (6)

An operation state control unit that shifts to a power saving mode that controls power supply and reduces power consumption when a state in which predetermined processing for data received from an external device is not executed is continued for a predetermined period or more with respect to the normal mode. An information processing apparatus whose main storage means for temporarily storing data received from outside for predetermined processing is a target of a power saving mode,
Auxiliary storage means in which power supply is not reduced even in the power saving mode;
Receiving data from the external device and including received data storage means for storing the received data, and when the received data stored in the received data storage means reaches a predetermined capacity, the predetermined capacity A notification means for notifying that
Receiving the notification from the notification means, DMA-transferring a predetermined signal to the auxiliary storage means triggered by the notification, and when the DMA transfer of the predetermined signal is completed, the normal mode of the main storage means DMA transfer means for generating an interrupt signal instructing the return to and transmitting the interrupt signal;
Receiving the interrupt signal, using the interrupt signal as a trigger, the operating state of the main memory means is returned from the power saving mode to the normal mode, and a return signal indicating that the main memory means has returned to the normal mode is transmitted. A data reception return control means,
An information processing apparatus, wherein the DMA transfer means receives the return signal and performs DMA transfer of the received data stored in the received data storage means to the main storage means using the return signal as a trigger. Read-only storage means in which a program related to return processing from the power saving mode to the normal mode is stored in advance,
The data reception return control means, after receiving the interrupt signal, restores the operating state of the main storage means from the power saving mode using the program stored in the read-only storage means in advance. The information processing apparatus according to claim 1, wherein a unit is in the normal mode.   The information processing apparatus according to claim 1, wherein the predetermined signal is a request signal for a write request to the auxiliary storage unit. An operation state control unit that shifts to a power saving mode that controls power supply and reduces power consumption when a state in which predetermined processing for data received from an external device is not executed is continued for a predetermined period or more with respect to the normal mode. And a data reception return control means for returning the power saving mode to the normal mode with the reception of an interrupt signal as a trigger, and a main storage means for temporarily storing data received from outside for predetermined processing; Auxiliary storage means, notification means for receiving data from the external device, received data storage means for storing the received data, DMA transfer means for DMA transfer of data or signals to the main storage means and the auxiliary storage means And a method of controlling an information processing apparatus in which the main storage means is a target of a power saving mode,
Even in the power saving mode, maintaining the power supply of the auxiliary storage means,
Receiving data from the external device;
The received data is stored in the received data storage means, and when the storage of the received data reaches a predetermined capacity, the notification means notifies the DMA transfer means to that effect,
Using the notification as a trigger, the DMA transfer means DMA-transfers a predetermined signal to the auxiliary storage means,
When the DMA transfer of the predetermined signal is completed, the DMA transfer unit generates an interrupt signal instructing the main memory unit to return to the normal mode, and the DMA transfer unit receives the generated interrupt signal in the data reception Sent to the hour return control means,
Using the interrupt signal as a trigger, the data reception return control means returns the operation state of the main storage means from the power saving mode to the normal mode, and a return signal indicating that the main storage means has returned to the normal mode. Transmitting to the DMA transfer means;
A method for controlling an information processing apparatus, wherein the DMA transfer means receives the return signal, and the received data stored in the received data storage means is DMA-transferred to the main storage means using the return signal as a trigger. A control method for an information processing apparatus, further comprising read-only storage means in which a program related to return processing from the power saving mode to the normal mode is stored in advance,
When the data reception return control means uses the interrupt signal as a trigger to return the operation state of the main storage means from the power saving mode to the normal mode, the program stored in advance in the read-only storage means is used. The method of controlling an information processing apparatus according to claim 4 . It said predetermined signal, according to claim 4 or claim 5 information processing apparatus control method according to wherein a request signal of the write request to the secondary storage means.

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