JP2003122536A - Printer controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve power-saving effect by mending the periodical return of a CPU 1 and a memory 3 from the power-saving state. SOLUTION: In the power-saving state, a print mechanism control circuit 25 automatically monitors the condition of a print mechanism 4, and informs the change of the condition of the print mechanism 4 to be informed to the CPU 1 with an interrupt. A console panel control circuit 27 presses a switch on a console panel 6, thereby generating an interrupt. On receiving the receive data from a host computer 7, a host interface circuit 28 generates an interrupt. Thus, each circuit automatically monitors the peripheral device of a printer controller 2, whereby it is not necessary to return the CPU 1 and the memory 3 periodically from the power-saving state so as to obtain an efficient power- saving effect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer controller between a printer such as an electrophotographic printer and a host computer and controlling the printer.

[0002]

2. Description of the Related Art The power saving mode of a printer controller is
It is used to reduce power consumption when the printer is on standby. FIG. 7 is a flowchart showing the operation of the conventional printer controller in the power saving mode. Less than,
A description will be given based on this drawing.

Although not shown, the printer is connected to a host computer and includes a printer mechanism, a printing mechanism, an LCD, an operation panel and the like. The printer controller has a CPU, a memory, a timer function, etc.,
It operates as follows according to the program.

First, when the power saving mode can be started, it is determined whether or not the preheating of the printing mechanism is turned off (step 151), and when it is determined that the preheating is turned off, a preheating OFF command is transmitted to the printing mechanism (step 152). Then set the memory to power down mode (step 1
53), the standby mode instruction of the CPU is executed (step 154). This allows the printing mechanism, memory and C
The PU has entered the power saving state.

However, the CPU returns from the standby mode at regular intervals and performs the processing described in step 158, that is, the status confirmation of the printing mechanism, the LCD display update, the operation panel monitoring, and the data reception from the host computer. You must check the situation. Therefore, the CPU returns from the standby mode by the interruption by the timer (steps 155 to 156). At this time, since it is possible to use the memory for the processing of step 158, the power down mode of the memory is also canceled (step 157).

Then, the above-mentioned processing is executed (step 158). When it is determined that the power saving state does not have to be canceled after the processing of step 158 is completed (step 159),
The processing to enter the power saving state is executed again from step 153. On the other hand, when it is determined that the power saving state is released in step 159, a preheat ON command is transmitted to the printing mechanism (step 160), and the power saving state is ended.

[0007]

However, the prior art has the following problems.

Even when the CPU is in the power saving state, the power saving state of the CPU and the memory is released at a constant cycle in order to monitor the state of the printing mechanism, the state of the switch of the operation panel, the presence or absence of data from the host computer. I had to. Therefore, even if it is not necessary to cancel the power saving state, the power saving state is canceled, so that power is wasted.

The CPU can set and release the power saving state.
And was running almost simultaneously in both memory. Therefore, even if it is sufficient to cancel the power saving of either one of them, the power of both of them is canceled, so that the power is wasted.

That is, in the conventional operation, the processing of step 158 shown in FIG. 7 is processing of a program, not hardware. Therefore, even if it is not necessary to recover from the power saving state, the CPU and the memory must be recovered in a constant cycle, and the power saving effect is reduced.

[0011]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a printer controller capable of improving the power saving effect.

[0012]

The present invention is a printer controller which is connected to a printing mechanism, a display and an operation panel of a printer and a host computer, and which includes a CPU and a memory and controls the printer. It has the following functions.

A status request command is transmitted to the printing mechanism while the CPU and the memory are in a power saving state, the status is acquired from the printing mechanism, and an interrupt to the CPU and the memory is generated according to the status. , A function for canceling the power saving state of the CPU and the memory (claim 1).

A function of monitoring the state of the switch on the operation panel during the power saving state of the CPU and the memory, generating an interrupt to the CPU and the memory according to the state, and canceling the power saving state of the CPU and the memory. (Claim 2).

When data is received from the host computer while the CPU and memory are in the power saving state, the CP
Generates an interrupt to U and the memory,
And a function for canceling the power saving state of the memory (claim 3).

When data is received from the host computer while the CPU and the memory are in the power saving state, an interrupt to the memory is generated to cancel the power saving state of the memory, and the received data is stored in the memory by DMA transfer. After that, a function of generating an interrupt to the CPU to cancel the power saving state of the CPU (claim 4).

In the printer controller according to any one of claims 1 to 3, a function of determining whether or not to generate an interrupt for the memory according to an interrupt factor (claim 5).

In the printer controller according to any one of claims 1 to 5, a function of enabling the power saving state by register setting and invalidating the power saving state by the interrupt (claim 6).

According to a sixth aspect of the present invention, there is provided a printer controller having two registers, one for the memory and the other for the register, and a function for enabling or disabling the power saving state separately.

In the printer controller according to any one of claims 1 to 7, a function of preventing erroneous display due to noise on the display by continuously transmitting display data to the display when the power saving state is achieved (claim 8) ).

In other words, according to the present invention, the power saving management circuit is provided in the printer controller of the printer, so that the printing mechanism, the display, the operation panel, the host computer, etc. can be operated without returning the CPU and the memory from the power saving state. It is characterized by being able to manage and reducing power consumption. More concretely, for example, the following configuration is adopted.

1. A printing mechanism control circuit that automatically sends a status request command to the printing mechanism when it is in a power saving state, acquires the status from the printing mechanism, analyzes the status, and generates an interrupt to the CPU.

2. A display control circuit that automatically sends display data to the display when it enters a power-saving state and prevents erroneous display due to display noise.

3. An operation panel control circuit that automatically monitors the status of the switch on the operation panel when it enters a power saving state and generates an interrupt depending on the status of the switch.

4. A host interface circuit that generates an interrupt to the CPU when data is received from the host computer during the power saving state.

5. When data is received from the host computer during the power saving state, first a signal is output to the memory to notify the power-down mode release, the received data is stored in the memory by DMA transfer, an interrupt is generated in the CPU, and the standby mode is released. Host interface circuit to let.

6. An interrupt control circuit that can set whether to generate an interrupt in the memory control circuit according to the interrupt factor.

7. A power saving management circuit that enables the power saving status notification signal by register setting and automatically disables the power saving status notification signal by interrupt.

8. Above 7. A power-saving management circuit that has two power-saving status notification signals for memory and other systems.

[0030]

1 is a block diagram showing a first embodiment of a printer controller according to the present invention. Hereinafter, description will be given with reference to this drawing.

The printer is connected to the host computer 7, and includes a printer controller 2, a printing mechanism 4, an LCD 5 as a display, an operation panel 6, and the like. In the printer controller 2, the CPU 1 accesses the memory 3 via the system bus control circuit 21 and the memory control circuit 24 to process print data and the like, and the printing mechanism 4 performs printing, and the interrupt control circuit 22. , A power saving management circuit 23, a memory control circuit 24,
A printing mechanism control circuit 25, an LCD control circuit 26, an operation panel control circuit 27, a host interface circuit 28, etc. are provided.

When the power saving management circuit 23 notifies that the CPU 1 is in the standby mode (power saving state), the memory control circuit 24, the printing mechanism control circuit 25, and the LCD control that the printer controller 2 is in the power saving state. Circuit 2
6, the operation panel control circuit 27, the host interface circuit 28, etc. are notified.

Then, the printing mechanism control circuit 25, the LCD control circuit 26, the operation panel control circuit 27, the host interface circuit 28, and the memory control circuit 24, which have been notified of the power saving state, operate as follows.

The printing mechanism control circuit 25 automatically monitors the state of the printing mechanism 4 and notifies the CPU 1 of a change in the state of the printing mechanism 4 that should be notified by an interrupt. The LCD control circuit 26 uses the LCD 5 due to external electrical noise.
In order to prevent erroneous display of, display data is automatically and periodically transmitted to the LCD 5. Operation panel control circuit 27
Generates an interrupt by pressing a switch on the operation panel 6. When the host interface circuit 28 receives the received data from the host computer 7,
Generate an interrupt. The memory control circuit 24 puts the memory 3 in the power down mode.

Therefore, each circuit automatically monitors the peripheral devices of the printer controller 2 and the CP
Since it is not necessary to periodically return the U1 and the memory 3 from the power saving state, an efficient power saving effect can be obtained.

Next, a more detailed description will be given.

The printer controller 2 has a CPU 1 and a memory 3 built-in, and is connected to the printing mechanism 4, the operation panel 6, the host computer 7, and the like. The CPU 1 processes the data from the host computer 7 using the memory 3 and sends the print data to the printing mechanism 4 to print it. The CPU 1 also monitors the state of the printing mechanism 4, transmits display data to the LCD 5 to display the state and settings of the printer, and monitors the operation panel 6 to accept settings to the printer. The memory 3 is composed of a synchronous DRAM (SDRAM) here.

The SDRAM is in a power down mode (power saving state) by transmitting a self refresh command.
Then, it can be released by operating the CKE terminal. It is assumed that the CPU 1 enters a standby mode (power saving state) in response to a program instruction and cancels it by an interrupt input.

The printing mechanism 4 is an electrophotographic system that receives print data from the printer controller 2 and prints. Further, various settings to the printing mechanism 4 are performed by sending commands from the printing mechanism control circuit 25.
In addition, the state of the printing mechanism 4 is confirmed by the printing mechanism control circuit 2
Printing mechanism 4 returns status data by transmitting a status request command from 5.

Next, the internal structure of the printer controller 2 will be described.

The system bus control circuit 21 determines the access timing of the CPU 1 and exchanges data between the CPU 1 and the memory 3 and between the printer controller 2.

The interrupt control circuit 22 controls an interrupt from inside the printer controller 2. That is, prioritization of each interrupt, max control, and holding of the interrupt status are performed, and an interrupt is generated for the CPU 1 according to the state.

The power-saving management circuit 23 has a power-saving mode register that receives the power-saving setting from the CPU 1. When the power-saving setting is received, the internal circuit of the printer controller 2 is notified of the power-saving state. Also, during the power saving state,
The interrupt from the interrupt control circuit 22 is monitored, and when the interrupt occurs, the power saving state is automatically canceled and the internal circuit is notified.

The memory control circuit 24 controls the exchange of data between the memory 3 and the system bus control circuit 21.
In addition, when it is notified that the power saving state has been entered, the memory 3
Issue a self-refresh command to the memory 3
To power down mode.

When the printing mechanism control circuit 25 receives the status notification request of the printing mechanism 4 from the CPU 1, it issues a status request command to the printing mechanism 4 and receives the status data from the printing mechanism 4. That is, when the notification of the power saving state is given, the CPU
According to the state notification request setting in the power saving state set by 1, the status request command is automatically and periodically issued to the printing mechanism 4, the status data received from the printing mechanism 4 is analyzed, and the CPU 1 should be notified. At that time, an interrupt is generated and notified.

The LCD control circuit 26 uses the L signal from the CPU 1.
When receiving the CD display data, the data is transmitted to the LCD 5. Normally, L due to electrical noise from the outside
In order to prevent erroneous display of the CD 5, the CPU 1 writes the LCD display data in the LCD control circuit 26 at a constant cycle,
The display of CD5 is being updated. On the other hand, when it is notified that the power saving state has been entered, the LCD control circuit 26 causes the LCD 5
LCD is automatically updated at regular intervals to update the display
Data is transmitted to 5.

The operation panel control circuit 27 includes the operation panel 6
The state of is reflected in the register. The CPU 1 reads the contents of the register and confirms the state of the switch on the operation panel 6. When the operation panel control circuit 27 is notified that the power saving state has been entered, the operation panel control circuit 27 automatically monitors the change of the switch on the operation panel 6 and generates an interrupt to generate a CPU.
Notify 1.

When receiving data from the host computer 7, the host interface circuit 28 writes the received data in the memory 3 via the memory control circuit 24 by normal DMA transfer. When notified of the power saving state, the host interface circuit 28 generates an interrupt upon receiving the data from the host computer 7, and C
It informs PU1 that it is receiving data. In addition,
The DMA (Direct Memory Access) transfer is a method of directly transferring data between the memory 3 and the input / output device without going through the CPU 1.

FIG. 2 [1] is a block diagram showing an example of the internal configuration of the power saving management circuit 23, and FIG. 2 [2] is a block diagram showing an example of the internal configuration of the printing mechanism control circuit 25. Hereinafter, description will be given with reference to FIGS. 1 and 2.

The power saving management circuit 23 includes a power saving mode register 232 which receives power saving settings from the CPU 1 and an interrupt detection circuit 23 which detects an interrupt from the interrupt control circuit 22.
1 and. When the CPU 1 sets the power saving mode register 232 to enter the power saving state, the power saving state notification signal becomes valid. On the other hand, when the interrupt signal becomes valid and the interrupt detection circuit 231 detects it, the power saving mode register 232 is reset and the power saving state notification signal becomes invalid.

The printing mechanism control circuit 25 includes a communication unit 251 that actually sends and receives data to and from the printing mechanism 4, and a normal time C
A command setting register 252 for setting a status reception request and a command issuing request from the PU 1, and a status register 2 for storing status data from the printing mechanism 4.
53, a power saving status request setting register 254 for setting a status request to be transmitted to the printing mechanism 4 during power saving, and an interrupt for setting and detecting how the status data changes during power saving to generate an interrupt. And generating means 256.

Under normal conditions, the CPU 1 transmits the status request set in the command setting register 252 to the printing mechanism 4 by the communication means 251 and stores the status data from the printing mechanism 4 in the status data register 253. Selector 2 when the power saving status notification signal is valid
As the status request transmitted by 55, the communication means 251 transmits the status request set in the power saving status request setting register 254. Further, the data stored in the status data register 253 is monitored by the interrupt generating means 256, and when a change in the set status is detected, a status interrupt is generated.

3 and 4 show the printer controller 2
6 is a flowchart showing an example of the operation of FIG. Below, Figure 1
The operation of the printer controller 2 will be described with reference to FIG.

First, when the power saving state can be started, the program determines whether or not to turn off the preheating of the printing mechanism 4 (step 131). When it is determined to turn it off, a preheating OFF command is issued via the printing mechanism control circuit 25. It is transmitted to the printing mechanism 4 (step 132). Subsequently, a status request command to be transmitted to the printing mechanism 4 in the power saving mode is set in the power saving status request setting register 254, and when any status data is sent from the printing mechanism 4, an interrupt is generated in the CPU 1. This is set in the interrupt generating means 256 (step 133). Then, the power saving mode register 232 is set to enter the power saving mode (step 34). As a result, the power saving mode notification signal becomes valid and notifies each circuit in the printer controller 2 that the power saving mode has been entered. Then, each circuit in the printer controller 2
The operation in each power saving mode is executed.

The LCD control circuit 26 transmits display data to the LCD 5 at regular intervals to prevent erroneous display of the LCD due to external electrical noise (step 1).
35). The memory control circuit 24 issues a self-refresh command to the memory 3 to cause the memory 3
To the power down mode (step 136). The print mechanism control circuit 25 uses the status request set in the power saving status request setting register 254.
The command is transmitted to the printing mechanism 4, and the status data for the command is received. The data is interrupted by means 2
It is analyzed at 56 to determine whether or not to generate an interrupt (step 137). The operation panel control circuit 27 monitors whether or not the switch on the operation panel 6 is pressed, and determines whether or not to generate an interrupt (step 13).
8). The host interface circuit 28 monitors the data reception status from the host computer 7 and determines whether or not to generate an interrupt (step 139). The power saving management circuit 23 monitors the interrupt signal from the interrupt control circuit 22 and determines whether to invalidate the power saving state notification signal (step 140). The CPU 1 executes the standby mode instruction at the same time as the above operation, and is in the standby mode (power saving state) (step 14).
1).

Then, when an interrupt is generated from any of the printing mechanism control circuit 25, the operation panel control circuit 27, and the host interface circuit 28, the interrupt control circuit 22 causes the CPU 1 and the power saving management circuit 23 to generate an interrupt. (Step 142). And CPU1
Returns from standby mode to normal operation (step 141). The power saving mode register 232 in the power saving management circuit 22 is reset, and the power saving state notification signal becomes invalid (step 140). Accordingly, the memory control circuit 24
Cancels the power down mode of the memory 3 (step 136). Printing mechanism control circuit 25, LCD control circuit 2
6, the operation panel control circuit 27, and the host interface circuit 28 end the operation automatically executed during power saving (steps 135, 137, 138, 139).

After that, when it is determined that the power saving state does not have to be released (step 143), the processing for entering the power saving state again from step 134 is performed. On the other hand, if it is determined in step 143 that the power saving state is released, a preheat ON command is transmitted to the printing mechanism 4 (step 144), and the power saving state is ended.

FIG. 5 is a block diagram showing a second embodiment of the printer controller according to the present invention. FIG. 6 is a block diagram showing an example of a power saving management circuit in the printer controller of FIG. Hereinafter, description will be given with reference to these drawings. However, in FIG. 5, the same parts as those in FIG.

Printer controller 2'of this embodiment
The basic configuration is the same as that of the first embodiment, but the interrupt control circuit 22 ', the power saving management circuit 23', and the host interface circuit 28 'are further devised.

The interrupt signals output from the interrupt control circuit 22 'are divided into those for the CPU 1 and the power saving management circuit 23' and those for only the power saving management circuit 23 '. CPU1
The interrupt signal to the interrupt management circuit 23 'is an interrupt generated by any interrupt factor. on the other hand,
The interrupt signal to only the power saving management circuit 23 'is stored in the memory 3
Is an interrupt signal for memory control for returning from the power-down mode. The interrupt control circuit 22 'is provided with a register for determining whether or not the memory 3 is returned from the power-down mode for each interrupt input, and the memory control interrupt signal is controlled by the register and the generated interrupt.

The power saving management circuit 23 'separately inputs an interrupt signal common to the CPU 1 and a memory control interrupt signal. The power saving state notification signal is divided between the other circuit and the memory control circuit 24. This is for separately controlling the power saving state notification signal to the memory control circuit 24 and the power saving state notification signal to other circuits.
Further, the interrupt signal output from the host interface circuit 28 'is divided into the interrupt control circuit 22' and the power saving management circuit 23 '. These are CPU1
The standby mode release and the power down mode release of the memory 3 are separated for separate control.

In FIG. 6, the power saving mode register A23
Reference numeral 2'denotes a register for setting a power saving mode other than the memory 3, and is reset when the interrupt detection circuit A231 'detects an interrupt signal common to the interrupt to the CPU1. The circuits other than the memory control circuit 24 are notified of the power saving state notification signal according to the contents set in the power saving mode register A232 '. On the other hand, power saving mode register B23
Reference numeral 4 is a register for setting the power saving mode of the memory 3, which is used to send an interrupt signal for memory control to the interrupt detection circuit A.
When it is detected by 233, it is reset. According to the contents set in the power saving mode register B234, the power saving state notification signal is notified to the memory control circuit 24.

Next, the operation of the printer controller 2'will be described.

First, the operation of returning only the memory 3 from the power down mode during the power saving mode will be described. Upon receiving the data from the host computer 7, the host interface circuit 28 'enables only the interrupt to the power saving management circuit 23'. When the interrupt detection circuit B233 of the power saving management circuit 23 'detects the interrupt, the power saving mode register B234 is reset and the power saving state notification signal (for the memory control circuit) becomes invalid. The memory control circuit 24 having received it returns the memory 3 from the power down mode.

After that, the host interface circuit 28 '
Stores the received data in the memory 3 via the memory control circuit 24 by DMA transfer. When the data reception from the host computer 7 is completed and the storage of the data in the memory 3 is completed, the host interface circuit 28 '
Generates an interrupt to the interrupt control circuit 22 'and returns the CPU 1 from the standby mode. By performing this operation, the CPU 1 can be kept in the standby mode for as long as possible, so that a more efficient power saving effect can be obtained as compared with the case where the memory 3 and the CPU 1 are simultaneously controlled.

Next, the operation for returning only the CPU 1 from the standby mode during the power saving mode will be described. Here, the operation when the switch of the operation panel 6 is pressed will be described, but the same applies when the status of the printing mechanism 4 is in the state of returning the standby mode of the CPU 1. It is assumed that the interrupt control circuit 22 'is set so that the interrupt for the operation panel control circuit 27 does not generate an interrupt for memory control.

When the operation panel control circuit 27 detects that the switch on the operation panel 6 is pressed during the power saving mode, it causes the interrupt control circuit 22 'to generate an interrupt signal. The interrupt control circuit 22 'is C according to the setting.
The interrupt to PU1 is generated, but the interrupt for memory control is not generated. As a result, the CPU 1 returns from the standby mode and confirms that the switch has been pressed. If it is determined that the operation of the switch is not enough to cancel the power saving mode, the power saving mode register A232 '
Then, the CPU 1 itself is set to the standby mode again. By performing this operation, it is possible to prevent the memory 3 from returning from the power down mode even when it is not necessary to return from the power down mode. Therefore, as compared with the case where the memory 3 and the CPU 1 are controlled at the same time, A more efficient power saving effect can be obtained.

[0068]

According to the printer controller of the present invention, it is not necessary to release the CPU from the power saving state (standby mode) in a constant cycle during the power saving state, so that wasteful recovery of the CPU from the power saving state is eliminated. The power saving effect can be obtained efficiently. Furthermore, since it is not necessary to release the memory from the power saving state (power down mode) at a constant cycle, it is possible to eliminate unnecessary recovery from the power saving state of the memory, and the power saving effect can be efficiently obtained. The reason for them is
This is because circuits other than the CPU automatically monitor the state around the printer controller, which was conventionally monitored by the CPU.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a printer controller according to the present invention.

FIG. 2 [1] is a block diagram showing an example of a power saving management circuit in the printer controller of FIG. 1.
2 [2] is a block diagram showing an example of a printing mechanism control circuit in the printer controller of FIG.

FIG. 3 is a flowchart showing an operation of the printer controller of FIG.

FIG. 4 is a flowchart showing an operation of the printer controller of FIG.

FIG. 5 is a block diagram showing a second embodiment of the printer controller according to the present invention.

6 is a block diagram showing an example of a power saving management circuit in the printer controller of FIG.

FIG. 7 is a flowchart showing the operation of a conventional printer controller.

[Explanation of symbols]

1 CPU 2,2 'printer controller 3 memory 4 printing mechanism 5 LCD (display) 6 Operation panel 7 Host computer 21 System Bus Control Circuit 22, 22 'interrupt control circuit 23, 23 'power saving management circuit 24 Memory control circuit 25 Printing mechanism control circuit 26 LCD control circuit 27 Operation panel control circuit 28, 28 'Host interface circuit

Continued front page    F-term (reference) 2C061 AQ06 HH11 HT03 HT06 HT09                       HT13                 2H027 DA50 EE08 EE09 EF16 EJ15                       GA31                 5B011 KK11 LL11                 5B021 AA02 BB01 BB04 CC05 MM02

Claims (8)

[Claims] 1. A CP connected to a printing mechanism, a display and an operation panel of a printer, and a host computer.
A printer controller including U and a memory, which controls the printer, transmits a status request command to the printing mechanism while the CPU and the memory are in a power saving state, acquires the status from the printing mechanism, and outputs the status. A printer controller having a function of generating an interrupt to the CPU and the memory according to the above and canceling the power saving state of the CPU and the memory. 2. A CP connected to a printing mechanism of a printer, a display and an operation panel, and a host computer,
A printer controller including a U and a memory for controlling the printer, monitors a state of a switch on the operation panel during a power saving state of the CPU and the memory, and controls the CP according to the state.
Generates an interrupt to U and the memory,
And a printer controller having a function of canceling the power saving state of the memory. 3. A CP connected to a printing mechanism of a printer, a display and an operation panel, and a host computer,
In a printer controller that includes U and a memory and controls the printer, when data is received from the host computer while the CPU and the memory are in the power saving state, an interrupt to the CPU and the memory is generated, and the CPU and the memory are in the power saving state. A printer controller characterized by having a function for canceling. 4. A CP connected to a printing mechanism of a printer, a display and an operation panel, and a host computer,
In a printer controller that includes U and a memory and controls the printer, when data is received from the host computer while the CPU and the memory are in the power saving state, an interrupt is generated for the memory to cancel the power saving state of the memory, After storing the received data in the memory by DMA transfer,
A printer controller having a function of generating an interrupt to the CPU to cancel a power saving state of the CPU. 5. The printer controller according to claim 1, further comprising a function of determining whether to generate an interrupt for the memory according to an interrupt factor. 6. The printer controller according to claim 1, further comprising a function of enabling the power saving state by register setting and invalidating the power saving state by the interrupt. 7. The printer controller according to claim 6, further comprising two registers, one for the memory and the other for the register, each of which further has a function of enabling or disabling the power saving state. 8. The display device further comprises a function of preventing display error due to noise of the display by continuously transmitting display data to the display when the power saving state is set. The printer controller according to 6 or 7.