JP4839605B2 - Electronics - Google Patents

Description

  The present invention relates to an electronic device that can easily rewrite firmware and the like and is suitable for use in household appliances and the like.

  A home electronic device such as an air conditioner, a refrigerator, a television, and a telephone incorporates a CPU that operates based on a program. Of these programs, what is positioned between hardware and software is generally called firmware. If this firmware is stored in a flash memory or the like, functions can be added and defects can be corrected later.

  However, in the stationary home appliances such as the refrigerator and the air conditioner, the firmware is not normally rewritten, and the function is not added. In addition, when rewriting (or replacing) the firmware to correct a problem, it is usually performed by a service person with a certain technique, and the user cannot rewrite the firmware easily. It was.

On the other hand, in Patent Document 1, when rewriting firmware, the normal operation mode is switched to a special mode, and data for firmware rewriting is input from an input terminal for digital audio signals or other terminals. An audio device is described that performs an upgrade by appropriately overwriting a reproduction processing program area of a memory.
JP 2002-149428 A

  However, in the apparatus described in Patent Document 1, data for firmware rewriting is obtained from a medium (such as a compact disk) handled by the audio apparatus. As described above, when the apparatus itself has a recording medium reproducing mechanism in a normal use state, the firmware can be rewritten by a method as disclosed in Patent Document 1.

  However, in home appliances that do not have a recording medium playback mechanism such as a refrigerator or an air conditioner, it is difficult to rewrite the firmware, and if a separate recording medium playback mechanism is provided for firmware rewriting, the structure is Complicated and costly.

  The present invention has been made in view of the above-described circumstances, and rewrites firmware or the like without providing a special reproduction mechanism for an electronic device such as a home appliance or using a special external device. The purpose is to provide an electronic device that can be used.

To solve the above problem, in the present invention, a storage means for pulp processor device controls the instrumentation置各portion at least one of firmware or data that is used is stored, input from an external audio device there an input circuit that converts the data signal receiving digital signals of the digital audio interface standard, the dividing positions at predetermined timing during one frame before SL data signal are entered from the input circuit via the terminal A command for rewriting the firmware by extracting and analyzing the data, the processor device for recognizing the firmware rewrite data or the reference update data, and the rewrite data recognized by the processor device Far in the storage means by the data or the updated data In the electronic device is a device for and a rewriting means for rewriting at least one of wear or data, the digital signal includes a data of a plurality of frequency division form according to the processing speed of the processor device, said data When data indicating a frequency division mode is extracted from the signal and the processor device recognizes a rewrite instruction command that matches its own processing speed as an analysis result, the data of the frequency division form corresponding to the own processing speed is obtained. It selects, and rewriting by the said rewriting means is started .

  Further, as a preferred aspect, the processor device may further function as the rewriting means.

In addition, a device main body provided with each part controlled by the processor device, the storage means, the rewriting means, and the processor device, and an adapter portion provided with the input circuit are provided separately, the data signal input circuit outputs are input provided Lud over data input terminal, before and Kide over data input terminal and the output side of the input circuit may be detachable.

  In addition, the electronic device can be applied to various devices such as an air conditioner, a refrigerator, a washing machine, a telephone, and a television that are household electric appliances.

  The firmware of a processor device used for home appliances can be rewritten using an output signal of an audio device.

(Configuration of the embodiment)
Embodiments of the present invention will be described below. FIG. 1 is a block diagram showing the configuration of the present embodiment. In the figure, reference numeral 1 denotes a control circuit, which controls a household refrigerator in this embodiment. 10 shown in the figure is a CPU that controls each part of the apparatus, and operates according to programs stored in the memory 11 and the flash memory 12. In this embodiment, the flash memory 12 stores firmware, data referred to by the CPU 10, an OS (operating system), application programs, and the like, and the memory 11 is used as a work area of the CPU 10.

  Reference numeral 15 denotes a drive control unit that performs drive control of the compressor of the refrigerator under the control of the CPU 10 while monitoring the temperature signal from the temperature sensor 15b so that the temperature set by the operation unit 15a that sets the temperature is obtained. Control the compressor. In addition, the drive control unit 15 includes a display unit 15 c that performs various displays under the control of the CPU 10. The configuration of the control circuit 1 in the present embodiment is the same as that of a general refrigerator control circuit.

  Next, 2 shown in FIG. 1 is an input circuit for receiving a signal for firmware update. The input circuit 2 includes an input terminal IN and a digital interface receiver (hereinafter abbreviated as DIR) 20.

  A digital audio signal DAS of the SPDIF (Sony / Philips Digital Interface Format) standard, which is one of the digital audio interface standards, is input to the input terminal IN. In the present embodiment, a portable CD player 30 outside the apparatus reproduces the compact disc 35 and supplies a digital audio signal DAS according to the SPDIF standard to the input terminal IN.

  The digital audio signal DAS is converted by DIR2 into a signal suitable for an I2S bus (The Inter-IC Sound Bus). The I2S bus is a standard generally used for transmission / reception of 2CH (stereo) audio sampling digital data. As shown in FIG. 2, a word clock LRCLK (see FIG. 2 (A)), a bit clock BCLK (FIG. 2 (B)) indicating the timing of each bit, and a data signal RDATA (FIG. 2 (C)) indicating the contents of the transferred data. In the word clock LRCLK, as shown in FIG. 2A, the L level period indicates L-ch (left channel), and the H level period indicates R-ch (right channel). In the actual I2S standard, as shown in FIG. 2 (d), the data signal RDATA is defined to be shifted by 1 bit from the falling edge of the word clock LRCLK. The description will be made assuming that there is no bit shift as shown in 2 (c).

In the I2S bus standard, the data length of one frame is not defined and is arbitrary, but in this embodiment, it is 64 bits. In this embodiment, the effective bits indicating the data contents of the 32 bits on one side channel are 16 bits, and the other bits are control data and empty (reserved) bits. For the sake of simplicity, in the following, it is assumed that one-side channel has 16 bits and all the bits are valid bits (see FIG. 3).
In the present embodiment, the word clock LRCLK and the data signal RDATA are supplied from the DIR 20 to the CPU 10.

  Here, the CPU 10 reads the data signal RDATA as follows. That is, as shown in FIG. 3, the data signal RDATA is read at the timing delayed by the time τ1 from the falling and rising of the word clock LRCLK, and then the data signal RDATA is read three times at the timing delayed by the time τ2. In this example, the time τ1 is set to about 1/8 time of one frame, and the time τ2 is set to 1/4 of one frame. As a result, as shown in FIG. 3, the CPU 10 reads the data signal RDATA four times for L-ch and R-ch, that is, eight times in one frame. That is, data that is originally transferred at a rate of 32 bits per frame is read at a speed obtained by dividing it by four. In other words, reading is performed once for each section divided by 4 bits. Although FIG. 3 shows the case of L-ch, the same reading is performed also in the case of R-ch.

  The time τ1 and τ2 in the reading process may be generated by software processing of the CPU 10, or the delay time may be set by hardware as shown in FIG. 4 is a pulse generator that generates a pulse at the falling or rising of the word clock LRCLK. 21 is a delay whose delay time is set to τ1, and 22 to 24 are each set to τ2. Delay. From the circuit shown in FIG. 4, a pulse is output after the time τ1 from the fall (or rise) of the word clock LRCLK, and thereafter, the pulse is output three times every time τ2 elapses. These pulses are used as reading pulses for the data signal RDATA.

  Here, another example of the reading timing (sampling point) of the CPU 10 will be described. When the effective bit length (16 bits in the case of FIG. 3) is divided into four as in this embodiment, any timing may be used as long as it is set in each section. For example, it may be a timing between bits as in a timing T1 shown in FIG. This is because “0” data continuation or “1” data continuation is arranged in each section and is not affected by the bit delimiter. Details of the data arrangement will be described later.

  Further, as in the circuit shown in FIG. 4, the reading timing in each section may not be set to an accurate divide-by-4. For example, the intervals may vary as shown in timings T1 to T4 shown in FIG. Therefore, as a method of creating the read timing, for example, the timing that enters each section may be created using the bit clock BCLK. In other words, it may be read at the 2-bit clock BCLK from the start of the frame, and thereafter read at intervals of the 4-bit clock BCLK, or the bit clock so that the reading timing is set in each section even if the intervals vary. The read timing may be set using BCLK. Of course, the read timing can be set in each section without using the bit clock BCLK.

(Operation of the embodiment)
Next, the operation of this embodiment configured as described above will be described. First, the control circuit 1 controls a compressor etc. similarly to the control circuit for general refrigerators. That is, in normal times, the input circuit 2 is not involved in the operation, and the operation is performed only by the control circuit 1.

  Next, a process in which the user rewrites the firmware stored in the flash memory 12 will be described. First, the user sets a compact disc 35 in which new firmware is recorded in the CD player 30. In this case, the firmware is recorded in accordance with the normal compact disc standard, and the sampling rate also conforms to the compact disc standard.

  In the compact disc 35 used in the present embodiment, normal audio data and firmware rewrite data are mixed. As a result, the CD player 30 can reproduce music and audio and output firmware rewriting data. The state of data mixing and the reading process of these data will be described later.

  In FIG. 1, data read from the compact disc 35 is output to the I2S bus by the DIR 20. Here, the data for firmware rewriting recorded on the compact disc 35 is set to have the same value for each section when one frame is divided into eight sections of 4 bits. For example, if the original data to be transferred is in binary display (1001), the first 4 bits of the data signal DA are (1111) as shown in FIG. 5, and so on (0000), (0000). ), (1111).

  Table 1 shown in FIG. 6 shows values that can be taken by 16-bit data of L-ch (or R-ch) in the present embodiment. Table 1 shows 16-bit data in which each row is transferred at one time. As can be seen from Table 1, the same value of 1 or 0 is written in each section divided by 4 bits.

  Table 2 shown on the right side of FIG. 6 corresponds to Table 1, and the first column of Table 2 shows the value of 16-bit data of L-ch (or R-ch) in hexadecimal notation. The second column of Table 2 shows a decimal display, the third column shows a signed decimal display when the most significant bit is a sign bit, and the fourth column shows data read by the CPU 10. Here, the signed decimal representation in the third column corresponds to the signed amplitude of the digital audio data. In other words, the fourth column indicates data embedded in 16-bit data.

  As described above, the CPU 10 recognizes 4-bit data (0000) to (1111) from 16 bits of L-ch by extracting data bit by bit at an appropriate timing within a continuous 4-bit section. . Therefore, 8-bit data is extracted and recognized from 32-bit data of one frame including L-ch and R-ch. Then, by analyzing the data extracted in this way, it is recognized as a command or recognized as firmware data for rewriting.

Here, an example of firmware rewriting processing will be described. In the present embodiment, for example, a series of rewriting is instructed in a format as shown in FIG.
In the example shown in this figure, first, (1) “0x00” is continued for 10 samples or more. (2) After that, “0x55” is arranged as a start identifier, and (3) 6-byte data indicating alphanumeric characters is arranged subsequently. Each 1-byte character string data is, for example, a character string “S”, “T”, “A”, “R”, “T”, “!”. Next, (4) data indicating the number of transmission data in 2 bytes, (5) a predetermined 2-byte command is arranged, and then (6) data for rewriting is continued. Finally, (7) add a 2-byte checksum.

According to the above format, when (1) to (3) are enumerated as data, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 55, “S”, “T ”,“ A ”,“ R ”,“ T ”,“! ”. The data 00 can occur at the beginning and end of the song, but perfectly matches the 56-bit data 55, “S”, “T”, “A”, “R”, “T”, “!” data to appear, since one half of the probability per bit becomes a one probability of 2 ⁵⁶ minutes, it occurs only at about 1/72000 trillion. In other words, it is unlikely that the rewrite command will be erroneously recognized.

  In (4) to (7), since the checksum of the received data can be confirmed, there is no possibility that all of them including this will match.

  As described above, when rewriting is instructed, the rewriting data (6) is rewritten in the flash memory 12. When rewriting the firmware, rewriting software is transferred from the flash memory 12 to the memory 11 and executed.

  In the compact disc 35 according to the present embodiment, audio data and firmware rewriting data are mixed, and the audio signal can be reproduced together with the rewriting of the firmware. Now, consider the noise generated during audio signal playback.

  During the firmware rewriting process described above or separately from the rewriting process, the CD player 30 can always reproduce the audio data. In the embodiment described above, the recording position of the audio data and the firmware rewriting data is different, so that when playing back the position where the audio data is recorded, normal music and voice are reproduced. When reproducing the position where the data for wear rewriting is recorded, the sound that is generated becomes noise. However, the noise generated in this embodiment is small as follows.

  As shown in FIG. 6, the difference between the maximum value and the minimum value of the signed decimal number (corresponding to the amplitude of the audio signal) is “8191”, and “1FFF” when displayed in hexadecimal. The number of bits necessary to indicate this difference is 13 bits. On the other hand, since the L-ch and R-ch data are each composed of 16 bits, it can be seen that the amplitude of the noise component is 3 bits less than the total number of bits (16).

The noise level (hereinafter simply referred to as noise level) with respect to the maximum amplitude of the audio data is represented by x as the number of bits in one section (hereinafter referred to as frequency division bit number).
20 * log (0.5 ^(x-1) ) dB
Therefore, in this embodiment,
20 * log (0.5 ³ ) dB
I.e., -18 dB.

  Thus, the sound is relatively small, and there is no worry that a large signal is suddenly supplied to the headphones or speakers while the firmware is being rewritten. Further, when the user accidentally reproduces the compact disc 35 on which the rewritten data is recorded on another reproducing apparatus, there is no fear that a large signal is supplied to the headphones or the speaker as described above.

  Therefore, even when data is recorded on the compact disc 35 so that voice guidance (such as guidance for firmware rewriting procedures) and firmware rewriting processing are alternately performed, the user is concerned about noise while listening to the guidance. The firmware can be rewritten without doing so.

  As described above, in the present embodiment, the firmware of the control circuit of a home appliance such as a refrigerator can be rewritten using a general CD player without using a dedicated device.

  Further, as shown in FIG. 1, since the DIR 20 and the input terminal IN are only added to the control circuit 1 of a normal home appliance, the configuration is not complicated and can be manufactured at low cost. . In particular, since the DIR and the input terminal are general-purpose parts, the manufacturing cost is extremely low.

  In the embodiment described above, since the data signal RDATA is divided and read, the data signal RDATA can be read sufficiently even if the operation of the CPU 10 is slow.

  A device for rewriting the firmware (or CPU reference data) may be provided separately, and the rewriting process may be performed by a device other than the CPU.

(Other embodiments)
The present invention can be implemented in various modes. An example is shown below.
1. Change of frequency division bit number In the above-described embodiment, the frequency division bit number is 4. However, 8-bit frequency division in which one section is 8 bits may be used, and 16 L-ch and R-ch 16 bits may be used. You may perform 16-bit frequency division which makes all bit data the same value.

Tables 3 and 4 shown in FIG. 7 show the case of 8-bit frequency division, and correspond to Tables 1 and 2 shown in FIG. 6, respectively. As shown in Table 4, the difference between the maximum value and the minimum value of the signed decimal number (corresponding to the amplitude of the audio signal) is “511”, and “1FF” in hexadecimal display. The number of bits necessary to indicate this difference is 9 bits. On the other hand, since the L-ch or R-ch data is composed of 16 bits, the amplitude of the noise component is 7 bits less than that of the audio signal. Therefore, the noise level in this example is
20 * log (0.5 ⁷ ) dB
I.e., -42 dB. In this way, it is a very small sound.

Next, Tables 5 and 6 shown in FIG. 8 show the case of 16-bit frequency division, and correspond to Tables 1 and 2 shown in FIG. As shown in Table 6, the difference between the maximum value and the minimum value of the signed decimal number is only “1”, and only one bit is required to indicate this difference. The noise level in this example is
20 * log (0.5 ¹⁵ ) dB
I.e., -90 dB. In this way, the sound is so small that it can hardly be heard.

  In the examples shown in FIGS. 7 and 8, since the effect of frequency division is greater than that of the above-described embodiment, it is more suitable when a slow CPU is used. The application of the present invention is not limited to the number of bits of one-side channel of one frame shown in the embodiment. The present invention can be applied to various bit numbers such as 16 bits, 24 bits, 32 bits, and 64 bits. In addition, the effective bit length in the total number of bits on one side channel can also be applied to any bit, that is, all the bits on one side channel may be effective bits, or the arbitrary number of bits may be effective bits. Good.

  Next, increasing the number of higher-order bits has the effect of lowering the noise level, so this point will be described. Here, a case where one side channel is 24 bits will be described as an example.

  Tables 7 and 8 shown in FIG. 9 show cases where the number of bits of the channel is 24 bits and the number of divided bits is 4 bits, and correspond to Tables 1 and 2 shown in FIG. As shown in Table 8, the difference between the maximum value and the minimum value of the signed decimal number is “2097151”, and the number of bits necessary to indicate this difference is 21 bits. The noise level in this example is -18 dB.

  On the other hand, Tables 9 and 10 shown in FIG. 10 correspond to Tables 7 and 8 of FIG. 9, but only 4 bits are extracted from the 24 bits of the one-side channel and read. The lower side of the data signal RDATA is divided by a 4-bit section, and the upper side is a 12-bit section. In this way, as shown in Table 10, the difference between the maximum value and the minimum value of the signed decimal number is only “8191”, and the number of bits necessary to indicate this difference is only 13 bits. It can be seen that the noise level in this example is −66 dB, which is significantly reduced compared to the case shown in FIG.

  In order to reduce noise, a method of not using the upper bit of the data signal RDATA (set to 0 from the beginning) is also effective. If 1 bit is not used from the higher order, the sound pressure will be reduced by 1/2 with respect to the original maximum amplitude, because this is the same for noise. FIG. 11 shows the degree of reduction in the sound pressure level of noise when one bit is not used from the top.

2. Simultaneous music playback In the above-described embodiment and other aspects, rewriting was performed using a compact disc 35 in which firmware rewriting data (or reference update data) and audio data were recorded at different positions. However, rewriting can be performed while playing music or the like (music or guidance voice, etc.). For example, when the channel on one side is 16 bits, the lower 8 bits are used as data for rewriting, and the upper 8 bits are used for music reproduction. Of the 16-bit data representing the musical sound, the higher-order side has a great influence on the amplitude. Even if the lower-order bits are used for data rewriting, there is a slight deterioration in sound quality, but there is a slight deterioration in sound quality in the human ear. You can also avoid feeling. Depending on the number of lower bits used for rewriting, there is no problem as long as the number of bits is appropriate. In this case, if the music to be played is a music having the maximum amplitude as much as possible, the effect is great. When the audio data is reproduced at the same time as the firmware rewriting as described above, for example, an explanation voice corresponding to the rewriting process can be recorded, and the operation procedure guidance can be reproduced in synchronization with the rewriting. Note that BGM can be superimposed on the operation procedure guidance.

  Considering the noise in this case, as shown in Table 11 of FIG. 12, the lower 8 bits are noise components. Here, Tables 11 and 12 shown in FIG. 12 correspond to Tables 1 and 2 in FIG. In this case, the difference between the maximum value and the minimum value of the signed decimal number is “255”, and the number of bits necessary to indicate this difference is 8 bits. Accordingly, noise of 8 bits is generated, which is the same as 8 bits used for firmware rewriting and has no noise reduction effect. Note that the noise level is -48 dB.

3. Mode of Rewrite Instruction Command The rewrite instruction method in the above-described embodiment is an example, and there are various other methods. For example, the command or command recognition pattern shown in FIG. 14 is an example in which a pattern in which a maximum value and a minimum value are alternately repeated, which cannot be audio data, is used as a rewrite start command. FIG. 15 is an example in which a pattern in which the maximum value continues for a certain time or longer is used as a rewrite start command. Alternatively, mute (0 data) may be arranged in a predetermined pattern, and if a mute pattern at a predetermined interval can be recognized, it may be determined as a rewrite recognition pattern.

4). Others (a) In the above-described embodiment, a CD player is taken as an example of an apparatus for providing an audio signal of the digital audio standard from the outside. However, the present invention is not limited to this, and a DVD player, MD player, HDD (hard disk) player, memory Various audio devices such as a player can be used.

(B) The above-described embodiment is directed to processing for processing a SPDIF standard digital audio signal. However, in the application of the present invention, a digital signal of other formats may be used. In short, it is only necessary to perform rewriting processing by extracting data at a predetermined timing position in one frame of a predetermined format. Further, the frequency of the word clock LRCLK may be different. For example, it may be 44.1 kHz or 48 kHz.

(C) The present invention is not limited to data read from a recording medium such as a compact disk or DVD, but can be applied to data supplied via a predetermined cable or the Internet, for example.

(D) As shown in FIG. 6 to FIG. 8, various frequency dividing modes are possible. For example, data in a plurality of frequency dividing modes is recorded on a compact disc and data corresponding to the processing speed of the CPU. A rewrite process may be performed by selecting. In this case, if the data indicating the frequency division mode is included as the rewrite instruction command, the CPU can start rewriting when it detects a command that matches its own speed. The same applies to the case where the digital signal is supplied via the Internet or the like.

(E) In the embodiment described above, the control circuit 1 is a circuit that controls the refrigerator. However, the control circuit 1 is not limited to this, and various devices such as air conditioners, televisions, telephones (home appliances, etc.) ) Can be controlled.

(F) The connection between the DIR 20 and the CPU 10 may be made via a switch SW as indicated by a broken line in FIG. In this case, the switch SW is turned on only when the firmware is rewritten. The switch SW may be turned on when the operator operates a switch or the like, or may be turned on by software processing based on a program.

(G) In each of the above-described embodiments, a digital signal having a predetermined format composed of m bits per frame can be read in the m-bit format based on the bit clock BCLK, and is divided by n. It can also be read as a signal. Therefore, it is possible to mix reading and processing a digital signal in an m-bit format and rewriting a program by extracting data as a signal divided by n. Depending on the mode of mixing, time-sharing processing is possible, and simultaneous processing is also possible.

(H) The firmware rewriting data and the audio data may not be mixed in the compact disc 35, and only the firmware rewriting data may be recorded.

(I) Instead of the CPU 10 shown in FIG. 1, a CPU chip having a built-in flash memory or RAM may be used to rewrite the firmware or data in the flash memory or RAM.

(N) Although the I2S standard is used in the embodiment shown in FIG. 1, the present invention is not limited to this standard, and various other formats can be applied.

(Le) The CPU read timing is not limited to the mode shown in the embodiment. For example, as shown in FIG. 16 (a), when the one-side channel is divided into four sections (more accurately, when the effective bits of the one-side channel are divided into four sections) The reading timing may be set, but the reading timing may be set only for the sections 3 and 4 (corresponding to the lower 2 bits) in the four sections as shown in FIG. In this case, the data of “0” or “1” is written in the sections 3 and 4, but any data can be written in the sections 1 and 2. In addition, as shown in FIG. 16C, even if the reading timing is set for each section, the data extracted in sections 1 and 2 are not adopted and ignored, and only the data read in sections 3 and 4 are extracted. It may be adopted as data. In this case, as in the case of FIG. 16B, arbitrary data can be written in the sections 1 and 2.

  Here, the reading timing is summarized as follows. First, the reading timing is a sampling point set in each section when the effective data length in one frame is divided into N sections (in the case of FIG. 16 (A)). Alternatively, as shown in FIG. 16 (W), the read timing is a sampling point set in M sections (M is less than N) when the effective data length in one frame is divided into N sections. is there. Further, as shown in FIG. 16C, analysis or rewrite processing of commands or the like may be performed while ignoring the read extracted data at a specific timing.

(W) In the embodiment described above, the CPU 10 is used. However, a DSP (digital signal processor) may be used to control each part of the apparatus. In short, the present invention can be applied to any processor device that operates based on a program.

(F) In the above-described embodiment, the example in which the input circuit 2 is built in the main body of the electronic device (household refrigerator) has been shown. However, the input circuit 2 is configured as an adapter device separately from the main body. Also good. More specifically, as shown in FIG. 17, the main body side on which the control circuit 1 is provided and the input circuit 2 are separated, and an input terminal IN2 is provided on the main body side, and DIR2 is provided for the input terminal IN2. The output line is configured to be detachably connected. In this case, the input terminal IN2 and the output line of DIR2 may be connected by using a detachable connection terminal such as a plug, a jack, or a connector. With the above configuration, the output side of the DIR 2 and the input terminal IN2 only need to be connected only when rewriting the firmware or the like, so that it does not change from an ordinary electronic device during normal use (for example, an electronic device) If it is a refrigerator, it can be used in substantially the same manner as a general refrigerator).

It is a block diagram which shows the structure of this embodiment. It is a wave form diagram showing a signal contained in an I2S bus in the embodiment. 4 is a timing chart showing timing when data is extracted from a digital audio signal in the embodiment. In the same embodiment, it is a block diagram which shows the circuit example in the case of extracting data extraction timing with a hardware. FIG. 6 is an explanatory diagram showing a processing method when data for rewriting is embedded in the format of a digital audio signal in the embodiment. 6 is a correspondence table showing the contents of a frame when performing 4-bit frequency division in the embodiment. 6 is a correspondence table showing the contents of a frame when 8-bit frequency division is performed in the embodiment. 5 is a correspondence table showing the contents of a frame when performing 16-bit frequency division in the embodiment. 4 is a correspondence table showing the contents of a frame in one aspect of frequency division when one frame is 24 bits in the embodiment. 4 is a correspondence table showing the contents of a frame in one aspect of frequency division when one frame is 24 bits in the embodiment. It is a graph which shows the reduction state of the noise level when not using a high-order bit. 10 is a correspondence table showing the contents of each frame when an audio signal and data for rewriting are mixed in one frame. 12 is a chart showing another example of a rewrite instruction command. It is a wave form diagram which shows the other example of rewriting instruction | command recognition. It is a wave form diagram which shows the other example of rewriting instruction | command recognition. It is a timing chart which shows the other example of reading timing. In the embodiment shown in FIG. 1, it is a block diagram which shows the case where the main body provided with the control circuit 1 and the input circuit 2 are comprised separately.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... CPU (extraction means, rewriting means), 11 ... Memory, 12 ... Flash memory (storage means, memory), 20 ... DIR, 30 ... CD player (external audio device), 35 ... Compact disc (recording medium), IN: Input terminal.

Claims (3)

Storage means for pulp processor device controls the instrumentation置各portion at least one of firmware or data that is used is stored,
An input circuit that converts the data signal receiving digital signals of the digital audio interface standard via the external input terminals from an audio device,
The command for instructing the rewriting of the firmware by the data extracted by the parsing in the dividing position at a predetermined timing in one frame before SL data signal from the input circuit are entered and, rewriting of the firmware The processor device for recognizing business data or reference update data;
In an electronic apparatus, comprising: rewriting means for rewriting at least one of firmware and data in the storage means by the rewriting data or the update data recognized by the processor device ,
The digital signal includes data of a plurality of frequency division forms according to the processing speed of the processor device,
When data indicating a frequency division mode is extracted from the data signal and the processor device recognizes a rewrite instruction command that matches the processing speed of its own as a result of the analysis, a frequency dividing mode corresponding to the processing speed of the self is obtained. Select data and start rewriting by the rewriting means
An electronic device characterized by that .   The electronic device according to claim 1, wherein the processor device further functions as the rewriting unit. The apparatus main body provided with each part controlled by the processor device, the storage means, the rewriting means and the processor device, and the adapter part provided with the input circuit are provided separately, and the input to the apparatus main body is the input claim, characterized in that the circuit a data signal is inputted Lud over data input terminals provided to output, the previous and Kide over data input terminal and the output side of the input circuit is configured to detachably 1 Or the electronic device of 2.

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