JP4826030B2 - Video signal generating apparatus and navigation apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a video signal generation device and the like.
[0002]
[Prior art]
Conventionally, a multi-vision system that is installed in a vehicle and synthesizes (including switching) video for navigation, video showing the status of an air conditioner / audio, etc., video received from a TV broadcast, etc. is known. It has been.
[0003]
For example, as shown in FIG. 3, such a conventional multi-vision system includes a display device 60 that generates a video signal indicating the state of an air conditioner / audio device, etc., and a navigation device 70 that generates a video signal for navigation. And a display device 80 that inputs and synthesizes and displays these video signals and a video signal from a television receiver (not shown).
[0004]
In the display device 60, the CPU 62 writes the display content in the memory 64b based on the state of the air conditioner or the like taken in from an I / O unit (not shown). On the other hand, the display video processing unit 64a generates and outputs a display video signal from the data written in the memory 64b.
[0005]
Similarly, in the navigation device 70, the CPU 72 writes the map data read from the storage device 76 such as a DVD player or a CD player into the memory 74b via the I / O unit 74c. The display video processing unit 74a generates and outputs a navigation video signal from the data written in the memory 74b.
[0006]
The display video signal, the navigation video signal, and the television video signal from the television receiver are output as, for example, analog RGB signals.
The video signal synthesis unit 82 of the display device 80 receives these video signals, selects one video signal from the input video signals according to the state of a switch (not shown) provided in the display device 80, and displays the video signal 84. Or a video signal obtained by processing the input video signal such as enlargement / reduction synthesis is output to the display 84. The display 84 performs display based on the video signal input from the video signal synthesis unit 82.
[0007]
[Problems to be solved by the invention]
The display 84 is composed of, for example, 320 × 240 pixels (hereinafter referred to as CGA), and a color liquid crystal display that receives and displays an analog RGB signal is used. However, for example, 640 × 480 pixels (hereinafter referred to as “VGA”), etc., for the purpose of improving the display content of the navigation device and for reproducing images recorded on a DVD or the like as the storage device 76 with high image quality. High-resolution displays may be used. In this case, it is necessary to control four times as many pixels as in the conventional CGA, and the memory 64b of the display device and the memory 74b of the navigation device require four times the conventional memory. In such a high-resolution display, a digital RGB signal is often used as an input video signal instead of a conventional analog RGB signal. Therefore, the analog RGB television video signal output from the television receiver must be once taken into the memory and converted into a digital RGB signal. Furthermore, since the resolution of the display is higher than the resolution of the television image, it is necessary to perform an enlargement process of the television image, and a memory for that is also required.
[0008]
As described above, in order to cope with a high-resolution display, it is necessary to quadruple the memory capacity of each device as compared with the conventional device or to newly provide a memory. Therefore, there is a problem that costs are increased and miniaturization becomes difficult.
SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal generation device and the like that can be used for a high-resolution display without unnecessarily increasing the memory capacity used to display various videos.
[0009]
[Means for Solving the Problems and Effects of the Invention]
The video signal generating apparatus according to claim 1, which has been made to solve the above-described problems, has a memory in a predetermined block with respect to the video signal generating means for generating the video signal selected by the video signal synthesizing means. Assigned in units.
[0010]
Here, “assignment in units of predetermined blocks” means that the entire memory is divided into a plurality of blocks (areas), and any one or more blocks among them are assigned. For example, the entire memory is divided into first to fourth blocks (parts), the first memory block is assigned to the first video signal generating means, and the second memory is assigned to the second video signal generating means. The third and fourth memory blocks are allocated. In such a case, the video signal generated by the first video signal generation unit and the video signal generated by the second video signal generation unit are synthesized by the video signal synthesis unit and output.
[0011]
Further, for example, the control unit allocates all the first to fourth memory blocks to the third video signal generation unit, and does not perform the allocation to the first and second video signal generation units. The video signal generated by the video signal generation means can also be output.
[0012]
Therefore, a memory block to be accessed can be shared among a plurality of video signal generating means for generating a video signal that does not require output at the same time. As described above, the memory block allocated to the video signal generating unit that does not require output can be allocated to the video signal generating unit that requires output. Therefore, the memory can be used efficiently. That is, at least, it is only necessary to secure the total capacity of the memory blocks allocated to the video signal generation means for generating video signals that need to be output simultaneously.
[0013]
For example, if the conventional configuration shown in FIG. 3 is applied to the above-described VGA display device as it is, when the navigation video signal and the display video signal are switched and displayed, the navigation video signal and the display video signal are displayed. Memory of the total capacity of the memory blocks required to generate each is required. However, according to the first aspect of the present invention, at least one of the capacity of the memory block necessary for generating the navigation video signal and the capacity of the memory block required for generating the display video signal. It is sufficient to prepare the memory capacity (area) of the larger one. Therefore, the required amount of memory can be reduced and the system can be miniaturized.
[0014]
Further, whether or not the video signal is to be output, that is, whether or not the video signal is to be selected, may be determined according to the state of the switch, for example, or may be in a state written in a memory or the like. You may make it determine based on. Further, when a predetermined signal is input, it may be determined according to the signal. For example, the signal or the like may be output from a CPU or a video signal selection unit and controlled.
[0015]
The video signal generating means, for example, as shown in claim 4, rendering the video signal from the external uptake in the memory, may be one for generating a video signal from the data in memory, in memory by C PU ( A video signal may be generated based on the stored data. Various video signals can be used as the video signal captured from the outside described in claim 4 . For example, as shown in claim 5 , it may be a video signal such as a television that requires resolution conversion.
[0016]
Further, as described in claim 2 , by making the memory accessible from the CPU, for example, a program executed by the CPU can be stored, used as a work area when the CPU executes the program, and various data Can be stored.
[0017]
Then, when allocating the memory in this way, as shown in claim 3, it is preferable that the allocation is performed so that the memory can be accessed as a continuous address space from the video signal generating means to be allocated or the CPU. In this way, the video signal generating means can continuously access the data in the memory and can easily generate the video signal. Therefore, the hardware configuration of each video signal generation means can be simplified. Since the CPU can also continuously access the memory without dividing the memory space, it is easy to design a data structure to be stored and to create a program.
[0018]
In this way, the configuration of each part can be simplified, and an unused memory generated by dividing the memory space, a program and hardware for dealing with the divided memory are unnecessary, and the memory capacity to be used Can be reduced. Therefore, the system can be miniaturized.
[0019]
Such a memory and each means may be provided in a chip as shown in claim 6 . In such a chip, the capacity of the memory to be mounted may be determined in advance, and even in such a case, the memory in the chip can be used effectively. In addition, the size can be reduced by using one chip.
[0020]
The video signal generation device described above can be provided in various electronic devices, and the memory of the electronic device can be reduced and the device can be downsized. For example, the navigation apparatus shown in claim 7 can be provided. In such a navigation apparatus, since the memory can be effectively used as described above, the memory capacity can be reduced, and the navigation apparatus can be downsized.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments to which the present invention is applied will be described below with reference to the drawings. Needless to say, the embodiments of the present invention are not limited to the following examples, and can take various forms as long as they belong to the technical scope of the present invention.
[0022]
FIG.1 and FIG.2 is a figure which shows the navigation apparatus 1 of an Example. The navigation device 1 includes an ASIC 10 and a CPU 20 that controls each unit, a storage device 30 that is a DVD player or a CD player, and a display 40.
The display 40 is a color liquid crystal display such as a VGA (800 × 480 pixels, etc.) that receives and displays digital RGB signals. This digital RGB signal, for example, transmits color information of each pixel together with a control signal such as a synchronization signal in parallel as a digital signal using eight signal lines for each of RGB.
[0023]
The ASIC 10 includes an A / D converter 11, a television video signal processing unit 12, a video signal synthesis unit 13, a display video signal processing unit 14, a memory 15 (memory 15 a to d), and an I / O unit 16. Is provided.
The CPU 20 realizes a navigation function, a television display function, and a display display function by executing a program stored in a ROM (not shown). The navigation function inputs the position specifying information from the GPS or the like (not shown) and the position specifying information and the map information from the recording medium set in the storage device 30 via the I / O unit 16, and displays the display information for navigation. It has a function of generating and writing to the memory 15 and displaying a navigation video on the display 40. The television display function is a function for displaying a television image based on a television image signal input from an external television receiver (not shown). The display display function inputs display instruction information output from an audio device or air conditioner (not shown) via a network from the I / O unit 16 to generate display information, and writes the display information in the memory 15. It is a function to display.
[0024]
The CPU 20 controls an output port (not shown) connected to the CPU 20 and controls a signal to each unit connected to the output port. That is, a television display control signal for the address decoder, a data capture control signal for the television video signal processing unit 12, a resolution instruction signal for the display video signal processing unit 14, and a synthesis instruction signal for the video signal synthesis unit 13 are output. Control by writing a value to the port register.
[0025]
The memory 15 is composed of four memory blocks (areas) of the memories 15a to 15d. The address decoder determines which of these memory blocks is allocated to the processing unit according to the state of the television display control signal from the output port of the CPU 20. That is, the address decoder connected to the memory allocates the memory 15a to the addresses i0 to i1 accessed by the television video signal processing unit 12 when the television display control signal is active. Further, the memory 15b is allocated to the addresses j1 to j2 accessed by the display video signal processing unit 14 and the CPU 20, the memory 15c is allocated to the addresses j2 to j3, and the memory 15d is allocated to the addresses j3 to j4.
[0026]
On the other hand, when the television display control signal is not active (inactive), the address decoder assigns all of the memories 15a to 15d to addresses j0 to j4 accessed by the display video signal processing unit 14 and the CPU 20. That is, the addresses j0 to j1 are allocated to the memory 15a, the memory 15b is allocated to the addresses j1 to j2, the memory 15c is allocated to the addresses j2 to j3, and the memory 15d is allocated to the addresses j3 to j4.
[0027]
When the data capture control signal from the output port of the CPU 20 is active, the TV video signal processing unit 12 uses the A / D converter 11 to output an analog RGB signal TV video signal input from an external TV video receiver. Is converted into digital data, and the converted digital data is taken into addresses i0 to i1. Then, the captured data is read out from the addresses i0 to i1, and a digital RGB video signal enlarged n times vertically and m times horizontally (for example, twice vertically and horizontally) is generated and output to the video signal synthesizer 13. On the other hand, when the data capture control signal from the output port of the CPU 20 is not active, the capture of data to the addresses i0 to i1 is stopped.
[0028]
The display video signal processing unit 14 reads out data from a memory area in a range of a predetermined address among the memories assigned to the addresses j0 to j4 and generates a video signal. For example, when the resolution instruction signal from the output port of the CPU 20 is in the high resolution display mode, all of the addresses j0 to j4 are accessed to read data from all the areas of the memories 15a to 15d to generate video signals. Output to the video signal synthesis unit 13. On the other hand, when the resolution instruction signal from the CPU 20 is in the low resolution display mode, the addresses j3 to j4 are accessed, data is read from the area of the memory 15d, a video signal is generated, and output to the video signal synthesis unit 14.
[0029]
The video signal synthesis unit 13 outputs the video signal output from the television video signal processing unit 12 to the display 40 when the synthesis instruction signal is in the television video output mode. On the other hand, when the synthesis instruction signal is in the display video output mode, the video signal output from the display video signal processing unit 12 is output to the display 40. When the synthesis instruction signal is in the video synthesis mode, the video signal from the television video signal processing unit 12 is superimposed on the video signal from the display video signal processing unit 14 and output to the display 40. .
[0030]
The CPU 20 detects a television video display instruction or navigation video display instruction from a user by monitoring the state of an input port connected to a switch or the like. In addition, an input of a display instruction indicating an operation state or the like is detected via a network from an audio device (not shown) or an air conditioner. When these display instructions are detected, the above-described signals are controlled. Accordingly, each unit operates based on the above-described signals, and a video signal to be displayed on the display 40 is generated.
[0031]
For example, when the CPU 20 detects the input of the display instruction of the television image, the CPU 20 activates the television display control signal to the address decoder, activates the data capture control signal to the television image signal processing unit 12, and the display image signal processing unit 14. A value is written to the register of the output port so that the resolution instruction signal is set to the low resolution mode and the synthesis instruction signal to the video signal synthesis unit 13 is set to the television video output mode. Therefore, the address decoder allocates the memory 15a to the addresses i0 to i1 accessed by the TV video signal processing unit 12, and allocates the addresses j1 to j4 accessed by the display video signal processing unit 14 and the CPU 20 to the memories 15b to 15d (see FIG. 1). ). Also, the TV video signal processing unit 12 converts the TV video signal input from the external TV video receiver into digital data by the A / D converter 11 and takes the converted digital data into addresses i0 to i1. That is, the data is taken into the memory 15a. Then, the data fetched into the memory 15 a is read from the addresses i 0 to i 1, and a digital RGB video signal enlarged n times vertically and m times horizontally (for example, twice vertically and horizontally) is generated and output to the video signal synthesizer 13. . Then, the video signal synthesis unit 13 outputs the video signal output from the television video signal processing unit 12 to the display 40. Therefore, a television image is displayed on the display 40, and a television display function can be realized.
[0032]
On the other hand, when the CPU 20 detects the input of the navigation video display instruction, the CPU 20 inactivates the data capture control signal to the television video signal processing unit 12, inactivates the television display control signal to the address decoder, and performs display video signal processing. The resolution instruction signal to the unit 14 is set to the high resolution mode, and the synthesis instruction signal to the video signal synthesis unit 13 is set to the display video output mode. Therefore, the television video signal processing unit 12 stops taking in data, and the address decoder allocates all of the memories 15a to 15d to the addresses j0 to j4 accessed by the display video signal processing unit 14 and the CPU 20 (see FIG. 2). . Then, the CPU 20 inputs information from a position detector such as a GPS and a gyro (not shown) or map data from a recording medium inserted in the storage device 30 via the I / O unit 16, and a map near the current position. The data for displaying the navigation information is written in the memories 15a to 15d assigned to the addresses j0 to j4. Since the resolution instruction signal has a high resolution, the display video signal processing unit 14 generates a video signal from the data at addresses j0 to j4. Further, the video signal synthesis unit 13 outputs the video signal of the navigation video output from the display video signal processing unit 14 to the display 40 because the synthesis instruction signal is in the display video output mode. Accordingly, the navigation video is displayed on the display 40. In this way, a navigation function can be realized.
[0033]
In addition, for example, as described above, a display instruction for a television image is input, and display instruction information indicating an operation state or the like from an audio device or an air conditioner (not shown) is displayed via the network while the television image is being displayed. The CPU 20 generates display information based on the display instruction information, writes the display information in the memory 15d assigned to the addresses j3 to j4, and outputs the synthesis instruction signal to the video signal synthesis unit 13 as video. Switch to composition mode. The display video signal processing unit 14 generates a video signal based on the data in the memory 15d and generates a video signal synthesis unit because the resolution instruction signal is set to the low resolution mode as described above during the display of the TV video. 13 is output. Since the synthesis instruction signal is in the video synthesis mode, the video signal synthesis unit 13 superimposes the video signal from the display video signal processing unit 14 on the video signal from the television video signal processing unit 12 and outputs it to the display 40. . Therefore, the display image is displayed so as to overlap the television image. Therefore, the state of the air conditioner and the audio device can be confirmed while watching the television. That is, a display function can be realized during the display of a television image.
[0034]
On the other hand, when a display instruction is input from the audio device or the air conditioner while the navigation video is displayed as shown in FIG. 2, the CPU 20 generates display information based on the display instruction information, and the memories 15a to 15a. The navigation video data written in 15d is overwritten. Therefore, even when the navigation image is displayed, the display image can be displayed.
[0035]
In this way, the memory 15 can be divided and the allocation (map destination) of the memory 15 can be changed according to the usage pattern. Therefore, it is not necessary to prepare the memory 15 separately for each display. That is, when the conventional apparatus configuration of FIG. 3 is applied to the display of the display 40 of FIG. 1, at least a memory corresponding to the memories 15a to 15d for displaying a high-resolution navigation video, and a TV video It is necessary to prepare a memory corresponding to the memory 15a for display and a memory corresponding to the memory 15d for display display. On the other hand, in this embodiment, only the memories 15a to 15d need be prepared. In addition to these, a work memory area of the CPU 20 can also be secured during the display of a television image.
[0036]
As described above, according to the navigation device 1 of the present embodiment, it is not necessary to provide separate memories for realizing the TV image display function, the navigation function, and the display function, and these functions are realized with a small memory capacity. be able to. Moreover, the memory 15a and the memories 15b to 15d are allocated as addresses j0 to j4 so as to be accessible as a continuous memory space. Therefore, when the CPU writes high-resolution navigation video, it can be written continuously, and the software can be simplified. The display video signal processing unit 14 can also continuously access the memories 15a to 15d to generate video signals, thereby simplifying the hardware.
[0037]
In this embodiment, the video signal input to the display 40, that is, the video signal output from the video signal synthesizer 13 is a digital RGB signal of the above-described system. Good.
In the present embodiment, the memory 15 is divided into four parts of the memories 15a to 15d and assigned to each part. However, this division can be freely determined. That is, it may not be four parts, and it may be divided into a plurality of parts (blocks). In addition, for example, one part may be allocated as a work area for executing a program in the CPU 20, and the remaining three parts may be allocated for generating a navigation video, or one part for generating a TV video. Allocation and the remaining three copies may be allocated for generation of navigation video.
[0038]
In addition, although the control of each unit is performed by the CPU, each signal may be directly generated from a switch or the like.
In this embodiment, the address decoder changes the address of the memory 15a depending on the state of the television display control signal. However, the address decoder overlaps with the address accessed by the television video signal processing unit 12 and the display video signal processing unit 14. It is also possible to automatically select the memory to be allocated according to the address accessed by the address decoder. For example, the memory 15a is assigned when the address i0 to i1 is accessed, and the memory 15a is also assigned when the address j0 to j1 is accessed. Addresses i0 to i1 and addresses j0 to j1 are assigned so as not to overlap. Then, in response to an instruction from a switch or the like, one of fetching the TV video data addresses i0 to i1 of the TV video signal processing unit 12 and writing to the navigation video addresses j0 to j4 of the CPU 20 is performed. The CPU 20 may be controlled at the same time.
[0039]
In this embodiment, the CPU 20 and the ASIC 10 correspond to a video signal generation device. The TV video signal processing unit 12 and the display video signal processing unit 14 correspond to a video signal generation unit, and the video signal synthesis unit 13 corresponds to a video signal synthesis unit. An address decoder corresponds to the control means. The ASIC 10 corresponds to a chip.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a memory allocation state when a television image is displayed in a navigation device according to an embodiment.
FIG. 2 is a diagram for explaining a memory allocation state when a navigation video is displayed in the navigation device of the embodiment.
FIG. 3 is a configuration diagram of a multi-vision system including a conventional navigation device.
[Explanation of symbols]
1 ... Navigation device 10 ... ASIC
DESCRIPTION OF SYMBOLS 11 ... A / D converter 12 ... Television video signal processing part 13 ... Video signal synthetic | combination part 14 ... Display video signal processing part 14 ... Video signal synthetic | combination part 15a-15d ... Memory 16 ... I / O part 20 ... CPU
30 ... Storage device 40 ... Display 60 ... Display device 64 ... Display ASIC
64a ... Display image processing unit 64b ... Memory 70 ... Navigation device 72 ... CPU
74 ... Navi ASIC 74a ... Display video processing unit 74b ... Memory 74c ... I / O unit 76 ... Storage device 80 ... Display device 82 ... Video signal synthesis unit 84 ... Display

Claims (7)

A plurality of video signal generating means for generating a video signal based on the data stored in the memory;
In a video signal generating apparatus comprising: a video signal synthesizing unit that selects one or more video signals from the plurality of video signals and generates a video signal to be output based on the selected video signal. ,
The video signal generating means for generating a video signal selected by the video signal combining unit, a memory required to generate a video signal is divided into predetermined block units, which is the divided Control means for assigning one of the memories to be accessible from the plurality of video signal generating means ;
At least one video signal generation unit among the plurality of video signal generation units stores data in the memory allocated by the control unit based on an instruction from the CPU, and video based on the data stored in the memory A video signal generating apparatus for generating a signal. A plurality of video signal generating means for generating a video signal based on the data stored in the memory;
In a video signal generating apparatus comprising: a video signal synthesizing unit that selects one or more video signals from the plurality of video signals and generates a video signal to be output based on the selected video signal. ,
In contrast to the video signal generating means for generating the video signal to be selected by the video signal synthesizing means, the memory necessary for generating the video signal is divided into predetermined blocks, and the divided Control means for assigning one of the memories to be accessible from the plurality of video signal generating means;
The video signal generation device according to claim 1, wherein the control means has a function of allocating the block of the memory so as to be accessible from the CPU . A plurality of video signal generating means for generating a video signal based on the data stored in the memory;
In a video signal generating apparatus comprising: a video signal synthesizing unit that selects one or more video signals from the plurality of video signals and generates a video signal to be output based on the selected video signal. ,
The video signal generating means for generating the video signal to be selected by the video signal synthesizing means can be accessed from the video signal generating means in a predetermined block unit for the memory necessary for generating the video signal. Control means to be assigned to
When the control means assigns a plurality of blocks of the memory to one video signal generation means or CPU, the control means assigns the video signal generation means or CPU so that they can be accessed at successive addresses. apparatus. In the video signal generating device according to any one of claims 1 to 3 ,
At least one video signal generating means out of the plurality of video signal generating means captures an external video signal as data into the memory allocated by the control means, and video based on the data captured in the memory A video signal generating apparatus for generating a signal. The video signal generation device according to claim 4 ,
The video signal generating apparatus according to claim 1, wherein the external video signal is a video signal that requires resolution conversion . In the video signal generating device according to any one of claims 1 to 5 ,
Each means in the said claim is provided in the chip | tip which mounts the said memory, The video signal generator characterized by the above-mentioned . A navigation device comprising the video signal generation device according to any one of claims 1 to 6.

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