JPH08292750A - Frame memory control method - Google Patents

Abstract

PURPOSE: To display perfect plural pieces of, picture information while keeping the amount of hardware increase to a minimum when plural pieces of coded picture information are received, decoded and simultaneously displayed on a display. CONSTITUTION: Two surface display frame memories 11 and 12, which temporarily store and display decoded picture information, are logically divided into plural regions. A flag 13 is provided to show which of memories 11 or 12 should be displayed for every region. Then, a reading is conducted for a writing and a displaying against the memories 11 and 12 and a switching is performed for every region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory management method for split type video display. In particular, it is effective when receiving a plurality of encoded video information, decoding it, and displaying it simultaneously on a display, such as in a multipoint video conference and a multipoint video surveillance.

[0002]

2. Description of the Related Art A general form for decoding and displaying encoded video information is shown in FIG. The video information 24 input by the video input means 31 such as a camera is converted into the video coded information 25 by the video encoder 34, passed through the communication or storage means 41, and then the video decoder 51.
Is decoded into video information 24 '. The decoded information is temporarily stored in the display frame memories 53 and 54 and then displayed at the display timing of the display 33.

The timing at which the video information 24 'is output from the video decoder 51 is often different from the display timing on the display 33. If a video frame in the middle of decoding is displayed as it is, a new video frame is displayed at the bottom of the screen. Since half-finished images that are not displayed will be displayed, the display frame memories 53 and 54 on two sides, the writing switch 52, and the display interlocking with the writing switch 52 are displayed in realizing the image device. It has a switch 55.

While the write switch 52 is writing the video information 24 'decoded by the video decoder 51 into the display frame memory 53 on the first surface, the display switch 5
5, the contents of the display frame memory 54 on the second surface which is not being written are displayed on the display 33 (in a broad sense, the changeover switch and the display frame memory may be collectively referred to as a video decoder. , In this specification,
Capture the video decoder in a narrow sense). ITU-T Recommendation H. This method is generally used even in the videophone / videoconference device using the ISDN line defined as 320.

A plurality of H.264. A multipoint video conference using 320 terminals will be described. FIG. 4 is a diagram showing a conventional multi-point video conference apparatus for simultaneously displaying images at a plurality of points.

As shown in FIG. 4, the image information 24a to 24d at the points A to D input by the image inputting means 31a to 31d such as a camera are H.D. 320 terminal 32a
Video encoding information 25 by the video encoder included in
It becomes a-d. The multipoint video conference control device 50 which receives these pieces of information via the communication network 4 has video decoders 51a to 51d and display frame memories 53a to 53d corresponding to the respective points. A plurality of pieces of video information from points A to D decoded by the video decoders 51a to 51d are reduced and combined as one piece of video information using the video information multiplexing unit 56, and then encoded by the video encoder 57. Copy the video coded information 25e, A ~
Return to point D. H. 320 terminals 32a-d
Then, this is decoded and the video information 24e is displayed on the displays 33a to 33d. Here, H. 320 terminal 32a
Reference characters d to d each include a video encoder, a video decoder, a display frame memory, a writing switch, and a display switch.

Since the conventional multipoint video conference control apparatus 50 has the above-mentioned configuration, it is necessary to have as many video decoders as the number of points to be simultaneously displayed and a display frame memory having twice the number of points. .

Therefore, in order to receive the images at the four points, four image decoders are required, which is expensive. There are three reasons for adopting such a configuration. The first reason is the restriction on the communication path. H. In N-ISDN, which is targeted for 320 terminals, a general terminal has only two B channels. Therefore, unless a special device such as a multipoint video conference controller is used, video coded information from a plurality of points can be simultaneously transmitted. That is, it is impossible to set a communication path for receiving.

The second reason is that the video decoder is not configured to simultaneously decode a plurality of videos even though the video from a plurality of points can be received at the same time. Third
The reason is that the display frame memory is not configured to display multiple images that are sent asynchronously.

The first reason is that future B-ISD
In ATM (Asynchronous Transfer Mode) adopted in N, even if a physical line is a pair of optical fibers, it is possible to set a large number of virtual channels VC, so that a mesh form is formed between a plurality of terminals. A virtual channel, which is a communication channel, can be set, and the terminal can receive video coded information from multiple points at the same time, which is expected to be solved.

The second reason is likely to be solved as follows. Video coding algorithm used in the B-ISDN era ITU-T Recommendation H.264 262
The so-called MPEG2 video can encode and decode various video frame sizes. Therefore, if the information from each point is encoded in advance with a small frame size to reduce the decoding processing amount per video, as shown in FIG. 5, the video decoder 59 is operated in a time sharing operation and the hardware is operated. It is considered that a single video decoder 59 can decode a plurality of videos.

However, as to the third reason, there is still no sufficient technique for solving it. In the conventional display frame memory management method, since the timings of the video frames included in the video coding information from the respective points do not match, as shown in FIG. , 54, 53-1, 54-1 for point A, 53-2, 54-2, C for point B, respectively
Even if the areas 53-3 and 54-3 and the area are separately used, the write switch 52 and the display switch 5 are used.
Since 5 operates only in video frame memory units,
For example, if switching is performed at the time when the writing of the video frame of the video information at the point A is completed, the decoding and writing of the video frames at the other points B and C are completed only halfway as shown on the display screen 58. It will be displayed in a state where it does not exist. That is, with the conventional technique, half-finished video is displayed during decoding and writing.

[0013]

SUMMARY OF THE INVENTION According to the present invention, when a video decoder has a processing capability of decoding a plurality of video coded information, a plurality of video information can be simultaneously processed with a minimum increase in hardware. Intended for display.

[0014]

There are two display frame memories for temporarily storing and displaying the decoded video information, and these display frame memories are logically divided into two.
By dividing into two or more areas, and having a flag for indicating which frame memory should be displayed for each of the divided areas, it is possible to selectively select from two display frame memories for each area. To display.

[0015]

When the respective areas of the divided display frame memory are allocated for the display of specific video information by using the above means and the video frame size of one video information does not fit within one area, Assigns a plurality of areas to the video information. Until the writing of one video frame of video information to the display frame memory is completed, the display flag corresponding to the area of the other display frame memory is set. This prevents the video frame being written from being displayed.

[0016]

EXAMPLE An example of the present invention will be described with reference to FIG.
In this embodiment, the display frame memories R1, R2 and R are used.
It has a display frame memory flag 13 indicating which of the two display frame memories 11 and 12 corresponding to the four areas is managed by being divided into four areas. A video decoder, which decodes video from multiple points by time sharing, uses the area R1 and area R3
The area R2 is allocated for the image from the point B, the area R2 is allocated for the image from the point C, and the area R4 is allocated for the image from the point C.

The video decoder or the system control unit for managing the video decoder and the display frame memory flag 13 initializes the display frame memory flag 13 to 0 at the time of system start-up, and then 1 video of the video at the specific point. When the decoding of the frame is completed, the display frame memory flag rewriting signal 23 for adding 1 to the display frame memory flag 13 of the corresponding area is sent. Since the display frame memory flag 13 takes only values of 0 and 1, by this procedure, when the decoding / writing of the video frame is completed for each area of the display frame memories 11 and 12, the display frame memory flag 13 is Are rewritten in the order of 0 → 1 → 0 → 1. The regions R1 and R3 are rewritten at the same time because they are assigned to a single image.

The write switch 14 receives the decoded video information 21a to 21c from the video decoder, and
Address information 22 indicating which position in the display frame memory to write this video information is received from the video decoder or the system control unit, and the display frame memory flag 13 corresponding to this address information 22 is referred to to display the frame memory 11 for display. , 12 to be written on.

The selection of the display frame memory surface for writing depends on how a plurality of pieces of video information are sent from the video decoder in an interleaved manner. on the other hand,
The display switch 15 causes, for each of the regions R1 to R4 of the display frame memories 11 and 12 which are divided and managed, the display frame memory surface opposite to the one in which writing is performed to be selected for display. As a result, the display screen 16 always displays a normal image in which writing has been completed in any area. In the example of FIG. 1, the regions R1, R3 and R4 are
The first display frame memory 11 is displayed, and the area R2 is displayed.
Displays the second display frame memory 12.

FIG. 2 shows a configuration example of a multipoint video conference apparatus to which the present invention is applied. Multipoint video conference control device 10
Then, the system control unit 17 initializes the display frame memory flag 13 to 0. The image information 24a to 24d of the points A to D input by the image inputting means 31a to 31d such as a camera is the H.D. 320 terminal 32a
Video encoding information 25 by the video encoder included in
It becomes a-d. The video coded information 25a to 25d are multiplexed and sent to the multipoint video conference control device 10 via the communication network 4.

In the multipoint video conference control device 10 that has received these information, the video decoder 18 decodes the video coded information 25a to 25d from each point, and the write switch 14 decodes the video decoder 18 in the video decoder 18. A-
The video information 21a to 21d at the point D and the address information indicating where to write it are received, and the display frame memory flag 13 corresponding to this address information is referred to which surface of the display frame memories 11 and 12 is displayed. Decide whether to write video information.

On the other hand, the display switch 15 selects the display frame memories 11 and 12, which are opposite to the ones in which writing is performed, for each area which is divided and managed, and the writing is completed normally. The image is displayed on the display screen 16. Further, this video information is encoded by the video encoder 19 and returned to each point as the video encoded information 26. H. The 320 terminals 32a to 32d respectively decode the video encoded information 26 and display the decoded video information 27 on the displays 33a to 33d.

[0023]

According to the present invention, the display frame memory is divided into a plurality of areas, the display frame memory flags corresponding to the respective areas are provided, and the write switch and the display switch refer to the display frame memory flags. With a simple structure that allows switching, simultaneous display of a plurality of images, which would increase hardware in the conventional technology, can be realized with less hardware.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an example of the present invention.

FIG. 2 is a diagram showing a configuration example of a multipoint video conference apparatus to which the present invention is applied.

FIG. 3 is a diagram illustrating the principles of encoding / decoding and display of video information.

FIG. 4 is a diagram showing an example of a conventional multipoint video conference apparatus.

FIG. 5 is a diagram illustrating a time sharing operation of a video decoder.

FIG. 6 is a diagram for explaining display of a plurality of images in the related art.

[Explanation of symbols]

 11 Display Frame Memory 11-1 A Point Display Frame Memory 11-2 B Point Display Frame Memory 11-3 C Point Display Frame Memory 12 Display Frame Memory 12-1 A Point Display Frame Memory 12-2 Point B display frame memory 12-3 Point C display frame memory 13 Display frame memory flag 14 Write switch 15 Display switch 16 Display screen 21a-c Video information 22 Address information 23 Display frame memory flag rewriting signal

Claims (1)

[Claims] 1. A display for temporarily storing the decoded video information in synchronization with the display in a device for simultaneously displaying the plurality of encoded video information on a display after decoding the video information. Frame memory for 2
It has two faces and the display frame memories are logically 2
By dividing the display frame memory into two or more areas, and having a flag for indicating which of the two display frame memories should be displayed for each divided area A frame memory management method characterized in that it can be displayed as a single display frame memory virtually by combining the regions selectively.