JP4780826B2 - Method for manufacturing electro-optical device - Google Patents

Description

【００６９】
ここでＱはＮ又はＣ−Ｒ（炭素鎖）であり、Ｍは金属、金属酸化物又は金属ハロゲン化物であり、Ｒは水素、アルキル、アラルキル、アリル又はアルカリルであり、Ｔ１、Ｔ２は水素、アルキル又はハロゲンのような置換基を含む不飽和六員環である。
【００７０】
また、正孔輸送層としての有機材料は芳香族第三アミンを用いることができ、好ましくは次のような一般式で表されるテトラアリルジアミンを含む。
【００７１】
【化２】

【００７２】
ここでＡｒｅはアリレン群であり、ｎは１から４の整数であり、Ａｒ、Ｒ₇、Ｒ₈、Ｒ₉はそれぞれ選択されたアリル群である。
【００７３】
また、ＥＬ層、電子輸送層又は電子注入層としての有機材料は金属オキシノイド化合物を用いることができる。金属オキシノイド化合物としては以下のような一般式で表されるものを用いれば良い。
【００７４】
【化３】

【００７５】
ここでＲ₂−Ｒ₇は置き換え可能であり、次のような金属オキシノイド化合物を用いることもできる。
【００７６】
【化４】

【００７７】
ここでＲ₂−Ｒ₇は上述の定義によるものであり、Ｌ₁−Ｌ₅は１から１２の炭素元素を含む炭水化物群であり、Ｌ₁、Ｌ₂又はＬ₂、Ｌ₃は共にベンゾ環を形成することができる。また、次のような金属オキシノイド化合物でも良い。
【００７８】
【化５】

【００７９】
ここでＲ₂−Ｒ₆は置き換え可能である。このように有機ＥＬ材料としては有機リガンドを有する配位化合物を含む。但し、以上の例は本発明のＥＬ材料として用いることのできる有機ＥＬ材料の一例であって、これに限定する必要はまったくない。
【００８０】
また、本発明ではＥＬ層の形成方法としてインクジェット方式を用いるため、好ましいＥＬ材料としてはポリマー系材料が多い。代表的なポリマー系材料としては、ポリパラフェニレンビニレン（ＰＰＶ）系やポリフルオレン系などの高分子材料が挙げられる。カラー化するには、例えば、赤色発光材料にはシアノポリフェニレンビニレン、緑色発光材料にはポリフェニレンビニレン、青色発光材料にはポリフェニレンビニレン及びポリアルキルフェニレンが好ましい。
【００８１】
但し、以上の例は本発明のＥＬ材料として用いることのできる有機ＥＬ材料の一例であって、これに限定する必要はまったくない。インクジェット法に使用できる有機ＥＬ材料については、特開平１０−０１２３７７号公報に記載されている材料を全て引用することができる。
【００８２】
なお、インクジェット方式はバブルジェット方式（サーマルインクジェット方式ともいう）とピエゾ方式とに大別されるが、本発明を実施するにはピエゾ方式が望ましい。
【００８３】
また、実際に画素電極上にＥＬ材料を塗布するときの形状は、実施形態１で示したようにストライプ状或いは複数のドットを連続させて長円状または長方形状に形成する。分離層１０１はインクジェット方式でＥＬ層を形成するに当たり隣接するＥＬ層が相互に混合しないための機能を有している。
【００８４】
カラー表示を行うには、図６で示すように赤色発光のＥＬ層４７Ｒ、緑色発光のＥＬ層４７Ｇ、青色発光のＥＬ層４７Ｂを形成する。このとき、それぞれのＥＬ層を順次形成しても良いし、赤、緑、青に対応するＥＬ層を同時に形成しても良い。また、ＥＬ形成溶液に含まれる溶媒を除去するためにベーク（焼成）処理が必要である。このベーク処理は全てのＥＬ層を形成した後で行っても良いし、各色のＥＬ層が形成し終えた時点で個別に行っても良い。このようにして、ＥＬ層の厚さを５０〜２５０ｎｍの厚さに形成する。
【００８５】
図２１は画素部における構成を説明するものであり、ストライプ状または長円状或いは長方形状に形成されたＥＬ層に複数の画素電極が形成されている様子を示している。図２１（Ａ）では異なる色で発光するＥＬ層１７０２ａ、１７０２ｂに対しそれぞれ複数の画素電極が設けられている。各画素電極にはスイッチング用ＴＦＴと電流制御用ＴＦＴの２つのＴＦＴが接続されている。またＥＬ層１７０２ａと１７０２ｂは分離層１７０１により分離されている。マルチカラー表示するには、画素電極１７０３ａと１７０３ｂを一組として一つの画素１７１０ａを形成する。同様に画素１７１０ｂを隣に設けるとき、その間隔をＤとするとその値はＥＬ層の厚さの５〜１０倍とする。即ち２５０〜２５００ｎｍとする。
【００８６】
図２１（Ｂ）は他の構成例を示すものであり、例えば、赤、緑、青といった様に異なる色で発光するＥＬ層１７０５ａ、１７０５ｂ、１７０５ｃに対しそれぞれ複数の画素電極が設けられている。これらのＥＬ層は分離層１７０４で分離されている。マルチカラー或いはＲＧＢフルカラー表示するには、画素電極１７０６ａ、１７０６ｂ、１７０６ｃを一組として一つの画素１７２０ａを形成する。同様に画素１７１０ｂを隣に設けるとき、その間隔をＤとすると、やはりその値はＥＬ層の厚さの５〜１０倍とする。即ち２５０〜２５００ｎｍとする。このようにすることで画像表示を鮮明なものとすることができる。
【００８７】
また、ＥＬ層４７を形成する際、処理雰囲気は極力水分の少ない乾燥雰囲気とし、不活性ガス中で行うことが望ましい。ＥＬ層は水分や酸素の存在によって容易に劣化してしまうため、形成する際は極力このような要因を排除しておく必要がある。例えば、乾燥窒素雰囲気、乾燥アルゴン雰囲気等が好ましい。
【００８８】
以上のようにしてＥＬ層４７をインクジェット方式により形成したら、次に陰極４８、補助電極４９を形成する。本明細書中では、画素電極（陽極）、ＥＬ層及び陰極で形成される発光素子をＥＬ素子と呼ぶ。
【００８９】
陰極４８は仕事関数の小さいマグネシウム（Ｍｇ）、リチウム（Ｌｉ）若しくはカルシウム（Ｃａ）を含む材料を用いる。好ましくはＭｇＡｇ（ＭｇとＡｌをＭｇ：Ａｇ＝１０：１で混合した材料）でなる電極を用いれば良い。他にもＭｇＡｇＡｌ電極、ＬｉＡｌ電極、また、ＬｉＦＡｌ電極が挙げられる。また、補助電極４９は陰極４８を外部の水分等から保護膜するために設けられる電極であり、アルミニウム（Ａｌ）若しくは銀（Ａｇ）を含む材料が用いられる。この補助電極４８には放熱効果もある。
【００９０】
なお、ＥＬ層４７及び陰極４８は大気解放せずに乾燥された不活性雰囲気中にて連続的に形成することが望ましい。これはＥＬ層として有機材料を用いる場合、水分に非常に弱いため、大気解放した時の吸湿を避けるためである。さらに、ＥＬ層４７及び陰極４８だけでなく、その上の補助電極４９まで連続形成するとさらに良い。
【００９１】
また、第３パッシベーション膜５０の膜厚は１０ｎｍ〜１μm（好ましくは２００〜５００ｎｍ）とすれば良い。第３パッシベーション膜５０を設ける目的は、ＥＬ層４７を水分から保護する目的が主であるが、第２パッシベーション膜４５と同様に放熱効果をもたせても良い。従って、形成材料としては第１パッシベーション膜４１と同様のものを用いることができる。但し、ＥＬ層４７として有機材料を用いる場合、酸素との結合により劣化する可能性があるので、酸素を放出しやすい絶縁膜は用いないことが望ましい。
【００９２】
また、上述のようにＥＬ層は熱に弱いので、なるべく低温（好ましくは室温から１２０℃までの温度範囲）で成膜するのが望ましい。従って、プラズマＣＶＤ法、スパッタ法、真空蒸着法、イオンプレーティング法又は溶液塗布法（スピンコーティング法）が望ましい成膜方法と言える。
【００９３】
このように、第２パッシベーション膜４５を設けるだけでも十分にＥＬ素子の劣化を抑制することはできるが、さらに好ましくはＥＬ素子を第２パッシベーション膜４５及び第２パッシベーション膜５０というようにＥＬ素子を挟んで形成された二層の絶縁膜によって囲み、ＥＬ層への水分、酸素の侵入を防ぎ、ＥＬ層からのアルカリ金属の拡散を防ぎ、ＥＬ層への熱の蓄積を防ぐ。その結果、ＥＬ層の劣化がさらに抑制されて信頼性の高いＥＬ表示装置が得られる。
【００９４】
また、本発明のＥＬ表示装置は図５のような構造の画素からなる画素部を有し、画素内において機能に応じて構造の異なるＴＦＴが配置されている。これによりオフ電流値の十分に低いスイッチング用ＴＦＴと、ホットキャリア注入に強い電流制御用ＴＦＴとが同じ画素内に形成でき、高い信頼性を有し、且つ、良好な画像表示が可能な（動作性能の高い）ＥＬ表示装置が得られる。
【００９５】
なお、図５の画素構造においてスイッチング用ＴＦＴとしてマルチゲート構造のＴＦＴを用いているが、ＬＤＤ領域の配置等の構成に関しては図１の構成に限定する必要はない。以上の構成でなる本発明について、以下に示す実施例でもってさらに詳細な説明を行うこととする。
【００９６】
【実施例】
[実施例１]
本発明の実施例について図７〜図９を用いて説明する。ここでは、画素部とその周辺に設けられる駆動回路部のＴＦＴを同時に作製する方法について説明する。但し、説明を簡単にするために、駆動回路に関しては基本回路であるＣＭＯＳ回路を図示することとする。
【００９７】
まず、図７（Ａ）に示すように、ガラス基板３００上に下地膜３０１を３００ｎｍの厚さに形成する。本実施例では下地膜３０２として窒化酸化珪素膜を積層して用いる。この時、ガラス基板３００に接する方の窒素濃度を１０〜２５ｗｔ％としておくと良い。
【００９８】
また、下地膜３０１の一部として、図５に示した第１パッシベーション膜４１と同様の材料からなる絶縁膜を設けることは有効である。電流制御用ＴＦＴは大電流を流すことになるので発熱しやすく、なるべく近いところに放熱効果のある絶縁膜を設けておくことは有効である。
【００９９】
次に下地膜３０１の上に５０ｎｍの厚さの非晶質珪素膜（図示せず））を公知の成膜法で形成する。なお、非晶質珪素膜に限定する必要はなく、非晶質構造を含む半導体膜（微結晶半導体膜を含む）であれば良い。さらに非晶質シリコンゲルマニウム膜などの非晶質構造を含む化合物半導体膜でも良い。また、膜厚は２０〜１００ｎｍの厚さであれば良い。
【０１００】
そして、公知の技術により非晶質珪素膜を結晶化し、結晶質珪素膜（多結晶シリコン膜若しくはポリシリコン膜ともいう）３０２を形成する。公知の結晶化方法としては、電熱炉を使用した熱アニール法、レーザー光を用いたレーザーアニール法、赤外光を用いたランプアニール法がある。本実施例では、ＸｅＣｌガスを用いたエキシマレーザー光を用いたレーザーアニール法で結晶化する。
【０１０１】
なお、本実施例では線状に加工したパルス発振型のエキシマレーザー光を用いるが、矩形であっても良いし、連続発振型のアルゴンレーザー光や連続発振型のエキシマレーザー光を用いることもできる。また、レーザー光の光源はエキシマレーザーに限定されるものではなく、ＹＡＧレーザーの第２高調波或いは第３高調波を用いても良い。
【０１０２】
本実施例では結晶質珪素膜をＴＦＴの活性層として用いるが、非晶質珪素膜を用いることも可能である。しかし、電流制御用ＴＦＴは大電流を流す必要性があるため、電流を流しやすい結晶質珪素膜を用いた方が有利である。
【０１０３】
なお、オフ電流を低減する必要のあるスイッチング用ＴＦＴの活性層を非晶質珪素膜で形成し、電流制御用ＴＦＴの活性層を結晶質珪素膜で形成することは有効である。非晶質珪素膜はキャリア移動度が低いため電流を流しにくくオフ電流が流れにくい。即ち、電流を流しにくい非晶質珪素膜と電流を流しやすい結晶質珪素膜の両者の利点を生かすことができる。
【０１０４】
次に、図７（Ｂ）に示すように、結晶質珪素膜３０２上に酸化珪素膜でなる保護膜３０３を１３０ｎｍの厚さに形成する。この厚さは１００〜２００ｎｍ（好ましくは１３０〜１７０ｎｍ）の範囲で選べば良い。また、珪素を含む絶縁膜であれば他の膜でも良い。この保護膜３０３は不純物を添加する際に結晶質珪素膜が直接プラズマに曝されないようにするためと、微妙な濃度制御を可能にするために設ける。
【０１０５】
そして、その上にレジストマスク３０４a、３０４bを形成し、保護膜３０３を介してｎ型を付与する不純物元素（以下、ｎ型不純物元素という）を添加する。なお、ｎ型不純物元素としては、代表的には１５族に属する元素、典型的にはリン又は砒素を用いることができる。なお、本実施例ではフォスフィン（ＰＨ₃）を質量分離しないでプラズマ励起したプラズマドーピング法を用い、リンを１×１０¹⁸atoms/cm³の濃度で添加する。勿論、質量分離を行うイオンインプランテーション法を用いても良い。
【０１０６】
この工程により形成されるｎ型不純物領域３０５、３０６には、ｎ型不純物元素が２×１０¹⁶〜５×１０¹⁹atoms/cm³（代表的には５×１０¹⁷〜５×１０¹⁸atoms/cm³）の濃度で含まれるようにドーズ量を調節する。
【０１０７】
次に、図７（Ｃ）に示すように、保護膜３０３を除去し、添加した１５族に属する元素の活性化を行う。活性化手段は公知の技術を用いれば良いが、本実施例ではエキシマレーザー光の照射により活性化する。勿論、パルス発振型でも連続発振型でも良いし、エキシマレーザー光に限定する必要はない。但し、添加された不純物元素の活性化が目的であるので、結晶質珪素膜が溶融しない程度のエネルギーで照射することが好ましい。なお、保護膜３０３をつけたままレーザー光を照射しても良い。尚、このレーザー光による不純物元素の活性化に際して、熱処理による活性化を併用しても構わない。熱処理による活性化を行う場合は、基板の耐熱性を考慮して４５０〜５５０℃程度の熱処理を行えば良い。
【０１０８】
この工程によりｎ型不純物領域３０５、３０６の端部、即ち、ｎ型不純物領域３０５、３０６の周囲に存在するｎ型不純物元素を添加していない領域との境界部（接合部）が明確になる。このことは、後にＴＦＴが完成した時点において、ＬＤＤ領域とチャネル形成領域とが非常に良好な接合部を形成しうることを意味する。
【０１０９】
次に、図７（Ｄ）に示すように、結晶質珪素膜の不要な部分を除去して、島状の半導体膜（以下、活性層という）３０７〜３１０を形成する。
【０１１０】
次に、図７（Ｅ）に示すように、活性層３０７〜３１０を覆ってゲート絶縁膜３１１を形成する。ゲート絶縁膜３１１としては、１０〜２００ｎｍ、好ましくは５０〜１５０ｎｍの厚さの珪素を含む絶縁膜を用いれば良い。これは単層構造でも積層構造でも良い。本実施例では１１０ｎｍ厚の窒化酸化珪素膜を用いる。
【０１１１】
次に、２００〜４００ｎｍ厚の導電膜を形成し、パターニングしてゲート電極３１２〜３１６を形成する。なお、本実施例ではゲート電極と、ゲート電極に電気的に接続された引き回しのための配線（以下、ゲート配線という）とを別の材料で形成する。具体的にはゲート電極よりも低抵抗な材料をゲート配線として用いる。これは、ゲート電極としては微細加工が可能な材料を用い、ゲート配線には微細加工はできなくとも配線抵抗が小さい材料を用いるためである。勿論、ゲート電極とゲート配線とを同一材料で形成してしまっても構わない。
【０１１２】
また、ゲート電極は単層の導電膜で形成しても良いが、必要に応じて二層、三層といった積層膜とすることが好ましい。ゲート電極の材料としては公知のあらゆる導電膜を用いることができる。ただし、上述のように微細加工が可能、具体的には２μm以下の線幅にパターニング可能な材料が好ましい。
【０１１３】
代表的には、タンタル（Ｔａ）、チタン（Ｔｉ）、モリブデン（Ｍｏ）、タングステン（Ｗ）、クロム（Ｃｒ）、導電性を有するシリコン（Ｓｉ）から選ばれた元素でなる膜、または前記元素の窒化物膜（代表的には窒化タンタル膜、窒化タングステン膜、窒化チタン膜）、または前記元素を組み合わせた合金膜（代表的にはＭｏ−Ｗ合金、Ｍｏ−Ｔａ合金）、または前記元素のシリサイド膜（代表的にはタングステンシリサイド膜、チタンシリサイド膜）を用いることができる。勿論、単層で用いても積層して用いても良い。本実施例では、５０ｎｍ厚の窒化タンタル（ＴａＮ）膜と、３５０ｎｍ厚のＴａ膜とでなる積層膜を用いる。これはスパッタ法で形成すれば良い。また、スパッタガスとしてＸｅ、Ｎｅ等の不活性ガスを添加すると応力による膜はがれを防止することができる。
【０１１４】
この時、ゲート電極３１３、３１６はそれぞれｎ型不純物領域３０５、３０６の一部とゲート絶縁膜３１１を介して重なるように形成する。この重なった部分が後にゲート電極と重なったＬＤＤ領域となる。
【０１１５】
次に、図８（Ａ）に示すように、ゲート電極３１２〜３１６をマスクとして自己整合的にｎ型不純物元素（本実施例ではリン）を添加する。こうして形成される不純物領域３１７〜３２３にはｎ型不純物領域３０５、３０６の１／２〜１／１０（代表的には１／３〜１／４）の濃度でリンが添加されるように調節する。具体的には、１×１０¹⁶〜５×１０¹⁸atoms/cm³（典型的には３×１０¹⁷〜３×１０¹⁸atoms/cm³）の濃度が好ましい。
【０１１６】
次に、図８（Ｂ）に示すように、ゲート電極等を覆う形でレジストマスク３２４a〜３２４cを形成し、ｎ型不純物元素（本実施例ではリン）を添加して高濃度にリンを含む不純物領域３２５〜３３１を形成する。ここでもフォスフィン（ＰＨ₃）を用いたイオンドープ法で行い、この領域のリンの濃度は１×１０²⁰〜１×１０²¹atoms/cm³（代表的には２×１０²⁰〜５×１０²¹atoms/cm³）となるように調節する。
【０１１７】
この工程によってｎチャネル型ＴＦＴのソース領域若しくはドレイン領域が形成されるが、スイッチング用ＴＦＴでは、図８（Ａ）の工程で形成したｎ型不純物領域３２０〜３２２の一部を残す。この残された領域が、図５におけるスイッチング用ＴＦＴのＬＤＤ領域１５a〜１５dに対応する。
【０１１８】
次に、図８（Ｃ）に示すように、レジストマスク３２４a〜３２４cを除去し、新たにレジストマスク３３２を形成する。そして、ｐ型不純物元素（本実施例ではボロン）を添加し、高濃度にボロンを含む不純物領域３３３、３３４を形成する。ここではジボラン（Ｂ₂Ｈ₆）を用いたイオンドープ法により３×１０²⁰〜３×１０²¹atoms/cm³（代表的には５×１０²⁰〜１×１０²¹atoms/cm³ノ）濃度となるようにボロンを添加する。
【０１１９】
なお、不純物領域３３３、３３４には既に１×１０²⁰〜１×１０²¹atoms/cm³の濃度でリンが添加されているが、ここで添加されるボロンはその少なくとも３倍以上の濃度で添加される。そのため、予め形成されていたｎ型の不純物領域は完全にＰ型に反転し、Ｐ型の不純物領域として機能する。
【０１２０】
次に、レジストマスク３３２を除去した後、それぞれの濃度で添加されたｎ型またはｐ型不純物元素を活性化する。活性化手段としては、ファーネスアニール法、レーザーアニール法、またはランプアニール法で行うことができる。本実施例では電熱炉において窒素雰囲気中、５５０℃、４時間の熱処理を行う。
【０１２１】
このとき雰囲気中の酸素を極力排除することが重要である。なぜならば酸素が少しでも存在していると露呈したゲート電極の表面が酸化され、抵抗の増加を招くと共に後にオーミックコンタクトを取りにくくなるからである。従って、上記活性化工程における処理雰囲気中の酸素濃度は１ｐｐｍ以下、好ましくは０．１ｐｐｍ以下とすることが望ましい。
【０１２２】
次に、活性化工程が終了したら図８（Ｄ）に示すように３００ｎｍ厚のゲート線３３５を形成する。ゲート配線３３５の材料としては、アルミニウム（Ａｌ）又は銅（Ｃｕ）を主成分（組成として５０〜１００％を占める。）とする金属膜を用いれば良い。配置としては図２のゲート配線２１１のように、スイッチング用ＴＦＴのゲート電極３１４、３１５（図２のゲート電極１９a、１９bに相当する）を電気的に接続するように形成する。
【０１２３】
このような構造とすることでゲート配線の配線抵抗を非常に小さくすることができるため、面積の大きい画像表示領域（画素部）を形成することができる。即ち、画面の大きさが対角１０インチ以上（さらには３０インチ以上）のＥＬ表示装置を実現する上で、本実施例の画素構造は極めて有効である。
【０１２４】
次に、図９（Ａ）に示すように、第１層間絶縁膜３３６を形成する。第１層間絶縁膜３３６としては、珪素を含む絶縁膜を単層で用いるか、その中で組み合わせた積層膜を用いれば良い。また、膜厚は４００ｎｍ〜１．５μmとすれば良い。本実施例では、２００ｎｍ厚の窒化酸化珪素膜の上に８００ｎｍ厚の酸化珪素膜を積層した構造とする。
【０１２５】
さらに、３〜１００％の水素を含む雰囲気中で、３００〜４５０℃で１〜１２時間の熱処理を行い水素化処理を行う。この工程は熱的に励起された水素により半導体膜の不対結合手を水素終端する工程である。水素化の他の手段として、プラズマ水素化（プラズマにより励起された水素を用いる）を行っても良い。尚、水素化処理は第１層間絶縁膜３３６を形成する間に入れても良い。即ち、２００ｎｍ厚の窒化酸化珪素膜を形成した後で上記のように水素化処理を行い、その後で残り８００ｎｍ厚の酸化珪素膜を形成しても構わない。
【０１２６】
次に、第１層間絶縁膜３３６に対してコンタクトホールを形成し、ソース配線３３７〜３４０と、ドレイン配線３４１〜３４３を形成する。なお、本実施例ではこの電極を、Ｔｉ膜を１００ｎｍ、Ｔｉを含むアルミニウム膜を３００ｎｍ、Ｔｉ膜１５０ｎｍをスパッタ法で連続形成した３層構造の積層膜とする。勿論、他の導電膜でも良い。
【０１２７】
次に、５０〜５００ｎｍ（代表的には２００〜３００ｎｍ）の厚さで第１パッシベーション膜３４４を形成する。本実施例では第１パッシベーション膜３４４として３００ｎｍ厚の窒化酸化珪素膜を用いる。これは窒化珪素膜で代用しても良い。勿論、図５の第１パッシベーション膜４１と同様の材料を用いることが可能である。
【０１２８】
なお、窒化酸化珪素膜の形成に先立ってＨ₂、ＮＨ₃等水素を含むガスを用いてプラズマ処理を行うことは有効である。この前処理により励起された水素が第１層間絶縁膜３３６に供給され、熱処理を行うことで、第１パッシベーション膜３４４の膜質が改善される。それと同時に、第１層間絶縁膜３３６に添加された水素が下層側に拡散するため、効果的に活性層を水素化することができる。
【０１２９】
次に、有機樹脂からなる第２層間絶縁膜３４７を形成する。有機樹脂としてはポリイミド、ポリアミド、アクリル、ＢＣＢ（ベンゾシクロブテン）等を使用することができる。特に、第２層間絶縁膜３４６は平坦化の意味合いが強いので、平坦性に優れたアクリルが好ましい。本実施例ではＴＦＴによって形成される段差を十分に平坦化しうる膜厚でアクリル膜を形成する。好ましくは１〜５μm（さらに好ましくは２〜４μm）とすれば良い。
【０１３０】
次に、第２層間絶縁膜３４７上に１００ｎｍ厚の第２パッシベーション膜３４８を形成する。本実施例ではＳｉ、Ａｌ、Ｎ、Ｏ及びＬａを含む絶縁膜を用いるため、その上に設けられるＥＬ層からのアルカリ金属の拡散を防止することができる。また、同時にＥＬ層に水分を侵入させず、且つ、ＥＬ層で発生した熱を分散させて、熱によるＥＬ層の劣化や平坦化膜（第２層間絶縁膜）の劣化を抑制することができる。
【０１３１】
そして、第２パッシベーション膜３４８、第２層間絶縁膜３４７及び第１パッシベーション膜３４４にドレイン配線３４３に達するコンタクトホールを形成し、画素電極３４９を形成する。本実施例では酸化インジウム・スズ（ＩＴＯ）膜を１１０ｎｍの厚さに形成し、パターニングを行って画素電極とする。この画素電極３４９がＥＬ素子の陽極となる。なお、他の材料として、酸化インジウム・チタン膜や酸化インジウム・亜鉛膜を用いることも可能である。
【０１３２】
尚、本実施例では画素電極３４９がドレイン配線３４３を介して電流制御用ＴＦＴのドレイン領域３３１へと電気的に接続された構造となっている。この構造には次のような利点がある。
【０１３３】
画素電極３４９はＥＬ層（発光層）や電荷輸送層などの有機材料に直接接することになるため、ＥＬ層等に含まれた可動イオンが画素電極中を拡散する可能性がある。即ち、本実施例の構造は画素電極３４９を直接活性層の一部であるドレイン領域３３１へ接続せず、ドレイン配線３４３を中継することによって活性層中への可動イオンの侵入を防ぐことができる。
【０１３４】
次に、図９（Ｃ）に示すように、ＥＬ層３５０をインクジェット方式により形成し、さらに大気解放しないで陰極（ＭｇＡｇ電極）３５１、補助電極３５２を形成する。このときＥＬ層３５０及び陰極３５１を形成するに先立って画素電極３４９に対して熱処理を施し、水分を完全に除去しておくことが望ましい。なお、本実施例ではＥＬ素子の陰極としてＭｇＡｇ電極を用いるが、公知の他の材料であっても良い。
【０１３５】
尚、ＥＬ層３５０としては実施形態２で説明した材料を用いることができる。例えば、正孔注入層（Hole injecting layer）、正孔輸送層（Hole transporting layer）、発光層（Emitting layer）及び電子輸送層（Electron transporting layer）でなる４層構造をＥＬ層としても良いし、電子輸送層を設けない場合もあり、電子注入層を設ける場合もある。また、正孔注入層を省略する場合もある。このように組み合わせは既に様々な例が報告されており、そのいずれの構成を用いても構わない。
【０１３６】
正孔注入層又は正孔輸送層としてはアミン系のＴＰＤ（トリフェニルアミン誘導体）を用いればよく、他にもヒドラゾン系（代表的にはＤＥＨ）、スチルベン系（代表的にはＳＴＢ）、スターバスト系（代表的にはｍ−ＭＴＤＡＴＡ）等を用いることができる。特にガラス転移温度が高く結晶化しにくいスターバスト系材料が好ましい。
【０１３７】
発光層としては赤色発光層としてはＢＰＰＣ、ペリレン、ＤＣＭが用いることができるが、特にＥｕ（ＤＢＭ）₃（Ｐｈｅｎ）で示されるＥｕ錯体（J.Kido et.al,Appl.Phys.,vol.35,pp.L394-396,1996に詳しい。）は６２０ｎｍの波長に鋭い発光をもち単色性が高い。
【０１３８】
また、緑色発光層として代表的にはＡｌｑ₃（8-hydroxyquinoline alminium）に数モル％のキナクリドン又はクマリンを添加した材料を用いることができる。化学式は以下のようになる。
【０１３９】
【化６】

【０１４０】
また、青色発光層として代表的にはＤＳＡ（ジスチルアリーレン誘導体）にアミノ置換ＤＳＡを添加したジスチルアリーレンアミン誘導体を用いることができる。特に、性能の高い材料であるジスチリルビフェニル（ＤＰＶＢｉ）を用いることが好ましい。化学式は以下のようになる。
【０１４１】
【化７】

【０１４２】
また、補助電極３５２でもＥＬ層３５０を水分や酸素から保護することは可能であるが、さらに好ましくは第３パッシベーション膜３５３を設けると良い。本実施例では第３パッシベーション膜３５３として３００ｎｍ厚の窒化珪素膜を設ける。この第３パッシベーション膜も補助電極３５２の後に大気解放しないで連続的に形成しても構わない。勿論、第３パッシベーション膜３５３としては、図５の第３パッシベーション膜５０と同一の材料を用いることができる。
【０１４３】
補助電極３５２はＭｇＡｇ電極３５１の劣化を防ぐために設けられ、Ａｌを主成分とする金属膜が代表的である。勿論、他の材料でも良い。また、ＥＬ層３５０、ＭｇＡｇ電極３５１は非常に水分に弱いので、補助電極３５２までを大気解放しないで連続的に形成し、外気からＥＬ層を保護することが望ましい。
【０１４４】
尚、ＥＬ層３５０の膜厚は１０〜４００ｎｍ（典型的には６０〜１６０ｎｍ）、ＭｇＡｇ電極３５１の厚さは１８０〜３００ｎｍ（典型的には２００〜２５０ｎｍ）とすれば良い。また、ＥＬ層３５０を積層構造とする場合、各層の膜厚は１０〜１００ｎｍの範囲とすれば良い。
【０１４５】
こうして図９（Ｃ）に示すような構造のアクティブマトリクス型ＥＬ表示装置が完成する。ところで、本実施例のアクティブマトリクス型ＥＬ表示装置は、画素部だけでなく駆動回路部にも最適な構造のＴＦＴを配置することにより、非常に高い信頼性を示し、動作特性も向上しうる。
【０１４６】
まず、極力動作速度を落とさないようにホットキャリア注入を低減させる構造を有するＴＦＴを、駆動回路を形成するＣＭＯＳ回路のｎチャネル型ＴＦＴ２０５として用いる。なお、ここでいう駆動回路としては、シフトレジスタ、バッファ、レベルシフタ、サンプリング回路（サンプル及びホールド回路）などが含まれる。デジタル駆動を行う場合には、Ｄ／Ａコンバータなどの信号変換回路も含まれうる。
【０１４７】
本実施例の場合、図９（Ｃ）に示すように、ｎチャネル型２０５の活性層は、ソース領域３５５、ドレイン領域３５６、ＬＤＤ領域３５７及びチャネル形成領域３５８を含み、ＬＤＤ領域３５７はゲート絶縁膜３１１を介してゲート電極３１３と重なっている。
【０１４８】
ドレイン領域側のみにＬＤＤ領域を形成しているのは、動作速度を落とさないための配慮である。また、このｎチャネル型ＴＦＴ２０５はオフ電流値をあまり気にする必要はなく、それよりも動作速度を重視した方が良い。従って、ＬＤＤ領域３５７は完全にゲート電極に重ねてしまい、極力抵抗成分を少なくすることが望ましい。即ち、いわゆるオフセットはなくした方がよい。
【０１４９】
また、ＣＭＯＳ回路のｐチャネル型ＴＦＴ２０６は、ホットキャリア注入による劣化が殆ど気にならないので、特にＬＤＤ領域を設けなくても良い。勿論、ｎチャネル型ＴＦＴ２０５と同様にＬＤＤ領域を設け、ホットキャリア対策を講じることも可能である。尚、駆動回路の中でもサンプリング回路は他の回路と比べて少し特殊であり、チャネル形成領域を双方向に大電流が流れる。即ち、ソース領域とドレイン領域の役割が入れ替わるのである。さらに、オフ電流値を極力低く抑える必要があり、そういった意味でスイッチング用ＴＦＴと電流制御用ＴＦＴの中間程度の機能を有するＴＦＴを配置することが望ましい。
【０１５０】
従って、サンプリング回路を形成するｎチャネル型ＴＦＴは、図１３に示すような構造のＴＦＴを配置することが望ましい。図１３に示すように、ＬＤＤ領域９０１a、９０１bの一部がゲート絶縁膜９０２を介してゲート電極９０３と重なる。この効果は電流制御用ＴＦＴ２０２の説明で述べた通りであり、サンプリング回路の場合はチャネル形成領域９０４を挟む形で設ける点が異なる。
【０１５１】
また、図５に示したような構造の画素を形成して画素部を形成している。画素内に形成されるスイッチング用ＴＦＴ及び電流制御用ＴＦＴの構造については、図５で既に説明したのでここでの説明は省略する。
【０１５２】
なお、実際には図９（Ｃ）まで完成したら、さらに外気に曝されないように気密性の高い保護フィルム（ラミネートフィルム、紫外線硬化樹脂フィルム等）やセラミックス製シーリングカンなどのハウジング材でパッケージング（封入）することが好ましい。その際、ハウジング材の内部を不活性雰囲気にしたり、内部に吸湿性材料（例えば酸化バリウム）を配置することでＥＬ層の信頼性（寿命）が向上する。
【０１５３】
また、パッケージング等の処理により気密性を高めたら、基板上に形成された素子又は回路から引き回された端子と外部信号端子とを接続するためのコネクター（フレキシブルプリントサーキット：ＦＰＣ）を取り付けて製品として完成する。このような出荷できる状態にまでしたＥＬ表示装置を本明細書中ではＥＬモジュールという。
【０１５４】
ここで本実施例のアクティブマトリクス型ＥＬ表示装置の構成を図１０の斜視図を用いて説明する。本実施例のアクティブマトリクス型ＥＬ表示装置は、ガラス基板６０１上に形成された、画素部６０２と、ゲート側駆動回路６０３と、ソース側駆動回路６０４で構成される。画素部のスイッチング用ＴＦＴ６０５はｎチャネル型ＴＦＴであり、ゲート側駆動回路６０３に接続されたゲート配線６０６、ソース側駆動回路６０４に接続されたソース配線６０７の交点に配置されている。また、スイッチング用ＴＦＴ６０５のドレインは電流制御用ＴＦＴ６０８のゲートに接続されている。
【０１５５】
さらに、電流制御用ＴＦＴ６０６のソース側は電源供給線６０９に接続される。本実施例のような構造では、電源供給線６０９には接地電位（アース電位）が与えられている。また、電流制御用ＴＦＴ６０８のドレインにはＥＬ素子６１０が接続されている。また、このＥＬ素子６１０のカソードには所定の電圧（本実施例では１０〜１２Ｖ）が加えられる。そして、外部入出力端子となるＦＰＣ６１１には駆動回路まで信号を伝達するための入出力配線（接続配線）６１２、６１３、及び電源供給線６０９に接続された入出力配線６１４が設けられている。
【０１５６】
また、図１０に示したＥＬ表示装置の回路構成の一例を図１１に示す。図１１の回路構成はアナログ駆動の例であり、ソース側駆動回路７０１、ゲート側駆動回路（Ａ）７０７、ゲート側駆動回路（Ｂ）７１１、画素部７０６を有している。なお、本明細書中において、駆動回路とはソース側処理回路およびゲート側駆動回路を含めた総称である。
【０１５７】
ソース側駆動回路７０１は、シフトレジスタ７０２、レベルシフタ７０３、バッファ７０４、サンプリング回路（サンプル及びホールド回路）７０５を備えている。また、ゲート側駆動回路（Ａ）７０７は、シフトレジスタ７０８、レベルシフタ７０９、バッファ７１０を備えている。ゲート側駆動回路（Ｂ）７１１も同様な構成である。
【０１５８】
ここで、シフトレジスタ７０２、７０８は駆動電圧が５〜１６Ｖ（代表的には１０Ｖ）であり、回路を形成するＣＭＯＳ回路に使われるｎチャネル型ＴＦＴは図９（Ｃ）の２０５で示される構造が適している。
【０１５９】
また、レベルシフタ７０３、７０９、バッファ７０４、７１０は、駆動電圧は１４〜１６Ｖと高くなるが、シフトレジスタと同様に、図９（Ｃ）のｎチャネル型ＴＦＴ２０５を含むＣＭＯＳ回路が適している。なお、ゲート配線をダブルゲート構造、トリプルゲート構造といったマルチゲート構造とすることは、各回路の信頼性を向上させる上で有効である。また、サンプリング回路７０５は駆動電圧が１４〜１６Ｖであるが、ソース領域とドレイン領域が反転する上、オフ電流値を低減する必要があるので、図１３のｎチャネル型ＴＦＴ２０８を含むＣＭＯＳ回路が適している。画素部７０６は駆動電圧が１４〜１６Ｖであり、図５に示した構造の画素を配置する。
【０１６０】
上記構成は、図７〜９に示した作製工程に従ってＴＦＴを作製することによって容易に実現することができる。また、本実施例では画素部と駆動回路の構成のみ示しているが、本実施例の作製工程に従えば、その他にも信号分割回路、Ｄ／Ａコンバータ回路、オペアンプ回路、γ補正回路など駆動回路以外の論理回路を同一基板上に形成することが可能であり、さらにはメモリ部やマイクロプロセッサ等を形成しうると考えている。
【０１６１】
さらに、ハウジング材をも含めた本実施例のＥＬモジュールについて図１４、図１５を用いて説明する。なお、必要に応じて図１０、図１１で用いた符号を引用することにする。
【０１６２】
図１４において、６０１は基板、６０２は画素部、６０３はソース側駆動回路、６０４はゲート側駆動回路、６１２は画素部６０２、ソース側駆動回路６０３、ゲート側駆動回路６０４をＦＰＣ（フレキシブルプリントサーキット）６１１に電気的に接続するための接続配線である。また、ＦＰＣは外部機器へと電気的に接続され、これにより画素部６０２、ソース側駆動回路６０３及びゲート側駆動回路６０４に外部からの信号を入力することができる。画素部６０２、ソース側駆動回路６０３及びゲート側駆動回路６０４は基板６０１上に形成された薄膜トランジスタ（以下、ＴＦＴという）で形成されている。なお、ＴＦＴとしては如何なる構造のＴＦＴを用いても良い。勿論、公知の構造であっても良い。さらに、充填材（図示せず）、カバー材１４０７、シール材（図示せず）及びフレーム材１４０８が形成される。
【０１６３】
ここで、図１４をＡ−Ａ’で切断した断面図を図１５（Ａ）に、Ｂ−Ｂ’で切断した断面図を図１５（Ｂ）に示す。なお、図１５（Ａ）、（Ｂ）では図１４と同一の部位に同一の符号を用いている。
【０１６４】
図１５（Ａ）に示すように、基板６０１上に画素部６０２、駆動回路６０３が形成されており、画素部６０２は電流制御用ＴＦＴ１５０１とそれに電気的に接続された画素電極１５０２を含む複数の画素により形成される。この画素電極１５０２はＥＬ素子の陽極として機能する。また、画素電極１５０２を覆うようにＥＬ層１５０３が形成され、その上にはＥＬ素子の陰極１５０４が形成される。
【０１６５】
陰極１５０４は全画素に共通の配線としても機能し、接続配線６１２を経由してＦＰＣ６１１に電気的に接続されている。さらに、画素部６０２及び駆動回路６０３に含まれる素子は全てパッシベーション膜１５０７で覆われている。
【０１６６】
さらに、ＥＬ素子を覆うようにして充填材１５０８を設ける。この充填材１５０８はカバー材１４０７を接着するための接着剤としても機能する。充填材１５０８としては、ＰＶＣ（ポリビニルクロライド）、エポキシ樹脂、シリコーン樹脂、ＰＶＢ（ポリビニルブチラル）またはＥＶＡ（エチレンビニルアセテート）を用いることができる。この充填材１５０８の内部に乾燥剤を設けておくと、吸湿効果を保ち続けられるので好ましい。
【０１６７】
また、カバー材１４０７としては、ガラス板、アルミニウム板、ステンレス板、ＦＲＰ（Fiberglass-Reinforced Plastics）板、ＰＶＦ（ポリビニルフロライド）フィルム、マイラーフィルム、ポリエステルフィルムまたはアクリルフィルムを用いることができる。なお、充填材１５０８としてＰＶＢやＥＶＡを用いる場合、数十μmのアルミニウムホイルをＰＶＦフィルムやマイラーフィルムで挟んだ構造のシートを用いることが好ましい。
【０１６８】
但し、ＥＬ素子からの発光方向（光の放射方向）によってはカバー材１４０７が透光性を有する必要がある。即ち、図１５の場合はカバー材１４０７の反対側に光が放射されるので材質は問わないが、カバー材１４０７側に放射されるような場合はカバー材１４０７に透光性の高い部材を用いる。
【０１６９】
次に、充填材１５０８を用いてカバー材１４０７を接着した後、充填材１５０８の側面（露呈面）を覆うようにフレーム材１４０８を取り付ける。フレーム材１４０８はシール材（接着剤として機能する）１５０９によって接着される。このとき、シール材１５０９としては、光硬化性樹脂を用いるのが好ましいが、ＥＬ層の耐熱性が許せば熱硬化性樹脂を用いても良い。なお、シール材１５０９はできるだけ水分や酸素を透過しない材料であることが望ましい。また、シール材１５０９の内部に乾燥剤を添加してあっても良い。
【０１７０】
以上のような方式を用いてＥＬ素子を充填材１５０８に封入することにより、ＥＬ素子を外部から完全に遮断することができ、外部から水分や酸素等のＥＬ層の酸化による劣化を促す物質が侵入することを防ぐことができる。従って、信頼性の高いＥＬ表示装置を作製することができる。
【０１７１】
[実施例２]
実施例１ではＴＦＴを形成した基板側にＥＬ素子で発光した光を放射する形式のＥＬ表示装置について示した。この場合には、少なくともＴＦＴが形成された領域は影となり、その分画素部の開口率は低下する。一方、ＥＬ素子で発光した光を上方（ＴＦＴが形成された基板の反対側）に放射する形式とすると、少なくとも開口率を向上させることは容易となる。
【０１７２】
図１８は上方に光を放射する形式のＥＬ表示素子の構成を示す。スイッチング用ＴＦＴ２０１と電流制御用ＴＦＴ２０２の構成は実施形態２と同様なものであり、ここではその他の部分の差異について説明する。
【０１７３】
電流制御用ＴＦＴ２０２のドレイン側に接続する陰極側画素電極９４９は第２パッシベーション膜９４５上に形成する。分離層９５１は有機樹脂材料で形成する。そして、陰極９４８をＭｇＡｇ（ＭｇとＡｌをＭｇ：Ａｇ＝１０：１で混合した材料）、ＭｇＡｇＡｌ、ＬｉＡｌ、ＬｉＦＡｌ等の材料を用いて形成する。
【０１７４】
ＥＬ層９４７も実施形態１または実施形態２と同様にしてインクジェット方式で形成する。さらに、ＩＴＯなどの透明導電膜材料で陽極側画素電極を形成し、その上に第３パッシベーション膜９５０を形成して上方に光を放射する形式のＥＬ表示素子が完成する。
【０１７５】
[実施例３]
本発明のインクジェット方式によるＥＬ層の作製方法、及び作製されたＥＬ層はパッシブ型のＥＬ表示装置にも適用できる。その実施例を図１６を用いて説明する。
【０１７６】
図１６（Ａ）において基板１６０１はコーニング社の＃１７３７ガラス基板に代表される無アルカリガラス基板、結晶化ガラス基板、表面に酸化珪素または窒化珪素等を形成したソーダライムガラス基板、プラスチック基板などを適用することができる。基板１６０１上には透明電極１６０２が５０〜２００ｎｍの厚さに形成され、エッチング処理やリフトオフ法等の手法により短冊状に複数個に分割する。透明電極１６０１はＩＴＯ、ＺｎＯ、ＳｎＯ₂、ＩＴＯ−ＺｎＯ等の材料で形成する。そして、ポリイミド等の有機樹脂材料を用いて、短冊状に形成した透明電極１６０２の側端部に接するように分離層１６０３を０．５〜２μｍの厚さで形成する。
【０１７７】
ＥＬ層は単層又は積層構造で用いられる。積層構造は、発光層、電子輸送層、電子注入層、正孔注入層又は正孔輸送層などを組み合わせた積層構造で形成されるが、本実施例では正孔注入層と発光層を積層させた構造で形成する。まず、図１６（Ｂ）に示すように正孔注入層１６０６を形成する。正孔注入層は必ずしも必要なものではないが、発光効率の向上のために設けると好ましい場合がある。正孔注入層の材料は実施形態１で示したように、テトラアリルジアミンを含む有機材料で形成する。この場合もインクジェット方式を用い、インクヘッド１６０４から吐出した溶液１６０５を、分離層の間にストライプ状、または複数のドットを連結させて長円状または長方形状に形成する。その後、ホットプレート等により１００℃程度に加熱し不要な水分等を蒸発させる。
【０１７８】
図１６（Ｃ）に示すように発光層もインクジェット方式で形成する。カラー表示をする場合には、赤、緑、青の各色のシリンダーを有するインクヘッドを用い、発光材料を含有するＥＬ形成溶液１６０９を正孔注入層上に吐出させて形成する。発光層１６０８は、好ましいＥＬ材料として、ポリパラフェニレンビニレン（ＰＰＶ）系やポリフルオレン系などの高分子材料がある。カラー化するには、例えば、赤色発光材料にはシアノポリフェニレンビニレン、緑色発光材料にはポリフェニレンビニレン、青色発光材料にはポリフェニレンビニレン及びポリアルキルフェニレンが好ましい。このようにして、赤、緑、青の各色に対応した発光層１６０８Ｒ、１６０８Ｇ、１６０８Ｂをストライプ状、または複数のを連結させて長円状または長方形状に形成する。インクジェット方式においても、形成時にＥＬ材料が酸化して劣化するのを防ぐために窒素またはアルゴン等の不活性ガス雰囲気中で作業を行うようにする。
【０１７９】
そして、陰極材料をＭｇＡｇ（ＭｇとＡｇをＭｇ：Ａｇ＝１０：１で混合した材料）、ＭｇＡｇＡｌ、ＬｉＡｌ、ＬｉＦＡｌ等の材料で形成する。この陰極材料は、代表的には真空蒸着法で１〜５０ｎｍの厚さで形成する。さらにこの上に補助電極としてＡｌなどを積層させる。図１６（Ｄ）の陰極層１６１０はこのような構成を示し、それぞれの膜形成時にマスク部材を用い短冊状に形成する。短冊状に形成された陰極層１６１０は、やはり同様に短冊状に形成した透明電極１６０２とほぼ直交するように形成する。この陰極層１６１０上には窒化珪素膜、窒化酸化珪素膜などでパッシベーション膜１６１１が形成される。
【０１８０】
ここで示したＥＬ層を形成する材料は水分や湿気等に弱いためハウジング材で封止することが望ましい。ハウジング材１６１４の材質はガラス、ポリマー等の絶縁性物質が好ましい。例えば、非晶質ガラス（硼硅酸塩ガラス、石英等）、結晶化ガラス、セラミックスガラス、有機系樹脂（アクリル系樹脂、スチレン系樹脂、ポリカーボネート系樹脂、エポキシ系樹脂等）、シリコーン系樹脂が挙げられる。また、セラミックスを用いても良い。また、接着剤１７０５が絶縁性物質であるならステンレス合金等の金属材料を用いることも可能である。
【０１８１】
また、ハウジング材１６１４をＥＬ層が形成された基板に張り合わせる接着剤１６１２の材質は、エポキシ系樹脂、アクリレート系樹脂等の接着剤を用いることが可能である。さらに、熱硬化性樹脂や光硬化性樹脂を接着剤として用いることもできる。但し、可能な限り酸素、水分を透過しない材質であることが必要である。接着剤１６１２には酸化バリウム等の乾燥剤１６１３を混入させておいても良い。このようにしてパッシブ型のＥＬ表示装置を形成することができる。
【０１８２】
[実施例４]
ＥＬ素子を形成する薄膜形成装置の一例を図１７に示す。図１７に示したのは発光層として高分子系有機ＥＬ層、陰極層として周期律表の１族若しくは２族に属する元素を含む金属膜、補助電極としてＡｌ等の導電膜、パッシベーション膜を連続して形成する装置である。
【０１８３】
図１７において、４０１は基板の搬入または搬出を行う搬送室であり、ロード・アンロード室とも呼ばれる。ここに基板をセットしたキャリア４０２が配置される。尚、搬送室４０１は基板搬入用と基板搬出用と区別されていても良い。また、４０３は基板４０４を搬送する機構（以下、搬送機構という）４０５を含む共通室である。基板のハンドリングを行うロボットアームなどは搬送機構（１）４０５の一種である。
【０１８４】
共通室４０３にはゲート４０６a〜４０６fを介して複数の処理室が連結されている。図１７の構成では共通室４０３を数ｍＴｏｒｒから数十ｍＴｏｒｒに減圧し、各処理室はゲート４０６a〜４０６fによって共通室４０３とは遮断されている。この場合、インクジェット印刷用処理室４１５とスピンコート用処理室４０８は窒素またはアルゴン等の不活性ガスを満たした常圧中で行われるため、共通室４０３との間に、真空排気用処理室４１２を設けた構成となっている。
【０１８５】
減圧下で所定の作業を行う各処理室には排気ポンプを設けることで真空下での処理を行うことが可能となる。排気ポンプとしては、油回転ポンプ、メカニカルブースターポンプ、ターボ分子ポンプ若しくはクライオポンプを用いることが可能であるが、水分の除去に効果的なクライオポンプが好ましい。
【０１８６】
発光層や注入層から成るＥＬ層の形成は、インクジェット印刷用処理室４１５、またはスピンコート用処理室４０８で行う。インクジェット印刷用処理室４１５には基板保持手段や図３で説明したインクヘッド等が設けられている。また、前述のように有機ＥＬ材料は水分に極めて弱いため、インクジェット印刷用処理室４１５、スピンコート用処理室４０８は常に不活性雰囲気に保たれている。
【０１８７】
基板の搬送は、まず真空排気用処理室４１２を共通室４０３と同じ圧力まで減圧しておき、その状態でゲート４０６dを開けて基板を搬送する。そして、ゲート４０６dを閉めた後、真空排気用処理室４１２内を不活性ガスでパージし、常圧に戻った時点でゲート４１３を開けて基板搬送室４１４にある搬送機構（２）４１８で基板をインクジェット印刷用処理室４１５、スピンコート用処理室４０８に搬送する。
【０１８８】
本発明では有機ＥＬ層はインクジェット方式で形成するものであるが、発光層をインクジェット方式で形成し、正孔または電子注入層や正孔または電子輸送層などの一部の層をスピンコート法で形成するといったように両者を適宣組み合わせて形成しても良い。
【０１８９】
ＥＬ層の形成工程が終了したら、ゲート４１３を開けて真空排気用処理室４１２へ基板を搬送し、ゲート４１３及びゲート４０６dを閉めた状態で真空排気を行う。真空排気用処理室４１２が共通室４０３と同じ減圧状態にまで達したら、ゲート４０６dを開けて基板を共通室へと搬送する。
【０１９０】
尚、ここでは焼成用処理室４０９を設けているが、真空排気用処理室４１２のサセプターを加熱できるようにして、ここで焼成工程を行っても良い。焼成後に真空排気することで、脱ガスを抑えることが可能である。
【０１９１】
第１成膜用処理室４１０では陰極の形成を行う。陰極材料としては、公知の材料を用いて行う。陰極は真空蒸着法で形成するが、そのとき基板表面（高分子系ＥＬ層が形成された面）は、上向き（フェイスアップ方式）であっても下向き（フェイスダウン方式）であっても良い。
【０１９２】
フェイスアップ方式の場合、共通室４０３から搬送された基板をそのままサセプターに設置すれば良いため非常に簡易である。フェイスダウン方式の場合、搬送機構（１）４０５若しくは第１成膜用処理室４１０に、基板を反転させるための機構を備えておく必要が生じるため搬送機構が複雑になるが、ゴミの付着が少ないという利点が得られる。
【０１９３】
尚、第１成膜用処理室１１０において蒸着処理を行う場合には、蒸着源を具備しておく必要がある。蒸着源は複数設けても良い。また、抵抗加熱方式の蒸着源としても良いし、ＥＢ（電子ビーム）方式の蒸着源としても良い。
【０１９４】
第２成膜用処理室４１１は、気相成膜法により電極を形成するための処理室である。ここでは陰極を補助するための補助電極の形成が行われる。また、蒸着法又はスパッタ法が用いられるが、蒸着法の方がダメージを与えにくいので好ましい。いずれにしてもゲート４０６fによって共通室４０３と遮断され、真空下で成膜が行われる。尚、気相成膜法として蒸着法を行う場合には、蒸着源を設ける必要がある。蒸着源に関しては第１気相成膜用処理室４１０と同様で構わないので、ここでの説明は省略する。
【０１９５】
陰極として良く用いられる金属膜は、周期律表の１族若しくは２族に属する元素を含む金属膜であるが、これらの金属膜は酸化しやすいので表面を保護しておくことが望ましい。また、必要な膜厚も薄いため、抵抗率の低い導電膜を補助的に設けて陰極の抵抗を下げ、加えて陰極の保護を図る。抵抗率の低い導電膜としてはアルミニウム、銅又は銀を主成分とする金属膜が用いられる。
【０１９６】
次に、第３成膜用処理室４０７では、第３パッシベーション膜を形成するための処理室である。第３パッシベーション膜は窒化珪素膜または窒化酸化珪素膜等をプラズマＣＶＤ法で形成する。従って、図示していないが、ＳｉＨ₄、Ｎ₂Ｏ、ＮＨ₃などのガス供給系、１３．５６〜６０ＭＨｚの高周波電源を用いたプラズマ発生手段、基板加熱手段などが設けられている。有機材料から成るＥＬ層は水分または湿気に弱いので、ＥＬ層を形成後大気雰囲気に晒すことなく連続してこのようなパッシベーション膜を設けると良い。
【０１９７】
以上の構成でなる薄膜形成装置の最大の特徴は、ＥＬ層の形成うインクジェット方式により行われ、且つ、そのための手段が陰極を形成する手段と共にマルチチャンバー方式の薄膜形成装置に搭載されている点にある。従って、透明導電膜でなる陽極上を表面酸化する工程から始まって、補助電極を形成する工程までを一度も外気に晒すことなく行うことが可能である。その結果、劣化に強い高分子系ＥＬ層を簡易な手段で形成することが可能となり、信頼性の高いＥＬ表示装置を作製することが可能となる。
【０１９８】
[実施例５]
実施例１では、結晶質珪素膜３０２の形成手段としてレーザー結晶化を用いているが、本実施例では異なる結晶化手段を用いる場合について説明する。
【０１９９】
本実施例では、非晶質珪素膜を形成した後、特開平７−１３０６５２号公報に記載された技術を用いて結晶化を行う。同公報に記載された技術は、結晶化を促進（助長）する触媒として、ニッケル等の元素を用い、結晶性の高い結晶質珪素膜を得る技術である。
【０２００】
また、結晶化工程が終了した後で、結晶化に用いた触媒を除去する工程を行っても良い。その場合、特開平１０−２７０３６３号若しくは特開平８−３３０６０２号に記載された技術により触媒をゲッタリングすれば良い。また、本出願人による特願平１１−０７６９６７の出願明細書に記載された技術を用いてＴＦＴを形成しても良い。
【０２０１】
以上のように、実施例１に示した作製工程は一実施例であって、図５又は実施例１の図９（Ｃ）の構造が実現できるのであれば、他の作製工程を用いても問題はない。尚、本実施例の構成は、実施形態２及び実施例１〜２のいずれの構成とも自由に組み合わせることが可能である。
【０２０２】
[実施例６]
本発明を実施して形成されたアクティブマトリクス型ＥＬ表示装置またはパッシブ型ＥＬ表示装置（ＥＬモジュール）は、自発光型であるため液晶表示装置に比べて明るい場所での視認性に優れている。そのため直視型のＥＬ表示装置（ＥＬモジュールを組み込んだ表示装置を指す）として用途は広い。
【０２０３】
尚、ＥＬ表示装置が液晶表示装置よりも有利な点の一つとして視野角の広さが挙げられる。従って、ＴＶ放送等を大画面で鑑賞するには対角３０インチ以上（典型的には４０インチ以上）の表示装置（表示モニタ）として本発明のＥＬ表示装置を用いるとよい。
【０２０４】
また、ＥＬ表示装置（パソコンモニタ、ＴＶ放送受信用モニタ、広告表示モニタ等）として用いるだけでなく、様々な電子装置の表示装置として用いることができる。その様な電子装置としては、ビデオカメラ、デジタルカメラ、ゴーグル型ディスプレイ（ヘッドマウントディスプレイ）、カーナビゲーション、パーソナルコンピュータ、携帯情報端末（モバイルコンピュータ、携帯電話または電子書籍等）、記録媒体を備えた画像再生装置（具体的にはコンパクトディスク（ＣＤ）、レーザーディスク（ＬＤ）又はデジタルビデオディスク（ＤＶＤ）等の記録媒体を再生し、その画像を表示しうるディスプレイを備えた装置）などが挙げられる。それら半導体装置の例を図１９と図２０に示す。
【０２０５】
図１９（Ａ）はＥＬディスプレイであり、筐体２００１、支持台２００２、表示部２００３等を含む。本発明のＥＬ表示装置は表示部２００３に用いることができる。本発明のＥＬ表示装置は特に大画面化した場合において有利であり、対角１０インチ以上（特に対角３０インチ以上）のディスプレイには有利である。
【０２０６】
図１９（Ｂ）はビデオカメラであり、本体２１０１、表示部２１０２、音声入力部２１０３、操作スイッチ２１０４、バッテリー２１０５、受像部２１０６等を含む。本発明のＥＬ表示装置を表示部２１０２に用いることができる。
【０２０７】
図１９（Ｃ）はヘッドマウント型ディスプレイであり、本体２２０１、信号ケーブル２２０２、固定バンド２２０３、表示部２２０４、光学系２２０５、ＥＬ表示装置２２０６等を含む。これは、ＥＬ表示装置２２０６で写し出された画像情報を光学系により表示部２２０４に映し出す構成になっており、本発明は表示装置２２０６に用いることができる。
【０２０８】
図１９（Ｄ）は記録媒体を備えた画像再生装置（具体的にはＤＶＤ再生装置）であり、本体２３０１、記録媒体（ＣＤ、ＬＤまたはＤＶＤ等）２３０２、操作スイッチ２３０３、表示部（ａ）２３０４、表示部（ｂ）２３０５等を含む。表示部（ａ）は主として画像情報を表示し、表示部（ｂ）は主として文字情報を表示するが、本発明のＥＬ表示装置はこれら表示部（ａ）、（ｂ）に用いることができる。なお、記録媒体を備えた画像再生装置としては、ＣＤ再生装置、ゲーム機器などに本発明を用いることができる。
【０２０９】
図１９（Ｅ）は携帯型（モバイル）コンピュータであり、本体２４０１、カメラ部２４０２、受像部２４０３、操作スイッチ２４０４、表示部２４０５等を含む。本発明のＥＬ表示装置は表示部２４０５に用いることができる。
【０２１０】
図１９（Ｆ）はパーソナルコンピュータであり、本体２５０１、表示部２５０３、キーボード２５０４等を含む。本発明のＥＬ表示装置は表示部２５０３に用いることができる。
【０２１１】
図２０（Ａ）は携帯電話であり、本体２６０１、音声出力部２６０２、音声入力部２６０３、表示部２６０４、操作スイッチ２６０５、アンテナ２６０６等から構成されている。本発明のＥＬ表示装置は低消費電力であり、表示部２６０４に好適に用いることができる。
【０２１２】
図２０（Ｂ）は車載用オーディオ機器であり、本体２７０１、表示部２７０２、操作スイッチ２７０３、２７０４等を含む。本発明のＥＬ表示装置は視野角が広いので視認性に優れることから表示部２７０２に好適に用いることができる。
【０２１３】
以上の様に、本発明の適用範囲は極めて広く、あらゆる分野の電子機器に適用することが可能である。また、本実施例の電子機器は実施例１〜５のどのような組み合わせからなる構成を用いても実現することができる。
【０２１４】
[実施例７]
図２２は本発明のインクジェット方式を用いてＥＬ層を形成した試料の顕微鏡写真を示す。試料の構造は、アクリル樹脂で形成した絶縁膜上にＩＴＯで形成した画素電極が設けられ、感光性アクリル樹脂で形成した分離層がストライプ状に設けられている。
【０２１５】
ＩＴＯ上には最初に溶液塗布法（スピンコーティング法）でＰＥＤＯＴ層が形成される。そのとき、ＩＴＯは疎水性であるので、親水性とするため酸素プラズマ処理とＣＦ₄プラズマ処理を行っている。
【０２１６】
ＥＬ層はアニソール２０ｍｇにＰＰＶを０．０４ｇの割合で溶かしたものを用い、インクジェット方式により形成している。分離層の間隔は９０μmであり、その間にＥＬ層が連続的に形成されている様子が分かる。このようにして、ＥＬ層の形成を簡便でかつ高速に処理することが可能となっている。
【０２１７】
【発明の効果】
本発明を用いることで、ＥＬ層の形成を簡便でかつ高速に処理することが可能となる。また、ＥＬ素子が水分や熱によって劣化することを抑制することができる。また、ＥＬ層からアルカリ金属が拡散してＴＦＴ特性に悪影響を与えることを防ぐことができる。その結果、ＥＬ表示装置の動作性能や信頼性を大幅に向上させることができる。
【０２１８】
また、そのようなＥＬ表示装置を表示ディスプレイとして有することで、画像品質が良く、耐久性のある（信頼性の高い）応用製品（電子装置）を生産することが可能となる。
【図面の簡単な説明】
【図１】 本発明のインクジェット方式でＥＬ層を連続的に形成する概念を説明するための図。
【図２】 マトリクス状に配列した各画素電極に対し、ＥＬ層をストライプ状或いは連続的に形成する概念を説明するための図。
【図３】 インクジェット方式を説明するための図。
【図４】 本発明のインクジェット方式でＥＬ層を連続的に形成する概念を説明するための図。
【図５】 ＥＬ表示装置の画素部の断面構造を示す図。
【図６】 ＥＬ表示装置の画素部の上面構造及び構成を示す図。
【図７】 アクティブマトリクス型ＥＬ表示装置の作製工程を示す図。
【図８】 アクティブマトリクス型ＥＬ表示装置の作製工程を示す図。
【図９】 アクティブマトリクス型ＥＬ表示装置の作製工程を示す図。
【図１０】 ＥＬモジュールの外観を示す図。
【図１１】 ＥＬ表示装置の回路ブロック構成を示す図。
【図１２】 ＥＬ表示装置の画素部を拡大した図。
【図１３】 ＥＬ表示装置のサンプリング回路の素子構造を示す図。
【図１４】 ＥＬモジュールの示す上面図。
【図１５】 ＥＬ表示装置の封止構造を示す断面図。
【図１６】 パッシブ型ＥＬ表示装置の作製工程を示す図。
【図１７】 ＥＬ表示装置を作製するための装置構成を説明する図。
【図１８】 ＥＬ表示装置の画素部の断面構造を示す図。
【図１９】 電子装置の具体例を示す図。
【図２０】 電子装置の具体例を示す図。
【図２１】 画素部の画素配列を説明する図。
【図２２】 本発明のインクジェット方式でＥＬ層を連続的に形成した試料の顕微鏡写真。[0001]
BACKGROUND OF THE INVENTION
The present invention includes an electro-optical device typified by an electroluminescence (EL) display device formed by fabricating a semiconductor element (an element using a semiconductor thin film) on a substrate, and the electro-optical device as a display display. The present invention relates to an electronic apparatus (electronic device). In particular, it relates to a manufacturing method thereof. In this specification, a layer including an organic compound from which electroluminescence is obtained is referred to as an EL layer. Minescence in an organic compound includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state, and includes both.
[0002]
[Prior art]
In recent years, a technique for forming a thin film transistor (hereinafter referred to as TFT) on a substrate has greatly advanced, and application development to an active matrix display device has been advanced. In particular, a TFT using a semiconductor film having a crystal structure (for example, a polysilicon film) has higher field effect mobility than a TFT using a conventional amorphous silicon film, and thus can operate at high speed. Therefore, a driver circuit connected to the pixel portion can be formed using a TFT and formed over the same substrate.
[0003]
Such an active matrix display device has various advantages such as reduction in manufacturing cost by making various circuits and elements on the same substrate, downsizing and thinning of the display device, increase in yield, and improvement in throughput. Has been attracting attention as it can be obtained.
[0004]
In the active matrix EL display device, each pixel is provided with a switching element made of a TFT, and a driving element that controls current is operated by the switching element to cause the EL layer (light emitting layer) to emit light. For example, there is an EL display device described in US Pat. No. 5,684,365 (see Japanese Laid-Open Publication No. 8-234683) and Japanese Laid-Open Publication No. 10-189252.
[0005]
In these color display methods using an EL display device, an attempt is made to arrange an EL layer that emits three primary colors of red (R), green (G), and blue (B) for each pixel. However, most of the materials generally used for the EL layer are organic materials, and it has been difficult to apply the photolithography technique used in microfabrication as it is. The reason is that the EL material itself is very weak against moisture and is difficult to handle as it easily dissolves in the developer.
[0006]
As a technique for solving such a problem, a technique for forming an EL layer by an inkjet method has been proposed. For example, Japanese Patent Application Laid-Open No. 10-012377 discloses an active matrix EL display body in which an EL layer is formed by an ink jet method. A similar technique is also disclosed in “Multicolor Pixel Patterning of Light-Emitting Polymers by Ink-jet Printing; T. Shimada et.al., p376-379, SID 99 DIGEST”.
[0007]
[Problems to be solved by the invention]
In the inkjet method, an EL layer can be formed for each pixel, and a process of patterning after forming the EL layer can be omitted. However, in both an active matrix EL display device and a passive EL display device, higher position accuracy and higher processing speed are required as the screen size increases and the pixel density increases.
[0008]
An object of the present invention is to easily and rapidly process formation of an EL layer by an ink jet method. It is another object of the present invention to provide a method for manufacturing an electro-optical device with high operation performance and reliability, particularly a method for manufacturing an EL display device. An object of the present invention is to improve the quality of an electronic device (electronic device) having the electro-optical device as a display for display by improving the image quality of the electro-optical device.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, when an EL layer is formed by an inkjet method, the EL layer is continuously provided over a plurality of pixels. Specifically, EL layers are continuously formed in stripes for a selected column or row for pixel electrodes arranged in a matrix of m rows and n columns. Alternatively, an EL layer is formed in an oval shape or a rectangular shape corresponding to each pixel electrode.
[0010]
In the ink jet method, a predetermined pattern is formed by repeatedly performing operations of ink head position control and ink discharge (a solution containing the material when forming an EL layer). However, as the screen size increases and the pixel density increases, the processing time becomes enormous in the method of forming the EL layer corresponding to each pixel electrode. However, in the method of forming the stripe shape, the oval shape, or the rectangular shape as described above, the EL layer can be formed by continuously scanning the ink head, and the processing time can be shortened.
[0011]
In order to manufacture an EL display device for color display, EL layers corresponding to red, green, and blue colors may be formed in a stripe shape, an oval shape, or a rectangular shape. Such an EL layer and a manufacturing method of the EL layer can be applied to either an active matrix type or a passive matrix type.
[0012]
Furthermore, in the present invention, alkali metal diffusion from an EL element formed by an ink jet method is prevented by an insulating film (passivation film) provided between the EL element and the TFT. Specifically, an insulating film that prevents permeation of alkali metal is provided over the planarization film that covers the TFT. That is, the insulating film having a sufficiently low alkali metal diffusion rate at the operating temperature of the EL display device may be used.
[0013]
Preferably, an insulating film that does not transmit moisture and alkali metal and has high thermal conductivity (high heat dissipation effect) is selected, and this insulating film is provided in contact with the EL element, or more preferably, such an insulating film is used. The EL element is surrounded by a film. That is, an insulating film that has a blocking effect on moisture and alkali metal and has a heat dissipation effect is provided at a position as close as possible to the EL element, and the deterioration of the EL element is suppressed by the insulating film.
[0014]
In the case where such an insulating film cannot be used as a single layer, an insulating film having a blocking effect on moisture and alkali metal and an insulating film having a heat dissipation effect can be stacked and used. Furthermore, an insulating film having a blocking effect on moisture, an insulating film having a blocking effect on alkali metal, and an insulating film having a heat dissipation effect can be stacked and used.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
FIG. 1 is a diagram for explaining the concept of the present invention. FIG. 1A illustrates a structure in which a pixel portion 102, a scanning line side driver circuit 103, and a data line side driver circuit 104 are provided over a substrate 101. A separation layer 105 is provided in a stripe shape in the pixel portion 102, and an EL layer is formed between the separation layers. The separation layer 105 is provided to prevent adjacent EL layers from being mixed with each other when the EL layer is formed by an inkjet method.
[0016]
The EL layer 106 is formed by discharging a solution containing an EL material from the ink head 107. There is no particular limitation on the material of the EL layer, but EL layers 106R, 106G, and 106B corresponding to red, green, and blue may be provided to perform color display.
[0017]
FIG. 2 is a diagram illustrating details when an EL layer is formed in the pixel portion. In FIG. 2A, in the pixel portion 120, a plurality of current control TFTs 122 and a plurality of pixel electrodes 123 connected thereto are provided corresponding to each pixel, arranged in a matrix, and selected in one selected row or row. A state in which the EL layer 121 is formed in a stripe shape with respect to the pixel electrode is shown. In order to perform color display, EL layers 121R, 121G, and 121B corresponding to red, green, and blue may be provided as illustrated.
[0018]
Alternatively, the EL layer 124 may be formed in an oval or rectangular shape with respect to the current control TFTs 125 arranged in a matrix of the pixel portion 120 and the pixel electrodes 126 connected thereto. In order to perform color display, EL layers 124R, 124G, and 124B are similarly provided as shown in the figure.
[0019]
FIG. 1B is a cross-sectional structure diagram of the conceptual diagram illustrated in FIG. 1A, and illustrates a state where the scan line side driver circuit 103 and the pixel portion 102 are formed over the substrate 101. A separation layer 105 is formed in the pixel portion 102, and EL layers 106R, 106G, and 106B are formed between the separation layers. The ink head 107 is of an ink jet type, and ink dots 108R, 108G, and 108B corresponding to red, green, and blue colors are ejected in accordance with a control signal. The ejected ink dots 108R, 108G, and 108B adhere to the substrate and function as an EL layer through a subsequent drying or baking process. However, as shown in FIG. Is characterized by being formed on the substrate in a striped, oval or rectangular shape. Since the ink head may be scanned in one direction for each column or row, the processing time required for forming the EL layer can be shortened.
[0020]
FIG. 1C is a diagram for explaining the pixel portion in more detail. A current control TFT 110 and a pixel electrode 112 connected to the current control TFT 110 are provided on a substrate, and an EL layer 106R is provided on each pixel electrode. , 106G, 106B are formed between the separation layers 105. It is desirable that an insulating film 111 having a blocking effect on alkali metal is formed between the pixel electrode 112 and the current control TFT 110.
[0021]
FIG. 3 is a diagram illustrating the configuration of the ink head, and is an example in which a piezo method is adopted. FIG. 3A shows a piezoelectric element (piezoelectric element) 131, a housing 132, and an EL forming solution 133. When voltage is applied, the piezo element is deformed and the housing 132 is also deformed. As a result, as shown in FIG. 3B, the internal EL forming solution 133 is ejected as droplets 134. In this way, the EL forming solution is applied by controlling the voltage applied to the piezo element. In this case, since the EL forming solution 133 is pushed out by a physical external pressure, there is no influence on the composition or the like.
[0022]
FIG. 4 is also a diagram for explaining the concept of the present invention. The pixel portion 142 formed on the substrate 141 is provided with a first separation layer 145 and a second separation layer 146 orthogonal to the first separation layer 145. The EL layer 147 is formed in a portion surrounded by the first separation layer 145 and the separation layer 146. The first separation layer 145 and the second separation layer 146 are provided corresponding to each pixel electrode. The EL layer is formed by discharging an EL forming solution containing an EL material from the ink head 148. In order to perform color display, EL layers 148R, 148G, and 148B corresponding to red, green, and blue may be provided.
[0023]
[Embodiment 2]
The active matrix EL display device of the present invention will be described with reference to FIGS. FIG. 5 is a cross-sectional view of a pixel of an active matrix EL display device according to the present invention, FIG. 6A is a top view thereof, and FIG. 6B is a circuit configuration thereof. Actually, a plurality of such pixels are arranged in a matrix to form a pixel portion (image display portion).
[0024]
Note that the cross-sectional view of FIG. 5 shows a cut surface cut along AA ′ in the top view shown in FIG. Here, since common reference numerals are used in FIGS. 5 and 6, it is preferable to refer to both drawings as appropriate.
[0025]
In FIG. 5, 11 is a substrate, and 12 is an insulating film (hereinafter referred to as a base film) serving as a base. As the substrate 11, a glass substrate, a glass ceramic substrate, a quartz substrate, a silicon substrate, a ceramic substrate, a metal substrate, or a plastic substrate (including a plastic film) can be used.
[0026]
The base film 12 is particularly effective when a substrate containing mobile ions or a conductive substrate is used, but it need not be provided on the quartz substrate. As the base film 12, an insulating film containing silicon may be used. Note that in this specification, the “insulating film containing silicon” specifically includes silicon, oxygen, or nitrogen such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film (indicated by SiOxNy) at a predetermined ratio. An insulating film.
[0027]
In addition, it is effective to dissipate the heat generated by the TFT by providing the base film 12 with a heat dissipation effect in order to prevent the deterioration of the TFT or the EL element. In that case, an alloy material containing Al as a component, such as an oxide or nitride of aluminum (Al), may be used.
[0028]
Two TFTs are formed in the pixel. Reference numeral 201 denotes a TFT that functions as a switching element (hereinafter referred to as a switching TFT), and 202 denotes a TFT that functions as a current control element that controls the amount of current flowing to the EL element (hereinafter referred to as a current control TFT). Is also formed of an n-channel TFT.
[0029]
However, the switching TFT and the current control TFT need not be limited to the n-channel TFT, and a p-channel TFT can be used for both or one of them. In any case, the TFT may be selected depending on the polarity of the bias voltage applied to the EL element connected to the current control TFT.
[0030]
The switching TFT 201 includes a source region 13, a drain region 14, LDD regions 15a to 15d, an active layer including a high concentration impurity region 16 and channel forming regions 17a and 17b, a gate insulating film 18, gate electrodes 19a and 19b, and a first interlayer. An insulating film 20, a source wiring 21, and a drain wiring 22 are formed.
[0031]
Although not shown, the gate electrodes 19a and 19b may have a double gate structure in which the gate electrodes 19a and 19b are electrically connected by a gate line formed of another material (a material having a lower resistance than the gate electrodes 19a and 19b). By adopting a simple configuration, it is possible to cope with an increase in screen size. Needless to say, not only a double gate structure but also a so-called multi-gate structure (a structure including an active layer having two or more channel formation regions connected in series) such as a triple gate structure may be used. The multi-gate structure is extremely effective in reducing the off-current value. In the present invention, the switching element 201 of the pixel has a multi-gate structure to realize a switching element with a low off-current value.
[0032]
The active layer is formed of a semiconductor film including a crystal structure. That is, a single crystal semiconductor film, a polycrystalline semiconductor film, or a microcrystalline semiconductor film may be used. The gate insulating film 18 may be formed of an insulating film containing silicon. For the gate electrode, the source line, or the drain line, a known wiring material typified by Al, tantalum (Ta), tungsten (W), or the like can be used.
[0033]
Further, in the switching TFT 201, the LDD regions 15a to 15d are provided so as not to overlap the gate electrodes 17a and 17b with the gate insulating film 18 interposed therebetween. Such a structure is very effective in reducing the off-current value.
[0034]
Note that it is more preferable to provide an offset region (a region made of a semiconductor layer having the same composition as the channel formation region to which no gate voltage is applied) between the channel formation region and the LDD region in order to reduce the off-state current value. In the case of a multi-gate structure having two or more gate electrodes, a high-concentration impurity region provided between channel formation regions is effective in reducing the off-current value.
[0035]
As described above, a switching element having a sufficiently low off-state current value can be realized by using a TFT having a multi-gate structure as the switching element 201 of the pixel. Therefore, the gate voltage of the current control TFT can be maintained for a sufficient time (between the selection and the next selection) without providing a capacitor as shown in FIG. 2 of JP-A-10-189252.
[0036]
That is, it is possible to eliminate the capacitor that has been a factor for reducing the effective light emitting area, and it is possible to widen the effective light emitting area. This means that the image quality of the EL display device can be brightened.
[0037]
The current control TFT 202 includes an active layer including a source region 31, a drain region 32, an LDD region 33, and a channel formation region 34, a gate insulating film 18, a gate electrode 35, a first interlayer insulating film 20, a source wiring 36 and a drain wiring 37. Formed. The gate electrode 35 has a single gate structure, but may have a multi-gate structure.
[0038]
As shown in FIG. 6, the drain of the switching TFT is connected to the gate of the current control TFT. Specifically, the gate electrode 35 of the current control TFT 202 is electrically connected to the drain region 14 of the switching TFT 201 via the drain line (also referred to as connection wiring) 22. The source line 36 is connected to the power supply line 212.
[0039]
The current control TFT 202 is characterized in that the channel width is larger than the channel width of the switching TFT 201. That is, as shown in FIG. 12, when the channel length of the switching TFT is L1, the channel width is W1, the channel length of the current control TFT is L2, and the channel width is W2, W2 / L2 ≧ 5 × W1 / The relational expression L1 (preferably W2 / L2 ≧ 10 × W1 / L1) is established. For this reason, it is possible to easily flow more current than the switching TFT.
[0040]
Note that the channel length L1 of the switching TFT 201 having a multi-gate structure is the sum of the channel lengths of two or more formed channel formation regions. In the case of FIG. 12, since it has a double gate structure, the channel length L1 of the switching TFT 201 is obtained by adding the channel lengths L1a and L1b of the two channel formation regions.
[0041]
In the present invention, the channel lengths L1 and L2 and the channel widths W1 and W2 are not limited to specific numerical ranges, but W1 is 0.1 to 5 μm (typically 1 to 3 μm), and W2 is 0. The thickness is preferably 5 to 30 μm (typically 2 to 10 μm). At this time, L1 is preferably 0.2 to 18 μm (typically 2 to 15 μm), and L2 is preferably 0.1 to 50 μm (typically 1 to 20 μm).
[0042]
In the current control TFT 202, it is desirable to set the channel length L to be longer in order to prevent an excessive current from flowing. Preferably, W2 / L2 ≧ 3 (preferably W2 / L2 ≧ 5). Desirably, it is set to 0.5 to 2 μA (preferably 1 to 1.5 μA) per pixel.
[0043]
By setting these numerical ranges, all standards are covered, from EL display devices having the number of VGA class pixels (640 × 480) to EL display devices having the number of high-definition class pixels (1920 × 1080 or 1280 × 1024). be able to. The length (width) of the LDD region formed in the switching TFT 201 may be 0.5 to 3.5 μm, typically 2.0 to 2.5 μm.
[0044]
Further, in the EL display device shown in FIG. 5, in the current control TFT 202, an LDD region 33 is provided between the drain region 32 and the channel formation region 34, and the LDD region 33 is interposed through the gate insulating film 18. It is also characterized in that it has a region that overlaps with the gate electrode 35 and a region that does not overlap.
[0045]
The current control TFT 202 supplies a current for causing the EL element 204 to emit light, and at the same time controls the supply amount to enable gradation display. Therefore, it is necessary to take measures against deterioration by hot carrier injection so as not to deteriorate even when a large current is passed. In addition, when displaying black, the current control TFT 202 is turned off. However, if the off-current value is high, a clear black display cannot be obtained, resulting in a decrease in contrast. Therefore, it is necessary to suppress the off-current value.
[0046]
Regarding deterioration due to hot carrier injection, it is known that a structure in which an LDD region overlaps a gate electrode is very effective. However, if the entire LDD region is overlaid on the gate electrode, the off-current value increases. Therefore, the applicant has a novel structure in which LDD regions that do not overlap with the gate electrode are provided in series, thereby preventing hot carriers and off-current. It solves value measures at the same time.
[0047]
At this time, the length of the LDD region overlapping with the gate electrode may be 0.1 to 3 μm (preferably 0.3 to 1.5 μm). If it is too long, the parasitic capacitance is increased, and if it is too short, the effect of preventing hot carriers is weakened. The length of the LDD region that does not overlap with the gate electrode may be 1.0 to 3.5 μm (preferably 1.5 to 2.0 μm). If it is too long, it will not be possible to pass a sufficient current, and if it is too short, the effect of reducing the off-current value will be weak.
[0048]
Further, in the above structure, a parasitic capacitance is formed in a region where the gate electrode and the LDD region overlap with each other. Therefore, it is preferable not to provide between the source region 31 and the channel formation region 34. Since the current control TFT always has the same direction of carrier (electrons) flow, it is sufficient to provide an LDD region only on the drain region side.
[0049]
Further, from the viewpoint of increasing the amount of current that can be passed, the thickness of the active layer (especially the channel formation region) of the current control TFT 202 may be increased (preferably 50 to 100 nm, more preferably 60 to 80 nm). It is valid. Conversely, in the case of the switching TFT 201, from the viewpoint of reducing the off-current value, the thickness of the active layer (especially the channel formation region) should be reduced (preferably 20 to 50 nm, more preferably 25 to 40 nm). Is also effective.
[0050]
The film thickness of the first passivation film 41 may be 10 nm to 1 μm (preferably 200 to 500 nm). As a material, an insulating film containing silicon (in particular, a silicon nitride oxide film or a silicon nitride film is preferable) can be used. The passivation film 41 has a role of protecting the formed TFT from alkali metal and moisture. The EL layer finally provided above the TFT contains an alkali metal such as sodium. That is, the first passivation film 41 also functions as a protective layer that prevents these alkali metals (movable ions) from entering the TFT side.
[0051]
It is also effective to prevent thermal degradation of the EL layer by providing the first passivation film 41 with a heat dissipation effect. However, since the EL display device having the structure shown in FIG. 5 emits light toward the substrate 11, the first passivation film 41 needs to have translucency. In the case where an organic material is used for the EL layer, it is preferable that an insulating film that easily releases oxygen is not used because it deteriorates due to bonding with oxygen.
[0052]
As a translucent material that prevents alkali metal from passing through and has a heat dissipation effect, at least one element selected from B (boron), C (carbon), and N (nitrogen), Al (aluminum), Si ( And an insulating film containing at least one element selected from silicon and P (phosphorus). For example, aluminum nitride represented by aluminum nitride (AlxNy), silicon carbide represented by silicon carbide (SixCy), silicon nitride represented by silicon nitride (SixNy), and boron nitride (BxNy) Boron phosphide represented by boron nitride and boron phosphide (BxPy) can be used. In addition, an aluminum oxide typified by aluminum oxide (AlxOy) has excellent translucency and a thermal conductivity of 20 Wm. ^-1 K ^-1 It can be said that it is one of the preferable materials. These materials not only have the above effects, but also have an effect of preventing moisture from entering.
[0053]
Other elements can be combined with the above compound. For example, it is possible to use aluminum nitride oxide represented by AlNxOy by adding nitrogen to aluminum oxide. This material has not only a heat dissipation effect but also an effect of preventing moisture, alkali metal and the like from entering.
[0054]
Moreover, the material described in Unexamined-Japanese-Patent No. 62-90260 can be used. That is, an insulating film containing Si, Al, N, O, and M (where M is at least one of rare earth elements, preferably Ce (cerium), Yb (ytterbium), Sm (samarium), Er (erbium), Y ( Yttrium), La (lanthanum), Gd (gadolinium), Dy (dysprosium), and Nd (neodymium). These materials have not only a heat dissipation effect but also an effect of preventing intrusion of moisture, alkali metals, and the like.
[0055]
In addition, a carbon film including at least a diamond thin film or an amorphous carbon film (in particular, a material having characteristics close to diamond, called diamond-like carbon) can be used. These have very high thermal conductivity and are extremely effective as a heat dissipation layer. However, as the film thickness increases, the film becomes brownish and the transmittance decreases. Therefore, it is preferable to use the film as thin as possible (preferably 5 to 100 nm).
[0056]
Note that the purpose of the first passivation film 41 is to protect the TFT from alkali metals and moisture to the last, and therefore the effect thereof must not be impaired. Accordingly, a thin film made of a material having a heat dissipation effect can be used alone, but these thin films and an insulating film (typically a silicon nitride film (SixNy) or a nitridation oxide) that can prevent alkali metal or moisture from permeating. It is effective to stack a silicon film (SiOxNy).
[0057]
In addition, the EL display device can be roughly divided into four color display methods, a method of forming three types of EL elements corresponding to RGB, a method of combining a white light emitting EL element and a color filter, and blue or blue-green. There are a method in which a light-emitting EL element and a phosphor (fluorescent color conversion layer: CCM) are combined, and a method in which a transparent electrode is used as a cathode (counter electrode) and EL elements corresponding to RGB are stacked. Although only one pixel is shown in FIG. 5, pixels having the same structure are formed corresponding to the respective colors of red, green, and blue, so that color display can be performed. A known material may be used for the EL layers of these colors. However, the present invention can be carried out regardless of the light emission method, and all the above four methods can be used in the present invention.
[0058]
When the first passivation film 41 is formed, a second interlayer insulating film (which may be referred to as a planarizing film) 44 is formed so as to cover each TFT, and a step formed by the TFT is planarized. As the second interlayer insulating film 44, an organic resin film is preferable, and polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like may be used. Of course, an inorganic film may be used if sufficient planarization is possible.
[0059]
It is very important to flatten the step due to the TFT by the second interlayer insulating film 44. Since the EL layer to be formed later is very thin, the presence of a step may cause a crack in the portion or a short circuit between the anode and the cathode. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0060]
The second passivation film 45 plays an important role of blocking alkali metal diffusing from the EL element. The film thickness may be 5 nm to 1 μm (typically 20 to 300 nm). The second passivation film 45 is an insulating film that can prevent permeation of alkali metal. As the material, the material used as the first passivation film 41 can be used. The second passivation film 45 also functions as a heat dissipation layer that functions to release heat generated in the EL element and prevent the heat from accumulating in the EL element. In addition, when the second interlayer insulating film 44 is an organic resin film, it is vulnerable to heat, so that the heat generated in the EL element does not adversely affect the second interlayer insulating film 44. In addition, the second passivation film 45 functions as a protective layer for preventing the alkali metal in the EL layer from diffusing to the TFT side as well as preventing the deterioration due to the heat, and further to the EL layer side to the TFT side. It also functions as a protective layer that prevents moisture and oxygen from entering.
[0061]
As described above, it is effective to planarize a TFT with an organic resin film in manufacturing an EL display device, but there has not been a structure that takes into account deterioration of an organic resin film due to heat generated in an EL element. It can be said that the present invention solves this problem by providing the second passivation film 45.
[0062]
The pixel electrode (EL element anode) 46 is a transparent conductive film, and a contact hole (opening) is formed in the second passivation film 45, the second interlayer insulating film 44, and the first passivation film 41, and then the formed opening is formed. The hole is formed so as to be connected to the drain wiring 37 of the current control TFT 202.
[0063]
When the pixel electrode 46 is formed, the separation layer 101 made of an organic resin film is formed on the second passivation film 45. In this embodiment, a photosensitive polyimide film is formed by a spin coating method, and the separation layer 101 is formed by patterning. The separation layer 101 is a mold for forming an EL layer by an ink jet method, and the location where the EL element is formed is defined by the arrangement of the separation layer.
[0064]
After the separation layer 101 is formed, an EL layer (an organic material is preferable) 47 is then formed by an ink jet method. The EL layer 47 is used in a single layer or a laminated structure, but is often used in a laminated structure. Various laminated structures have been proposed by combining a light emitting layer, an electron transport layer, an electron injection layer, a hole injection layer, a hole transport layer, or the like, but any structure may be used in the present invention. Further, the EL layer may be doped with a fluorescent dye or the like.
[0065]
Any known EL material can be used in the present invention. As a known material, an organic material is widely known, and it is preferable to use an organic material in consideration of a driving voltage. As the organic EL material, for example, materials disclosed in the following US patents or publications can be used.
[0066]
U.S. Patent No. 4,356,429, U.S. Patent No. 4,539,507, U.S. Patent No. 4,720,432, U.S. Patent No. 4,769,292, U.S. Patent No. 4,885,211, US Patent No. 4,950,950, US Patent No. 5,059,861, US Patent No. 5,047,687, US Patent No. 5,073,446, US Patent No. 5,059,862, US Pat. No. 5,061,617, US Pat. No. 5,151,629, US Pat. No. 5,294,869, US Pat. No. 5,294,870, JP-A-10-189525, JP-A-10-189525 JP-A-8-241048, JP-A-8-78159.
[0067]
Specifically, as the organic material for the hole injection layer, those represented by the following general formula can be used.
[0068]
[Chemical 1]

[0069]
Where Q is N or C—R (carbon chain), M is a metal, metal oxide or metal halide, R is hydrogen, alkyl, aralkyl, allyl or alkaryl, T1, T2 are hydrogen, An unsaturated six-membered ring containing a substituent such as alkyl or halogen.
[0070]
An aromatic tertiary amine can be used as the organic material for the hole transport layer, and preferably includes tetraallyldiamine represented by the following general formula.
[0071]
[Chemical 2]

[0072]
Where Are is an arylene group, n is an integer of 1 to 4, Ar, R ₇ , R ₈ , R ₉ Are the selected allyl groups.
[0073]
In addition, a metal oxinoid compound can be used as the organic material for the EL layer, the electron transport layer, or the electron injection layer. What is necessary is just to use what is represented with the following general formulas as a metal oxinoid compound.
[0074]
[Chemical 3]

[0075]
Where R ₂ -R ₇ Can be replaced, and the following metal oxinoid compounds can also be used.
[0076]
[Formula 4]

[0077]
Where R ₂ -R ₇ Is as defined above, L ₁ -L _Five Is a group of carbohydrates containing 1 to 12 carbon elements and L ₁ , L ₂ Or L ₂ , L _Three Together can form a benzo ring. Moreover, the following metal oxinoid compounds may be used.
[0078]
[Chemical formula 5]

[0079]
Where R ₂ -R ₆ Can be replaced. As described above, the organic EL material includes a coordination compound having an organic ligand. However, the above example is an example of the organic EL material that can be used as the EL material of the present invention, and it is not absolutely necessary to limit to this.
[0080]
In the present invention, since an ink jet method is used as a method for forming an EL layer, polymer materials are often used as preferable EL materials. Typical polymer materials include polymer materials such as polyparaphenylene vinylene (PPV) and polyfluorene. For colorization, for example, cyanopolyphenylene vinylene is preferable for the red light emitting material, polyphenylene vinylene is preferable for the green light emitting material, and polyphenylene vinylene and polyalkylphenylene are preferable for the blue light emitting material.
[0081]
However, the above example is an example of the organic EL material that can be used as the EL material of the present invention, and it is not absolutely necessary to limit to this. With respect to the organic EL material that can be used in the ink jet method, all materials described in JP-A-10-012377 can be cited.
[0082]
The ink jet method is roughly classified into a bubble jet method (also referred to as a thermal ink jet method) and a piezo method, but the piezo method is desirable for carrying out the present invention.
[0083]
In addition, the shape when the EL material is actually applied on the pixel electrode is formed in an oval shape or a rectangular shape by continuously forming a stripe shape or a plurality of dots as shown in the first embodiment. The separation layer 101 has a function for preventing adjacent EL layers from mixing with each other when forming an EL layer by an inkjet method.
[0084]
In order to perform color display, as shown in FIG. 6, a red light emitting EL layer 47R, a green light emitting EL layer 47G, and a blue light emitting EL layer 47B are formed. At this time, each EL layer may be formed sequentially, or EL layers corresponding to red, green, and blue may be formed simultaneously. In addition, a baking (firing) treatment is necessary to remove the solvent contained in the EL forming solution. This baking process may be performed after all the EL layers are formed, or may be performed individually when the formation of the EL layers of the respective colors is completed. In this way, the EL layer is formed to a thickness of 50 to 250 nm.
[0085]
FIG. 21 illustrates a configuration of the pixel portion, and shows a state in which a plurality of pixel electrodes are formed in an EL layer formed in a stripe shape, an oval shape, or a rectangular shape. In FIG. 21A, a plurality of pixel electrodes are provided for EL layers 1702a and 1702b that emit light of different colors. Two TFTs, a switching TFT and a current control TFT, are connected to each pixel electrode. Further, the EL layers 1702a and 1702b are separated by a separation layer 1701. For multi-color display, one pixel 1710a is formed by combining the pixel electrodes 1703a and 1703b. Similarly, when the pixel 1710b is provided next to the pixel 1710b, if the interval is D, the value is 5 to 10 times the thickness of the EL layer. That is, the thickness is set to 250 to 2500 nm.
[0086]
FIG. 21B shows another configuration example. For example, a plurality of pixel electrodes are provided for EL layers 1705a, 1705b, and 1705c that emit light in different colors such as red, green, and blue. . These EL layers are separated by a separation layer 1704. For multi-color or RGB full color display, one pixel 1720a is formed by combining the pixel electrodes 1706a, 1706b, and 1706c. Similarly, when the pixel 1710b is provided next to the pixel 1710b, if the interval is D, the value is 5 to 10 times the thickness of the EL layer. That is, the thickness is set to 250 to 2500 nm. By doing so, the image display can be made clear.
[0087]
Further, when forming the EL layer 47, it is desirable that the treatment atmosphere is a dry atmosphere with as little moisture as possible, and is performed in an inert gas. Since the EL layer easily deteriorates due to the presence of moisture and oxygen, it is necessary to eliminate such factors as much as possible when forming the EL layer. For example, a dry nitrogen atmosphere or a dry argon atmosphere is preferable.
[0088]
After the EL layer 47 is formed by the ink jet method as described above, a cathode 48 and an auxiliary electrode 49 are formed next. In this specification, a light-emitting element formed using a pixel electrode (anode), an EL layer, and a cathode is referred to as an EL element.
[0089]
The cathode 48 uses a material containing magnesium (Mg), lithium (Li) or calcium (Ca) having a low work function. An electrode made of MgAg (a material in which Mg and Al are mixed at Mg: Ag = 10: 1) is preferably used. Other examples include MgAgAl electrodes, LiAl electrodes, and LiFAl electrodes. The auxiliary electrode 49 is an electrode provided for protecting the cathode 48 from external moisture and the like, and a material containing aluminum (Al) or silver (Ag) is used. The auxiliary electrode 48 also has a heat dissipation effect.
[0090]
Note that the EL layer 47 and the cathode 48 are desirably formed continuously in a dry inert atmosphere without being released to the atmosphere. This is because, when an organic material is used as the EL layer, it is very sensitive to moisture, so that moisture absorption when released to the atmosphere is avoided. Furthermore, it is better to continuously form not only the EL layer 47 and the cathode 48 but also the auxiliary electrode 49 thereon.
[0091]
The thickness of the third passivation film 50 may be 10 nm to 1 μm (preferably 200 to 500 nm). The purpose of providing the third passivation film 50 is mainly for the purpose of protecting the EL layer 47 from moisture. However, as with the second passivation film 45, a heat dissipation effect may be provided. Accordingly, the same material as the first passivation film 41 can be used as the forming material. However, in the case where an organic material is used for the EL layer 47, there is a possibility that the EL layer 47 may be deteriorated due to bonding with oxygen. Therefore, it is preferable not to use an insulating film that easily releases oxygen.
[0092]
Further, since the EL layer is vulnerable to heat as described above, it is desirable to form the film at as low a temperature as possible (preferably in a temperature range from room temperature to 120 ° C.). Therefore, the plasma CVD method, the sputtering method, the vacuum deposition method, the ion plating method, or the solution coating method (spin coating method) can be said to be a preferable film forming method.
[0093]
As described above, it is possible to sufficiently suppress the deterioration of the EL element only by providing the second passivation film 45, but it is more preferable that the EL element is referred to as the second passivation film 45 and the second passivation film 50. Surrounded by a two-layer insulating film sandwiched between them, moisture and oxygen are prevented from entering the EL layer, alkali metal diffusion from the EL layer is prevented, and heat accumulation in the EL layer is prevented. As a result, the EL layer can be further prevented from deteriorating and a highly reliable EL display device can be obtained.
[0094]
In addition, the EL display device of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 5, and TFTs having different structures are arranged in the pixels according to functions. As a result, a switching TFT having a sufficiently low off-current value and a current control TFT resistant to hot carrier injection can be formed in the same pixel, have high reliability, and can display a good image (operation) An EL display device with high performance is obtained.
[0095]
Although the multi-gate TFT is used as the switching TFT in the pixel structure of FIG. 5, the arrangement of the LDD region and the like need not be limited to those shown in FIG. The present invention having the above-described configuration will be described in more detail with the following examples.
[0096]
【Example】
[Example 1]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a TFT of a pixel portion and a driver circuit portion provided around the pixel portion will be described. However, in order to simplify the description, a CMOS circuit, which is a basic circuit, is illustrated with respect to the drive circuit.
[0097]
First, as shown in FIG. 7A, a base film 301 is formed to a thickness of 300 nm over a glass substrate 300. In this embodiment, a silicon nitride oxide film is stacked as the base film 302. At this time, the nitrogen concentration in contact with the glass substrate 300 is preferably set to 10 to 25 wt%.
[0098]
In addition, it is effective to provide an insulating film made of the same material as that of the first passivation film 41 shown in FIG. Since the current control TFT flows a large current, it easily generates heat, and it is effective to provide an insulating film having a heat dissipation effect as close as possible.
[0099]
Next, an amorphous silicon film (not shown) having a thickness of 50 nm is formed on the base film 301 by a known film formation method. Note that the semiconductor film is not limited to an amorphous silicon film, and any semiconductor film including an amorphous structure (including a microcrystalline semiconductor film) may be used. Further, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used. The film thickness may be 20 to 100 nm.
[0100]
Then, the amorphous silicon film is crystallized by a known technique to form a crystalline silicon film (also referred to as a polycrystalline silicon film or a polysilicon film) 302. Known crystallization methods include a thermal annealing method using an electric furnace, a laser annealing method using laser light, and a lamp annealing method using infrared light. In this embodiment, crystallization is performed by a laser annealing method using excimer laser light using XeCl gas.
[0101]
In this embodiment, a pulse oscillation type excimer laser beam processed into a linear shape is used. However, a rectangular shape, a continuous oscillation type argon laser beam, or a continuous oscillation type excimer laser beam may be used. . The light source of the laser light is not limited to the excimer laser, and the second harmonic or the third harmonic of the YAG laser may be used.
[0102]
In this embodiment, a crystalline silicon film is used as an active layer of a TFT, but an amorphous silicon film can also be used. However, since the current control TFT needs to pass a large current, it is advantageous to use a crystalline silicon film that easily allows a current to flow.
[0103]
It is effective to form the active layer of the switching TFT that needs to reduce the off current from an amorphous silicon film, and to form the active layer of the current control TFT from a crystalline silicon film. Since the amorphous silicon film has low carrier mobility, it is difficult for an electric current to flow and an off current is difficult to flow. That is, the advantages of both an amorphous silicon film that hardly allows current to flow and a crystalline silicon film that easily allows current to flow can be utilized.
[0104]
Next, as shown in FIG. 7B, a protective film 303 made of a silicon oxide film is formed on the crystalline silicon film 302 to a thickness of 130 nm. This thickness may be selected in the range of 100 to 200 nm (preferably 130 to 170 nm). Any other film may be used as long as it is an insulating film containing silicon. This protective film 303 is provided in order to prevent the crystalline silicon film from being directly exposed to plasma when an impurity is added and to enable fine concentration control.
[0105]
Then, resist masks 304 a and 304 b are formed thereon, and an impurity element imparting n-type (hereinafter referred to as an n-type impurity element) is added through the protective film 303. Note that as the n-type impurity element, an element typically belonging to Group 15, typically phosphorus or arsenic can be used. In this embodiment, phosphine (PH _Three ) Using a plasma doping method in which plasma is excited without mass separation, and phosphorus is 1 × 10 ¹⁸ atoms / cm ^Three Add at a concentration of Of course, an ion implantation method for performing mass separation may be used.
[0106]
In the n-type impurity regions 305 and 306 formed by this step, an n-type impurity element is 2 × 10 6. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three (Typically 5 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three ) Adjust the dose so that it is included at the concentration of
[0107]
Next, as shown in FIG. 7C, the protective film 303 is removed, and the added elements belonging to Group 15 are activated. As the activation means, a known technique may be used. In this embodiment, activation is performed by irradiation with excimer laser light. Of course, the pulse oscillation type or the continuous oscillation type may be used, and it is not necessary to limit to the excimer laser beam. However, since the purpose is to activate the added impurity element, it is preferable to irradiate with energy that does not melt the crystalline silicon film. Note that laser light may be irradiated with the protective film 303 attached. It should be noted that activation by the heat treatment may be used in combination with the activation of the impurity element by the laser beam. When activation by heat treatment is performed, heat treatment at about 450 to 550 ° C. may be performed in consideration of the heat resistance of the substrate.
[0108]
By this step, the end portion of the n-type impurity regions 305 and 306, that is, the boundary portion (junction portion) with the region to which the n-type impurity element existing around the n-type impurity regions 305 and 306 is not added becomes clear. . This means that when the TFT is later completed, the LDD region and the channel formation region can form a very good junction.
[0109]
Next, as shown in FIG. 7D, unnecessary portions of the crystalline silicon film are removed, and island-shaped semiconductor films (hereinafter referred to as active layers) 307 to 310 are formed.
[0110]
Next, as shown in FIG. 7E, a gate insulating film 311 is formed so as to cover the active layers 307 to 310. As the gate insulating film 311, an insulating film containing silicon with a thickness of 10 to 200 nm, preferably 50 to 150 nm may be used. This may be a single layer structure or a laminated structure. In this embodiment, a silicon nitride oxide film having a thickness of 110 nm is used.
[0111]
Next, a conductive film having a thickness of 200 to 400 nm is formed and patterned to form gate electrodes 312 to 316. Note that in this embodiment, the gate electrode and a wiring (hereinafter referred to as a gate wiring) electrically connected to the gate electrode are formed using different materials. Specifically, a material having a resistance lower than that of the gate electrode is used for the gate wiring. This is because a material that can be finely processed is used for the gate electrode, and a material that has a low wiring resistance is used for the gate wiring even though it cannot be finely processed. Of course, the gate electrode and the gate wiring may be formed of the same material.
[0112]
The gate electrode may be formed of a single-layer conductive film, but it is preferable to form a stacked film of two layers or three layers as necessary. Any known conductive film can be used as the material of the gate electrode. However, a material that can be finely processed as described above, specifically, that can be patterned to a line width of 2 μm or less is preferable.
[0113]
Typically, a film made of an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), conductive silicon (Si), or the element Nitride films (typically tantalum nitride films, tungsten nitride films, titanium nitride films), alloy films combining the above elements (typically Mo—W alloys, Mo—Ta alloys), or of the above elements A silicide film (typically a tungsten silicide film or a titanium silicide film) can be used. Of course, it may be used as a single layer or may be laminated. In this embodiment, a laminated film including a tantalum nitride (TaN) film having a thickness of 50 nm and a Ta film having a thickness of 350 nm is used. This may be formed by sputtering. Further, when an inert gas such as Xe or Ne is added as a sputtering gas, peeling of the film due to stress can be prevented.
[0114]
At this time, the gate electrodes 313 and 316 are formed so as to overlap part of the n-type impurity regions 305 and 306 with the gate insulating film 311 interposed therebetween. This overlapped portion later becomes an LDD region overlapping with the gate electrode.
[0115]
Next, as shown in FIG. 8A, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligning manner using the gate electrodes 312 to 316 as masks. The impurity regions 317 to 323 thus formed are adjusted so that phosphorus is added at a concentration of 1/2 to 1/10 (typically 1/3 to 1/4) of the n-type impurity regions 305 and 306. To do. Specifically, 1 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three (Typically 3x10 ¹⁷ ~ 3x10 ¹⁸ atoms / cm ^Three ) Is preferred.
[0116]
Next, as shown in FIG. 8B, resist masks 324a to 324c are formed so as to cover the gate electrodes and the like, and an n-type impurity element (phosphorus in this embodiment) is added to contain phosphorus at a high concentration. Impurity regions 325 to 331 are formed. Again phosphine (PH _Three The concentration of phosphorus in this region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ^{twenty one} atoms / cm ^Three ).
[0117]
In this step, the source region or drain region of the n-channel TFT is formed. However, in the switching TFT, a part of the n-type impurity regions 320 to 322 formed in the step of FIG. This remaining region corresponds to the LDD regions 15a to 15d of the switching TFT in FIG.
[0118]
Next, as shown in FIG. 8C, the resist masks 324a to 324c are removed, and a new resist mask 332 is formed. Then, a p-type impurity element (boron in this embodiment) is added to form impurity regions 333 and 334 containing boron at a high concentration. Here, diborane (B ₂ H ₆ 3 × 10 by ion doping method using ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three (Typically 5 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three B) Add boron to achieve a concentration.
[0119]
Note that the impurity regions 333 and 334 already have 1 × 10 6. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three However, the boron added here is added at a concentration at least three times that of phosphorus. Therefore, the n-type impurity region formed in advance is completely inverted to the P-type and functions as a P-type impurity region.
[0120]
Next, after removing the resist mask 332, the n-type or p-type impurity element added at each concentration is activated. As the activation means, furnace annealing, laser annealing, or lamp annealing can be used. In this embodiment, heat treatment is performed in an electric furnace in a nitrogen atmosphere at 550 ° C. for 4 hours.
[0121]
At this time, it is important to eliminate oxygen in the atmosphere as much as possible. This is because the presence of even a small amount of oxygen oxidizes the exposed surface of the gate electrode, which increases resistance and makes it difficult to make ohmic contact later. Therefore, the oxygen concentration in the treatment atmosphere in the activation step is 1 ppm or less, preferably 0.1 ppm or less.
[0122]
Next, when the activation process is completed, a gate line 335 having a thickness of 300 nm is formed as shown in FIG. As a material of the gate wiring 335, a metal film containing aluminum (Al) or copper (Cu) as a main component (occupying 50 to 100% as a composition) may be used. As the arrangement, the gate electrodes 314 and 315 (corresponding to the gate electrodes 19a and 19b in FIG. 2) of the switching TFT are formed so as to be electrically connected as in the gate wiring 211 in FIG.
[0123]
With such a structure, the wiring resistance of the gate wiring can be extremely reduced, so that an image display region (pixel portion) having a large area can be formed. That is, the pixel structure of this embodiment is extremely effective in realizing an EL display device having a screen size of 10 inches or more (or 30 inches or more) diagonally.
[0124]
Next, as shown in FIG. 9A, a first interlayer insulating film 336 is formed. As the first interlayer insulating film 336, an insulating film containing silicon may be used as a single layer, or a laminated film combined therewith may be used. The film thickness may be 400 nm to 1.5 μm. In this embodiment, a structure is formed in which a silicon oxide film having a thickness of 800 nm is stacked on a silicon nitride oxide film having a thickness of 200 nm.
[0125]
Further, a hydrogenation treatment is performed by performing a heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. This step is a step in which the dangling bonds of the semiconductor film are terminated with hydrogen by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. The hydrogenation process may be performed while the first interlayer insulating film 336 is formed. That is, after the 200 nm-thick silicon nitride oxide film is formed, the hydrogenation treatment may be performed as described above, and then the remaining 800 nm-thick silicon oxide film may be formed.
[0126]
Next, contact holes are formed in the first interlayer insulating film 336, and source wirings 337 to 340 and drain wirings 341 to 343 are formed. In this embodiment, this electrode is a laminated film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film 150 nm is continuously formed by sputtering. Of course, other conductive films may be used.
[0127]
Next, a first passivation film 344 is formed with a thickness of 50 to 500 nm (typically 200 to 300 nm). In this embodiment, a silicon nitride oxide film having a thickness of 300 nm is used as the first passivation film 344. This may be replaced by a silicon nitride film. Of course, it is possible to use the same material as that of the first passivation film 41 of FIG.
[0128]
Prior to the formation of the silicon nitride oxide film, H ₂ , NH _Three It is effective to perform plasma treatment using a gas containing isohydrogen. Hydrogen excited by this pretreatment is supplied to the first interlayer insulating film 336 and heat treatment is performed, whereby the film quality of the first passivation film 344 is improved. At the same time, since hydrogen added to the first interlayer insulating film 336 diffuses to the lower layer side, the active layer can be effectively hydrogenated.
[0129]
Next, a second interlayer insulating film 347 made of an organic resin is formed. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 346 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. The thickness is preferably 1 to 5 μm (more preferably 2 to 4 μm).
[0130]
Next, a second passivation film 348 having a thickness of 100 nm is formed on the second interlayer insulating film 347. In this embodiment, since an insulating film containing Si, Al, N, O, and La is used, diffusion of alkali metal from the EL layer provided thereon can be prevented. At the same time, moisture can be prevented from entering the EL layer and heat generated in the EL layer can be dispersed to suppress deterioration of the EL layer and planarization film (second interlayer insulating film) due to heat. .
[0131]
Then, a contact hole reaching the drain wiring 343 is formed in the second passivation film 348, the second interlayer insulating film 347, and the first passivation film 344, and a pixel electrode 349 is formed. In this embodiment, an indium tin oxide (ITO) film having a thickness of 110 nm is formed and patterned to form a pixel electrode. This pixel electrode 349 becomes the anode of the EL element. As other materials, an indium oxide / titanium film or an indium oxide / zinc film can be used.
[0132]
In this embodiment, the pixel electrode 349 is electrically connected to the drain region 331 of the current control TFT via the drain wiring 343. This structure has the following advantages.
[0133]
Since the pixel electrode 349 is in direct contact with an organic material such as an EL layer (light emitting layer) or a charge transport layer, mobile ions contained in the EL layer or the like may diffuse in the pixel electrode. That is, in the structure of this embodiment, the pixel electrode 349 is not directly connected to the drain region 331 which is a part of the active layer, and the penetration of the mobile ions into the active layer can be prevented by relaying the drain wiring 343. .
[0134]
Next, as shown in FIG. 9C, an EL layer 350 is formed by an inkjet method, and a cathode (MgAg electrode) 351 and an auxiliary electrode 352 are formed without being released to the atmosphere. At this time, it is preferable that the pixel electrode 349 is subjected to a heat treatment before the EL layer 350 and the cathode 351 are formed to completely remove moisture. In this embodiment, an MgAg electrode is used as the cathode of the EL element, but other known materials may be used.
[0135]
Note that the material described in Embodiment 2 can be used for the EL layer 350. For example, a four-layer structure including a hole injecting layer, a hole transporting layer, a light emitting layer (Emitting layer), and an electron transporting layer may be used as the EL layer. An electron transport layer may not be provided, and an electron injection layer may be provided. Further, the hole injection layer may be omitted. As described above, various examples of combinations have already been reported, and any of the configurations may be used.
[0136]
As the hole injection layer or the hole transport layer, an amine-based TPD (triphenylamine derivative) may be used. Besides, hydrazone (typically DEH), stilbene (typically STB), star A bust system (typically m-MTDATA) or the like can be used. In particular, a star bust material having a high glass transition temperature and being difficult to crystallize is preferable.
[0137]
As the light emitting layer, BPPC, perylene, and DCM can be used as the red light emitting layer, and in particular Eu (DBM). _Three The Eu complex represented by (Phen) (detailed in J. Kido et.al, Appl. Phys., Vol. 35, pp. L394-396, 1996) has sharp emission at a wavelength of 620 nm and high monochromaticity.
[0138]
Moreover, as a green light emitting layer, typically, Alq _Three (8-hydroxyquinoline alminium) to which a few mol% quinacridone or coumarin is added can be used. The chemical formula is as follows.
[0139]
[Chemical 6]

[0140]
As the blue light-emitting layer, a distyarylene amine derivative obtained by adding amino-substituted DSA to DSA (distyryarylene derivative) can be typically used. In particular, it is preferable to use distyrylbiphenyl (DPVBi), which is a high-performance material. The chemical formula is as follows.
[0141]
[Chemical 7]

[0142]
In addition, although the auxiliary electrode 352 can protect the EL layer 350 from moisture and oxygen, it is more preferable to provide a third passivation film 353. In this embodiment, a silicon nitride film having a thickness of 300 nm is provided as the third passivation film 353. This third passivation film may also be formed continuously after the auxiliary electrode 352 without being released to the atmosphere. Of course, as the third passivation film 353, the same material as that of the third passivation film 50 of FIG. 5 can be used.
[0143]
The auxiliary electrode 352 is provided to prevent the deterioration of the MgAg electrode 351, and a metal film containing Al as a main component is typical. Of course, other materials may be used. Further, since the EL layer 350 and the MgAg electrode 351 are very sensitive to moisture, it is desirable that the auxiliary electrode 352 be continuously formed without being released to the atmosphere to protect the EL layer from the outside air.
[0144]
Note that the thickness of the EL layer 350 may be 10 to 400 nm (typically 60 to 160 nm), and the thickness of the MgAg electrode 351 may be 180 to 300 nm (typically 200 to 250 nm). In the case where the EL layer 350 has a stacked structure, the thickness of each layer may be in the range of 10 to 100 nm.
[0145]
Thus, an active matrix EL display device having a structure as shown in FIG. 9C is completed. By the way, the active matrix EL display device of this embodiment can provide extremely high reliability and improve the operating characteristics by arranging TFTs having an optimal structure not only in the pixel portion but also in the drive circuit portion.
[0146]
First, a TFT having a structure that reduces hot carrier injection so as not to reduce the operating speed as much as possible is used as an n-channel TFT 205 of a CMOS circuit that forms a driving circuit. Note that the drive circuit here includes a shift register, a buffer, a level shifter, a sampling circuit (sample and hold circuit), and the like. In the case of performing digital driving, a signal conversion circuit such as a D / A converter may be included.
[0147]
In this embodiment, as shown in FIG. 9C, the active layer of the n-channel type 205 includes a source region 355, a drain region 356, an LDD region 357, and a channel formation region 358, and the LDD region 357 has gate insulation. The gate electrode 313 overlaps with the film 311 interposed therebetween.
[0148]
The reason why the LDD region is formed only on the drain region side is to prevent the operation speed from being lowered. In addition, the n-channel TFT 205 does not need to care about the off-current value, and it is better to focus on the operation speed than that. Therefore, it is desirable that the LDD region 357 is completely overlapped with the gate electrode and the resistance component is reduced as much as possible. That is, it is better to eliminate the so-called offset.
[0149]
In addition, since the p-channel TFT 206 of the CMOS circuit is hardly concerned about deterioration due to hot carrier injection, it is not particularly necessary to provide an LDD region. Needless to say, it is possible to provide an LDD region as in the case of the n-channel TFT 205 and take measures against hot carriers. Of the driving circuits, the sampling circuit is a little special compared to other circuits, and a large current flows bidirectionally in the channel formation region. That is, the roles of the source region and the drain region are interchanged. Furthermore, it is necessary to keep the off-current value as low as possible, and in that sense, it is desirable to dispose a TFT having an intermediate function between the switching TFT and the current control TFT.
[0150]
Therefore, it is desirable to dispose a TFT having a structure as shown in FIG. 13 as the n-channel TFT forming the sampling circuit. As shown in FIG. 13, part of the LDD regions 901a and 901b overlaps with the gate electrode 903 with the gate insulating film 902 interposed therebetween. This effect is as described in the description of the current control TFT 202, and is different in that the sampling circuit is provided so as to sandwich the channel formation region 904.
[0151]
In addition, a pixel portion is formed by forming a pixel having a structure as shown in FIG. Since the structure of the switching TFT and the current control TFT formed in the pixel has already been described with reference to FIG. 5, the description thereof is omitted here.
[0152]
Actually, when completed up to FIG. 9C, packaging with a housing material such as a highly airtight protective film (laminate film, UV curable resin film, etc.) or ceramic sealing can so as not to be exposed to the outside air ( (Encapsulation) is preferable. At that time, the reliability (life) of the EL layer is improved by making the inside of the housing material an inert atmosphere or disposing a hygroscopic material (for example, barium oxide) inside.
[0153]
In addition, when the airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting the terminal routed from the element or circuit formed on the substrate and the external signal terminal is attached. Completed as a product. In this specification, an EL display device that can be shipped is referred to as an EL module.
[0154]
Here, the configuration of the active matrix EL display device of this embodiment will be described with reference to the perspective view of FIG. The active matrix EL display device of this embodiment includes a pixel portion 602, a gate side driver circuit 603, and a source side driver circuit 604 formed on a glass substrate 601. The switching TFT 605 in the pixel portion is an n-channel TFT, and is arranged at the intersection of the gate wiring 606 connected to the gate side driving circuit 603 and the source wiring 607 connected to the source side driving circuit 604. The drain of the switching TFT 605 is connected to the gate of the current control TFT 608.
[0155]
Further, the source side of the current control TFT 606 is connected to the power supply line 609. In the structure as in this embodiment, a ground potential (ground potential) is applied to the power supply line 609. An EL element 610 is connected to the drain of the current control TFT 608. A predetermined voltage (10 to 12 V in this embodiment) is applied to the cathode of the EL element 610. The FPC 611 serving as an external input / output terminal is provided with input / output wirings (connection wirings) 612 and 613 for transmitting signals to the drive circuit, and input / output wiring 614 connected to the power supply line 609.
[0156]
FIG. 11 shows an example of a circuit configuration of the EL display device shown in FIG. The circuit configuration in FIG. 11 is an example of analog driving, and includes a source side driver circuit 701, a gate side driver circuit (A) 707, a gate side driver circuit (B) 711, and a pixel portion 706. Note that in this specification, the drive circuit is a generic name including a source side processing circuit and a gate side drive circuit.
[0157]
The source side driver circuit 701 includes a shift register 702, a level shifter 703, a buffer 704, and a sampling circuit (sample and hold circuit) 705. The gate side driver circuit (A) 707 includes a shift register 708, a level shifter 709, and a buffer 710. The gate side driver circuit (B) 711 has a similar structure.
[0158]
Here, the shift registers 702 and 708 have a driving voltage of 5 to 16 V (typically 10 V), and an n-channel TFT used in a CMOS circuit forming the circuit has a structure indicated by 205 in FIG. Is suitable.
[0159]
The level shifters 703 and 709 and the buffers 704 and 710 have a drive voltage as high as 14 to 16 V, but a CMOS circuit including the n-channel TFT 205 in FIG. 9C is suitable as in the shift register. In addition, it is effective in improving the reliability of each circuit that the gate wiring has a multi-gate structure such as a double gate structure or a triple gate structure. The sampling circuit 705 has a driving voltage of 14 to 16 V. However, since the source region and the drain region are inverted and the off current value needs to be reduced, a CMOS circuit including the n-channel TFT 208 in FIG. 13 is suitable. ing. The pixel portion 706 has a driving voltage of 14 to 16 V, and pixels having the structure shown in FIG.
[0160]
The above configuration can be easily realized by manufacturing a TFT according to the manufacturing steps shown in FIGS. In addition, in this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of this embodiment, other driving such as a signal dividing circuit, a D / A converter circuit, an operational amplifier circuit, and a γ correction circuit is performed. It is considered that logic circuits other than circuits can be formed on the same substrate, and further, a memory portion, a microprocessor, and the like can be formed.
[0161]
Further, the EL module of this embodiment including the housing material will be described with reference to FIGS. Note that the reference numerals used in FIGS. 10 and 11 are cited as necessary.
[0162]
In FIG. 14, 601 is a substrate, 602 is a pixel portion, 603 is a source side driver circuit, 604 is a gate side driver circuit, 612 is a pixel portion 602, source side driver circuit 603, and gate side driver circuit 604 are FPC (flexible printed circuit). ) Connection wiring for electrical connection to 611. In addition, the FPC is electrically connected to an external device, whereby an external signal can be input to the pixel portion 602, the source side driver circuit 603, and the gate side driver circuit 604. The pixel portion 602, the source side driver circuit 603, and the gate side driver circuit 604 are formed using thin film transistors (hereinafter referred to as TFTs) formed over a substrate 601. Note that a TFT having any structure may be used as the TFT. Of course, a known structure may be used. Further, a filler (not shown), a cover material 1407, a seal material (not shown), and a frame material 1408 are formed.
[0163]
Here, FIG. 15A shows a cross-sectional view taken along line AA ′ of FIG. 14 and FIG. 15B shows a cross-sectional view taken along line BB ′. 15A and 15B, the same reference numerals are used for the same portions as those in FIG.
[0164]
As shown in FIG. 15A, a pixel portion 602 and a driver circuit 603 are formed over a substrate 601, and the pixel portion 602 includes a plurality of current control TFTs 1501 and pixel electrodes 1502 electrically connected thereto. It is formed by pixels. The pixel electrode 1502 functions as an anode of the EL element. Further, an EL layer 1503 is formed so as to cover the pixel electrode 1502, and a cathode 1504 of an EL element is formed thereon.
[0165]
The cathode 1504 also functions as a wiring common to all pixels, and is electrically connected to the FPC 611 through the connection wiring 612. Further, all elements included in the pixel portion 602 and the driver circuit 603 are covered with a passivation film 1507.
[0166]
Further, a filler 1508 is provided so as to cover the EL element. This filler 1508 also functions as an adhesive for bonding the cover material 1407. As the filler 1508, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 1508 because the moisture absorption effect can be maintained.
[0167]
As the cover material 1407, a glass plate, an aluminum plate, a stainless steel plate, a FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 1508, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0168]
However, the cover material 1407 needs to have a light-transmitting property depending on a light emission direction from the EL element (light emission direction). That is, in the case of FIG. 15, light is radiated to the opposite side of the cover material 1407 so that the material is not limited. However, when radiated to the cover material 1407 side, a highly transparent member is used for the cover material 1407. .
[0169]
Next, after the cover material 1407 is bonded using the filler 1508, the frame material 1408 is attached so as to cover the side surface (exposed surface) of the filler 1508. The frame material 1408 is bonded by a seal material (functioning as an adhesive) 1509. At this time, a photocurable resin is preferably used as the sealant 1509, but a thermosetting resin may be used if the heat resistance of the EL layer permits. Note that the sealant 1509 is desirably a material that does not transmit moisture and oxygen as much as possible. Further, a desiccant may be added inside the sealing material 1509.
[0170]
By encapsulating the EL element in the filler 1508 using the above-described method, the EL element can be completely blocked from the outside, and a substance that promotes deterioration due to oxidation of the EL layer such as moisture or oxygen from the outside can be obtained. Intrusion can be prevented. Accordingly, a highly reliable EL display device can be manufactured.
[0171]
[Example 2]
In the first embodiment, an EL display device in which light emitted from an EL element is emitted to the substrate side on which a TFT is formed is shown. In this case, at least the region where the TFT is formed becomes a shadow, and the aperture ratio of the pixel portion is lowered accordingly. On the other hand, when the light emitted from the EL element is emitted upward (on the opposite side of the substrate on which the TFT is formed), it is easy to improve at least the aperture ratio.
[0172]
FIG. 18 shows a configuration of an EL display element that emits light upward. The configurations of the switching TFT 201 and the current control TFT 202 are the same as those in the second embodiment, and differences in other parts will be described here.
[0173]
A cathode side pixel electrode 949 connected to the drain side of the current control TFT 202 is formed on the second passivation film 945. The separation layer 951 is formed using an organic resin material. Then, the cathode 948 is formed using a material such as MgAg (a material in which Mg and Al are mixed at Mg: Ag = 10: 1), MgAgAl, LiAl, LiFAl, and the like.
[0174]
The EL layer 947 is also formed by an inkjet method in the same manner as in the first or second embodiment. Further, an anode side pixel electrode is formed of a transparent conductive film material such as ITO, and a third passivation film 950 is formed thereon, thereby completing an EL display element that emits light upward.
[0175]
[Example 3]
The method for manufacturing an EL layer by the inkjet method of the present invention and the manufactured EL layer can also be applied to a passive EL display device. The embodiment will be described with reference to FIG.
[0176]
In FIG. 16A, a substrate 1601 is a non-alkali glass substrate typified by Corning # 1737 glass substrate, a crystallized glass substrate, a soda lime glass substrate having a surface formed of silicon oxide or silicon nitride, a plastic substrate, or the like. Can be applied. A transparent electrode 1602 is formed to a thickness of 50 to 200 nm on the substrate 1601, and is divided into a plurality of strips by a technique such as etching or a lift-off method. The transparent electrode 1601 is made of ITO, ZnO, SnO ₂ And made of a material such as ITO-ZnO. Then, using an organic resin material such as polyimide, a separation layer 1603 is formed with a thickness of 0.5 to 2 μm so as to be in contact with a side end portion of the transparent electrode 1602 formed in a strip shape.
[0177]
The EL layer is used in a single layer or a stacked structure. The laminated structure is formed by a laminated structure in which a light emitting layer, an electron transport layer, an electron injection layer, a hole injection layer, or a hole transport layer are combined. In this embodiment, the hole injection layer and the light emitting layer are laminated. The structure is formed. First, as shown in FIG. 16B, a hole injection layer 1606 is formed. The hole injection layer is not always necessary, but it may be preferable to provide it for improving the light emission efficiency. As shown in Embodiment Mode 1, the material for the hole injection layer is formed of an organic material containing tetraallyldiamine. In this case as well, an ink jet method is used, and the solution 1605 discharged from the ink head 1604 is formed into an oval shape or a rectangular shape by connecting stripes or a plurality of dots between separation layers. Then, unnecessary moisture and the like are evaporated by heating to about 100 ° C. with a hot plate or the like.
[0178]
As shown in FIG. 16C, the light emitting layer is also formed by an ink jet method. In the case of performing color display, an ink head having cylinders of red, green, and blue colors is used, and an EL forming solution 1609 containing a light emitting material is discharged onto the hole injection layer. The light-emitting layer 1608 includes a polymer material such as a polyparaphenylene vinylene (PPV) type or a polyfluorene type as a preferable EL material. For colorization, for example, cyanopolyphenylene vinylene is preferable for the red light emitting material, polyphenylene vinylene is preferable for the green light emitting material, and polyphenylene vinylene and polyalkylphenylene are preferable for the blue light emitting material. In this manner, the light emitting layers 1608R, 1608G, and 1608B corresponding to the respective colors of red, green, and blue are formed in a stripe shape or a plurality of shapes in an oval shape or a rectangular shape. Also in the ink jet method, the work is performed in an inert gas atmosphere such as nitrogen or argon in order to prevent the EL material from being oxidized and deteriorated during the formation.
[0179]
The cathode material is formed of a material such as MgAg (a material in which Mg and Ag are mixed at Mg: Ag = 10: 1), MgAgAl, LiAl, LiFAl, or the like. This cathode material is typically formed with a thickness of 1 to 50 nm by vacuum deposition. Further, Al or the like is laminated thereon as an auxiliary electrode. The cathode layer 1610 in FIG. 16D has such a structure, and is formed in a strip shape using a mask member when forming each film. The cathode layer 1610 formed in a strip shape is formed so as to be substantially orthogonal to the transparent electrode 1602 formed in a strip shape. A passivation film 1611 is formed on the cathode layer 1610 using a silicon nitride film, a silicon nitride oxide film, or the like.
[0180]
Since the material for forming the EL layer shown here is vulnerable to moisture, moisture, and the like, it is desirable to seal with a housing material. The material of the housing material 1614 is preferably an insulating material such as glass or polymer. For example, amorphous glass (borosilicate glass, quartz, etc.), crystallized glass, ceramic glass, organic resin (acrylic resin, styrene resin, polycarbonate resin, epoxy resin, etc.), silicone resin Can be mentioned. Ceramics may also be used. Further, if the adhesive 1705 is an insulating substance, a metal material such as a stainless alloy can be used.
[0181]
The material of the adhesive 1612 that bonds the housing material 1614 to the substrate on which the EL layer is formed can be an adhesive such as an epoxy resin or an acrylate resin. Furthermore, a thermosetting resin or a photocurable resin can also be used as an adhesive. However, it is necessary that the material does not transmit oxygen and moisture as much as possible. The adhesive 1612 may be mixed with a desiccant 1613 such as barium oxide. In this manner, a passive EL display device can be formed.
[0182]
[Example 4]
An example of a thin film forming apparatus for forming an EL element is shown in FIG. FIG. 17 shows a polymer organic EL layer as a light emitting layer, a metal film containing an element belonging to Group 1 or 2 of the periodic table as a cathode layer, a conductive film such as Al as an auxiliary electrode, and a passivation film. It is an apparatus to be formed.
[0183]
In FIG. 17, reference numeral 401 denotes a transfer chamber for loading or unloading substrates, which is also called a load / unload chamber. A carrier 402 on which a substrate is set is disposed here. It should be noted that the transfer chamber 401 may be distinguished from substrate carry-in and substrate carry-out. Reference numeral 403 denotes a common chamber including a mechanism (hereinafter referred to as a transport mechanism) 405 for transporting the substrate 404. A robot arm or the like that handles the substrate is a kind of the transport mechanism (1) 405.
[0184]
A plurality of processing chambers are connected to the common chamber 403 through gates 406a to 406f. In the configuration of FIG. 17, the common chamber 403 is depressurized from several mTorr to several tens of mTorr, and each processing chamber is isolated from the common chamber 403 by gates 406a to 406f. In this case, since the processing chamber for ink-jet printing 415 and the processing chamber for spin coating 408 are performed under normal pressure filled with an inert gas such as nitrogen or argon, the processing chamber 412 for evacuation between the common chamber 403 is used. Is provided.
[0185]
It is possible to perform processing under vacuum by providing an exhaust pump in each processing chamber that performs a predetermined operation under reduced pressure. As the exhaust pump, an oil rotary pump, a mechanical booster pump, a turbo molecular pump, or a cryopump can be used, but a cryopump effective for removing water is preferable.
[0186]
The EL layer formed of a light emitting layer or an injection layer is formed in the ink jet printing processing chamber 415 or the spin coating processing chamber 408. The ink jet printing processing chamber 415 is provided with a substrate holding means, the ink head described with reference to FIG. Further, as described above, since the organic EL material is extremely sensitive to moisture, the inkjet printing processing chamber 415 and the spin coating processing chamber 408 are always kept in an inert atmosphere.
[0187]
In transferring the substrate, first, the evacuation processing chamber 412 is depressurized to the same pressure as the common chamber 403, and in that state, the gate 406d is opened to transfer the substrate. After closing the gate 406d, the inside of the processing chamber 412 for evacuation is purged with an inert gas. When the pressure returns to normal pressure, the gate 413 is opened and the substrate is transferred by the transfer mechanism (2) 418 in the substrate transfer chamber 414. Are transferred to the ink jet printing processing chamber 415 and the spin coating processing chamber 408.
[0188]
In the present invention, the organic EL layer is formed by an ink jet method, but a light emitting layer is formed by an ink jet method, and some layers such as a hole or electron injection layer or a hole or electron transport layer are formed by a spin coat method. It may be formed by properly combining the two, such as forming.
[0189]
When the EL layer formation step is completed, the gate 413 is opened, the substrate is transferred to the processing chamber 412 for evacuation, and evacuation is performed with the gate 413 and the gate 406d closed. When the vacuum evacuation treatment chamber 412 reaches the same pressure reduction state as the common chamber 403, the gate 406d is opened and the substrate is transferred to the common chamber.
[0190]
Note that although the firing processing chamber 409 is provided here, the firing step may be performed so that the susceptor of the vacuum exhaust processing chamber 412 can be heated. Degassing can be suppressed by evacuation after firing.
[0191]
In the first film formation chamber 410, a cathode is formed. As the cathode material, a known material is used. The cathode is formed by a vacuum deposition method. At that time, the substrate surface (the surface on which the polymer EL layer is formed) may be upward (face-up method) or downward (face-down method).
[0192]
In the case of the face-up method, the substrate transferred from the common chamber 403 is simply installed on the susceptor as it is, which is very simple. In the case of the face-down method, the transport mechanism (1) 405 or the first film formation processing chamber 410 needs to be provided with a mechanism for inverting the substrate. The advantage of less is obtained.
[0193]
In addition, when performing a vapor deposition process in the 1st film-forming process chamber 110, it is necessary to provide the vapor deposition source. A plurality of vapor deposition sources may be provided. Further, a resistance heating type vapor deposition source or an EB (electron beam) type vapor deposition source may be used.
[0194]
The second deposition process chamber 411 is a process chamber for forming electrodes by a vapor deposition method. Here, an auxiliary electrode for assisting the cathode is formed. Further, a vapor deposition method or a sputtering method is used, but the vapor deposition method is preferable because it is less likely to cause damage. In any case, the common chamber 403 is cut off by the gate 406f, and film formation is performed under vacuum. In addition, when performing a vapor deposition method as a vapor-phase film-forming method, it is necessary to provide a vapor deposition source. Since the vapor deposition source may be the same as that of the first vapor phase film deposition processing chamber 410, description thereof is omitted here.
[0195]
A metal film often used as a cathode is a metal film containing an element belonging to Group 1 or Group 2 of the periodic table. However, since these metal films are easily oxidized, it is desirable to protect the surface. In addition, since the necessary film thickness is thin, a conductive film having a low resistivity is supplementarily provided to lower the resistance of the cathode, and in addition, the cathode is protected. As the conductive film having a low resistivity, a metal film containing aluminum, copper, or silver as a main component is used.
[0196]
Next, the third film formation processing chamber 407 is a processing chamber for forming a third passivation film. As the third passivation film, a silicon nitride film, a silicon nitride oxide film, or the like is formed by a plasma CVD method. Therefore, although not shown, SiH _Four , N ₂ O, NH _Three A gas supply system such as a plasma generating means using a high frequency power source of 13.56-60 MHz, a substrate heating means, and the like are provided. Since an EL layer made of an organic material is vulnerable to moisture or moisture, it is preferable to continuously provide such a passivation film without exposing it to the air atmosphere after the EL layer is formed.
[0197]
The greatest feature of the thin film forming apparatus having the above configuration is that it is performed by an ink jet method for forming an EL layer, and the means for that purpose is mounted on a multi-chamber type thin film forming apparatus together with a means for forming a cathode. It is in. Therefore, it is possible to start from the step of oxidizing the surface of the anode made of the transparent conductive film to the step of forming the auxiliary electrode without being exposed to the outside air. As a result, it is possible to form a polymer EL layer that is resistant to deterioration by simple means, and a highly reliable EL display device can be manufactured.
[0198]
[Example 5]
In the first embodiment, laser crystallization is used as a means for forming the crystalline silicon film 302. In this embodiment, a case where a different crystallization means is used will be described.
[0199]
In this embodiment, after an amorphous silicon film is formed, crystallization is performed using the technique described in Japanese Patent Laid-Open No. 7-130652. The technique described in this publication is a technique for obtaining a crystalline silicon film having high crystallinity by using an element such as nickel as a catalyst for promoting (promoting) crystallization.
[0200]
Further, after the crystallization step is completed, a step of removing the catalyst used for crystallization may be performed. In that case, the catalyst may be gettered by the technique described in JP-A-10-270363 or JP-A-8-330602. Further, a TFT may be formed using the technique described in the application specification of Japanese Patent Application No. 11-076967 by the present applicant.
[0201]
As described above, the manufacturing process described in Example 1 is one example, and other manufacturing processes can be used as long as the structure of FIG. 5 or FIG. 9C of Example 1 can be realized. No problem. In addition, the structure of a present Example can be freely combined with any structure of Embodiment 2 and Examples 1-2.
[0202]
[Example 6]
An active matrix EL display device or a passive EL display device (EL module) formed by implementing the present invention is a self-luminous type, and thus has better visibility in a bright place than a liquid crystal display device. Therefore, the application is wide as a direct-view type EL display device (referring to a display device incorporating an EL module).
[0203]
Note that one of the advantages of the EL display device over the liquid crystal display device is a wide viewing angle. Therefore, in order to watch TV broadcasts or the like on a large screen, the EL display device of the present invention may be used as a display device (display monitor) having a diagonal of 30 inches or more (typically 40 inches or more).
[0204]
Moreover, it can be used not only as an EL display device (a personal computer monitor, a TV broadcast reception monitor, an advertisement display monitor, etc.) but also as a display device for various electronic devices. Such electronic devices include video cameras, digital cameras, goggle-type displays (head-mounted displays), car navigation systems, personal computers, personal digital assistants (such as mobile computers, mobile phones or electronic books), and images with recording media. A playback device (specifically, a device provided with a display capable of playing back a recording medium such as a compact disc (CD), a laser disc (LD), or a digital video disc (DVD) and displaying an image thereof). Examples of these semiconductor devices are shown in FIGS.
[0205]
FIG. 19A illustrates an EL display, which includes a housing 2001, a support base 2002, a display portion 2003, and the like. The EL display device of the present invention can be used for the display portion 2003. The EL display device of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly, a diagonal of 30 inches or more).
[0206]
FIG. 19B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like. The EL display device of the present invention can be used for the display portion 2102.
[0207]
FIG. 19C illustrates a head-mounted display, which includes a main body 2201, a signal cable 2202, a fixed band 2203, a display portion 2204, an optical system 2205, an EL display device 2206, and the like. This is a configuration in which image information projected on the EL display device 2206 is projected on the display portion 2204 by an optical system, and the present invention can be used for the display device 2206.
[0208]
FIG. 19D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium, which includes a main body 2301, a recording medium (CD, LD, DVD, etc.) 2302, an operation switch 2303, and a display unit (a). 2304, a display unit (b) 2305, and the like. The display unit (a) mainly displays image information, and the display unit (b) mainly displays character information. The EL display device of the present invention can be used for these display units (a) and (b). Note that the present invention can be used for a CD playback device, a game machine, or the like as an image playback device including a recording medium.
[0209]
FIG. 19E illustrates a portable (mobile) computer, which includes a main body 2401, a camera portion 2402, an image receiving portion 2403, operation switches 2404, a display portion 2405, and the like. The EL display device of the present invention can be used for the display portion 2405.
[0210]
FIG. 19F illustrates a personal computer, which includes a main body 2501, a display portion 2503, a keyboard 2504, and the like. The EL display device of the present invention can be used for the display portion 2503.
[0211]
FIG. 20A illustrates a mobile phone, which includes a main body 2601, an audio output portion 2602, an audio input portion 2603, a display portion 2604, operation switches 2605, an antenna 2606, and the like. The EL display device of the present invention has low power consumption and can be preferably used for the display portion 2604.
[0212]
FIG. 20B illustrates an on-vehicle audio device, which includes a main body 2701, a display portion 2702, operation switches 2703, 2704, and the like. Since the EL display device of the present invention has a wide viewing angle and is excellent in visibility, it can be suitably used for the display portion 2702.
[0213]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-5.
[0214]
[Example 7]
FIG. 22 shows a micrograph of a sample in which an EL layer is formed using the ink jet system of the present invention. In the structure of the sample, pixel electrodes made of ITO are provided on an insulating film made of acrylic resin, and separation layers made of photosensitive acrylic resin are provided in stripes.
[0215]
A PEDOT layer is first formed on ITO by a solution coating method (spin coating method). At that time, since ITO is hydrophobic, oxygen plasma treatment and CF _Four Plasma treatment is performed.
[0216]
The EL layer is formed by an inkjet method using 20 mg of anisole and PPV dissolved at a ratio of 0.04 g. The interval between the separation layers is 90 μm, and it can be seen that the EL layers are continuously formed therebetween. In this way, the formation of the EL layer can be processed easily and at high speed.
[0217]
【The invention's effect】
By using the present invention, the EL layer can be formed easily and at high speed. In addition, the EL element can be prevented from being deteriorated by moisture or heat. Further, it is possible to prevent the alkali metal from diffusing from the EL layer and adversely affecting the TFT characteristics. As a result, the operation performance and reliability of the EL display device can be greatly improved.
[0218]
In addition, by having such an EL display device as a display display, it is possible to produce an application product (electronic device) having good image quality and durability (high reliability).
[Brief description of the drawings]
FIG. 1 is a view for explaining a concept of continuously forming an EL layer by an ink jet method of the present invention.
FIG. 2 is a diagram for explaining a concept of forming an EL layer in a stripe shape or continuously for each pixel electrode arranged in a matrix.
FIG. 3 is a diagram for explaining an ink jet method.
FIG. 4 is a view for explaining the concept of continuously forming an EL layer by the inkjet method of the present invention.
FIG. 5 illustrates a cross-sectional structure of a pixel portion of an EL display device.
FIGS. 6A and 6B illustrate a top structure and a structure of a pixel portion of an EL display device. FIGS.
FIGS. 7A to 7C illustrate a manufacturing process of an active matrix EL display device. FIGS.
FIG. 8 illustrates a manufacturing process of an active matrix EL display device.
FIG. 9 illustrates a manufacturing process of an active matrix EL display device.
FIG. 10 is a diagram showing the appearance of an EL module.
FIG. 11 is a diagram showing a circuit block configuration of an EL display device.
FIG. 12 is an enlarged view of a pixel portion of an EL display device.
FIG. 13 is a diagram showing an element structure of a sampling circuit of an EL display device.
FIG. 14 is a top view showing an EL module.
FIG. 15 is a cross-sectional view illustrating a sealing structure of an EL display device.
FIG. 16 illustrates a manufacturing process of a passive EL display device.
FIGS. 17A and 17B illustrate a device structure for manufacturing an EL display device. FIGS.
FIG 18 illustrates a cross-sectional structure of a pixel portion of an EL display device.
FIG. 19 illustrates a specific example of an electronic device.
FIG. 20 illustrates a specific example of an electronic device.
FIG. 21 is a diagram illustrating a pixel arrangement of a pixel portion.
FIG. 22 is a micrograph of a sample in which an EL layer is continuously formed by the inkjet method of the present invention.

Claims (2)

Forming a pixel portion and a drive circuit portion in which a plurality of TFTs are formed;
Forming a third insulating film made of aluminum oxide or aluminum nitride oxide on the pixel portion and the drive circuit portion;
Forming an organic resin film on the third insulating film;
Forming a first insulating film made of aluminum oxide or aluminum nitride oxide in contact with the organic resin film;
Forming a plurality of first electrodes arranged in a matrix in contact with the first insulating film;
By continuously ejecting ink dots from the ink head while continuously scanning the ink head in one direction for each column or row of the matrix, a striped EL for each column or row of the matrix Forming a layer,
Forming a second electrode on the EL layer;
Forming an auxiliary electrode made of a material containing aluminum or silver in contact with the second electrode;
Forming a second insulating film made of aluminum oxide or aluminum nitride oxide in contact with the auxiliary electrode;
The driving circuit section is provided with a plurality of CMOS circuits having an n-channel TFT and a p-channel TFT,
In the CMOS circuit other than the sampling circuit, the n-channel type TFT has an LDD region overlapping the only gate electrode is provided on only the drain region side, not provided with an LDD region in the p-channel type TFT,
In the CMOS circuit used for the sampling circuit, the n-channel type TFT is provided in both LDD region on the drain region side and a source region side having both a region which does not overlap with the region overlapping the gate electrode, p-channel A manufacturing method of an electro-optical device, wherein an LDD region is not provided in a type TFT. Forming a pixel portion and a drive circuit portion in which a plurality of TFTs are formed;
Forming a third insulating film made of aluminum oxide or aluminum nitride oxide on the pixel portion and the drive circuit portion;
Forming an organic resin film on the third insulating film;
Forming a first insulating film made of aluminum oxide or aluminum nitride oxide in contact with the organic resin film;
Forming a plurality of first electrodes arranged in a matrix in contact with the first insulating film;
By continuously ejecting ink dots from the ink head while continuously scanning the ink head in one direction for each column or row of the matrix, the first for each column or row of the matrix. Forming a plurality of oval or rectangular EL layers corresponding to each of the electrodes;
Forming a second electrode on the EL layer;
Forming an auxiliary electrode made of a material containing aluminum or silver in contact with the second electrode;
Forming a second insulating film made of aluminum oxide or aluminum nitride oxide in contact with the auxiliary electrode;
The driving circuit section is provided with a plurality of CMOS circuits having an n-channel TFT and a p-channel TFT,
In the CMOS circuit other than the sampling circuit, the n-channel type TFT has an LDD region overlapping the only gate electrode is provided on only the drain region side, not provided with an LDD region in the p-channel type TFT,
In the CMOS circuit used for the sampling circuit, the n-channel type TFT is provided in both LDD region on the drain region side and a source region side having both a region which does not overlap with the region overlapping the gate electrode, p-channel A manufacturing method of an electro-optical device, wherein an LDD region is not provided in a type TFT.

Images