JP4778667B2 - Sheet material for underfill, semiconductor chip underfill method, and semiconductor chip mounting method - Google Patents
Sheet material for underfill, semiconductor chip underfill method, and semiconductor chip mounting method Download PDFInfo
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- JP4778667B2 JP4778667B2 JP2002531444A JP2002531444A JP4778667B2 JP 4778667 B2 JP4778667 B2 JP 4778667B2 JP 2002531444 A JP2002531444 A JP 2002531444A JP 2002531444 A JP2002531444 A JP 2002531444A JP 4778667 B2 JP4778667 B2 JP 4778667B2
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- Prior art keywords
- underfill
- wafer
- semiconductor chip
- resin layer
- underfill resin
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- 239000004065 semiconductor Substances 0.000 title claims description 67
- 239000000463 material Substances 0.000 title claims description 52
- 238000000034 method Methods 0.000 title claims description 39
- 229920005989 resin Polymers 0.000 claims description 109
- 239000011347 resin Substances 0.000 claims description 109
- 239000010410 layer Substances 0.000 claims description 63
- 239000000758 substrate Substances 0.000 claims description 30
- 239000000853 adhesive Substances 0.000 claims description 15
- 230000001070 adhesive effect Effects 0.000 claims description 13
- 238000003825 pressing Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 52
- 238000010586 diagram Methods 0.000 description 13
- 238000010030 laminating Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000000428 dust Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- BZHJMEDXRYGGRV-UHFFFAOYSA-N Vinyl chloride Chemical compound ClC=C BZHJMEDXRYGGRV-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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Description
【技術分野】
【0001】
本発明は、半導体チップに設けられたバンプのバンプ間を埋めるために用いるアンダーフィル用シート材、半導体チップのアンダーフィル方法および半導体チップの実装方法に関する。
【背景技術】
【0002】
半導体チップを基板(配線基板、パッケージを含む)に実装する場合、半導体チップにバンプを形成し、このバンプを介して半導体チップを基板にフリップチップ実装する方法がある。
この場合、半導体チップの回路面の保護、バンプの腐植防止、チップと基板との接合強度の向上等のため、チップと基板との間に、絶縁材料からなるアンダーフィル樹脂材を充填するようにしている。
この樹脂材の充填は、一般的には、液状の樹脂材をディスペンサーを用いて、個々の半導体チップ毎に充填するようにしている。しかしながら、この方法では、非常に多くの作業時間を要する。またディスペンサーでは樹脂の供給量が不安定であり、未充填個所が残ったり、逆に樹脂のはみ出しが多くなったりする課題がある。
【0003】
この課題を解決するものとして、例えば、特開平5−55278号公報に示されるように、ウエハにバンプを形成した状態で、シート状に形成したアンダーフィル樹脂材(樹脂層)をバンプが形成されたウエハ面に押し付け、バンプをアンダーフィル樹脂材に埋没させるようにする方法が知られている。これによれば、ウエハの段階で一括してアンダーフィル樹脂材を供給でき、作業効率の大幅な改善ができる。
上記のようにアンダーフィル樹脂材を供給した後、アンダーフィル樹脂材と共にウエハをダイシングし、アンダーフィル樹脂材付きの個片の半導体チップに分離できる。
このように分離した半導体チップを実装基板に実装し、アンダーフィル樹脂材を熱硬化させればよいのである。
【0004】
また、特開平8−288293号公報に示される方法では、ウエハにバンプを形成した段階で、バンプの上部が突出するように、ウエハの上面に樹脂封止膜をスピンコートして形成した後、ウエハを個片の半導体チップに切断、分離するようにしている。
【0005】
また、特開2000−299333号公報に示される方法では、バンプが形成されたウエハ面に封止用樹脂シートを載置し、加熱下で、ウエハと封止用樹脂シートとを貼り合わせ、その後ウエハを個片の半導体チップに切断、分離するようにしている。
【0006】
さらに、特開2000−195901号公報に示される方法では、樹脂層が形成された支持フイルムを樹脂層がウエハ表面と接触するように熱圧着し、次いで樹脂層を光硬化し、支持フイルムを剥離した後、ウエハを個片の半導体チップに切断、分離するようにしている。
【発明の概要】
【発明が解決しようとする課題】
【0007】
しかしながら、例えば、上記特開平5−55278号公報に示される方法では、図20〜図22に示す工程によらなければならない。
すなわち、まず、図20に示すように、剥離シート10上に形成されたアンダーフィル樹脂層12を、バンプ13が形成されたウエハ14の面に押し付けてアンダーフィル樹脂層12にバンプ13を埋没させ、剥離シート10を剥離して、アンダーフィル樹脂材付きのウエハ14(図21)を得る。
このウエハ14をダイシングするために、公知の、接着剤付きのダイシングフイルム15上に、ウエハ14とリングフレーム16とを固定し(図22)、リングフレーム16を介してダイシング装置(図示せず)に装着し、ダイシングフイルム15を切り込まない状態にウエハ14をアンダーフィル樹脂層12と共に個片の半導体チップに切断、分離するのである。
ダイシングフイルム15は、紫外線を照射することによって、接着剤はその接着力を低下させるので、ダイシングフイルム15から、個片にした、アンダーフィル樹脂材付きの半導体チップを容易に取り出すことができる。
【0008】
しかしながら、この工程では、ウエハ14にアンダーフィル樹脂層12を押し付けて、アンダーフィル樹脂材付きのウエハ14を得る工程と、このウエハ14をダイシングフイルム15に接着する工程との2段階の別工程が必要となり、工数が増大して、それだけコストの上昇を招くという課題がある。
上記他の3つの従来方法の場合にも、同様に、アンダーフィル樹脂材付きのウエハ14を得る工程と、このウエハ14をダイシングフイルム15に接着する工程との2段階の別工程が必要となるという課題がある。
そこで、本発明は上記課題を解決すべくなされたものであり、その目的とするところは、工数を減じ、コストの低減化が図れる、アンダーフィル用シート材、半導体チップのアンダーフィル方法および半導体チップの実装方法を提供するにある。
【課題を解決するための手段】
【0009】
本発明に係る半導体チップのアンダーフィル方法では、半導体チップに設けられたバンプ間をアンダーフィル樹脂材で埋める半導体チップのアンダーフィル方法において、ウエハの表面を覆うことのできる大きさのアンダーフィル樹脂層の両面に、該アンダーフィル樹脂層よりも大きく、アンダーフィル樹脂層から剥離可能な剥離シートが積層され、一方の剥離シートの外面に、前記アンダーフィル樹脂層よりも大きく、接着剤が塗布されたダイシングフイルムが該接着剤により貼付されているアンダーフィル用シート材を用い、該アンダーフィル用シート材の前記ダイシングフィルムと前記一方の剥離シートとを剥離すると共に該一方の剥離シートを除去する工程と、該一方の剥離シートが除去された、前記アンダーフィル用シート材の前記アンダーフィル樹脂層側と、剥離された前記ダイシングフィルムの接着剤層側との間に、バンプを前記アンダーフィル樹脂層側に向けてウエハと、該ウエハを囲むリングフレームとを配置する工程と、前記ウエハとリングフレームとを介在させて、前記ダイシングフイルムと他方の剥離シートとを押圧し、ウエハとリングフレームとを前記ダイシングフレームに接着すると共に、ウエハのバンプを前記アンダーフィル樹脂層に埋没させる押圧工程と、前記他方の剥離シートを剥離する剥離工程とを含むことを特徴としている。
このように、本発明では、ウエハへのアンダーフィル樹脂層の積層と、ウエハおよびリングフレームのダイシングフイルムへの接着とを同一の工程で行えるので、工数が減じられ、コストの低減化を図ることができる。また、ウエハのハンドリングも容易となる。
【図面の簡単な説明】
【0010】
図1は、ダイシングフイルムを剥離した状態のアンダーフィル用シート材の説明図、
図2は、アンダーフィル用シート材から、ダイシングフイルムと剥離シートを剥離した状態の説明図、
図3は、押圧ローラにより、ウエハとアンダーフィル樹脂層とを加圧する工程の説明図、
図4は、リングフレームにウエハが支持された状態を示す説明図、
図5は個片に分離された状態の半導体チップの説明図、
図6は半導体チップを基板に実装する工程の説明図、
図7は基板に半導体チップが実装された状態を示す説明図、
図8は幅広の第1のブレードによるダイシング工程を示す説明図、
図9は幅狭の第2のブレードによるダイシング工程を示す説明図、
図10は、個片に分離された半導体チップの説明図、
図11は、図10の半導体チップを基板に実装した状態の説明図、
図12は断面V字状の切刃を有する第1のブレードによるダイシング工程を示す説明図、
図13は幅狭の第2のブレードによるダイシング工程を示す説明図、
図14は個片に分離された半導体チップの説明図、
図15は、図14の半導体チップを基板に実装した状態の説明図、
図16は、基板を上側に、半導体チップを下側に配置して実装した状態を示す説明図、
図17は、基板に凹溝を設けて樹脂溜まりとした状態の説明図、
図18は、基板に凹部を設けて樹脂溜まりとした状態の説明図、
図19は、基板に貫通孔を設けて樹脂溜まりとした状態の説明図、
図20〜図22は従来技術の説明図であり、
図20は、ウエハにアンダーフィル樹脂層を積層する工程の説明図、
図21は、アンダーフィル樹脂層が積層された状態のウエハの説明図、
図22は、ウエハとリングフレームをダイシングフイルムに接着した状態の説明図である。
【発明を実施するための形態】
【0011】
実施例
以下本発明の好適な実施例を添付図面に基づいて詳細に説明する。
(第1実施例)
図1は、アンダーフィル用シート材20を示す。
21はシート状に形成されたアンダーフィル樹脂層である。このアンダーフィル樹脂層12の両面に、アンダーフィル樹脂層21の接着力により、剥離可能な剥離シート22が積層される。そして、一方の剥離シート22の外面に、接着剤付きの公知のダイシングフイルム23がその接着剤により貼付されてアンダーフィル用シート材20が構成される。
アンダーフィル樹脂層21は、ウエハの表面を覆うに足りる十分な大きさのものであり、剥離シート22やダイシングフイルム23はアンダーフィル樹脂層21よりも大きなものが用いられる。
アンダーフィル樹脂層21とダイシングフイルム23との間に剥離シート22を介在させるのは、アンダーフィル樹脂層21とダイシングフイルム23とが強固に接着して、剥離不能になるのを防止するためである。また、アンダーフィル樹脂層21の両面がシート材で覆われるので、ゴミ等の異物の付着が防止され、ハンドリングも容易となる。
アンダーフィル樹脂材21は、熱硬化性樹脂からなる。例えば、エポキシ樹脂にフィラーを60wt%程度混入し、硬化剤を添加したものが一例として挙げられる。しかし、これに限定されるものではない。厚さは60μm程度が好適である。
剥離シート22は、例えば、厚さ30μm程度のポリエチレンテレフタレート(PET)のシートを用いることができる。
ダイシングフイルム23は、貼付されたウエハを支持できる強度を有するシート材、例えば塩化ビニルシートが使用可能である。このダイシングフイルム23の表面には、接着剤が塗布されており、この接着剤は紫外線照射によりその接着力が弱いものとなるものが使用される。
【0012】
上記アンダーフィル用シート材20を用いて、半導体チップにアンダーフィル樹脂層21を積層するには次のようにする。
まず、図2に示すように、ダイシングフイルム23を剥離する。また中間の剥離シート22を剥離し、かつ除去する。これらの作業は、手作業で行ってもよいが、自動機(図示せず)で行える。
自動機中では、剥離されたダイシングフイルム23と、アンダーフィル樹脂層21との間に所要の隙間が維持されるように保持される。
次に、図3に示すように、上記の隙間内に、ウエハ25がバンプ(金のワイヤバンプ)26をアンダーフィル樹脂層21方向に向けてアンダーフィル樹脂層21上に乗るように、また、リングフレーム27がウエハ25を囲むようにして挿入される。このウエハ25とリングフレーム27の挿入も自動機で行える。
【0013】
次に、自動機内に配設されている押圧ローラ28、28を走行させ、該押圧ローラ28、28により、ダイシングフイルム23と剥離シート22を介して、ウエハ25とアンダーフィル樹脂層21とを押圧する。
これにより、バンプ26が、アンダーフィル樹脂層21内に埋没する状態となる。
金のワイヤバンプの場合には、バンプ26の先端が尖っているので、先端がアンダーフィル樹脂層21から突出することもあるが、先端は必ずしもアンダーフィル樹脂層21から突出しないようにしてもよい。
次いで剥離シート22を剥離する。
【0014】
上記のようにして、図4に示すように、アンダーフィル樹脂層21にバンプ26が埋没した状態のウエハ25と、リングフレーム27とをダイシングフイルム23に接着した状態のものを準備できる。
しかも、ウエハ25に、アンダーフィル樹脂層21にバンプ26が埋没する状態でアンダーフィル樹脂層21を積層させる工程と、このウエハ25およびリングフレーム27をダイシングフイルム23上に接着する工程とを同時に行うことができ、作業性が大幅に向上し、作業時間も短縮できて、コストの低減化が図れるのである。
上記のように、リングフレーム27に保持されたウエハ25を公知のダイシング装置(図示せず)に装着し、アンダーフィル樹脂層21と共にウエハ25を切断して個片の半導体チップ30(図5)に分離する。なお、ダイシングフイルム23には、浅く、約30μm程度切り込むだけであり、ダイシングフイルム23は分離しない。
【0015】
次に、ダイシングフィルム23に紫外線を照射する。これにより、接着剤の接着力は弱まる。
ダイシングフイルム23上から、個片に分離された半導体チップ30を吸着ノズル(図示せず)により吸着して、基板31上に位置決めして載せ、加圧、加熱することにより、半導体チップ30を基板31上に実装できる(図6、図7)。加熱によって、アンダーフィル樹脂材は熱硬化するが、若干はみ出しが生じる。しかし、アンダーフィル樹脂材の供給量は一定しているので、はみ出し量も一定している。
【0016】
(第2実施例)
図8〜図11に第2実施例を示す。
本実施例では、ダイシング工程において、まず.比較的幅広の、例えば40μm幅の第1のブレード(図示せず)によりアンダーフィル樹脂層21側からウエハ25の厚みの中途部まで切り込み(図8)、次いで、第1のブレードよりも幅の狭い、例えば25μm幅の第2のブレード(図示せず)により、第1のブレードにより形成された溝内を切り込んで、個片の半導体チップ30に分離するのである(図9)。このようにすることで、周縁部に段差32が形成された個片の半導体チップに30が形成される(図10)。
この半導体チップ30を上記と同様の方法で、基板31に実装する。アンダーフィル樹脂材のはみ出しが生じるが、段差32が樹脂溜まりとなることから、樹脂材のはみ出しを極力少なくできる(図11)。
【0017】
(第3実施例)
図12〜図15に第3実施例を示す。
本実施例においては、ダイシング工程において、断面V字状の切刃を有する第1のブレード(図示せず)によりアンダーフィル樹脂層21側からウエハ25の厚みの中途部まで切り込んで断面V字状の溝を形成し(図12)、次いで、第1のブレードよりも幅の狭い第2のブレードにより、第1のブレードにより形成されたV字状の溝内を切り込んで、個片の半導体チップ30に分離するのである(図13)。これにより、周縁部に面取り部33が形成された半導体チップ30が形成される(図14)。
この半導体チップ30を上記と同様の方法で、基板31に実装する。アンダーフィル樹脂材のはみ出しが生じるが、面取り部33が樹脂溜まりとなることから、樹脂材のはみ出しを極力少なくできる(図15)。
【0018】
(第4実施例)
図16は、基板31への半導体チップ30の実装時、基板31を上側に、半導体チップ30を下側にして実装する実施例を示す。
このように半導体チップ30を下側にすることで、軟化したアンダーフィル樹脂材は、半導体チップ30の側面を覆うように下方に垂れ下がるので、外方へのアンダーフィル樹脂材のはみ出しをそれだけ少なくできる。
【0019】
(第5実施例)
図17は、樹脂のはみ出しを防止する他の実施例を示す。
本実施例では、基板31の半導体チップ搭載部の周りに、搭載する半導体チップ30を囲むようにして、凹溝34を設けている。この凹溝34が樹脂溜まりとして機能するので、アンダーフィル樹脂材のはみ出しを少なくできる。凹溝34は、基板31の配線パターン(図示せず)には至らないように、表層のソルダーレジスト層に浅く設けるとよい。
【0020】
(第6実施例)
図18は、半導体チップ30の搭載部を凹部35としたものである。この凹部35自体が樹脂溜まりとして機能する。
【0021】
(第7実施例)
図19は、基板31に貫通孔36を設けて樹脂溜まりとした実施例を示す。
【発明の効果】
【0022】
以上のように、本発明に係るアンダーフィル用シート材によれば、アンダーフィル樹脂層とダイシングフイルムとの間に剥離シートを介在させているので、アンダーフィル樹脂層とダイシングフイルムとが強固に接着して、剥離不能になるのを防止でき、また、アンダーフィル樹脂層の両面がシート材で覆われるので、ゴミ等の異物の付着が防止され、ハンドリングも容易となる。
また本発明に係る半導体チップのアンダーフィル方法では、ウエハに、アンダーフィル樹脂層にバンプが埋没する状態でアンダーフィル樹脂層を積層させる工程と、このウエハおよびリングフレームをダイシングフイルム上に接着する工程とを同時に行うことができ、作業性が大幅に向上し、作業時間も短縮できて、コストの低減化が図れるのである。
また、半導体チップに段差部や面取り部からなる樹脂溜まりを、あるいは基板側に凹溝や凹部、貫通孔からなる樹脂溜まりを設ければ、基板に半導体チップを実装した際、アンダーフィル樹脂材のはみ出しを極力防止できて好適である。
【符号の説明】
【0023】
20 アンダーフィル用シート材、
21 アンダーフィル樹脂層、
22 剥離シート、
23 ダイシングフィルム、
25 ウエハ、
26 バンプ、
27 リングフレーム、
28 押圧ローラ、
30 半導体チップ、
31 基板、
32 段差、
33 面取り部、
34 凹溝、
35 凹部、
36 貫通孔、 【Technical field】
[0001]
The present invention relates to an underfill sheet material used to fill a gap between bumps provided on a semiconductor chip, a semiconductor chip underfill method, and a semiconductor chip mounting method.
[Background]
[0002]
When a semiconductor chip is mounted on a substrate (including a wiring board and a package), there is a method in which bumps are formed on the semiconductor chip and the semiconductor chip is flip-chip mounted on the substrate via the bumps.
In this case, an underfill resin material made of an insulating material is filled between the chip and the substrate in order to protect the circuit surface of the semiconductor chip, prevent humming of the bump, and improve the bonding strength between the chip and the substrate. ing.
In general, the resin material is filled with a liquid resin material for each semiconductor chip using a dispenser. However, this method requires a great deal of work time. Further, in the dispenser, there is a problem that the amount of resin supplied is unstable, and unfilled portions remain, or conversely, the resin overflows.
[0003]
In order to solve this problem, for example, as shown in Japanese Patent Application Laid-Open No. 5-55278, a bump is formed with an underfill resin material (resin layer) formed in a sheet shape in a state where the bump is formed on the wafer. A method is known in which a bump is buried in an underfill resin material by pressing against the wafer surface. According to this, underfill resin material can be supplied collectively at the wafer stage, and work efficiency can be greatly improved.
After supplying the underfill resin material as described above, the wafer can be diced together with the underfill resin material and separated into individual semiconductor chips with the underfill resin material.
The semiconductor chip thus separated is mounted on a mounting substrate, and the underfill resin material is thermally cured.
[0004]
In the method disclosed in JP-A-8-288293, after forming a bump on the wafer, a resin sealing film is formed on the upper surface of the wafer by spin coating so that the upper portion of the bump protrudes. The wafer is cut and separated into individual semiconductor chips.
[0005]
Further, in the method disclosed in Japanese Patent Laid-Open No. 2000-299333, a sealing resin sheet is placed on the wafer surface on which bumps are formed, and the wafer and the sealing resin sheet are bonded together under heating, and then The wafer is cut and separated into individual semiconductor chips.
[0006]
Further, in the method disclosed in Japanese Patent Application Laid-Open No. 2000-195901, the support film on which the resin layer is formed is thermocompression bonded so that the resin layer is in contact with the wafer surface, and then the resin layer is photocured and the support film is peeled off. After that, the wafer is cut and separated into individual semiconductor chips.
SUMMARY OF THE INVENTION
[Problems to be solved by the invention]
[0007]
However, for example, in the method disclosed in Japanese Unexamined Patent Publication No. 5-55278, the steps shown in FIGS.
That is, first, as shown in FIG. 20, the
In order to dice the
When the
[0008]
However, in this step, the
In the case of the other three conventional methods, similarly, a two-step separate process is required, that is, a process for obtaining the
Accordingly, the present invention has been made to solve the above-mentioned problems, and the object of the present invention is to provide a sheet material for underfill, a semiconductor chip underfill method, and a semiconductor chip that can reduce the number of steps and reduce the cost. To provide an implementation method.
[Means for Solving the Problems]
[0009]
In an underfill method for a semiconductor chip according to the present invention, an underfill resin layer having a size capable of covering the surface of a wafer in the underfill method for a semiconductor chip in which a space between bumps provided on the semiconductor chip is filled with an underfill resin material. A release sheet that is larger than the underfill resin layer and can be peeled off from the underfill resin layer is laminated on both sides of the sheet, and an adhesive is applied to the outer surface of one release sheet that is larger than the underfill resin layer. Using a sheet material for an underfill to which a dicing film is adhered with the adhesive, peeling the dicing film and the one release sheet of the underfill sheet material, and removing the one release sheet; Before the underfill sheet material from which the one release sheet is removed And the under-fill resin layer side, between the adhesive layer side of the dicing film is peeled off, and the wafer toward the bump to the under-fill resin layer side, placing a ring frame surrounding the wafer, The wafer and the ring frame are interposed, the dicing film and the other release sheet are pressed, the wafer and the ring frame are bonded to the dicing frame, and the wafer bumps are buried in the underfill resin layer. It includes a pressing step and a peeling step for peeling the other release sheet.
As described above, in the present invention, the lamination of the underfill resin layer to the wafer and the bonding of the wafer and the ring frame to the dicing film can be performed in the same process, thereby reducing the man-hours and reducing the cost. Can do. In addition, handling of the wafer becomes easy.
[Brief description of the drawings]
[0010]
FIG. 1 is an explanatory diagram of a sheet material for underfill in a state where a dicing film is peeled off,
FIG. 2 is an explanatory diagram of a state where the dicing film and the release sheet are peeled from the underfill sheet material,
FIG. 3 is an explanatory diagram of a process of pressurizing the wafer and the underfill resin layer with a pressing roller.
FIG. 4 is an explanatory view showing a state in which the wafer is supported on the ring frame.
FIG. 5 is an explanatory view of a semiconductor chip in a state separated into individual pieces,
FIG. 6 is an explanatory diagram of a process of mounting a semiconductor chip on a substrate.
FIG. 7 is an explanatory view showing a state where a semiconductor chip is mounted on a substrate,
FIG. 8 is an explanatory view showing a dicing process using a wide first blade,
FIG. 9 is an explanatory view showing a dicing process by a narrow second blade,
FIG. 10 is an explanatory diagram of a semiconductor chip separated into individual pieces,
11 is an explanatory diagram of a state in which the semiconductor chip of FIG. 10 is mounted on a substrate.
FIG. 12 is an explanatory view showing a dicing process by a first blade having a V-shaped cutting edge,
FIG. 13 is an explanatory view showing a dicing process by a narrow second blade;
FIG. 14 is an explanatory diagram of a semiconductor chip separated into individual pieces,
FIG. 15 is an explanatory diagram of a state where the semiconductor chip of FIG. 14 is mounted on a substrate.
FIG. 16 is an explanatory view showing a state where the substrate is mounted on the upper side and the semiconductor chip is mounted on the lower side,
FIG. 17 is an explanatory diagram of a state where a concave groove is provided on the substrate to form a resin reservoir,
FIG. 18 is an explanatory diagram of a state in which a recess is provided in the substrate to form a resin reservoir,
FIG. 19 is an explanatory diagram of a state in which a through hole is provided in the substrate to form a resin reservoir,
20-22 is explanatory drawing of a prior art,
FIG. 20 is an explanatory diagram of a process of laminating an underfill resin layer on a wafer.
FIG. 21 is an explanatory diagram of a wafer in a state where an underfill resin layer is laminated,
FIG. 22 is an explanatory view showing a state in which the wafer and the ring frame are bonded to the dicing film.
BEST MODE FOR CARRYING OUT THE INVENTION
[0011]
The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
(First embodiment)
FIG. 1 shows an
The
The reason why the
The
As the
As the dicing
[0012]
The
First, as shown in FIG. 2, the dicing
In the automatic machine, it is held so that a required gap is maintained between the peeled
Next, as shown in FIG. 3, the
[0013]
Next, the
As a result, the
In the case of a gold wire bump, the tip of the
Next, the
[0014]
As described above, as shown in FIG. 4, a
In addition, the step of laminating the
As described above, the
[0015]
Next, the dicing
The
[0016]
(Second embodiment)
8 to 11 show a second embodiment.
In this embodiment, in the dicing process, first, A relatively wide first blade (not shown) having a width of 40 μm, for example, is cut from the
The
[0017]
(Third embodiment)
A third embodiment is shown in FIGS.
In the present embodiment, in the dicing process, a first blade (not shown) having a cutting edge with a V-shaped section is cut from the
The
[0018]
(Fourth embodiment)
FIG. 16 shows an embodiment in which the
By lowering the
[0019]
(5th Example)
FIG. 17 shows another embodiment for preventing the resin from protruding.
In this embodiment, a groove 34 is provided around the semiconductor chip mounting portion of the
[0020]
(Sixth embodiment)
In FIG. 18, the mounting portion of the
[0021]
(Seventh embodiment)
FIG. 19 shows an embodiment in which a through
【The invention's effect】
[0022]
As described above, according to the underfill sheet material of the present invention, since the release sheet is interposed between the underfill resin layer and the dicing film, the underfill resin layer and the dicing film are firmly bonded. Thus, it becomes possible to prevent the peeling from becoming impossible, and since both surfaces of the underfill resin layer are covered with the sheet material, adhesion of foreign matters such as dust is prevented and handling is facilitated.
In the underfill method for a semiconductor chip according to the present invention, a step of laminating an underfill resin layer on a wafer with bumps embedded in the underfill resin layer, and a step of bonding the wafer and the ring frame on a dicing film Thus, workability can be greatly improved, work time can be shortened, and costs can be reduced.
In addition, if the semiconductor chip is provided with a resin reservoir consisting of a stepped portion or a chamfered portion, or a resin reservoir consisting of a concave groove, a concave portion, or a through hole on the substrate side, when the semiconductor chip is mounted on the substrate, the underfill resin material This is preferable because it can prevent protrusion as much as possible.
[Explanation of symbols]
[0023]
20 Sheet material for underfill,
21 Underfill resin layer,
22 release sheet,
23 Dicing film,
25 wafers,
26 Bump,
27 Ring frame,
28 pressure roller,
30 semiconductor chip,
31 substrate,
32 steps,
33 Chamfered part,
34 Groove,
35 recess,
36 through holes,
Claims (6)
ウエハの表面を覆うことのできる大きさの前記アンダーフィル樹脂層の両面に、該アンダーフィル樹脂層よりも大きく、アンダーフィル樹脂層から剥離可能な剥離シートが積層され、一方の剥離シートの外面に、前記アンダーフィル樹脂層よりも大きく、接着剤が塗布されたダイシングフイルムが該接着剤により貼付されていることを特徴とするアンダーフィル用シート材。In the sheet material for underfill in which the underfill resin layer for filling between the bumps provided in the semiconductor chip is formed on the release sheet,
A release sheet that is larger than the underfill resin layer and can be peeled off from the underfill resin layer is laminated on both sides of the underfill resin layer having a size that can cover the surface of the wafer. A sheet material for underfill, characterized in that a dicing film larger than the underfill resin layer and coated with an adhesive is stuck to the adhesive.
請求項1記載のアンダーフィル用シート材を用い、該アンダーフィル用シート材のダイシングフィルムと一方の剥離シートとを剥離すると共に該一方の剥離シートを除去する工程と、
該一方の剥離シートが除去された、前記アンダーフィル用シート材のアンダーフィル樹脂層側と、剥離された前記ダイシングフィルムの接着剤層側との間に、バンプを前記アンダーフィル樹脂層側に向けてウエハと、該ウエハを囲むリングフレームとを配置する工程と、
前記ウエハとリングフレームとを介在させて、前記ダイシングフイルムと他方の剥離シートとを押圧し、ウエハとリングフレームとを前記ダイシングフレームに接着すると共に、ウエハのバンプを前記アンダーフィル樹脂層に埋没させる押圧工程と、
前記他方の剥離シートを剥離する剥離工程とを含むことを特徴とする半導体チップのアンダーフィル方法。In the semiconductor chip underfill method of filling the space between the bumps provided on the semiconductor chip with an underfill resin material,
Using the underfill sheet material according to claim 1, the step of peeling the dicing film of the underfill sheet material and one release sheet and removing the one release sheet;
The bump is directed to the underfill resin layer side between the underfill resin layer side of the underfill sheet material from which the one release sheet is removed and the adhesive layer side of the peeled dicing film. Placing the wafer and a ring frame surrounding the wafer;
The wafer and the ring frame are interposed, the dicing film and the other release sheet are pressed, the wafer and the ring frame are bonded to the dicing frame, and the wafer bumps are buried in the underfill resin layer. A pressing step;
A semiconductor chip underfill method, comprising: a peeling step of peeling the other release sheet.
請求項1記載のアンダーフィル用シート材を用い、該アンダーフィル用シート材のダイシングフィルムと一方の剥離シートとを剥離すると共に該一方の剥離シートを除去する工程と、
該一方の剥離シートが除去された、前記アンダーフィル用シート材のアンダーフィル樹脂層側と、剥離された前記ダイシングフィルムの接着剤層側との間に、バンプを前記アンダーフィル樹脂層側に向けてウエハと、該ウエハを囲むリングフレームとを配置する工程と、
前記ウエハとリングフレームとを介在させて、前記ダイシングフイルムと他方の剥離シートとを押圧し、ウエハとリングフレームとを前記ダイシングフレームに接着すると共に、ウエハのバンプを前記アンダーフィル樹脂層に埋没させる押圧工程と、
前記他方の剥離シートを剥離する剥離工程と、
前記ダイシングフイルムに接着されたウエハを、前記リングフレームを介してダイシング装置に装着し、前記アンダーフィル樹脂層と共にウエハをダイシングして、個片の半導体チップに分離するダイシング工程と、
個片に分離された半導体チップを、基板の端子部に位置合わせして接合すると共に、加熱して前記アンダーフィル樹脂層を硬化させる実装工程とを含むことを特徴とする半導体チップの実装方法。In the semiconductor chip mounting method, the semiconductor chip is flip-chip connected to the substrate, and the resin material is underfilled in the gap between the semiconductor chip and the substrate.
Using the underfill sheet material according to claim 1, the step of peeling the dicing film of the underfill sheet material and one release sheet and removing the one release sheet;
The bump is directed to the underfill resin layer side between the underfill resin layer side of the underfill sheet material from which the one release sheet is removed and the adhesive layer side of the peeled dicing film. Placing the wafer and a ring frame surrounding the wafer;
The wafer and the ring frame are interposed, the dicing film and the other release sheet are pressed, the wafer and the ring frame are bonded to the dicing frame, and the wafer bumps are buried in the underfill resin layer. A pressing step;
A peeling step of peeling the other release sheet;
A wafer bonded to the dicing film is mounted on a dicing device via the ring frame, and the wafer is diced together with the underfill resin layer, and a dicing process for separating the wafer into individual semiconductor chips;
A semiconductor chip mounting method comprising: a mounting step of aligning and bonding the semiconductor chips separated into individual pieces to a terminal portion of a substrate and heating to cure the underfill resin layer.
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PCT/JP2001/005687 WO2003003445A1 (en) | 2001-06-29 | 2001-06-29 | Sheet for underfill, method for underfilling semiconductor chip, and method for mounting semiconductor chip |
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WO2006075197A1 (en) * | 2005-01-12 | 2006-07-20 | Infineon Technologies Ag | Flip-chip semiconductor packages and methods for their production |
JP2006261529A (en) * | 2005-03-18 | 2006-09-28 | Lintec Corp | Underfill tape for flip chip mount and manufacturing method of semiconductor device |
JP5535915B2 (en) * | 2007-09-12 | 2014-07-02 | スモルテック アーベー | Connection and bonding of adjacent layers by nanostructures |
DE102011112659B4 (en) * | 2011-09-06 | 2022-01-27 | Vishay Semiconductor Gmbh | Surface mount electronic component |
CN115176333A (en) * | 2020-02-27 | 2022-10-11 | 琳得科株式会社 | Protective film forming sheet, method for manufacturing chip with protective film, and laminate |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6485712A (en) * | 1987-09-28 | 1989-03-30 | Nec Corp | Dicing method of semiconductor |
JPH0451144U (en) * | 1990-09-03 | 1992-04-30 | ||
JPH06334036A (en) * | 1993-05-25 | 1994-12-02 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
WO1999030362A1 (en) * | 1997-12-08 | 1999-06-17 | Minnesota Mining And Manufacturing Company | Method and apparatuses for making z-axis electrical connections |
JP2000299333A (en) * | 1999-02-09 | 2000-10-24 | Nitto Denko Corp | Manufacture of semiconductor device |
-
2001
- 2001-06-29 WO PCT/JP2001/005687 patent/WO2003003445A1/en active Search and Examination
- 2001-06-29 JP JP2002531444A patent/JP4778667B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6485712A (en) * | 1987-09-28 | 1989-03-30 | Nec Corp | Dicing method of semiconductor |
JPH0451144U (en) * | 1990-09-03 | 1992-04-30 | ||
JPH06334036A (en) * | 1993-05-25 | 1994-12-02 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
WO1999030362A1 (en) * | 1997-12-08 | 1999-06-17 | Minnesota Mining And Manufacturing Company | Method and apparatuses for making z-axis electrical connections |
JP2000299333A (en) * | 1999-02-09 | 2000-10-24 | Nitto Denko Corp | Manufacture of semiconductor device |
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JPWO2003003445A1 (en) | 2004-10-21 |
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