JP4778339B2 - Automatic placement method, apparatus, and program - Google Patents

Description

  The present invention automatically determines the position of an adjustment cell to be inserted for timing adjustment on a target net in which a timing error has occurred in a net connecting cells of the designed electronic circuit. Related to technology.

  At present, electronic circuits are usually designed using CAD. In CAD, elements or components that are functional or logical units of an electronic circuit are registered in a library as basic elements (cells). For this reason, logical design is basically performed by selecting necessary cells from the cells registered in the library and connecting the selected cells. The cells are connected by connecting the pins of each cell.

  In the design of electronic circuits, relatively small changes in the design are made. Such design changes are called ECO (engineering change orders). The ECO is often performed to correct a timing error (an error in a hold time check for checking whether or not a signal capturing timing is too early) generated in a net connecting cells. The correction is usually done by adding an adjustment cell (usually a buffer) that delays the signal on the net. When such an adjustment cell is added, only the wiring where the cell is inserted is changed from the existing design.

FIG. 1 is a diagram illustrating a general design process flow when ECO is performed. Here, the general flow of the design process will be specifically described with reference to FIG.
In the logic synthesis in step S1, an RTL (register transfer level) description expressed in a hardware description language, a truth table, a state transition description, a logical expression (which does not depend on a specific semiconductor manufacturing technology), etc. A gate level logic circuit (net list) is automatically generated. In the layout process of step S2, the net list is read, cell placement determination and wiring placement are performed, and the design is finalized. Data representing the design is stored in a placement and routing database. At this time, the cell is instantiated.

  In step S3, each value of resistance and capacitance of the arranged wiring is calculated. In step S4, the delay of the electronic circuit is estimated by calculation, and using the estimated delay value, static timing analysis (STA) for confirming whether a malfunction (malfunction or the like) occurs due to a time difference in which the signal propagates. I do. In step S5, path information indicating a wiring (net) that generates a timing error (here, hold timing error) found by the STA, and slack information indicating an actual delay are output. In step S6, timing adjustment for correcting the timing error is performed, and an ECO list D1 indicating the adjustment content is created. The ECO list D1 describes the target net with, for example, an instance name and a pin (terminal) name. ECO is performed in the layout process of step S2.

  There is not always an area where an adjustment cell can be inserted on a net where a timing error has occurred. The area may not exist due to another cell or wiring. For this reason, as in the prior art described in Patent Document 1, a position where an adjustment cell can be arranged on a wiring is searched to determine an insertion position (insertion point). However, in reality, the load required for the search is heavy. If the number of wirings to be searched for increases, the load becomes very heavy and enormous processing time is required. In addition, it is not known whether or not an area where insertion can be performed can be found even after searching. For this reason, it is considered important to reduce the load while maintaining the search accuracy of the area where the adjustment cell can be inserted.

Many electronic circuits to be designed are semiconductor integrated circuits formed on a semiconductor chip (substrate). In recent designs of deep submicron semiconductor integrated circuits, it has become difficult to correct timing errors with a short TAT (turnaround time) as the circuit becomes more highly integrated and faster. This is because another timing error is likely to occur due to a design change for correcting the timing error. For this reason, it is often the case that iterations for design changes are repeated. For this reason, in the search for the area where the adjustment cell can be inserted, it is considered important to consider the influence caused by the insertion of the adjustment cell.
JP 2001-168199 A JP 2000-269347 A

A first object of the present invention is to provide a technique for searching for an area (insertion point) in which an adjustment cell can be inserted while maintaining search accuracy with a lighter load.
In addition, a second object of the present invention is to provide a technique for searching for an area (insertion point) in which the adjustment cell can be inserted in consideration of the influence caused by the insertion of the adjustment cell.

  Both the automatic placement methods of the first to third aspects of the present invention are inserted for timing adjustment on a target net in which a timing error has occurred in a net connecting cells of the designed electronic circuit. This is a method for automatically determining the position of the power adjustment cell, and the position where the adjustment cell is to be inserted is determined as follows.

  In the automatic arrangement method according to the first aspect, the substrate on which the electronic circuit is formed is divided into a plurality of areas, and a margin for inserting the adjustment cell for each area is evaluated in advance, and the area where the target net exists Based on the margin evaluated in step 1, it is determined whether or not an adjustment cell can be inserted on the target net, and the adjustment cell should be inserted for the target net that is determined to be able to insert the adjustment cell. Determine the position.

  In the automatic placement method of the second aspect, it is confirmed whether or not the adjustment cell can be inserted in the vicinity of at least one of the output side cell that outputs a signal to the target net and the input side cell that inputs the signal. , Confirming whether or not the adjustment cell should be inserted in the vicinity of the one, and by the confirmation, the adjustment cell can be inserted in the vicinity of the one and the adjustment cell should be inserted If it is found, the vicinity of the one is selected and determined as the position where the adjustment cell is to be inserted.

  In the automatic placement method according to the third aspect, when the target net is formed of a plurality of layers and is composed of a plurality of net segments, the plurality of net segments are divided according to the length of the net segment, A net segment into which an adjustment cell is to be inserted is selected and determined in such a manner that a net segment having a long length is given priority among the segments.

  The automatic placement apparatus of the present invention automatically positions the adjustment cell to be inserted for timing adjustment on the target net in which the timing error has occurred in the net connecting the cells of the designed electronic circuit. There is an evaluation means for dividing a substrate on which an electronic circuit is formed into a plurality of areas and evaluating a margin for inserting an adjustment cell for each area, and a target net. Based on the margin evaluated in the area, a determination unit that determines whether or not an adjustment cell can be inserted on the target net, and a target net that is determined by the determination unit that the adjustment cell can be inserted Arrangement determining means for determining a position where the adjustment cell is to be inserted.

  The program of the present invention automatically determines the position of the adjustment cell to be inserted for timing adjustment on the target net where the timing error has occurred in the net connecting the cells of the designed electronic circuit. A program executed by a computer to divide a substrate on which an electronic circuit is formed into a plurality of areas, and an evaluation function that evaluates in advance the margin for inserting an adjustment cell for each area; Based on the margin evaluated in the area where the net exists, the determination function that determines whether or not the adjustment cell can be inserted on the target net, and the target net determined by the determination function that the adjustment cell can be inserted Thus, an arrangement determining function for determining a position where the adjustment cell is to be inserted is realized.

  In the present invention, the substrate on which the electronic circuit is formed is divided into a plurality of areas, and a margin for inserting the adjustment cell for each area is evaluated in advance, and based on the margin evaluated in the area where the target net exists. Thus, by determining whether or not the adjustment cell can be inserted on the target net, the position where the adjustment cell is to be inserted is determined only for the target net for which it has been determined that the adjustment cell can be inserted. A search for searching for a position to be inserted on the target net has a heavy load. If the number of target nets increases, the load becomes extremely heavy, and an enormous processing time is required. However, if the target net into which the adjustment cell can be inserted is selected (restricted) based on the margin required with a relatively light load, it is possible to avoid performing a useless search. As a result, the area (insertion point) in which the adjustment cell can be inserted can be determined (searched) with a lighter load while maintaining the search accuracy.

  In the present invention, it is confirmed whether or not the adjustment cell can be inserted in the vicinity of at least one of the output side cell that outputs a signal to the target net and the input side cell that inputs the signal. When it is determined whether or not the adjustment cell should be inserted, and it is found that the adjustment cell can be inserted in the vicinity of one of the confirmation cells and the adjustment cell should be inserted Then, one of the neighbors is selected and determined as the position where the adjustment cell is to be inserted. By arranging the adjustment cell in the vicinity of the output side cell or the input side cell, it is possible to minimize changes in the resistance value and the capacitance value generated in the target net by the placement (insertion). Placement of the cell for adjustment (insertion) is performed in the vicinity where the placement is to be performed, that is, in a situation where the placement does not cause another failure and the possibility of the failure is small. ) Can also be minimized. As a result, it is possible to more reliably avoid the occurrence of another timing error due to the arrangement of the adjustment cells, thereby minimizing the occurrence of iteration.

  In the present invention, when the target net is formed of a plurality of layers by being formed in a plurality of layers, the plurality of net segments are divided according to the length of the net segment, and the length of the net segment is The net segment into which the adjustment cell is to be inserted is selected and determined in such a manner that the net segment having a longer length is prioritized. A certain net segment length is required to insert the adjustment cell. Therefore, it is possible to search for a net segment into which the adjustment cell can be inserted at higher speed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 2 is a diagram for explaining the configuration of an automatic layout processing apparatus equipped with the automatic placement apparatus according to the present embodiment.

  As shown in FIG. 2, the layout processing apparatus includes an input processing unit 31 for inputting data by a designer as a user, a display control unit 32 for displaying information to be displayed on the display device, an automatic An automatic layout processing unit 33 that executes layout processing, an automatic placement processing unit 34 that automatically determines a position where an adjustment cell should be inserted on a wiring (net) in which a timing error has occurred, and various data and programs And a storage unit 35 that can store the data.

  The automatic layout processing unit 54 can perform the design process of steps S2 to S5 shown in FIG. A design process instructed by the designer via the input processing unit 31 is performed. The design data determined by executing the layout process in step S2 is stored in a placement and routing database (DB). The DB is constructed on the storage unit 35.

  FIG. 3 is a diagram for explaining a hardware configuration of a computer that can be used as the automatic layout processing apparatus. Prior to the detailed description of FIG. 2, the configuration of a computer that can be used as an automatic layout processing apparatus will be specifically described.

  The computer shown in FIG. 3 has a CPU 61, a memory 62, an input device 63, an output device 64, an external storage device 65, a medium drive device 66, and a network connection device 67, which are connected to each other by a bus 68. It has become. The configuration shown in the figure is an example, and the present invention is not limited to this.

  The CPU 61 controls the entire computer. The memory 62 is a memory such as a RAM that temporarily stores a program or data stored in the external storage device 65 (or the portable recording medium MD) during program execution, data update, or the like. The CPU 61 performs overall control by reading the program into the memory 62 and executing it.

  The input device 63 can be connected to or has an external input device such as a keyboard and a mouse, for example. The user's operation on such an external input device is detected, and the detection result is notified to the CPU 61.

The output device 64 can be connected to, for example, a display, or has the same. The data sent under the control of the CPU 61 is output on the display.
The network connection device 67 is for communicating with other devices via a communication network such as a LAN or the Internet. The external storage device 65 is, for example, a hard disk device. Mainly used for storing various data and programs.

The medium driving device 66 accesses a portable recording medium MD such as an optical disk or a magneto-optical disk.
The automatic layout processing device shown in FIG. 2 is realized by the CPU 61 reading out, for example, a program stored in the external storage device 65 to the memory 62 and executing it. The program may be acquired by the network connection device 67 via a communication network, or read by the medium driving device 66 from the recording medium MD.

The automatic arrangement processing unit 34 illustrated in FIG. 2 includes a map creation unit 41, a search unit 42, and a list creation unit 43. They perform the following processing.
The higher the density of the cells constituting the electronic circuit on the substrate, the smaller the vacant space. However, the mounting density is not always uniform. Focusing on these points, in the present embodiment, the substrate on which the designed electronic circuit is formed is divided into a plurality of areas, and the margin for inserting the adjustment cell for each area is evaluated in advance. Yes. The map creation unit 41 performs the evaluation. The evaluation of the margin is performed by calculating the ratio of the area (vacant space) where no cell or wiring exists for each area to the whole. Hereinafter, the ratio is referred to as “free space rate” (%), and the area for which the free space rate is obtained is referred to as “block”.

  FIG. 6 is a diagram for explaining the divided blocks and their empty space ratios. In FIG. 6, each frame represents a block, and the empty space rate of the block is represented by a pattern in the frame. Here, the free space rate is 0, that is, there is no free space, the free space rate is less than 50% (more precisely, 50> free space rate> 0), and the free space rate is 50% or more. Represents the free space rate.

  The adjustment cell must be arranged so as not to overlap other cells. Connection between cells is made by connecting pins. The wiring is placed between the pins. Therefore, in this embodiment, the division into blocks is performed so that each includes one pin of the cell (FIG. 12). The cell pins are hereinafter also referred to as “terminals”. A terminal that outputs a signal is called a source terminal, and a terminal that inputs the signal is called a sink terminal.

FIG. 7 is a diagram for explaining a description method of an empty space map.
Each block has one pin (terminal) that each cell has. Therefore, in the description of the free space map, a method of describing the free space rate for each block using the instance name representing the cell and the name of one pin of the cell as information for block identification is adopted. Yes. In “TOP / CellA.IN 90%” described in the first line in FIG. 7, “TOP / CellA” represents an instance name, “IN” represents a pin name, and “90%” represents an empty space rate. Yes.

  The placement and wiring DB stores information about cells and placement information thereof. The map creation unit 41 refers to the placement and routing DB, determines the shape and position of each block so as to include one pin of each cell, and calculates the free space rate. In this way, an empty space map is created.

  The search unit 42 performs a process of searching for a position (insertion point) where the adjustment cell is to be inserted for each wiring (net) in which a timing error has occurred. The search is performed only when the free space rate of the block in which the target net exists is larger than a predetermined threshold value. The threshold value is determined in consideration of the relationship between the empty space rate and the probability of actually finding a space (insertion point) in which an adjustment cell can be inserted. As a result, the insertion point is searched only when it can be expected to find the insertion point.

  In this way, the target nets into which adjustment cells are to be inserted are excluded from those that cannot be expected, and the search is limited to only the insertion points where the possibility can be expected. Since such narrowing is performed, the load required for searching for the insertion point can be further reduced. An empty space map for narrowing down can be created with a relatively light load. From this, the overall load can be further reduced and the processing time can be further reduced as compared with the case where the search is performed in all of the target nets. In addition, since the insertion point is searched in the target net into which the adjustment cell can be inserted, high search accuracy can be maintained.

The search for the insertion point is performed with priority given to the following. This will be specifically described with reference to FIGS.
FIG. 8 is a diagram for explaining an ideal insertion point of the adjustment cell in consideration of the resistance / capacitance of the net.

  Recently, the calculation (estimation) of the delay value generated in the net is performed in consideration of the resistance and capacitance (FIG. 1). As the resistance and capacitance change, the delay value generated in the net also changes. The change in the delay value again increases the possibility of performing ECO, that is, the possibility of iteration. Therefore, it is desirable to minimize the change in resistance and capacitance that occurs before and after the adjustment cell is inserted into the net. Therefore, in this embodiment, the adjustment cell (buff) is arranged as close as possible to either the source terminal or the sink terminal. FIG. 8 shows an example in which a buffer (buff) to be inserted as an adjustment cell in a net connecting cell A and cell B is arranged close to the source terminal of cell A. By arranging in this way, the resistance / capacitance of the net connecting the adjustment cell and the terminal on the near side can be made almost negligible, and the resistance / capacity of the net connecting the adjustment cell and the terminal on the far side can be neglected. The capacity can be approximately the same as those of the net before insertion.

It is desirable to select the terminal where the adjustment cell should be placed in the vicinity according to the situation. The selection may be performed as follows, for example.
FIG. 9 is a diagram for explaining a situation in which a source terminal should be selected. In FIG. 9, three situation examples 1 to 3 are shown in FIGS. 9 (a) to 9 (c), respectively. Hereinafter, a cell that outputs a signal to the net is referred to as a “source cell”, and a cell that receives the signal is referred to as a “sink cell”.

  The timing adjustment with the adjustment cell inserted is basically performed to correct a hold timing error (hereinafter abbreviated as “hold error”). In the situation example 1 shown in FIG. 9A, a hold error occurs in a plurality of sink cells to which signals output from the source cell are input, and an adjustment cell (buffer) is inserted on the source cell side. This is when there is space. In such a case, by arranging the adjustment cell on the source cell side, it is possible to eliminate all the hold errors that have occurred in the plurality of sink cells.

  Situation example 2 shown in FIG. 9B is a case where a hold error has occurred in only one sync cell, but there is no insertion space in the vicinity thereof. In such a case, it is desirable to arrange an adjustment cell on the source cell side in order to suppress a design change amount.

  Situation example 3 shown in FIG. 9C is a case where another net (net B) exists in the vicinity of the sync cell in which the hold error occurs. In such a case, the amount of crosstalk noise superimposed on another net is increased by inserting an adjustment cell on the sink cell side. The noise causes a crosstalk delay. Therefore, it is desirable to arrange the adjustment cell on the source cell side.

FIG. 10 is a diagram for explaining a situation where a sync terminal should be selected. In FIG. 10, four situation examples 1 to 4 are shown in FIGS. 10 (a) to 10 (d), respectively.
The situation example 1 shown in FIG. 10A is a case where there are a plurality of sync cells to which a signal output from a source cell is input, and only a hold error has not occurred in all the sync cells. Is. In that case, a hold error occurs in at least one sync cell, and there is no timing error among the other sync cells, or a setup timing error (hereinafter abbreviated as “setup error”). There is something that has occurred. For this reason, if an adjustment cell is arranged on the source cell side, there is a possibility that a new timing error is generated in other sink cells or the timing error is further deteriorated. Accordingly, it is desirable to arrange the adjustment cell on the sink cell side where only the hold error has occurred.

  Situation example 2 shown in FIG. 10B is a case where a hold error has occurred in only one sync cell, but there is no insertion space on the source cell side. In such a case, it is desirable to arrange an adjustment cell on the sink cell side in order to suppress a design change amount.

Situation example 3 shown in FIG. 10C is a case where another net (net B) exists in the vicinity of the source cell in which the hold error occurs. In such a case, it is desirable to arrange an adjustment cell on the sink cell side in order to avoid an increase in the amount of crosstalk noise superimposed on another net.

  Situation example 4 shown in FIG. 10D is a case where a slew rate error has occurred in the sync cell in addition to a hold error. The slew rate error is an error detected by waveform analysis for confirming whether or not the waveform of the propagated signal maintains a form that guarantees the operation. Since the signal waveform is lost during propagation, the adjustment cell is preferably arranged on the sink cell side. Such an arrangement may eliminate slew rate errors.

  A net (wiring) may be arranged in multiple layers. At present, it is common to use a substrate having a multilayer structure, and in reality, many nets are arranged in multiple layers. The length of the net segment that is a part of each layer may have been determined in consideration of the surrounding state. If it is determined in consideration of the surrounding state, there is a high possibility that there is no adjustment cell insertion space in a net segment with a short length. Therefore, in the present embodiment, when the target net is arranged in multiple layers, the net segment for searching for the insertion point of the adjustment cell is performed from the longest one. Thereby, the adjustment cell is inserted in such a manner that a longer net segment is prioritized.

  The search unit 42 searches for the insertion point of the adjustment cell as described above. The priority based on the length of the net segment is adopted when there is no insertion space in the vicinity of the terminal where it is desirable to arrange the adjustment cell among the source terminal and the sink terminal. As a result, the emphasis is on making design changes smaller and reducing the effects of those changes.

  The list creation unit 43 creates a list in which adjustment cells to be inserted at insertion points found by the search unit 42 and information indicating the insertion points are collected for each target net. The list is, for example, as shown in FIG. As the information, for example, a resistance value and a capacitance value of a net newly connecting the source terminal and the adjustment cell are adopted.

  In the list, the target net is represented by an instance name and the name of one terminal that it has, similarly to the empty space map shown in FIG. “Buff1 (0 mΩ, 4 pf)” indicates that the adjustment cell candidate is a buffer, and that the buffer should be connected to the source terminal via a net having a resistance value and a capacitance value of 0 mΩ and 4 pf, respectively. “DontAdjust” indicates that no insertion point was found in the target net. In the target net that is excluded by narrowing down or the insertion point cannot be found by searching, it is described.

  FIG. 4 is a flowchart of the adjustment cell automatic arrangement processing. Next, the operation of the automatic placement processing unit 34 will be described in detail with reference to FIG. The arrangement processing shows a flow of processing executed for automatically determining an insertion point at which the adjustment cell is to be inserted into the target net in which the timing error has occurred. For example, it is realized by the CPU 61 shown in FIG. 3 reading out the program stored in the external storage device 65 to the memory 62 and executing it.

  First, in step S11, an empty space map (FIG. 7) is created with reference to the placement and routing DB. In subsequent step S12, it is determined whether or not the free space rate of the block in which the target net exists is not 0%. In the present embodiment, as described above, the division into blocks is performed so that only one terminal of the cell exists. For this reason, if the two free space ratios are both 0%, the determination is no, the process proceeds to step S15, the result for the target net is stored, and the series of processes is terminated. Otherwise, the determination is yes and the process moves to step S13. When the process proceeds from step S12 to step S15, “DontAdjust” is described in the target net (FIG. 11).

  In step S13, it is determined whether or not the two free space rates are both equal to or less than a threshold value. If the two free space ratios are both equal to or less than the threshold value, the determination is YES and the process proceeds to step S14. After the target net is excluded from the timing adjustment targets, the process proceeds to step S15. As a result, even when the process proceeds from step S14 to step S15, “DonAdjust” is described in the target net (FIG. 11). On the other hand, if this is not the case, that is, if the free space rate is greater than the threshold, the determination is no and the process moves to step S16, and an insertion point search process for searching for an insertion point at which the adjustment cell is to be inserted is executed. Then, the process proceeds to step S15.

  The above steps S12 to S16 are executed for each target net that is a target of timing adjustment in accordance with the target net. As a result, a list as shown in FIG. 11 is created.

FIG. 5 is a flowchart of the insertion point search process executed as step S16. Here, the search process will be described in detail with reference to FIG.
First, in step S21, nets (wirings) are divided into net segments and sorted in descending order of length. In the subsequent step S22, the target net segment as a target is selected from the sorted net segments, and the insertion point is searched over the whole. In step S23, which moves to the subsequent step, it is determined whether or not there are a plurality of searched insertion points. If a new insertion point is found as a result of executing the process of step S22 in a state where there is an insertion point that has already been found, the determination is yes and the process moves to step S24. Otherwise, the determination is no and the process moves to step S25.

  In step S24, an insertion point is selected according to the priority according to the status of the target net. In step S25, the process proceeds to step S25, in which it is determined whether there is an insertion point at which the resistance value / capacitance value (RC) is to be calculated. When the insertion point is found for the first time, or when the insertion point selected by executing the process of step S24 is newly found, it is necessary to calculate RC indicating the insertion point. After the answer is YES and the RC is calculated in step S26, the process proceeds to step S27. Otherwise, the determination is no and the process of step S27 is then executed.

  In step S27, it is determined whether there is another net segment to be searched. As described above, the desired insertion point of the adjustment cell varies depending on the situation of the target net. The search for the net segment is performed from the longest. If no insertion point is found, the search for the unsearched net segment must be continued. Therefore, if there is an unsearched net segment for which adjustment cell insertion is more desirable, or if there is an unsearched net segment and no insertion point is found, the determination is YES and step Returning to S22, the net segment having the longest length among the net segments not targeted is selected to search for the insertion point. If none of them is applicable, the determination is no, the process proceeds to step S28, the search result is output, and the series of processes is terminated. As the search result, the presence / absence of the found insertion point, and the calculated RC if the insertion point exists are output.

  In this way, in the present embodiment, the most desirable one of the found insertion points is selected according to the status of the target net. Thus, the insertion point is determined with an emphasis on making the design change smaller and reducing the influence of the change.

  In this embodiment, the division into blocks is performed so that only one terminal of the cell exists, but another division method may be employed. For example, the image may be divided into blocks with a predetermined shape and size. Or you may make it divide | segment so that each terminal of each cell connected with a net | network may be included.

  The evaluation of the margin for inserting the adjustment cell is performed by calculating the empty space rate, but another index may be adopted. The empty space rate is the empty space rate shown in the entire block, but the insertion space where the adjustment cell is preferably arranged is an area that does not overlap the cell on the net. Even if it is not on the net, it is desirable to be in the vicinity of the original net. Even if it is arranged in such a place, there is a space that can be inserted only on the back side of the terminal to which the target net is connected, and the design change compared to the case where adjustment cells are arranged in that space Is smaller. Therefore, as shown in FIG. 12, an area 1201 having a predetermined size may be assumed on the side where the terminal net is connected, and the free space rate of the area 1201 may be obtained. In such a case, it becomes possible to identify the target net on which the adjustment cell can be placed more reliably.

  The area 1201 may be searched for a position where the free space ratio is more desirable by moving in the direction away from the net or the two directions intersecting the direction with the coordinates of the terminal as the base point. good. In such a case, the target net on which the adjustment cell can be arranged can be specified more reliably. The shape and size of the area 1201 may be fixed, but may be arbitrarily set by the designer.

(Appendix 1)
This is a method for automatically determining the position of an adjustment cell to be inserted for timing adjustment on a target net where a timing error has occurred among the nets connecting the cells of the designed electronic circuit. And
Dividing the substrate on which the electronic circuit is formed into a plurality of areas, and evaluating in advance the margin that the adjustment cell can be inserted for each area;
Based on the margin evaluated in the area where the target net exists, determine whether the adjustment cell can be inserted on the target net,
For the target net determined to be able to insert the adjustment cell, determination of the position where the adjustment cell is to be inserted,
An automatic placement method characterized by that.

(Appendix 2)
Determination of the position where the adjustment cell is to be inserted is performed in the form of giving priority to one of the output side cell that outputs a signal to the target net and the input side cell that inputs the signal.
The automatic placement method according to supplementary note 1, wherein:

(Appendix 3)
When the target net is formed of a plurality of net segments by being formed in a plurality of layers, the position where the adjustment cell is to be inserted is determined by selecting a net segment having a long length among the net segments. To give priority to,
The automatic placement method according to supplementary note 1, wherein:

(Appendix 4)
The division into the plurality of areas is performed in such a manner that one pin of one cell exists in each area.
The automatic placement method according to supplementary note 1, wherein:

(Appendix 5)
The margin evaluation is limited to the side to which the target net is connected, focusing on at least one of the output side cell that outputs a signal to the target net and the input side cell that inputs the signal. Do,
The automatic placement method according to supplementary note 1, wherein:

(Appendix 6)
This is a method for automatically determining the position of an adjustment cell to be inserted for timing adjustment on a target net where a timing error has occurred among the nets connecting the cells of the designed electronic circuit. And
It is confirmed whether or not the adjustment cell can be inserted in the vicinity of at least one of the output side cell that outputs a signal to the target net and the input side cell that inputs the signal, and the adjustment is made in the vicinity of the one Check if the cell should be inserted,
When it is determined by the confirmation that the adjustment cell can be inserted in the vicinity of the one and the adjustment cell is to be inserted, the adjustment cell is set as the position to be inserted. Select and determine the neighborhood of
An automatic placement method characterized by that.

(Appendix 7)
This is a method for automatically determining the position of an adjustment cell to be inserted for timing adjustment on a target net where a timing error has occurred among the nets connecting the cells of the designed electronic circuit. And
When the target net is formed of a plurality of layers by being formed in a plurality of layers, the plurality of net segments is divided according to the length of the net segment,
Selecting and determining a net segment in which the adjustment cell is to be inserted in a manner that prioritizes a net segment having a long length among the net segments;
An automatic placement method characterized by that.

(Appendix 8)
It is an automatic placement device that automatically determines the position of an adjustment cell to be inserted for timing adjustment on a target net where a timing error has occurred among the nets connecting the cells of the designed electronic circuit. And
An evaluation unit that divides a substrate on which the electronic circuit is formed into a plurality of areas, and evaluates in advance a margin for inserting the adjustment cell for each area;
Determining means for determining whether or not the adjustment cell can be inserted on the target net based on the margin evaluated in the area where the target net exists;
Placement determination means for determining a position where the adjustment cell should be inserted, targeting the target net determined by the determination means that the adjustment cell can be inserted;
An automatic placement apparatus comprising:

(Appendix 9)
It is an automatic placement device that automatically determines the position of an adjustment cell to be inserted for timing adjustment on a target net where a timing error has occurred among the nets connecting the cells of the designed electronic circuit. And
It is confirmed whether or not the adjustment cell can be inserted in the vicinity of at least one of the output side cell that outputs a signal to the target net and the input side cell that inputs the signal, and the adjustment is made in the vicinity of the one A confirmation means for confirming whether or not a cell for insertion should be inserted,
When it is determined by the checking means that the adjustment cell can be inserted in the vicinity of the one and the adjustment cell is to be inserted, the adjustment cell is set as the position to be inserted. An arrangement determining means for selecting and determining one of the neighborhoods;
An automatic placement apparatus comprising:

(Appendix 10)
It is an automatic placement device that automatically determines the position of an adjustment cell to be inserted for timing adjustment on a target net where a timing error has occurred among the nets connecting the cells of the designed electronic circuit. And
When the target net is formed of a plurality of net segments by being formed in a plurality of layers, sorting means for dividing the plurality of net segments according to the length of the net segment;
Arrangement determining means for selecting and determining a net segment into which the adjustment cell is to be inserted, in a form that gives priority to a net segment having a long length among the net segments divided by the length by the sorting means;
An automatic placement apparatus comprising:

(Appendix 11)
Executed in a computer to automatically determine the position of the adjustment cell to be inserted for timing adjustment on the target net where the timing error has occurred in the net connecting the cells of the designed electronic circuit A program to
An evaluation function that divides the substrate on which the electronic circuit is formed into a plurality of areas, and evaluates in advance the margin that the adjustment cell can be inserted for each area;
A determination function for determining whether or not the adjustment cell can be inserted on the target net based on the margin evaluated in the area where the target net exists,
An arrangement determination function for determining the position where the adjustment cell should be inserted, targeting the target net determined by the determination function that the adjustment cell can be inserted;
A program to realize

(Appendix 12)
The determination of the position where the adjustment cell is to be inserted by the placement determination function is performed by giving priority to the vicinity of one of the output side cell that outputs a signal to the target net and the input side cell that inputs the signal. Do,
The program according to appendix 11, which is characterized by the above.

(Appendix 13)
When the target net is formed of a plurality of net segments by being formed in a plurality of layers, the determination of the position where the adjustment cell is to be inserted by the placement determination function is a length within the net segment. Is done in a way that prioritizes long net segments,
The program according to appendix 11, which is characterized by the above.

(Appendix 14)
The division into the plurality of areas by the evaluation function is performed in such a manner that one pin of one cell exists in each area.
The program according to appendix 11, which is characterized by the above.

(Appendix 15)
The evaluation of the margin by the evaluation function is performed by paying attention to at least one of an output side cell that outputs a signal to the target net and an input side cell that inputs the signal. Limited to
The program according to appendix 11, which is characterized by the above.

(Appendix 16)
Executed in a computer to automatically determine the position of the adjustment cell to be inserted for timing adjustment on the target net where the timing error has occurred in the net connecting the cells of the designed electronic circuit A program to
It is confirmed whether or not the adjustment cell can be inserted in the vicinity of at least one of the output side cell that outputs a signal to the target net and the input side cell that inputs the signal, and the adjustment is made in the vicinity of the one A confirmation function for confirming whether or not a cell for insertion should be inserted,
When it is determined by the confirmation function that the adjustment cell can be inserted in the vicinity of the one and the adjustment cell is to be inserted, the adjustment cell is set as the position to be inserted. An arrangement determination function for selecting and determining one of the neighborhoods;
A program to realize

(Appendix 17)
Executed in a computer to automatically determine the position of the adjustment cell to be inserted for timing adjustment on the target net where the timing error has occurred in the net connecting the cells of the designed electronic circuit A program to
When the target net is composed of a plurality of net segments by being formed in a plurality of layers, a sorting function that divides the plurality of net segments according to the length of the net segment;
An arrangement determining function for selecting and determining a net segment into which the adjustment cell is to be inserted, in a form in which a net segment having a long length is prioritized among the net segments divided by length by the sort function;
A program to realize

It is a figure explaining the flow of the general design process in case ECO is performed. It is a figure explaining the structure of the automatic layout processing apparatus carrying the automatic arrangement | positioning apparatus by this Embodiment. It is a figure explaining the hardware constitutions of the computer which can be used as an automatic layout processing apparatus carrying the automatic arrangement | positioning apparatus by this Embodiment. It is a flowchart of the cell arrangement | positioning process for adjustment automatically. It is a flowchart of an insertion point search process. It is a figure explaining the divided | segmented block and its empty space rate. It is a figure explaining the description method of an empty space map. It is a figure explaining the ideal insertion point of the cell for adjustment when the resistance and capacity of the net are taken into consideration. It is a figure explaining the condition which should select a source terminal. It is a figure explaining the condition which should select a sink terminal. It is a figure explaining the list created by search of an insertion point. It is a figure explaining the other method of calculating | requiring an empty space rate.

Explanation of symbols

Reference Signs List 31 Input processing unit 32 Display control unit 33 Automatic layout processing unit 34 Automatic placement processing unit 35 Storage unit 41 Map creation unit 42 Search unit 43 List creation unit

Claims (5)

Automatic in an automatic placement device that automatically determines the position of an adjustment cell to be inserted for timing adjustment on a target net where timing errors occur among the nets connecting the cells of the designed electronic circuit An arrangement method,
After the cell and wiring layout design, the evaluation means provided in the automatic placement apparatus divides the substrate on which the electronic circuit is formed into a plurality of areas, and the area where no cell or wiring exists in each area Calculate the percentage of free space that is a percentage of
The determination means provided in the automatic placement device determines whether or not the adjustment cell can be inserted on the target net based on the empty space rate calculated in the area where the target net exists,
The placement determining means provided in the automatic placement apparatus has the output side cell that outputs a signal to the target net that is determined to be able to insert the adjustment cell, and the input side cell that inputs the signal in the vicinity of one of the output side cells. When determining the position where the adjustment cell is to be inserted, that is, inserting the adjustment cell, and the target net is formed of a plurality of layers to form a plurality of net segments, the adjustment cell the determination of the net segment to be inserted to, are performed by the form to prioritize long net segment length among the plurality of net segments, the adjuster cell in a net segment was determined to be inserting the adjuster cell To determine where to insert
The position where the adjustment cell is to be inserted,
When a timing error occurs in a plurality of the input side cells and there is a space for inserting the adjustment cell in the output side cell, a timing error occurs in the input side cell, and the input side cell In the case where there is no space for insertion of the adjustment cell, and there is a timing error in the input side cell, and there is another input side cell in the vicinity of the input side cell, the output side Determined in the vicinity of the cell,
When there is an input side cell in which a timing error has not occurred among the plurality of input side cells, a timing error occurs in the input side cell, and there is a space for inserting the adjustment cell in the output side cell. If there is no other input side cell in the vicinity of the output side cell, or if a timing error or a slew rate error has occurred in the input side cell, the input side cell Determine in the neighborhood,
An automatic placement method characterized by that. The evaluation means performs the division into the plurality of areas by determining the shape and position of each area so that one pin of one cell exists in each area .
The automatic placement method according to claim 1, wherein: The evaluation means calculates the empty space ratio by paying attention to at least one of an output side cell that outputs a signal to the target net and an input side cell that inputs the signal. Limited to the other side,
3. The automatic arrangement method according to claim 1, wherein the automatic arrangement method is performed. It is an automatic placement device that automatically determines the position of an adjustment cell to be inserted for timing adjustment on a target net where a timing error has occurred among the nets connecting the cells of the designed electronic circuit. And
After the cell and wiring layout design, the substrate on which the electronic circuit is formed is divided into a plurality of areas, and an empty space rate is calculated for each area, which is the ratio of the area where no cells or wirings exist. An evaluation means;
A determination means for determining whether or not the adjustment cell can be inserted on the target net based on an empty space rate calculated in an area where the target net exists;
The adjustment cell is inserted in the vicinity of one of an output side cell that outputs a signal to the target net determined by the determination means that the adjustment cell can be inserted, and an input side cell that inputs the signal. Determine the position where the adjustment cell is to be inserted, and if the target net is formed of a plurality of layers by forming the target net in a plurality of layers, determine the net segment where the adjustment cell is to be inserted and the decision are performed by the manner that is giving priority to long net segment length, to be inserted the adjuster cell in a net segment was determined to be inserting the adjuster cell position among the plurality of net segments Done
The position where the adjustment cell is to be inserted,
When a timing error occurs in a plurality of the input side cells and there is a space for inserting the adjustment cell in the output side cell, a timing error occurs in the input side cell, and the input side cell In the case where there is no space for insertion of the adjustment cell, and there is a timing error in the input side cell, and there is another input side cell in the vicinity of the input side cell, the output side Determined in the vicinity of the cell,
When there is an input side cell in which a timing error has not occurred among the plurality of input side cells, a timing error occurs in the input side cell, and there is a space for inserting the adjustment cell in the output side cell. If there is no other input side cell in the vicinity of the output side cell, or if a timing error or a slew rate error has occurred in the input side cell, the input side cell Arrangement determining means for determining in the vicinity ;
An automatic placement apparatus comprising: The computer realizes the function of automatically determining the position of the adjustment cell to be inserted for timing adjustment on the target net where the timing error has occurred in the net connecting the cells of the designed electronic circuit. A program to
After the cell and wiring layout design, the substrate on which the electronic circuit is formed is divided into a plurality of areas, and an empty space rate is calculated for each area, which is the ratio of the area where no cells or wirings exist. Evaluation function,
A determination function for determining whether or not the adjustment cell can be inserted on the target net, based on an empty space rate calculated in an area where the target net exists;
The adjustment cell is inserted in the vicinity of one of an output side cell that outputs a signal to the target net determined by the determination function that the adjustment cell can be inserted, and an input side cell that inputs the signal. Determine the position where the adjustment cell is to be inserted, and if the target net is formed of a plurality of layers by forming the target net in a plurality of layers, determine the net segment where the adjustment cell is to be inserted and the decision are performed by the manner that is giving priority to long net segment length, to be inserted the adjuster cell in a net segment was determined to be inserting the adjuster cell position among the plurality of net segments Done
The position where the adjustment cell is to be inserted,
When a timing error occurs in a plurality of the input side cells and there is a space for inserting the adjustment cell in the output side cell, a timing error occurs in the input side cell, and the input side cell In the case where there is no space for insertion of the adjustment cell, and there is a timing error in the input side cell, and there is another input side cell in the vicinity of the input side cell, the output side Determined in the vicinity of the cell,
When there is an input side cell in which a timing error has not occurred among the plurality of input side cells, a timing error occurs in the input side cell, and there is a space for inserting the adjustment cell in the output side cell. If there is no other input side cell in the vicinity of the output side cell, or if a timing error or a slew rate error has occurred in the input side cell, the input side cell Placement determination function to determine in the vicinity ,
A program to make a computer realize.