JP2005258657A - Clock layout system and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock layout system and method capable of designing layout while evaluating the level of congestion due to buffer insertion, so that flip-flops are evenly placed. <P>SOLUTION: The clock layout system includes an F/F identifying part 12b that identifies flip-flops among cells placed in the design area of a logic circuit; a cut-line setting part 12c that divides the design area by means of a first segment; an F/F relocating part 12d that relocates the flip-flops so that the difference in number of flip flops between the divided areas is minimized; and a cell relocating part 12e that relocates the cells other than the flip-flops in the divided areas so that the number of wires crossing the first segment dividing the design area is minimized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a clock layout system and a clock layout method for arranging cells according to an integrated circuit device.

  In the conventional circuit design, first, a placement process for placing cells related to an integrated circuit device is performed, and a circuit in which the degree of congestion of cells on a semiconductor substrate is averaged needs to be generated. As a method for generating a circuit in which the degree of congestion is averaged, there is a mini-cut arrangement method (see, for example, Patent Document 1). “Mini cut placement method” means that the design area of a logic circuit is divided by one line segment (hereinafter referred to as “cut line”), and the “cell density” becomes equal in the two divided areas, and This is a technique of rearranging cells in divided areas so that the number of nets intersecting the cut line (hereinafter referred to as “the number of cuts”) is minimized. Then, a clock design is performed in which cells arranged by the mini-cut arrangement process are wired by clock wiring. When designing the clock, a buffer for amplifying the signal is inserted into the clock wiring. The “cell density” refers to the ratio of the cell area to the design area.

However, when inserting a buffer by clock design, the cell position has already been determined by the cell placement process, so in places where cells are concentrated, inserting the buffer increases the degree of congestion, The problem that it becomes impossible to insert occurs. Even when the cell congestion level is averaged by the mini-cut arrangement method, the arrangement of flip-flops (F / F) for driving the clock signal may be biased. In this case, in a place where the F / F is concentrated, there is a problem that the degree of congestion is increased by inserting a buffer or the buffer cannot be inserted.
JP 2001-24153 A

  An object of the clock layout system and the clock layout method according to the present invention is to reduce the degree of congestion in consideration of buffer insertion in clock design.

  The first feature of the present invention is that an F / F discriminating unit that discriminates a flip-flop among cells arranged in a design region of a logic circuit, a cut line setting unit that divides the design region by a first line segment, The F / F rearrangement section for rearranging the flip-flops and the number of wirings intersecting the first line segment for dividing the design area are minimized so that the difference in the number of flip-flops in the divided area is minimized. Thus, the gist of the present invention is to provide a clock layout system including a cell rearrangement unit that rearranges cells other than flip-flops in divided areas.

  The second feature of the present invention is that the F / F discriminating unit of the arithmetic processing unit discriminates the flip-flop among the cells arranged in the design area of the logic circuit, and the cut line setting unit of the arithmetic processing unit includes The step of dividing the design area by the first line segment and the F / F rearrangement unit of the arithmetic processing unit rearrange the flip-flop so that the difference in the number of flip-flops in the divided area is minimized. And the cell rearrangement unit of the arithmetic processing unit rearranges cells other than the flip-flop in the divided area so that the number of wirings intersecting the first line segment dividing the design area is minimized. And a clock layout method comprising steps.

   According to the clock layout system and the clock layout method of the present invention, it is possible to alleviate the degree of congestion in consideration of buffer insertion in clock design.

(Clock layout system)
A clock layout system according to an embodiment of the present invention will be described. As shown in FIG. 1, the clock layout system according to the embodiment of the present invention includes a bus 11, a logic circuit data input device 14 connected to the bus 11, an output device 17, a specified value input device 15, and a timing constraint input. A device 16, a cut line information storage device 18, a logic circuit information storage device 19, and a CPU 12 are provided. The CPU 12 includes an initial placement unit 12a, an F / F determination unit 12b, a cut line setting unit 12c, an F / F rearrangement unit 12d, a temporary clock layout processing unit 13, a buffer number counting unit 12f, a buffer number comparison unit 12g, and a clock layout. A processing unit 12j and a timing constraint determination unit 12h are provided. The temporary clock layout processing unit 13 further includes a clock wiring processing unit 13a, a congestion degree determination unit 13b, and a buffer insertion unit 13c. The logic circuit data input device 14 inputs the logic circuit to the logic circuit information storage device 19 as data. The output device 17 outputs data stored in the logic circuit information storage device 19, data processed by the CPU 12, and the like. The logic circuit information storage device 19 stores data input by the logic circuit input device, data processed by the CPU 12, and the like. The designated value input device 15 inputs a designated value for designating the number of buffers arranged in one area divided by the cut line to the CPU 12. The timing constraint input device 16 inputs a timing condition to be satisfied by a signal input to the cell. The cut line information storage device 18 stores the position of the cut line and the order in which the cut line is drawn.

  The initial placement unit 12a places cells whose positions are fixed, and places cells whose positions are not fixed. The cells whose positions are not fixed are arranged so as to satisfy the timing constraint input by the timing constraint input device 16. For example, as illustrated in FIG. 2, the initial placement unit 12 a places the route driver 10 whose position is fixed on the design region 4 at the fixed position. The initial placement unit 12a places the F / Fs 1a to 1p and the logic elements 2a to 2j, which are cells whose positions are not fixed, on the design region 4 so as to satisfy the timing constraint. The timing constraint is determined by the wiring capacity and length of the wiring connecting the F / F and the logic element. For example, a wiring 6ad that connects the logic elements 2a and 2d, a wiring 6ae that connects the logic elements 2a and 2e, a wiring 6de that connects the logic elements 2d and 2e, a wiring 6df that connects the logic elements 2d and 2f, a logic element 2b, Wiring 6bf for connecting 2f, wiring 6bc for connecting logic elements 2b and 2c, wiring 6fi for connecting logic elements 2f and 2i, wiring 6eh for connecting logic elements 2e and 2h, wiring 6eg for connecting logic elements 2e and 2g Wiring capacity and length of the wiring 6gh connecting the logic elements 2g and 2h, the wiring 6hi connecting the logic elements 2h and 2i, the wiring 6ij connecting the logic elements 2i and 2j, and the wiring 6gj connecting the logic elements 2g and 2j Thus, timing constraints are determined. In FIG. 2, wirings connecting the F / Fs 1a to 1p and the logic elements 2a to 2j are omitted.

  The F / F determination unit 12b determines the F / F among the cells arranged by the initial arrangement unit 12a. For example, F / F 1a to 1p shown in FIG. The cut line setting unit 12 c sets a cut line drawn in the design area 4. The cut line setting unit 12c sets a cut line according to a predetermined order. For example, the cut line 5a is set as shown in FIG. 3, the cut line 5b is set as shown in FIG. 4, and the cut line 5c is set as shown in FIG. Here, the cut line set first is referred to as a “first cut line”, and the cut line set in an area delimited by the first cut line is referred to as a “second cut line”. In this way, by setting the first cut line, the second cut line, the third cut line,..., And further the cut lines, the area delimited by the cut lines is subdivided. In FIG. 3, the cut line 5a is a “first cut line”, and the cut line 5b and the cut line 5c are “second cut lines”.

  The F / F rearrangement unit 12d determines the F / F determined by the F / F determination unit 12b so that the difference in the number of F / Fs in the area divided by the cut line is minimized. Rearrange. For example, as shown in FIG. 3, F / F1a to 1p are divided into the area 41 divided by the cut line 5a as F / F1a, F / F1b, F / F1d, F / F1f, F / F1g, F / F1i, Rearrange F / F1j. Then, F / F1e, F / F1h, F / F1k, F / F1l, F / F1m, F / F1n, F / F1o, and F / F1p are rearranged in the region 42. In this case, the number of F / Fs in the region 41 and the region 42 is equal to 8, and the difference in the number of F / Fs is 0, which is the minimum. 4, F / F1e, F / F1h, F / F1k, and F / F1l are rearranged in the area 42a divided by the cut line 5b, and F / F1m, F / F1n, Rearrange F / F1o and F / F1p. Further, as shown in FIG. 5, F / F1a, F / F1b, and F / F1d are rearranged in the area 42a divided by the cut line 5c, and F / F1f, F / F1g, F / F1i, Rearrange F / F1j. The rearranged F / Fs 1a to 1p are rearranged equally in each region.

  The cell rearrangement unit 12e rearranges cells other than the F / F in the area divided by the cut lines so that the cell density is uniform and the number of cuts is minimized. For example, as shown in FIG. 3, when the cut line 5a is set, the cell rearrangement unit 12e rearranges the logic elements 2b, 2c, 2f, 2i, and 2j in the region 41, and the logic elements 2a, 2d, and 2e, 2h, and 2g are rearranged in the region 42. In this case, the areas of the region 41 and the region 42 are substantially equal, and the number of logic elements rearranged in each region is also equal, so that the cell density is uniform. The number of cuts is 3. This number of cuts is the minimum value when the number of logic elements rearranged in each region is equal. Similarly, as shown in FIG. 4, when the cut line 5b is set, the cell rearrangement unit 12e rearranges the logic elements 2a, 2d, and 2e in the region 42a, and places the logic elements 2h and 2g in the region 42b. Rearrange to Further, as shown in FIG. 5, when the cut line 5c is set, the cell rearrangement unit 12e rearranges the logic elements 2b, 2c, and 2f in the region 41a and rearranges the logic elements 2i and 2j in the region 41b. Deploy.

  The temporary clock layout processing unit 13 temporarily performs clock layout processing on the F / F rearranged by the F / F rearrangement unit 12d. The temporary clock layout processing unit 13 connects the F / F with a clock wiring and inserts a buffer necessary for driving the F / F. The clock wiring processing unit 13a connects the F / Fs with a clock wiring. The congestion degree determination unit 13b determines whether a buffer can be inserted into the clock wiring routed by the clock wiring processing unit 13a. If the buffer cannot be inserted at the position where the F / F is driven because the cell congestion level is high, the congestion level determination unit 13b determines that the buffer cannot be inserted. The buffer insertion unit 13c inserts the buffer at a position where the buffer can drive the F / F.

  For example, as shown in FIG. 6, in the area 41a, the clock wiring processing unit 13a connects the F / Fs 1a and 1c with the clock wiring 9e, and the buffer insertion unit 13c inserts the buffer 8e. The clock wiring processing unit 13a connects the F / Fs 1b and 1d with the clock wiring 9f, and the buffer insertion unit 13c inserts the buffer 8f. The clock wiring processing unit 13a connects the buffer 8e and the buffer 8f with the clock wiring 9k. Similarly, in the region 41b, the clock wiring processing unit 13a connects the F / Fs 1f, 1g, 1i, and 1j with the clock wirings 9g, 9h, and 9l, and the buffer insertion unit 13c inserts the buffers 8g and 8h. In the area 42a, the clock wiring processing unit 13a connects the F / Fs 1e, 1h, 1k, and 11 with the clock wirings 9a, 9b, and 9i, and the buffer insertion unit 13c inserts the buffers 8a and 8b. Then, the provisional clock layout processing unit 13 connects the F / Fs in the two regions separated by the last set cut line (hereinafter referred to as “final cut line”) through the clock wiring. For example, as illustrated in FIG. 7, the clock wiring processing unit 13 a includes F / F 1 a, 1 b, 1 c, 1 d in the areas 41 a and 41 b separated by the cut line 5 c that is the final cut line of the area 41 a, and F / F1f, 1g, 1i, and 1j are connected by the clock wiring 9n, and the buffer insertion unit 13c inserts the buffers 8e and 8l. Similarly, the clock wiring processing unit 13a clocks the F / F 1e, 1k, 11 and 1h and the F / F 1m, 1n, 1o and 1p in the regions 42a and 42b delimited by the cut line 5b which is the final cut line. Connected by the wiring 9m, the buffer insertion unit 13c inserts the buffers 8i and 8j.

  In addition, the temporary clock layout processing unit 13 connects F / Fs in two areas separated by the cut line in descending order from the final cut line, and inserts a buffer. For example, as shown in FIG. 7, the cut line 5b and the cut line 5c, which are the final cut lines, are the second cut lines, and therefore the clock wiring processing unit 13a is divided by the cut line 5a that is the first cut line. The F / F1a to F / F1p in the regions 41a, 41b, 42a, and 42b are connected by the clock wiring 9o, and the buffer insertion unit 13c inserts the buffers 8m and 8n. Finally, the clock wiring processing unit 13a connects the F / Fs 1a to 1p to the root driver 10 through the clock wiring 9p. As described above, the temporary clock layout processing unit 13 sequentially connects the F / Fs to the root driver in the bottom-up manner through the clock wiring, and inserts a buffer for driving the F / Fs.

  The buffer number counting unit 12f counts the number of buffers arranged in one area divided by the cut line. The buffer number comparison unit 12g compares the number of buffers designated by the designated value input device 15 with the number of buffers counted by the buffer number counting unit 12f. When the number of buffers designated by the designated value input device 15 is larger than the number of buffers counted by the buffer number counting unit 12f, the buffer number comparing unit 12g instructs the cut line setting unit 12c to stop setting the cut line. . The timing constraint determination unit 12 h determines whether or not the F / F connected by the clock wiring by the temporary clock layout processing unit 13 satisfies the timing constraint input by the timing constraint input device 16. When the timing constraint determination unit 12h determines that the timing is not satisfied, and when the congestion level determination unit 13b determines that the buffer cannot be inserted at the position where the F / F is driven because the cell congestion level is high. The cut line changing unit 12i deletes the final cut line and resets the final cut line. Even if the final cut line is deleted and the final cut line is reset, if the timing constraint is not satisfied and the buffer cannot be inserted, the cut line changing unit 12i deletes the cut lines in descending order from the final cut line, Reset the cut line. For example, the cut line changing unit 12 i deletes the cut line 5 b illustrated in FIG. 7 and resets the final cut line in the region 42. If the timing constraint is still not satisfied and the buffer cannot be inserted, the cut line changing unit 12i proceeds from the cut line 5b that is the second cut line and the cut line 5c to the cut line 5a that is the first cut line in descending order. The cut line is deleted, the cut line 5d is reset as shown in FIG. 8, and the cut lines 5e and 5f are reset. The clock layout processing unit 12j routes the F / F clock wiring when the timing constraint is satisfied and the clock layout in which the buffer is inserted at a position where the F / F can be driven is determined. Insert the necessary buffers for wiring.

  According to the clock layout system of the embodiment of the present invention, the insertion and placement of the buffers necessary for the clock layout are completed by performing the cell placement process and the clock design in parallel. A layout that evaluates the degree can be designed. Further, since the clock wiring process is completed at the same time, the clock wiring process can be easily performed and has little influence on the circuit. Further, the F / Fs are evenly arranged.

(Clock layout method)
A clock layout method according to an embodiment of the present invention will be described with reference to FIGS.

  (A) In step S100, the initial placement unit 12a performs placement of cells whose positions are fixed and cells whose positions are not fixed. In step S101, the F / F determination unit 12b determines the F / F among the cells arranged by the initial arrangement unit 12a. In step S102, the cut line setting unit 12c sets a cut line drawn in the design area. The cut line setting unit 12c sets a cut line according to a predetermined order. In step S103, the F / F rearrangement unit 12d causes the F / F discriminated by the F / F discrimination unit 12b to minimize the difference in the number of F / Fs in the area divided by the cut line. , F / F is rearranged. In step S104, the cell rearrangement unit 12e rearranges cells other than the F / F in the region divided by the cut line so that the cell density is uniform and the number of cuts is minimized.

  (B) In step S105, the clock wiring processing unit 13a connects the F / Fs with the clock wiring. In step S106, the congestion degree determination unit 13b determines whether a buffer can be inserted into the clock wiring routed by the clock wiring processing unit 13a. In step S107, when the congestion degree determination unit 13b determines that the buffer cannot be inserted, in step S109, the cut line changing unit 12i resets the cut line, returns to step S103, and the F / F rearrangement unit 12d. Rearranges the F / F. If the congestion determination unit 13b determines in step S107 that a buffer can be inserted, in step S108, the buffer insertion unit 13c inserts the buffer at a position where the buffer can drive the F / F.

  (C) In step S110, the buffer number counting unit 12f counts the number of buffers arranged in one area divided by the cut line. In step S111, the buffer number comparing unit 12g compares the number of buffers designated by the designated value input device 15 with the number of buffers counted by the buffer number counting unit 12f. In step S111, when the number of buffers designated by the designated value input device 15 is equal to or less than the number of buffers counted by the buffer number counting unit 12f, the process returns to step S102, and the cut line setting unit 12c further sets cut lines. . In step S111, when the number of buffers specified by the specified value input device 15 is larger than the number of buffers counted by the buffer number counting unit 12f, the timing constraint determining unit 12h uses the temporary clock layout processing unit 13 in step S112. It is determined whether the F / F connected by the clock wiring satisfies the timing constraint input by the timing constraint input device 16. If the timing constraint determination unit 12h determines in step S112 that the timing is not satisfied, in step S109, the cut line changing unit 12i resets the cut line, returns to step S103, and the F / F rearrangement unit 12d rearranges the F / F. If the timing constraint determining unit 12h determines that the timing is satisfied in step S112, in step S113, the clock layout processing unit 12j routes the F / F clock wiring and a buffer necessary for clock wiring wiring. Insert.

  Note that the rearrangement of the cut lines in step S109 is performed as follows.

  (D) In step S109a, the cut line changing unit 12i deletes the final cut line. When the cut line changing unit 12i determines in step S109b that the final cut line has not been reset yet, in step S109c, the cut line changing unit 12i resets the final cut line. In step S109b, when the cut line changing unit 12i determines that the final cut line has already been reset in step S109c, in step S109d, the cut line changing unit 12i sets the cut line numbers in descending order from the final cut line. Deletes the cut line that is one smaller. For example, in FIG. 7, when the third cut line (not shown) that divides the region 42 a is the final cut line, the cut line changing unit 12 i uses the second cut line that is one smaller in number than the third cut line. A certain cut line 5b is deleted. In step S109e, when the cut line changing unit 12i determines that the cut line whose number is one smaller than the final cut line has not been reset, the cut line changing unit 12i resets the cut line in step S109f. To do. In step S109e, when the cut line changing unit 12i determines that a cut line having a number one smaller than the final cut line has already been reset in step S109f, the cut line changing unit 12i further decreases the number by one. Delete the cut line. For example, in FIG. 7, when the cut line 5b that is the second cut line has already been reset, the cut line changing unit 12i uses the cut line that is the first cut line that is one smaller in number than the second cut line. Delete the cut line up to 5a. As described above, even if the cut line is reset, if the timing constraint is not satisfied and the buffer is not inserted, the cut line is further reset in descending order.

  According to the clock layout method according to the embodiment of the present invention, the insertion and placement of the buffers necessary for the clock layout are completed by performing the cell placement process and the clock design in parallel. A layout that evaluates the degree can be designed. Further, since the clock wiring process is completed at the same time, the clock wiring process can be easily performed and has little influence on the circuit. Further, the F / Fs are evenly arranged.

  The cut line setting unit further divides the design area divided by the first line segment by the second line segment.

  The cut line changing unit deletes the first line segment and the third line segment when the buffer cannot be inserted due to the congestion degree of the wiring in the area divided by the third line segment, and the design area by the fourth line segment. A clock layout system characterized by dividing the clock. A clock layout method, wherein the cut line setting unit further comprises a step of dividing the design region divided by the first line segment by the second line segment.

  The clock wiring processing unit of the arithmetic processing device connects the flip-flops with the clock wiring, and the congestion determination unit of the arithmetic processing device determines whether the buffer can be inserted into the clock wiring from the congestion level of the wiring. A clock layout method, further comprising: a step of deleting a second line segment and dividing a design area by a third line segment when a buffer cannot be inserted.

  A step of counting the number of buffers arranged in one region divided by the second line segment, and a number of buffers comparing unit of the arithmetic processing unit is a predetermined value specified in advance. A step of comparing the number of buffers counted by the buffer number counting unit and, when the specified value is larger than the number of buffers, giving a stop instruction to stop the design area to be divided by the second line segment to the cut line setting unit; A clock layout method comprising: a clock layout method comprising:

  The timing constraint determining unit of the arithmetic processing unit determines whether the flip-flop connected by the clock wiring satisfies a timing constraint to be satisfied by a signal input to a cell arranged in the design area, and the timing constraint If not, the cut line changing unit further comprises a step of deleting the second line segment and dividing the design area by the third line segment.

  In the area divided by the third line segment, when the buffer cannot be inserted due to the congestion degree of the wiring, the cut line changing unit deletes the first line segment and the third line segment, and the design area is formed by the fourth line segment. A clock layout method comprising the step of dividing

It is a figure showing an example of a clock layout system concerning an embodiment of the invention. It is the figure which showed an example of the design area | region where the root driver and the cell were initially arranged. It is the figure which showed an example of the design area | region which set the 1st cut line. It is the figure which showed an example of the design area | region which set the 2nd cut line. It is the figure which showed an example of the design area | region which rearranged the cell to the area | region divided | segmented by the cut line. It is the figure which showed an example of the design area | region which connected the rearranged cell by wiring and inserted the buffer. It is the figure which showed an example of the design area | region which connected the cell to the route driver with wiring, and inserted the buffer. It is the figure which showed an example of the design area | region which reset the cut line. It is the flowchart which showed an example of the clock layout method which concerns on embodiment of this invention. It is the flowchart which showed an example of the clock layout method which concerns on embodiment of this invention.

Explanation of symbols

F / F1a to F / F1p Flip-flop 2a to 2j Logic element 4 Design area 5a to 5f Cut line 8a to 8n Buffer 9a to 9p Clock wiring 10 Route driver 11 Bus 12 CPU
12a Initial arrangement unit 12b F / F determination unit 12c Cut line setting unit 12d Relocation unit 12e Cell relocation unit 12f Buffer number counting unit 12g Buffer number comparison unit 12h Timing constraint determination unit 12i Cut line changing unit 12j Clock layout processing unit 13 Temporary clock layout processing unit 13a Clock wiring processing unit 13b Congestion degree determination unit 13c Buffer insertion unit 14 Logic circuit data input device 15 Designated value input device 16 Timing constraint input device 17 Output device 18 Cutline information storage device 19 Logic circuit information storage device 41, 42, 41a, 41b, 42a, 42b

Claims (5)

An F / F discriminating unit for discriminating a flip-flop among the cells arranged in the design area of the logic circuit;
A cut line setting unit that divides the design area by a first line segment;
An F / F rearrangement unit for rearranging the flip-flops so that a difference in the number of flip-flops in the divided area is minimized;
A cell rearrangement unit that rearranges cells other than the flip-flops in the divided area so that the number of wirings intersecting the first line segment dividing the design area is minimized. And clock layout system. The cut line setting unit further divides the design area divided by the first line segment by a second line segment,
A clock wiring processing unit for connecting the flip-flops by clock wiring;
A congestion degree determination unit that determines whether a buffer can be inserted into the clock line from the degree of congestion of the wiring;
The clock layout system according to claim 1, further comprising: a cut line changing unit that deletes the second line segment and divides the design area by the third line segment when the buffer cannot be inserted. A designated value input device for inputting a designated value for designating the number of buffers arranged in one area divided by the second line segment;
A buffer number counting unit for counting the number of the buffers;
A buffer that compares the specified value with the number of buffers, and gives a stop command to the cutline setting unit to stop dividing the design area by the second line segment when the specified value is larger than the number of buffers. The clock layout system according to claim 1, further comprising: a number comparison unit. A timing constraint input device for inputting a timing constraint to be satisfied by a signal input to a cell arranged in the design region;
A timing constraint determining unit that determines whether or not the flip-flop connected by the clock wiring satisfies the timing constraint;
The said 2nd line segment is deleted when it does not satisfy | fill the said timing restrictions, The cutline change part which divides | segments the said design area | region with a 3rd line segment is further provided. Clock layout system. A step in which the F / F determination unit of the arithmetic processing unit determines a flip-flop among the cells arranged in the design area of the logic circuit;
The cut line setting unit of the arithmetic processing unit divides the design region by a first line segment;
The F / F rearrangement unit of the arithmetic processing unit rearranges the flip-flop so that the difference in the number of flip-flops in the divided area is minimized;
The cell rearrangement unit of the arithmetic processing unit rearranges cells other than the flip-flops in the divided area so that the number of wirings intersecting the first line segment dividing the design area is minimized. A clock layout method comprising the steps of:

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