JP4772302B2 - Micro-electromechanical system and manufacturing method thereof - Google Patents

Description

  The present invention relates to a microelectromechanical system in which a transducer and a wiring portion that provides electrical connection to the transducer are integrated on the same substrate, and a manufacturing method thereof.

  Conventionally, research and development of a micro electro mechanical system (MEMS) in which a transducer and a control circuit are integrated on the same substrate have been advanced. Here, the “transducer” means an element having a function of converting electrical energy into other forms of energy and / or a function of converting other forms of energy into electrical energy. A microactuator or microsensor including at least a part of a physically deformable structure is one of typical transducers that perform electro-mechanical energy conversion.

  The manufacture of the micro electro mechanical system as described above is realized by forming a transducer after a control circuit is formed on a substrate. For this reason, when the process temperature in the process of forming the transducer is high, there is a problem that the control circuit is deteriorated.

  In general, transducers are required to exceed reference levels in terms of residual stress, creep strength, wear strength, fatigue failure strength, and surface roughness. This mechanical characteristic is not required for a normal LSI manufactured by a semiconductor manufacturing process. In order to improve such mechanical characteristics, in order to form a transducer, a thin film deposition process or an annealing process that requires high-temperature processing is often indispensable. For example, polysilicon, one of the materials most widely studied for application to microelectromechanical systems, is at least 600 ° C. for 150 minutes or more, or 1050 ° C. in order to obtain good film properties with low residual stress. An annealing process of 30 minutes or more is necessary. Silicon nitride is known to have a silicon-rich composition that can reduce the residual stress to 10 MPa or less when annealed in an oxygen environment. At this time, annealing conditions of 825 to 850 ° C. for 180 minutes or more are necessary. is there. In addition, the oxide ferroelectric lead zirconate titanate (PZT) needs to be heat-treated at about 600 to 650 ° C. in order to enhance the orientation of the crystal phase, and silicon carbide having extremely high mechanical chemical strength is formed. Sometimes a temperature condition of 750-800 ° C. is required. In this way, polysilicon, silicon nitride, lead zirconate titanate, and silicon carbide have excellent material properties and are typical materials in semiconductor processes, but to use them as structural materials for high-quality transducers A high temperature process of 600 ° C. or higher is required.

  On the other hand, the heat resistant temperature of the control circuit is about 450 to 525 ° C. in a general CMOS circuit. Therefore, if a transducer that requires a high-temperature process as described above is formed after the control circuit is formed, the control circuit may be damaged.

  It is known that the main cause of breakage of the control circuit is an increase in resistance and disconnection of an aluminum alloy usually used in the wiring portion. Since aluminum has a low melting point of 660 ° C., a process for increasing the temperature to about 660 ° C. or higher cannot be performed after the control circuit is formed using aluminum or an alloy thereof. In addition, aluminum tends to generate voids and the like with grain growth and atomic diffusion even at a temperature of 660 ° C. or lower. When the wiring for the control circuit is formed from aluminum having a low melting point, the wiring is deteriorated in the transducer forming process. For this reason, when aluminum is used as the wiring material of the control circuit, it is necessary to form a transducer in a temperature range that does not deteriorate the aluminum wiring, and the deterioration temperature of the aluminum defines the heat resistant temperature of the control circuit. Become.

  As a method for increasing the heat resistance temperature of the control circuit, tungsten, which is a refractory metal widely known in the field of semiconductor integrated circuit technology, can be used instead of aluminum (see, for example, FIG. 4 of Non-Patent Document 1). Non-Patent Document 1 discloses a micro electro mechanical system including a control circuit using tungsten as a conductor and a transducer using polysilicon. In this microelectromechanical system, the polysilicon constituting the transducer is annealed at a high temperature of 1050 ° C. for 1 hour, and the control circuit has heat resistance against this high temperature process.

  On the other hand, in the normal LSI field, a damascene method is widely used in which an unnecessary portion of a conductor is ground and removed using a CMP (Chemical Mechanical Polishing) process. According to this damascene method, it is possible to use a copper-based material that has been difficult to use because etching is difficult before that. The damascene method is a technique that enables the formation of finer wiring by eliminating the influence of the topology of the lower wiring. Since the resistivity of copper is lower than the resistivity of aluminum, the use of copper wiring can reduce the electrical resistance of the wiring and improve the operating frequency of the CPU.

  The copper wiring is provided with a barrier layer such as titanium nitride for preventing diffusion of copper atoms. The limiting thickness of the barrier layer is set so that the specific resistance value of the copper wiring using the barrier layer is smaller than the specific resistance value of the aluminum wiring not using the barrier layer (1.58 times that of copper). . Conventionally, copper wiring by the damascene method has been applied only to fine wiring having a rule of 0.25 μm or less, so that the barrier layer used is also extremely thin with a thickness of 40 nm or less.

  Further, it is known that when 2.98 wt% titanium is mixed in copper, the grain growth of copper can be suppressed even during annealing at 800 ° C. (for example, see Non-Patent Document 2).

The damascene method is also applied to the production of micromachines (see Non-Patent Document 3, for example). In Non-Patent Document 3, anisotropic etching is performed using a copper wiring / low-k interlayer insulating film laminate formed according to the 0.18 μm rule as an inductor and the low-k interlayer insulating film as a top metal layer as a mask. After the removal, the substrate is removed by isotropic etching to provide a hollow structure under the inductor.
J. et al. M.M. Bustillo, R.A. T.A. Howe, R.A. S. Muller, “Surface Micromachining for Microelectro-mechanical Systems”, Proceedings of the IEEE, Vol. 86, no. 8, pp. 1552-1574 (August 1998) C. J. et al. Liu, J .; S. Jeng, J .; S. Chen, "Effects of Ti addition on the morphology, interfacial reaction, and diffusion of Cu on SiO2", Journal of Vacuum Science & Technology. Technology. 20, no. 6, pp. 2361-2366 (Nov / Dec 2002) H. Lakdawala, et al. “Micromachined High-Q Inductors in a 0.18-μm Copper Interconnect Low-K Directive CMOS Process”, IEEE Journal of Solid-State Circuits. 37, no. 3, pp. 394-403 (March 2002)

  However, the configuration described in Non-Patent Document 1 has a large resistance value of tungsten as a conductor and a large temperature change of the resistance value. For this reason, the operating speed of the micro electro mechanical system is reduced, the power consumption is increased, or the operating characteristics of the element are changed due to the temperature characteristics of the wiring portion.

  In addition, copper wiring intended for ordinary LSI needs to prevent copper atoms from diffusing with a thin barrier layer of 40 nm or less. is necessary. The main diffusion path of the barrier layer is at the grain boundary of the barrier material. For this reason, in order to enhance the diffusion preventing effect, it is particularly effective to increase the grain size of the barrier material and align the crystal orientation between the grains. However, if the thickness of the barrier layer is small, many of the atoms in the barrier layer are affected by the interface effect with the insulating film, and the grain size is reduced and the crystal orientation is easily randomized. This can be reliably prevented. To do so, strict management and inspection of wiring quality is required.

  Moreover, in order to prevent the grain growth of copper, when about 2.98 wt% titanium is mixed into copper, the specific resistance value is larger than 5 μΩcm, and the specific resistance value of aluminum is 2.7 μΩcm. It was not an effective configuration for the purpose of lowering.

  Non-Patent Document 3 discloses that the damascene method is applied to manufacture of a micromachine. According to this method, the inductor corresponding to the transducer is formed by a low-temperature process, and Non-Patent Document 3 makes no mention of a configuration that solves the problem when the transducer requires a high-temperature process. Further, after patterning the interlayer insulating film by an anisotropic etching technique, the silicon substrate is removed by an isotropic etching technique to provide a hollow structure. For this reason, the structure of the transducer that can be formed is limited to a very simple one. In addition, since the region to be removed by etching in the silicon substrate cannot be clearly defined, it is difficult to prevent damage to the control circuit due to overetching and deterioration in reliability due to underetching of the transducer.

  The present invention has been made in view of the above circumstances, and a purpose thereof is a micro-electromechanical system that realizes both prevention of high-temperature destruction of a wiring portion, ensuring of transducer characteristics, and reduction of wiring resistance, and a manufacturing method thereof. Is to provide.

  Another object of the present invention is to provide a microelectromechanical system in which a transducer having a complicated shape is formed reliably and at low cost, and a manufacturing method thereof.

  A micro electro mechanical system of the present invention is a micro electro mechanical system comprising a substrate, a transducer supported by the substrate, and a conductor layer supported by the substrate and electrically connected to the transducer. The transducer has a portion formed of silicon or a silicon compound, and the conductor layer contains at least one element selected from the group consisting of copper, gold, and silver as a main component. And at least a portion of the conductor layer is located at a level between the portion of the transducer formed from silicon or a silicon compound and the substrate.

  In a preferred embodiment, the transducer includes a structure including the portion formed of silicon or a silicon compound, and a gap provided around the structure, and a part of the conductor layer includes: It is located below the structure.

  In a preferred embodiment, the portion of the transducer is formed from polysilicon, silicon nitride, lead zirconate titanate, and / or silicon carbide.

  In a preferred embodiment, the refractory conductor contains 0.1 to 1.0 wt% of any element of Ti, Ta, W, Mo, and Si.

  In a preferred embodiment, the surface of the refractory conductor is covered with a barrier layer having a thickness of 50 nm or more.

  In a preferred embodiment, the barrier layer includes any one of Ti, W, Ta, and Re, a nitride of any of the metals, and / or a silicide of any of the metals.

  In a preferred embodiment, the conductor layer has a wiring pattern, and the minimum line width of the wiring pattern is 0.35 μm or more.

  In a preferred embodiment, the wiring pattern of the conductor layer includes an upper layer wiring portion and a lower layer wiring portion formed at different levels.

  Another microelectromechanical system of the present invention is a microelectromechanical system comprising a substrate, and a wiring portion region and a transducer region supported by the substrate, wherein the wiring portion region includes a plurality of conductors, An insulator provided between the plurality of conductors, the transducer region having at least one transducer, the transducer comprising a structure and a gap provided around the structure; And a shielding wall that is formed at a boundary portion between the wiring portion region and the transducer region and separates the insulator and the gap.

  In a preferred embodiment, the insulator in the wiring region is formed from an unetched portion of the insulating film in which the gap is formed by etching a part that functions as a sacrificial layer.

  In a preferred embodiment, the shielding wall is made of a material that functions as a barrier against an etchant for etching the insulating film.

  In a preferred embodiment, the shielding wall hermetically separates the wiring portion region from the transducer region.

  In a preferred embodiment, at least a part of the shielding wall is formed of the same material as the conductor and / or the structure.

  In a preferred embodiment, at least a part of the conductor is formed of the same material as the structure.

  In a preferred embodiment, the conductor and the structure are collectively formed by a damascene method.

  In a preferred embodiment, the surface of the structure is smoothed, and the surface functions as an optical reflecting surface.

  In a preferred embodiment, the transducer further includes an electrode for driving the structure, and a surface of the electrode is smoothed by the damascene method and faces the structure through the gap.

  In a preferred embodiment, the structure is formed by a dual damascene method, and the surface of the structure facing the electrode functions as a non-smoothing surface.

  In preferable embodiment, it has the conductive protective film formed integrally with the said structure and / or the said conductor.

  In a preferred embodiment, the conductive protective film includes gold and / or silver.

  A method of manufacturing a micro electro mechanical system according to the present invention is a method of manufacturing a micro electro mechanical system including a transducer and a wiring portion electrically connected to the transducer, and an insulator having a recess is formed on a substrate. A first step of forming, a second step of forming a conductor layer by embedding the recess with a refractory conductor mainly composed of copper, gold, or silver, and a structure of the transducer The third step includes a step of raising the temperature of the substrate to 600 ° C. or higher.

  In a preferred embodiment, the second step includes depositing the refractory conductor so as to cover the insulator, and performing a smoothing process on the refractory conductor to thereby form the refractory conductor. And a step of removing a portion located outside the concave portion.

  In a preferred embodiment, at least a part of the structure is formed of any one of polysilicon, silicon nitride, lead zirconate titanate, and silicon carbide.

  In another microelectromechanical system manufacturing method according to the present invention, a wiring region for forming a conductor and an insulator provided between the conductors, a structure, and a periphery of the structure are provided on a substrate. Forming a transducer region for forming a sacrificial layer, a shielding wall for separating the wiring region and the transducer region, and forming a void by removing the sacrificial layer by isotropic etching. A manufacturing method of a micro electro mechanical system including a first step of forming a stopper layer having resistance to etching on the substrate, and forming the insulator and the sacrificial layer on the stopper layer A second step, a third step of forming a shielding wall having resistance to etching at the boundary between the insulator and the sacrificial layer so as to be continuous with the stopper layer; And a fourth step of forming a protective film for protecting the edge member so as to be continuous with the shield wall, and a fifth step of removing by isotropically etching the sacrificial layer.

  In a preferred embodiment, a part of the conductor and / or a part of the structure is formed simultaneously with the shielding wall.

  In a preferred embodiment, the structure is formed by a damascene method.

  In a preferred embodiment, the surface of the structure to be an optical reflecting surface is smoothed.

  In a preferred embodiment, at least one of the structure and the opposing surfaces of the electrodes that drive the structure facing each other through a gap is smoothed.

  In a preferred embodiment, the structure is formed by a dual damascene method so that the surface of the structure facing the electrode is a non-smoothing surface.

  In a preferred embodiment, a first insulating layer and a second insulating layer are formed through a stopper provided with an opening in at least a part thereof, and the first and second insulating layers are used as the sacrificial layer. Make it work.

  In a preferred embodiment, the opening is used as an inlet of an etchant for etching the sacrificial layer.

  According to the microelectromechanical system of the present invention, by forming a wiring portion with a conductor mainly composed of copper, gold, or silver, and forming a transducer using either silicon or a silicon compound, The characteristics of the transducer can be enhanced while preventing the wiring portion from being destroyed. Wiring resistance can be reduced.

  In addition, if a sacrificial layer or the like is etched at the boundary between the wiring portion region and the transducer region on the substrate and the sacrificial layer is etched, a transducer structure having a complicated shape can be formed. Can improve the reliability.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, refer to FIG. FIGS. 1A to 1C are cross-sectional views showing an enlarged part of a substrate in the first half of the manufacturing process in the present embodiment.

  FIG. 1A shows a cross section of the substrate at a stage where the step of forming the first conductor layer is performed. The substrate used in this embodiment is an n-type silicon substrate 1, and a wiring part region 2 and a transducer region 3 are formed on the n-type silicon substrate 1.

  A CMOS circuit or a BiCMOS circuit is mainly formed in the wiring portion region 2 and generates a drive signal for driving the transducer in accordance with an external input signal. In the transducer area 3, a plurality of transducers and a plurality of switching elements for selecting a transducer to be driven are mainly formed. The switching element is formed by an nMOS transistor.

  The switching elements in the wiring portion region 2 and the transducer region 3 in this embodiment are both constituted by transistors formed on the surface of the silicon substrate 1. A part of the switching element may be a thin film transistor formed on the silicon substrate 1. When all the switching elements are formed of thin film transistors, the substrate 1 does not have to be a single crystal silicon substrate, and may be an insulating substrate such as a quartz substrate, or a conductive substrate having an insulating layer on the surface. May be. In any case, however, the substrate must have the property of withstanding high temperature processes performed when forming the transducer.

  The above circuit is manufactured by using a relatively rough manufacturing process having a design rule of 0.35 μm or more, for example. The design rule of this embodiment is 0.5 μm. The main purpose of setting the design rule to 0.35 μm or more is to further improve the resistance to a high temperature process at the time of transducer formation. By setting a large design rule, the thickness of the gate oxide film 6 can be increased to 7 nm or more as a first effect, so that it is easy to cope with a decrease in effective film thickness due to impurity diffusion. Further, as a second effect, the film thickness of the barrier layer 14 can be increased to 50 μm or more as will be described later while securing a sufficient wiring width.

  In a normal LSI, setting a large design rule directly leads to an increase in chip area, but such a problem is unlikely to occur in a microelectromechanical system. This is because the dominant factor that determines the substrate size in the micro electro mechanical system is not the circuit scale of the wiring region 2 but the area required for the transducer region 3 in many cases. For this reason, in a microelectromechanical system, it is effective in terms of both manufacturing cost and heat resistance to adopt a design rule that is relatively coarser than the design rule used in the latest LSI.

In the manufacturing process of the circuit in the present embodiment, n / p wells 4, element isolation oxide films 5, gate oxide films 6, and gate electrodes 7 are formed in this order on the substrate 1 using a known LSI manufacturing technique. Proceed by doing. The gate electrode 7 is composed of polysilicon 7a and metal silicide (TiSi ₂ or the like) 7b formed on the upper layer for reducing resistance. After the gate electrode 7 is formed, the source / drain 8 and the interlayer insulating film 9 are formed.

  The interlayer insulating film 9 is preferably formed from a material having high heat resistance. In this embodiment, the interlayer insulating film 9 is formed from a silicon oxide film deposited by LPCVD (Low Pressure CVD). After the surface of the interlayer insulating film 9 is smoothed by CMP, a via is formed.

Next, after forming a seed layer 10 such as TiSi ₂ , a buried metal 11 such as tungsten is formed thereon. After sequentially depositing a silicon nitride film stopper 12 and a silicon oxide line-to-line insulating film 13, a recess for wiring is formed by RIE (Reactive Ion Etching). This recess is filled with the barrier layer 14 and the conductor 15.

  The barrier layer 14 is made of a refractory metal (Ti, W, Ta, Re, etc.) or a nitride thereof (TiN, WN, TaN, etc.), silicide (TiSi, TaSi, WSi, etc.), or a ternary amorphous material. A material having an appropriate composition ratio is selected from (TiSiN, WSiN, TaSiN, etc.). Here, the material of the barrier layer 14 is TiN. Since the barrier layer 14 is formed as a thick film having a film thickness of 50 nm or more, the portion other than the vicinity of the interface with the inter-line insulating film 13 has a larger grain size and a uniform crystal orientation, thereby preventing diffusion. The effect is greatly increased. Therefore, it does not require process management with particularly strict wiring quality, and has a heat resistance of 850 ° C. for 3 hours or more. The barrier layer 14 may be subjected to stuffing for performing heat treatment at about 600 ° C. in an oxygen atmosphere. Alternatively, the barrier layer 14 may be a laminated film of a composite type such as Ti / TiN / Ti.

  The conductor 15 is a metal of copper, gold, or silver, or an alloy using these metals as a base material. Copper, gold, and silver all have a melting point of 960 ° C. or higher, which is significantly higher than the melting point of aluminum, 660 ° C. In addition, the specific resistance values of copper, gold, and silver are all 2.35 μΩcm or less, and are smaller than the specific resistance value of tungsten of 5.65 μΩcm.

  In the present embodiment, alloying is performed to suppress the movement of the grain boundary and suppress the generation of voids. This is realized, for example, by adding 0.60 to 0.65 wt% Ti to copper. By adding such an impurity, the crystal direction of copper is strongly oriented to the (111) plane, thereby minimizing the surface energy, and the grain boundaries can be pinned by the precipitated Ti microcrystals. In order to keep the resistance low, it is preferable to set the Ti addition amount within a range of 0.1 to 1 wt%. In addition to Ti, Ta, W, Mo, and / or Si may be selected as the element to be added.

  Of the conductor 15 formed on the inter-line insulating film 13, an unnecessary portion located outside the recess is removed by CMP, and then the upper barrier layer 16 is formed. The material of the barrier layer 16 may be the material of the barrier layer 14.

  FIG. 1B is an enlarged cross-sectional view of the substrate at the stage where the step of forming the second conductor layer (2nd Wire) is performed. The conductor formed here functions as a second wiring layer in the wiring region 2 and functions as the fixed electrodes 25 and 26 of the transducer in the transducer region 3. The step of forming the conductor is performed using a dual damascene process. Among the dual damascene processes, the trench first method is used in this step. Details of this process will be described below.

  First, a stopper 17, an interlayer insulating film 18, a stopper 19, and an inter-wiring insulating film 20 are sequentially deposited on the interline insulating film 13. The material of the stoppers 17 and 19 in this embodiment is silicon nitride, and the material of the interlayer insulating film 18 and the line insulating film 20 is silicon oxide.

  Next, after applying a photoresist on the inter-line insulating film 20, a pattern defining a wiring pattern is applied to the photoresist by an exposure / development process. Specifically, a photoresist having openings defining the second wiring layer and the fixed electrodes 25 and 26 is formed. By etching the inter-line insulating film 20 using the photoresist patterned in this way, a recess corresponding to the opening is formed, and the inter-wiring insulating film 20 is defined. The bottom surface of the recess is defined by the stopper 19. That is, the stopper 19 functions as an etching stop layer when the inter-wiring insulating film 20 is etched.

  After removing this photoresist, the next photoresist is applied. By this exposure / development process, a pattern defining vias is applied to the photoresist. That is, an opening having a position and a size corresponding to the via pattern is formed in the photoresist, and a part of the lower stopper 19 is exposed at the bottom of the opening. After the stopper 19 is removed through the opening in the region where the via is to be formed, the interlayer insulating film 18 and the stopper 17 in that region are sequentially removed. Thus, an opening (via hole) reaching the first layer wiring is formed.

  Next, the opening (via hole) and the recess are sequentially filled with the barrier layer 21 and the conductor 22. Specifically, after sequentially depositing a film to be the barrier layer 21 and the conductor 22 so as to cover the inter-wiring insulating film 20, regions other than the openings (via holes) and the recesses in the barrier layer 21 and the conductor 22. Remove unnecessary parts located at. Thus, a second layer wiring pattern electrically connected to the lower layer wiring via the via is formed.

  Thereafter, the upper barrier layer 23 is formed. The details of the barrier layers 22 and 24 and the conductor 23 are the same as those of the barrier layers 14 and 16 and the conductor 15, respectively, and have high heat resistance.

  In the transducer region 3, a base 24 for supporting the movable electrode and fixed electrodes 25 and 26 for driving the movable electrode are formed simultaneously with the formation of the wiring. The upper surfaces of the fixed electrodes 25 and 26 are smoothed by the CMP process already described. For this reason, the electric field concentration on the convex shape of the surface does not occur, and as will be described later, the discharge breakdown between the movable electrode hardly occurs and the electrostatic withstand voltage can be increased.

  In addition, when performing a lithography process for forming vias after forming a wiring pattern, there is a problem inherent to the trench first method that the exposure margin is narrow, but this problem is solved because the design rule is as coarse as 0.35 μm or more. ing. As a result, it is possible to take advantage of the same method that etching is easy to perform.

  Reference is now made to FIG. FIG. 1C is an enlarged cross-sectional view of the substrate at the stage where the step of forming a third polysilicon conductor layer is performed. This conductor layer functions as a third-layer wiring pattern in the wiring portion region 2, and functions as a movable electrode of the transducer in the transducer region 3. This step of forming the conductor is also performed using a dual damascene process.

  In the step of forming the conductor, a Middle First method is used in which the intermediate stopper 29 is first patterned. This is because an opening 29a serving as an etchant inlet at the time of sacrificial layer etching is formed simultaneously. However, unlike the normal Middle First method, the inter-line insulating film 30 is left on the opening 29a without being removed. Details of this step will be described.

  First, the stopper 27, the interlayer insulating film 28, and the stopper 29 are stacked on the structure shown in FIG. In this embodiment, the material of the stoppers 27 and 29 is silicon nitride, and the material of the interlayer insulating film 28 is silicon oxide. A part of the interlayer insulating film 28 functions as a sacrificial layer in the transducer region 3 and is removed by etching in a later process.

  Next, a photoresist is applied on the stopper 29, and a via pattern is formed by an exposure / development process. Specifically, an opening that defines a via is formed in the photoresist. The stopper 29 is patterned through this opening. At this time, the opening 29a is also formed simultaneously with the via pattern.

  After the stopper 29 is patterned, a film to be the inter-wiring insulating film 30 is deposited. Next, a photoresist is applied on the film, and a wiring pattern is applied to the photoresist by an exposure / development process. By using this photoresist as an etching mask, the film that forms the inter-wiring insulating film 30 and the interlayer insulating film 28 are continuously etched to form a recess that defines the wiring pattern. At this time, a portion of the film that becomes the inter-line insulating film 30 that is not covered with the photoresist is etched, and the portion forms the concave portion. Further, since the interlayer insulating film 28 is also etched at a portion where the opening for the via is opened in the stopper 29, a via recess is formed. A part of the inter-wiring insulating film 30 also functions as a sacrificial layer in the transducer region 3 and is removed by etching in a later process.

  In the normal Middle First method, all of the via openings of the stopper 29 are provided under the region not covered with the photoresist. That is, the interlayer insulating film 28 under the via opening is completely removed to form a recess, which is used for embedding the conductor 31 in the next step.

  On the other hand, the opening 29a in the present embodiment is provided under the region covered with the photoresist. Therefore, in this portion, neither the film to be the inter-line insulating film 30 nor the interlayer insulating film 28 is etched, and only the opening 29a is formed in the remaining state. Therefore, in the final sacrificial layer etching step, the opening 29a can function as an etchant inlet.

Next, after removing the stopper 27, the recesses located between the inter-line insulating films 30 and the recesses formed in the interlayer insulating film 28 are filled with the conductor 31. Here, the conductor 31 is n-doped polysilicon. The polysilicon film is deposited by the LPCVD method, and the doping is performed by in-situ doping in which an impurity gas such as phosphine (PH ₃ ) is simultaneously mixed into the silane (SiH ₄ ) gas. The film forming temperature is 580 ° C., the annealing temperature is 600 ° C., and the annealing time is 3 hours.

  Next, the polysilicon film is smoothed by a CMP process, and the conductor 31 embedded in the recess is produced. As a result, a third-layer wiring conductor 31 is formed in the wiring portion region 2. The third conductor layer functions as the uppermost wiring layer, and external connection terminals 32 are formed at the same time.

  In the transducer region 3, a movable electrode 33, which is a transducer structure, is formed from a part of the polysilicon film. The movable electrode 33 is connected to the base 24 and fixed, is supported rotatably around the hinge portion 33a, and can be tilted left and right by an electrostatic force acting between the fixed electrodes 25 and 26. It is a tilt mirror. Since polysilicon is used, the hinge part 33a is excellent in mechanical characteristics such as creep characteristics.

  Further, as will be described later, a reflective film is formed on the upper surface 33b of the movable electrode 33 and used as an optical reflective surface. Since the upper surface 33b is smoothed by the CMP process at the time of wiring formation, the flatness and the surface roughness show preferable values. That is, the effect of forming a pattern by removing unnecessary conductors and the effect of improving the reflection efficiency of the optical reflecting surface are simultaneously achieved by one CMP process. Further, since polysilicon is highly compatible with the CMP process, it is effective in increasing the flatness accuracy of the upper surface 33b.

  In the present embodiment, simultaneously with the formation of the conductor 31 and the movable electrode 33, a shielding wall 34 is formed between the wiring portion region 2 and the transducer region 3. That is, the shielding wall 34 is formed from polysilicon filling the grooves formed in the interlayer insulating film 28 and the inter-wiring insulating film 30. The shielding wall 34 of the present embodiment is formed on a closed ring when viewed from a planar shape so as to separate the wiring part region 2 and the transducer region 3. Thereby, the shielding wall 34 prevents the etchant from flowing into the wiring part region 2 when performing the sacrificial layer etching of the transducer region 3, and protects the interlayer insulating film 28 and the inter-line insulating film 30 in the wiring part region 2. To do. In other words, the shielding wall 34 is etched in the interlayer insulating film 28 and the inter-line insulating film 30 after forming a gap in the transducer region 3 by etching a part of the inter-layer insulating film 28 and the inter-line insulating film 30. The boundary between the part that has not been etched and the part that has been etched (gap) is defined. The details will be described again in the sacrificial layer etching step.

  Here, regarding the distance accuracy of the gap between the movable electrode 33 and the fixed electrodes 25 and 26, the effect of using the dual damascene method will be described. The gap distance greatly affects the characteristics of the transducer, and manufacturing accuracy control is important. On the other hand, in general, it is difficult to determine the end point in the CMP process, and it is difficult to manage the film thickness accuracy.

  On the other hand, in this embodiment, the upper surfaces of the fixed electrodes 25 and 26 and the upper surface 33b of the movable electrode 33, which require a smooth surface but do not require height accuracy as an absolute position, correspond to the CMP processing surface of the dual damascene method. In addition, the lower surface of the movable electrode 33 that particularly requires gap distance accuracy is made to correspond to the non-CMP processing surface of the dual damascene method. In other words, the distance accuracy of the gap between the upper surfaces of the fixed electrodes 25 and 26 and the lower surface of the movable electrode 33 can be accurately controlled only by the deposited film thickness of the interlayer insulating film 28 and the stopper 27, and the variation of the transducer characteristics can be suppressed to a small level. The overall characteristics can be maximized.

  Hereinafter, the latter half of the manufacturing process will be described with reference to FIGS. 2 (a) and 2 (b).

  FIG. 2A is an enlarged sectional view of the substrate after two conductive / insulating protective films are formed. The conductive protective film 35 is a film having conductivity and corrosion resistance against the subsequent etching process, and a metal film containing gold or silver is preferable as the material. Here, the conductive protective film 35 is a gold (Au) film having a purity of 4N or more. In order to obtain adhesion to the polysilicon conductor 31, a thin chromium (Cr) layer is formed at the interface. The thickness of the conductive protective film 35 is preferably 200 to 500 nm, and pattern formation is performed by a lift-off method. The photoresist pattern is the same as that for forming the wiring pattern of the third layer, and the same mask is provided so as to reduce the manufacturing cost.

  The conductive protective film 35 has four different effects as described below.

  1) The conductive protective film 35a formed on the wiring conductor 31 has the effect of reducing the wiring resistance. Even if the polysilicon conductor 31 is deeply doped, the specific resistance is as large as 300 μΩcm or more, which is disadvantageous for long-distance wiring applications. However, the low-resistance conductive protective film 35 a has a small specific resistance of 2.4 μΩcm. By integrating, the resistance value can be greatly reduced, and the wiring performance can be improved.

  2) The conductive protective film formed on the terminal 32 for external connection serves as the contact pad 35b and has the effect of ensuring rust resistance and connection reliability with the bonding wire. Further, the contact pad 35b can function as an etching stopper when performing the opening etching of the insulating protective film 36, and can function as a protective film against this etchant when performing the sacrificial layer etching.

  3) The conductive protective film formed on the movable electrode 33 functions as a light reflecting film 35c having corrosion resistance. In particular, the Au or Ag film has an effect of reflecting the visible light in a wide wavelength range with high efficiency and increasing the mirror efficiency.

  4) The conductive protective film 35d formed on the shielding wall 34 has resistance against the etchant of sacrificial layer etching, and has an effect of protecting the wiring portion region 2 in cooperation with the shielding wall 34.

  Thus, by making the one conductive protective film 35 have four effects different from each other in each place, it is possible to achieve both improvement in performance and reliability and improvement in productivity.

  The insulating protective film 36 is a film having insulation and corrosion resistance (etching resistance) against the sacrificial layer etching process. Here, the material of the insulating protective film 36 is silicon nitride.

  The insulating protective film 36 covers the entire surface of the wiring part region 2 except the contact window 36a, and protects the wiring part region 2 from being damaged during the sacrifice layer etching. In addition, the transducer region 3 is basically opened to allow sacrificial layer etching. At the boundary between the wiring portion region 2 and the transducer region 3, the shielding wall 34 and the conductive protection film 35d are in close contact with each other without any gap, and the etchant is completely separated during the sacrifice layer etching.

  FIG. 2B shows a cross section of the wafer when the sacrificial layer etching process is completed.

As for the sacrificial layer etching, isotropic etching is performed using an etchant that selectively removes the interlayer insulating layer 28 and the inter-line insulating layer 30. In this embodiment, since the material of the interlayer insulating film 28 and the line insulating film 30 is silicon oxide, an etchant such as CF ₄ + H ₂ is used for dry etching and HF is used for wet etching.

  The contact pad 35b, the insulating protective film 36, the conductive protective film 35d, the shielding wall 34, and the stopper 27 form a continuous and seamless etching-resistant film with respect to the above etchant. The That is, by the function of the shielding wall 34 (barrier effect against the etchant), only the interlayer insulating film 28 and the inter-line insulating film 30 that are in the transducer region 3 are removed.

  The etchant enters from the top of the figure, and first the inter-line insulating film 30 is removed. As already described, since the opening 29 a is provided in advance in the stopper 29, the etchant can reach the interlayer insulating film 28. The etching is completed when the interlayer insulating film 28 is completely removed.

  After the sacrificial layer etching is completed, rinsing, drying, and inspection are performed, followed by dicing to bond each chip to a package (not shown). Thereafter, wire bonding for connecting the contact pad 35b and the package is performed, and a transparent lid is attached and sealed to complete.

  Thus, in the present embodiment, the transducer side of the interlayer insulating film 28 and the inter-line insulator 30 functions as a sacrificial layer for forming a gap around the structure. In this embodiment, since the interlayer insulating film in the wiring region and the sacrificial layer in the transducer region are formed by the same process, the manufacturing process can be simplified.

  The effect of the shielding wall 34 can also be obtained when the structure of the wiring portion region and the transducer region is formed using a metal such as aluminum. In this case, since the shielding wall 34 is formed from a metal such as aluminum, it is preferable to etch the sacrificial layer using an etchant that does not etch the metal such as aluminum to form a void in the transducer region.

  In the above embodiment, the shielding wall 34 is formed in the step of forming the conductor indicated by “3rdWire”. However, the shielding wall 34 may be formed in a step different from the pattern of these conductors. .

  FIG. 3A is an enlarged cross-sectional view of the micro electro mechanical system in the present embodiment, and FIG. 3B is a top view thereof. In the figure, the microelectromechanical system is completed and operating.

  An input signal from the outside is given to the control circuit via the bonding wire 37. A control circuit formed on the substrate 1 in the wiring portion region 2 performs arithmetic processing and generates a drive signal for each transducer. The transducers to be driven are sequentially scanned and switched. At this time, the gate electrode 38 corresponding to the fixed electrode 26 functions as a word line, and the source-side electrode 39 functions as a bit line. A predetermined charge is injected into the selected fixed electrode 26 and the movable electrode 33 is interposed between them. An electrostatic force is generated, and the movable electrode 33 is tilted.

  The stopper 27 serves as a short-circuit prevention film between the movable electrode 33 and the fixed electrode 26. In other words, even when the movable electrode 33 is largely inclined due to malfunction or external force, the movable electrode 33 does not directly touch the fixed electrode 26 because of the stopper 27, and the occurrence of a failure due to a short circuit can be prevented.

  Thus, the stopper 27 acts as a stopper during via formation in the third conductor layer forming step, and acts as an etchant isolation protective film in the sacrificial layer etching step. It acts as a short-circuit prevention film between the movable electrode 33 and the fixed electrode 26. Since one stopper 27 exhibits different effects in three different processes as described above, the manufacturing process can be simplified and the reliability can be improved at the same time.

  FIG. 4 is a plan view showing the micro electro mechanical system in the present embodiment. FIG. 4 shows a state where the silicon wafer is separated into individual chips, and packaging has not yet been performed. Separation into chips is performed by dicing a silicon wafer.

  The substrate 1 shown in FIG. 4 has a rectangular shape of 5 mm × 5 mm, and a transducer region 3 having a diameter of about 4.5 mm is provided at the center of the substrate 1. A large number of movable electrodes 33 are formed in the transducer region 3 to constitute a micromirror array.

  A wiring portion region 2 is provided outside the transducer region 3. A large number of contact pads 35 b are formed in the wiring portion region 2. A closed annular shielding wall 34 is provided at the boundary between the wiring portion region 2 and the transducer region 3 so as to surround the transducer region 3 and separates the wiring portion region 2 and the transducer region 3.

  In this embodiment, since the sacrificial layer is etched before dicing the wafer, the shielding wall 34 is provided only at the boundary between the wiring region 2 and the transducer region 3. However, another similar shielding wall 34 may be provided in a closed ring around the periphery of the chip. By doing so, it becomes possible to perform sacrificial layer etching after dicing. This is because by providing a closed annular shielding wall at the periphery of the chip, it is possible to effectively prevent the etchant from entering from the periphery of the chip.

  The shielding wall 34 may be formed so as to surround the wiring portion region 2. In the step after the sacrificial layer etching is completed, a part of the shielding wall 34 may be removed or cut.

  As described above, according to the present embodiment, the wiring portion is formed of a conductor mainly composed of copper, gold, or silver, and is formed of polysilicon, silicon nitride, lead zirconate titanate, or silicon carbide. Since the transducer is formed by either of them, it is possible to provide a solution to the temperature condition that achieves both prevention of destruction of the wiring portion and ensuring of the characteristics of the transducer, and it is possible to reduce the wiring resistance.

  Furthermore, in this embodiment, the following effects can be obtained.

  Since any element of Ti, Ta, W, Mo, and Si is contained in an amount of 0.1 to 1.0 wt%, an increase in wiring resistance can be suppressed while suppressing grain growth of the conductor.

  Since the outer peripheral surface of the conductor is covered with a barrier layer having a thickness of 50 nm or more, high heat resistance reliability can be ensured without requiring strict manufacturing management.

  Since a shielding wall that separates the wiring portion region and the transducer region on the substrate is formed and the sacrificial layer is etched, a transducer structure having a complicated shape can be formed. Furthermore, the manufacturing reliability of the wiring part region can be improved.

  Since at least a part of the shielding wall is formed at the same time as the conductor and the structure, an increase in manufacturing cost can be suppressed without requiring a special mask or manufacturing process for forming the shielding wall.

  Since the surface of the structure smoothed by the damascene method is used as an optical reflection surface, it has the effect of removing unnecessary conductors to form a pattern and improving the reflection efficiency of the optical reflection surface. It can be performed simultaneously in one damascene process.

  Since the surface of the fixed electrode smoothed by the damascene method is opposed to the movable electrode, the effect of patterning by removing unnecessary conductors and the concentration of the electric field by smoothing the opposing electrode surface The effect of preventing and suppressing discharge breakdown can be achieved simultaneously by one smoothing process.

  Since the structure is formed by the dual damascene method and the surface of the structure facing the electrode is a non-smoothed surface, the distance accuracy of the gap between the electrode and the structure can be managed with high accuracy, and the variation in transducer characteristics can be reduced. Can be suppressed.

  Since the conductive protective film is formed integrally with the structure or the conductor, the resistance of the wiring portion can be reduced and the protection can be performed at the same time.

  Since a film containing gold or silver is formed as the material of the conductive protective film, in addition to the above-described reduction in resistance and protection, the light reflectance of the transducer can be further improved.

  The inter-layer insulating film and the inter-line insulating film are laminated in this order via a stopper provided with an opening in at least a part thereof, and an inlet for the sacrificial layer etchant of the transducer is formed in this opening. Therefore, an increase in manufacturing cost can be suppressed without requiring a special mask or manufacturing process to form the inlet of the etchant.

  Although the micro electro mechanical system of the present embodiment includes a tilt mirror as a transducer, the present invention is not limited to this. The configuration of the transducer is arbitrary.

  In the present embodiment, the transducer structure is formed of polysilicon, but other materials that require processing in the range of 600 to 850 ° C., such as silicon nitride, silicon oxide, lead zirconate titanate, Alternatively, it may be formed from silicon carbide.

  The microelectromechanical system and the manufacturing method thereof according to the present invention are suitably used for a microactuator or a microsensor having a wiring layer and a transducer. In particular, the present invention is suitably applied to a microelectromechanical system that requires a high-temperature process of 600 ° C. or higher after the formation of the wiring layer.

(A) to (c) are process cross-sectional views showing an embodiment of a method of manufacturing a micro electro mechanical system according to the present invention. (A) And (b) is process sectional drawing which shows embodiment of the manufacturing method of the micro electro mechanical system by this invention. (A) is an expanded sectional view of the micro electro mechanical system by this invention, (b) is the top view. It is a top view of the micro electro mechanical system in the embodiment of the present invention.

Explanation of symbols

1 Substrate 2 Wiring area (Control circuit area)
3 Transducer region 14, 16, 21, 23 Barrier layer 15, 22, 31 Conductor 17, 19, 27, 29 Stopper 18, 28 Interlayer insulating film 20, 30 Inter-wiring insulator 25, 26 Fixed electrode 29a Opening 33 Movable Electrode 34 Shielding wall 35 Conductive protective film

Claims (20)

A microelectromechanical system comprising a substrate and a wiring region and a transducer region supported by the substrate,
The wiring area is
A plurality of conductors and an insulator provided between the plurality of conductors;
The transducer area is
Having at least one transducer;
The transducer is
A structure,
A gap provided around the structure, and
A microelectromechanical system further comprising a shielding wall formed at a boundary portion between the wiring portion region and the transducer region and separating the insulator and the gap. 2. The microscopic structure according to claim 1 , wherein the insulator in the wiring region is formed from an unetched portion of the insulating film in which the gap is formed by etching a part that functions as a sacrificial layer. Electromechanical system. The micro electro mechanical system according to claim 2 , wherein the shielding wall is made of a material that functions as a barrier against an etchant for etching the insulating film. The micro electro mechanical system according to claim 1 , wherein the shielding wall hermetically separates the wiring portion region from the transducer region. At least in part, the micro electro mechanical system as claimed in claim 1, which is formed of the same material as the conductor and / or the structure of the shielding wall. Wherein at least a portion of the conductor, the micro electro mechanical system as claimed in claim 1, which is formed of the same material as said structure. The micro electro mechanical system according to claim 1 , wherein the conductor and the structure are collectively formed by a damascene method. The microelectromechanical system according to claim 7 , wherein a surface of the structure is smoothed, and the surface functions as an optical reflecting surface. The transducer further comprises an electrode for driving the structure,
Surface of the electrode, the is smoothed by a damascene method, micro-electromechanical system according to claim 1 which is opposite to the structure through the gap. The structure is formed by a dual damascene method,
The microelectromechanical system according to claim 9 , wherein a surface of the structure facing the electrode functions as a non-smoothing surface. Microelectromechanical system according to claim 1 having the structure and / or the conductor integrally formed on the conductive protective layer. The micro electro mechanical system according to claim 11 , wherein the conductive protective film includes gold and / or silver. A wiring region for forming a conductor and an insulator provided between the conductors on a substrate, a transducer region for forming a structure and a sacrificial layer provided around the structure, and the wiring region Forming a shielding wall separating the transducer region and the transducer region;
A method of manufacturing a microelectromechanical system including a step of removing the sacrificial layer by isotropic etching to form a void,
Forming a stopper layer having resistance to the etching on the substrate;
A second step of forming the insulator and the sacrificial layer on the stopper layer;
A third step of forming a shielding wall having resistance to the etching at the boundary between the insulator and the sacrificial layer so as to be continuous with the stopper layer;
A fourth step of forming a protective film for protecting the insulator so as to be continuous with the shielding wall;
And a fifth step of removing the sacrificial layer by isotropic etching. The method of manufacturing a micro electro mechanical system according to claim 13 , wherein a part of the conductor and / or a part of the structure is formed simultaneously with the shielding wall. The method of manufacturing a micro electro mechanical system according to claim 13 , wherein the structure is formed by a damascene method. The method of manufacturing a micro electro mechanical system according to claim 15 , wherein the surface of the structure serving as an optical reflecting surface is smoothed. The method of manufacturing a micro electro mechanical system according to claim 15 , wherein at least one of the structure facing each other through a gap and an opposing surface of an electrode that drives the structure are smoothed. 18. The method of manufacturing a micro electro mechanical system according to claim 17 , wherein the structure is formed by a dual damascene method so that a surface of the structure facing the electrode is a non-smoothing surface. The first insulating layer and the second insulating layer is formed, the first and claim 14 to function the second insulating layer as the sacrificial layer which are laminated through a stopper having an opening portion in at least a part A manufacturing method of the micro electro mechanical system described in 1. The method of manufacturing a micro electro mechanical system according to claim 19 , wherein the opening is used as an inlet of an etchant for etching the sacrificial layer.