JP4762547B2 - Manufacturing method of multilayer structure - Google Patents

Description

  The present invention relates to a method for manufacturing a multilayer structure made of a semiconductor material. This structure includes a substrate made of a first semiconductor and a thin surface layer made of a second semiconductor, the two materials having substantially different lattice constants.

  This type of method is already known.

  Accordingly, it is well known to produce structures that include a substrate made of a material such as silicon and a thin surface layer made of a material such as silicon-germanium (SiGe) or germanium (Ge).

  French patent application 0208600, in the name of the applicant, produces a structure comprising a thin layer of semiconductor material from a wafer comprising a lattice constant matching layer comprising an upper layer made of a semiconductor material having a first lattice constant. Related to the method. This method has (a) a second nominal lattice constant that is substantially different from the first lattice constant, and a minimum thickness sufficient to maintain the first lattice constant of the upper layer of the underlying conforming layer. Therefore, a growth stage on top of the conforming layer of the distorted semiconductor material coating; and (b) a growth stage on this coating of a relaxation layer of semiconductor material having a nominal lattice constant substantially the same as the first lattice constant; (C) removing at least a portion of the wafer on the side of the conforming layer relative to the relaxation layer, forming an embrittlement zone on the side of the conforming layer relative to the relaxation layer, and separating the structure including the relaxation layer from the wafer And a stage including a power supply operation in the embrittlement zone.

  Therefore, in the method of this patent application, a desired wafer is constructed using a layer transfer technique (specifically, a Smart Cut (registered trademark) type or an Eltran (registered trademark) type).

  The starting element of this method is a wafer with a lattice constant matching layer corresponding to the region of its surface where there is a layer of material that is substantially relaxed without numerous structural defects such as dislocations.

  A relaxation layer is understood to mean any layer of a semiconductor material having an unstrained crystal structure, i.e. a layer having a lattice constant approximately equal to the nominal lattice constant of the material forming the layer. deep.

  Conversely, a strained layer means that its crystal structure undergoes tensile or compressive strain during crystal growth, such as epitaxy, so that at least the lattice constant is substantially different from the nominal lattice constant of this material. Refers to any layer of semiconductor material.

  This method of French patent application No. 0208600 constitutes an advantageous solution for building a structure as described at the beginning of this description.

  The purpose of the present invention is to provide a complementary role to the teachings of this patent application.

  In order to achieve this object, the present invention proposes a method of manufacturing a multilayer structure made of a semiconductor material. This structure comprises a substrate made of a first semiconductor material and a skin layer made of a second semiconductor material, the two semiconductor materials having substantially different lattice constants. The method includes the steps of: creating a layer comprising a thin surface layer on a support substrate; creating an embrittlement zone in an assembly formed by the support substrate and a deposited layer; and Bonding, separating at the level of the embrittlement zone, and treating the surface of the resulting structure.

  Other aspects, objects, and advantages of the present invention will become apparent from the following description of the invention, with reference to the accompanying drawings, which illustrate the main steps for carrying out embodiments of the present invention in FIGS. It will be clear.

  Referring first to FIG. 1a, this figure shows a support substrate 100 on which a layer 105 (shown as shaded) is deposited.

  The support substrate 100 is made of a semiconductor material having a first lattice constant. For example, it is made of silicon.

  The layer 105 is a layer made of a material having a second lattice constant different from the first lattice constant described above.

  Therefore, the layer 105 can be made of SiGe and further made of Ge.

  This layer 105 is deposited at a desired thickness of a material whose lattice constant is substantially different from the lattice constant of the support substrate to be deposited, while such a deposition is substantially free of transitional defects. It is said to be deposited by a technique that allows the construction of a surface layer.

  For example, International Patent Application No. 00/15885 teaches a method of depositing SiGe or Ge on silicon.

  Thus, such a deposition method can include, for example, a temperature stabilization step of the single crystal silicon substrate at a first set stabilization temperature of 400 ° C. to 500 ° C., preferably 430 ° C. to 460 ° C., and a final desired on the support substrate. From the first set temperature of the vapor phase chemical growth (CVD) step at the first set temperature until the Ge base layer having a set thickness of less than the thickness is obtained, Step of heating to 850 ° C., preferably 800 ° C. to 850 ° C., to a second set temperature, and vapor phase chemical growth of Ge at the second set temperature until the final desired thickness of the single crystal Ge layer is obtained In accordance with a first mode of depositing single crystal Ge on a single crystal silicon support substrate.

  Such a deposition method can also be carried out according to a variant as disclosed, for example, by international patent application 00/15885.

  Other methods for obtaining relaxed SiGe or a thin layer of relaxed Ge directly on a support substrate that can be made of silicon are also possible.

  B. Hollander et al., “Pseudo-lattice-matched Si1-xGex / Si (100 after hydrogen or helium ion implantation for virtual substrate fabrication, incorporated as part of this disclosure.” See also: "Restriction of heterostructures," Nuclear Instruments and Methods in Physics Research, Nuclear Facilities and Methods in Physics Research, B175-177, 2001, pages 357-367.

  In such a method, the strained layer is created and the layer 110 is relaxed to produce the layer 110.

  Development of a new type of SiGe thin strain relaxed buffer based on incorporation of a thin layer of relaxed SiGe, based on the incorporation of a carbon-containing layer (development of a new type of SiGe thin strained buffer on the inc.) SiGe Technology and Device Meeting (ISTDM), 2003, Nagoya, Japan, pp. 15-17, “Thin SiGe Buffers High Ge for Thin-Ge Geometry for n-MOSFETs” content for n-Mossets) Lytovic et al., Material Science & Engineering, Materials Chemistry and Engineering, B89, 2002, pages 341-345, and “Relaxed SiGe Buffer of Less than 0.1 μm” (Bauer et al., (Thin Solid Films, 369, 2000, pages 152-156). These disclose methods for obtaining layers that can be implemented in the present invention and are incorporated as part of the present disclosure.

  Returning to the method of the invention, in all cases, a layer 110 with a skin layer to be produced of the structure is produced on the support substrate 100.

  That is, the intermediate wafer 10 having the SiGe or Ge layer 110 (with a desired Si / Ge ratio) on the support substrate 100 has been produced.

  The free surface of this layer 100 can be polished to allow bonding of this intermediate wafer 10 to continue in the process.

  The surface roughness of the intermediate wafer 10 must be an effective value of several angstroms in the case of such bonding.

  Accordingly, an interface 105 is defined between the layer 110 and the support 100.

  It is noted that by using this type of deposition method, dislocation type defects are confined in the region of layer 110 adjacent to interface 105.

  The confinement is considered to mean that most of the dislocation type defects exist in the region. Although not completely free of defects in the rest of layer 110, its concentration is suitable for microelectronic applications.

  Thus, this region where the dislocation type defects in layer 110 are confined forms a lattice constant matching layer between the support substrate 100 made of silicon and the surface region of layer 110, which in itself is Ge. Alternatively, a layer of the wafer 10 made of relaxed SiGe is formed.

  This Ge or relaxed SiGe layer has the desired thickness as a result of the deposition made early in the process. This desired thickness can specifically be on the order of 0.5 to 1 micron.

  Next, referring to FIG. 1 b, an embrittlement zone 120 is created in the thickness of the wafer 10.

  This embrittlement zone can be made specifically by injecting a chemical through layer 110.

  The injected chemical is one or several atoms, or one or several molecules, such as hydrogen or helium ions, or hydrogen or helium molecules.

  This injection may be a co-injection of different chemicals, such as hydrogen and helium. It is noted herein that “injection” includes such simultaneous injection of at least two chemicals as well.

  When this embrittlement zone is created by implantation, the implantation parameters can be determined so that the embrittlement zone is located in the support substrate 100 as shown in FIG. 1b.

  These implantation parameters can also be determined so that the embrittlement zone is located in the layer 110 itself (preferably in the region of the layer adjacent to the interface 105).

  It is noted that this embrittlement zone can also be made by forming a porous region in the support substrate 100 before depositing the layer 110.

  Next, the wafer moves to a wafer having an embrittlement zone, and this wafer is bonded to the target substrate 20.

  This target substrate 20 can be made of silicon.

  The surface of the wafer 10 attached to the target substrate is a surface corresponding to the relaxed surface of the layer 110.

  In order to perform this bonding, the surfaces are cleaned before contacting them and optionally inserting a bonding layer between the surfaces.

  An electrical insulating layer, such as an oxide film, can also be inserted between the wafer and the target substrate.

  Such an oxide film can be brought about by oxidation of the surface of the target substrate 20.

  It can also be brought about by oxidation of its surface when layer 110 is made of SiGe.

  If layer 110 is made of Ge or SiGe, the oxide layer can also be bonded to layer 110 by oxide deposition prior to bonding.

  Thus, these wafers and / or target substrates can be bonded to the insulating layer prior to bonding.

  If necessary, one or both surfaces of the substrates to be bonded can be treated to reduce the surface roughness of these substrates to a value suitable for bonding (ie, not exceeding an effective value of a few angstroms).

  Such surface treatment may be a polishing step.

  After bonding, classical heat treatment can be continued to strengthen the bonding interface.

  Next, we move on to separation at the level of the embrittled interface by supplying heat and / or mechanical power.

  As a result, as shown in FIG. 1d, a structure is obtained that includes the target substrate 20, the layer 110, and optionally the remainder of the support substrate 100.

  In this structure, the layer 110 itself includes a lattice constant matching layer (a portion of the layer 110 adjacent to the rest of the support substrate 100) and a relaxation layer of a desired thickness.

  In the event that this embrittlement zone is established by injection into the layer of the “lattice constant matching layer” of the layer 110, the resulting structure 30 does not contain the rest of the support substrate, and during the separation this lattice constant A portion of the conforming layer is separated from this structure 30.

  In this case, the surface of the resulting structure is treated (FIG. 1e) to improve the surface condition of layer 110.

  This surface treatment can include polishing as well as other types of treatment.

  Implantation can also be performed to obtain an embrittlement zone in the relaxed portion of layer 110.

  In such cases, the transferred layer does not contain defects (or only a few) such as dislocations, and the resulting structure after separation does not require any additional processing (results from the relaxed portion of layer 110). A surface layer can be provided.

  When creating an embrittlement zone in the layer of support substrate 100 (by implantation or by pre-forming a porous region), the next step is to selectively erode the remainder of this support substrate.

  This selective erosion may be a selective chemical etch that erodes only the material of the support substrate.

  Such etching can be performed by a wet method (selecting an appropriate etching solution) or a dry method (selectively etching by energy plasma or grinding).

  Polishing can be performed before such etching.

  The free surface of layer 110 is treated early in this selective erosion to remove the lattice constant matching layer corresponding to the portion of layer 110 where the transitional defects are confined.

  Described above are two main variants for carrying out the present invention (formation of embrittlement zones in the support substrate and in the layer 110, respectively).

  In these two cases, the final structure active layer corresponds to the relaxed portion of layer 110.

According to a third main variant, layer 110 is actually configured at different levels (ie hierarchies), this layer 110 being:
To produce a relaxed thin layer, for example, the technique as disclosed by International Patent Application No. 00/15885, or the references mentioned above by B. Hollander et al., Or any other Formed by a first level deposition according to known techniques, a second level deposition constituting a stop layer for chemical corrosion, and a third level deposition corresponding to a relaxation layer to build the active layer of the final structure. . Such deposition is performed at a desired thickness for the active layer.

  This first level corresponds to the lattice constant matching layer. This can be made of SiGe or Ge.

  The second level must at the same time have good selectivity to the third level and have chemical corrosiveness to itself (in this respect different materials than in level 2 and level 3 must be used) Do not introduce too much difference in terms of the two levels surrounding itself and the lattice constant (in this respect, levels 1, 2 and 3 must not be too different).

For example, the following combinations can be formed.
Material level 1 Material level 2 Material level 3
Ge SiGe (50/50) SiGe or Ge
SiGe strained Si SiGe or Ge
Preferably, the level 1 and level 3 layers are made from materials of the same nature so that the level 2 layer inserted between these two layers is uniformly constrained on both sides.

In this case, it is preferable to use the following materials.
Material level 1 Material level 2 Material level 3
Ge SiGe (50/50) Ge
SiGe strained Si SiGe
In this third major variant, the same steps follow to form the embrittlement zone, bond and separate the structure 30.

  Therefore, this embrittlement zone can be located in the layer 110 again. In this case, it is preferably located in the first level layer in which the embrittlement zone is formed by implantation.

  First selective corrosion to eliminate the first level remainder to obtain the final structure (this corrosion is specifically chemical corrosion and therefore requires a level of insertion corresponding to the stop layer) ), And a second selective corrosion to eliminate the stop layer itself.

  It is also possible for the layer 110 to consist of only two levels. The first level is as described above and the second level is similar to levels 2 and 3 described above.

  In this case, the second level is made of strained silicon, for example, while the first level is made of SiGe or Ge.

  That is, the second level creates an active layer of the final structure, while the first level still constitutes the lattice constant matching layer.

In this case, the following materials can still be used (this table is given as a non-limiting example as in the previous table):
Material level 1 Material level 2
Ge SiGe (50/50)
SiGe strained Si
In all cases, conventional surface treatment methods can continue after the structure of FIG.

  The invention thus makes it possible, for example, to produce a multilayer structure comprising a layer of Ge or SiGe on a silicon substrate.

  For the present invention, the conforming layer of layer 110 is a concentration gradient in the layer (eg, germanium if the conforming layer is between a Si support substrate and a relaxation layer in a given Ge concentration of Ge or SiGe). It should be noted that there is no concentration gradient.

  Conventional matching layers often have such a concentration gradient, which corresponds to the lattice constant gradient in the matching layer.

  However, such a conforming layer having a concentration gradient is necessarily relatively thick (the thicker the conforming layer, the more important the difference in lattice constants on both sides of the conforming layer).

  International Patent Application No. 02/15244 discloses an example of such a conventional conformable layer with a concentration gradient.

  In contrast, in the case of the present invention, the conforming layer can be very thin.

  In fact, recall that defects (eg, dislocations) are confined to the region of layer 110 adjacent to interface 105 with support substrate 100.

  This particular aspect of the present invention is advantageous (eg, compared to known techniques such as disclosed in International Patent Application No. 02/15244).

  An example of an advantage associated with this embodiment is that such a thin conformal layer can be injected into the support substrate 100 to form an embrittlement zone as the implanted chemical crosses the conformal layer. There is.

  Thereby, after separation and removal of the remaining material (Si etc.) of the support substrate 100, the hassle to treat the divided surface as obtained by separation in the embrittlement zone located in the conforming layer itself. It is possible to obtain a surface with a very good quality of the final structure without the need for a tedious treatment (this is the case with a graded conforming layer and is too thick to be traversed by injection).

  It should also be noted that the structure obtained by the present invention is an example of a dislocation type defect even in the buried region.

  The resulting structure can then be used to have additional layers, for example strained silicon grown by epitaxy on SiGe or Ge layers.

  If the level 2 layer is made of strained Si, it may be advantageous to have only one selective etch to keep the final structure of the two layers of strained silicon-SiGe on the silicon substrate. is there.

  In this case, the final structure preserves the stop layer.

  Finally, a strained silicon layer may be deposited on the level 3 layer prior to the step of bonding the structure onto the target substrate so that a structure comprising a layer of strained silicon on the silicon substrate is finally produced. Is possible.

It is a figure which shows the main steps for implementing embodiment of this invention. It is a figure which shows the main steps for implementing embodiment of this invention. It is a figure which shows the main steps for implementing embodiment of this invention. It is a figure which shows the main steps for implementing embodiment of this invention. It is a figure which shows the main steps for implementing embodiment of this invention.

Claims (19)

In the method of manufacturing a multilayer structure made of a semiconductor material, the multilayer structure includes a target substrate (20) made of a first semiconductor material and a relaxed surface thin layer made of a second semiconductor material, and the two semiconductor materials have different lattice constants. A method comprising:
A stage for preparing a support substrate (100) made of a first semiconductor material having a first lattice constant;
Depositing a layer (110) on the support substrate (100) to form an intermediate wafer (10) having an interface (105) between the layer (110) and the support substrate (100). The layer (110) is made of a second semiconductor material having a second lattice constant different from the first lattice constant of the support substrate (100), and the deposition is adjacent to the interface (105). steps were carried out so as to form a lattice constant adaptation layer located in the region, most of the defects of the dislocation type, to form the lattice constant adaptation layer which is confined to form the relaxed skin layer When,
Forming an embrittlement zone in the intermediate wafer (10);
Bonding a target substrate (20) to the layer (110 ) of the intermediate wafer (10);
Separating at the level of the embrittlement zone to obtain a structure (30);
Treating the free surface of the resulting structure to remove the lattice constant matching layer;
A method comprising the steps of:   The method of claim 1, wherein the step of depositing the layer (110) on the support substrate (100) is done by epitaxy. The epitaxy is
A temperature stabilization step of the support substrate (100) at a first set stabilization temperature;
Chemical growth in the gas phase at the first set stabilization temperature until a base layer with a set thickness less than the final desired thickness of the layer comprising the relaxed skin layer is obtained on the support substrate (100). Steps,
Raising the temperature of the chemical growth in the gas phase from the first set stabilization temperature to the second set temperature;
3. The method according to claim 2, characterized in that it is performed using the step of continuing chemical growth in the gas phase at the second set temperature until a final desired thickness of the layer (110) is obtained.   The method according to claim 3, wherein the first preset temperature is in the range of 400C to 500C, and the second preset temperature is in the range of 750C to 850C.   The method according to claim 4, wherein the first preset temperature is in the range of 430C to 460C, and the second preset temperature is in the range of 800C to 850C.   The method according to claim 1, characterized in that the layer (110) of the second semiconductor material is produced by forming a strained layer and relaxing the layer. 7. A method according to any one of the preceding claims, characterized in that the formation of the embrittlement zone is carried out by implantation.   The method according to claim 7, wherein the injection is a simultaneous injection of at least two chemicals. Said injection, said characterized in that it is carried out in until the bonding step from the formation stage of the embrittlement zone, The method according to claim 7 or 8.   10. A method according to claim 9, characterized in that implantation is performed to define the embrittlement zone in the thickness of the support substrate (100). Injection, prior SL is performed so as to define the embrittlement zone to the lattice constant adaptation layer, The method of claim 9, characterized in that. Injection, the characterized in that it is carried out to define the embrittlement zone before Symbol relaxed skin layer, The method of claim 9.   The method according to any one of the preceding claims, characterized in that an electrical insulating layer is inserted between the intermediate wafer (10) and the target substrate (20) before bonding.   14. Method according to claim 13, characterized in that an electrical insulating layer is formed on the surface of the intermediate wafer (10) prior to bonding.   15. A method according to any one of claims 13 to 14, characterized in that an electrical insulating layer is formed on the target substrate (20) prior to bonding.   The method according to claim 13, wherein the electrically insulating layer is an oxide layer.   17. A method according to any one of the preceding claims, characterized in that the target substrate (20) of the multilayer structure is made of silicon.   18. A method according to any one of the preceding claims, characterized in that the support substrate (100) is made of silicon.   19. A method according to any one of the preceding claims, characterized in that the layer (110) is made of SiGe or Ge.

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