JP4748007B2 - LDPC decoder operation control data generation method and LDPC decoder - Google Patents

Description

  The present invention relates to decoding of a low density parity check code (LDPC), and more particularly to a decoding procedure and decoding apparatus for an LDPC code when an arbitrary check matrix is given.

  A low density parity check code is known as an encoding method for transmitting digital information in a communication system and storing digital information in a storage system because of its excellent characteristics.

In the LDPC encoding method, encoding and decoding are performed according to the procedure described below.
1) Encoding When the information bits to be encoded are M bits, an N = (M + K) -bit code is generated by adding M check bits to K bits. An N-bit LDPC code can be generated by creating a K-row N-column generator matrix and multiplying the N bits of information or bits by the generator matrix. The generator matrix may be an arbitrary matrix.
2) Decoding Decoding can be performed by arbitrarily generating a parity check matrix (hereinafter referred to as a check matrix) of M rows and N columns and multiplying N bits by LDPC encoded information and the check matrix.

  The check matrix may be defined as an arbitrary matrix having few matrix elements “1”. Select according to the nature of the LDPC codeword in the applicable field.

  The check matrix has different characteristics depending on the nature of the matrix, and the appropriate check matrix differs depending on the number of iterations until convergence and the nature of the LDPC codeword. For this reason, it is necessary to check the characteristics by changing the check matrix.

  As a decoding method of the LDPC code, iterative calculation is performed by the set check matrix K and the sum-product method or the Min-sum method, and a decoded signal is obtained from the value after the repeated calculation. An LDPC code decoding method will be described based on the Min-sum method.

  FIG. 6 is a diagram showing decoding of an LDPC code by the Min-sum method. The Tanner graph shows the procedure for decoding the LDPC code by sequentially calculating the received word between the message node and the check node by the Min-sum method.

  The Tanner graph is a graph in which N message nodes and M check nodes are connected corresponding to the position of “1” in the parity check matrix. In the Tanner graph, columns of the check matrix correspond to message nodes, and rows correspond to check nodes.

The connection between the message node and the check node is that the j-th message node and the i-th check node are connected when the element in the i-th row and j-th column of the check matrix is “1”. As a result, the number required for one calculation of α _mn and β _mn is determined by the number of “1”, and when calculating one α _mn , all message nodes connected to the mth check node are calculated. β is required, and when calculating one β _mn , α of all check nodes connected to the nth message is required. The number of times required for one calculation depends on the number of “1”, M × column weight number (= N × row weight number). Here, the column weight is the number of 1s present in one column, and the row weight is the number of 1s present in one row.

Decoding procedures will be described.
1) β _mn is calculated by (Equation 1).

The initial value of alpha _mn is set to "0", the lambda _n is input words y _n as shown in (Equation 3). Here, “m ′” of α _m′n means that m which coincides with m of β _mn is not included in the calculation.
2) α _mn is calculated by (Expression 2).

Here β _{mn 'of} the "n'" is n that matches the n of β _mn means that you do not want to include in the calculation. The value of sign (x) is “1” when x> =, and the value “0” when x <0.
3) The received word y _n is determined by determining Q _n obtained in (Expression 4) by (Expression 5).

図７はＬＤＰＣ符号の復号手順を示す図である。図６で示したＭｉｎ−ｓｕｍ法を例にしてＬＤＰＣ符号の復号手順を示している。
Ｓ１１：Ｍ行Ｎ列の検査行列を与える。
Ｓ１２：ＬＤＰＣ符号情報ｙ_ｎ(n＝１〜Ｎ)を得る。
Ｓ１３：下記の初期設定を行なう。
ア．尤度λ_ｎは受信語のｙ_ｎ(n＝１〜Ｎ)とし保持する。
イ．α_ｍｎ＝０と設定し、(ｍ＝１〜Ｍ、n＝１〜Ｎ）とし保持する。
ウ．演算繰り返し回数をＬとし、最大演算繰り返しＬｍａｘと初期値Ｌ＝０を設定する。
Ｓ１４：（式１）によりβ_ｍｎの演算の演算を行いβ格納メモリに保持する。
Ｓ１５：（式２）によりα_ｍｎの演算の演算を行いα格納メモリ保持する。
Ｓ１６、Ｓ１７：設定した繰り返し回数まで演算を繰り返し、あるいは、繰り返し演算により演算結果が収束したと判断した場合に切り返し演算を終了する。
Ｓ１８：（式４）、（式５）によりＱ_ｎの値より受信語(ｙ_ｎ)’を推定し決定する。

FIG. 7 is a diagram showing a decoding procedure of the LDPC code. The decoding procedure of the LDPC code is shown taking the Min-sum method shown in FIG. 6 as an example.
S11: A check matrix of M rows and N columns is given.
S12: LDPC code information y _n (n = 1 to N) is obtained.
S13: The following initial settings are made.
A. The likelihood λ _n is held as y _n (n = 1 to N) of the received word.
I. α _mn = 0 is set and held as (m = 1 to M, n = 1 to N).
C. The number of calculation repetitions is set to L, and the maximum calculation repetition Lmax and an initial value L = 0 are set.
S14: The calculation of β _mn is performed according to (Expression 1) and held in the β storage memory.
S15: The calculation of α _mn is performed by (Expression 2), and the α storage memory is held.
S16, S17: The calculation is repeated up to the set number of repetitions, or when it is determined that the calculation result has converged by the repetition calculation, the switching operation is terminated.
S18: The received word (y _n ) ′ is estimated and determined from the value of Q _{n according} to (Expression 4) and (Expression 5).

  Next, the scales of α computation and β computation necessary for decoding the LDPC code depend on the number of “1” in one parity check matrix as described above.

  On the other hand, in a communication system to which an LDPC code is applied, for example, N = 10,000 words are required as the code length N, and the parity check matrix has a size of a parity check matrix of 5,000 rows and 10,000. If the row weight of the parity check matrix is 6 and the column weight is 3, the number of parity check matrices “1” is 30,000. The number of β required for one α calculation (the number of α required for one β calculation) is 30,000.

  Thus, for example, in the case where all are realized by parallel calculation, from 30,000 β to 5,000 α arithmetic units are used (the input to the α arithmetic unit is 6 inputs, one from six βs. (Calculation of α and assumption) α is calculated. Further, the control for simultaneously reading β to 30,000 to the α calculator and writing to the memory for storing the calculation result is complicated, and the number of wiring connections between the calculator and the memory is as follows. Become enormous. Similarly, the β calculation is complicated and enormous. Moreover, the case of a variable check matrix is further complicated.

  In addition, even when a common arithmetic unit is used, data input / output control to the arithmetic unit is enormous. If the check matrix is fixed, it may be set once even if the wiring or input / output control is enormous. However, in a system to which an LDPC code is applied, it is necessary to investigate and improve the performance of the system by setting a plurality of check matrices, and an LDPC complex with a variable check matrix is desired.

Patent Document 1 discloses a technique for generating and decoding a parity check matrix in which the positions of elements “1” of the parity check matrix are regularly arranged. However, a decoding method for an arbitrary check matrix is not described.
JP 2005-340920 A

  The problem to be solved is that since a general-purpose LDPC decoder is configured corresponding to an arbitrary check matrix, control data for an arithmetic unit and storage memory is generated from the check matrix and there is no general-purpose LDPC decoder.

  A first aspect of the present invention is an LDPC decoder that includes an α calculator, an α storage memory, a β calculator, and a β storage memory, and performs decoding by repeatedly executing α and β operations on an input check matrix. This is a data generation method for calculation control data of an LDPC decoder that generates calculation unit control data.

  The calculation control data generation method extracts one row for each column of the check matrix, and generates row number data with dummy data added to column numbers whose extracted row numbers are insufficient for the maximum column weight. And an array in which connection information representing information connected to a combination having no dummy data is further combined with a combination of a column number and an intra-column number as an in-column number with an order for the generated row numbers. Generating an array in which connection information representing unconnected information is combined with a combination of a column number having dummy data and an in-column number, and searching the array having the connected connection information in ascending order of row numbers. Group the same row number, and the number of the grouped array is insufficient for the maximum row weight, the combination of the column number and the in-column number having the connection information that is not connected A character string in which line numbers are added in ascending order and the column numbers are arranged in ascending order in the row number group is generated, and the generated character string is read from the β storage memory at the time of α calculation, α It is assumed that control data for writing stored data to the α memory of the calculation result is used.

  The second invention is the data generation method of the first invention.

  The generated character string is used as the β storage memory, the address of the α storage memory, and memory area selection data.

  The third invention is an LDPC decoder having an α calculator, an α storage memory, a β calculator, and a β storage memory, and performing decoding by repeatedly executing α calculation and β calculation on the input check matrix. is there.

The LDPC decoder comprises means for extracting one row for each column of the parity check matrix;
Means for generating row number data with dummy data attached to column numbers whose extracted row numbers are insufficient for the maximum column weight;
An array obtained by further combining connection information representing information connected to a combination having no dummy data with respect to a combination of the column number and the in-column number as an in-column number with an order for the generated row number, and a dummy Means for generating an array that combines connection information representing information that is not connected to a combination of a column number and a number in a column of data;
Means for searching the array having the connected connection information in ascending order of row numbers and grouping the same row numbers;
If the number of grouped arrays is insufficient for the maximum number of row weights, add the number of combinations of column numbers and in-column numbers having connection information that are not connected, and add row numbers in ascending order. In the group, a means for generating a string in which column numbers are arranged in ascending order,
Means for reading out the generated character string from the β storage memory at the time of α calculation and using the result of α calculation as control data for writing stored data to the α storage memory .

  According to the present invention, decoding for an arbitrary check matrix can be performed, and a general-purpose LDPC decoder with a small circuit scale can be realized.

Example 1
FIG. 1 is a diagram showing a procedure for generating an arithmetic unit and memory control data for LDPC decoding according to the present invention. This shows a procedure for reading data from the storage memory and for generating data write data to the storage memory for operation control when performing LDPC decoding operation by the Min-sum method from the set check matrix.

The aforementioned row weights for one check matrix are different for each row, and the column weights are also different for each column. For this reason, in the future explanation, the maximum weight and the weight for each row are distinguished, and the maximum row weight is described as Rw and the maximum column weight is described as Cw.
S1: A check matrix (M rows and N columns) is set.
S2: A row having “1” is extracted for each column of the check matrix. Here, the number of extracted line numbers is the number of Cw.
S3: Dummy data is attached to the column numbers that are insufficient in Cw, and a table of row numbers corresponding to Cw is created for all column numbers.

In this data, the column numbers are arranged in ascending order, the row numbers having “1” are arranged in ascending order, the row number is “i”, and the column number is “j”, which corresponds to β _ij .
S4: An array of (column number, in-column number) is generated by adding an order to the row numbers for each column number generated in S3 and using the numbers in the column.
S5: An array (connection information, in-column number, column number) in which connection information is combined with the array generated in S4 is generated.
A. When there is no dummy data: An array of (0, in-column number, column number) is generated with connection information set to 0. Connection information “0” indicates that the connection is established. The meaning of this arrangement indicates that the check node of the row number is connected to the message node of the column number, and the number of connections corresponds to the maximum number in the column numbered in order.
I. When there is dummy data: An array of (1, column number, column number) is generated with connection information as 1. Connection information “1” indicates that the connection is not established.
S6, S7: a. The row numbers are searched in ascending order with respect to the array generated in (1), and an array (0, in-column number, column number) divided into groups for each row number is generated.

Since the column weight varies depending on each column, the number of arrays is made the same in accordance with the number of Cw. Set the array generated in step 1 after the array of each row number group. The method is the same as that in S5 in which there is dummy data for each line number group that is insufficient for Cw. Fill column numbers from ascending order in ascending order. The numbers agree with each other from the dummy data generation procedure. Description is omitted.
S8: A character string is generated for the array generated in S7 in ascending order of row numbers, and in ascending order of column numbers in the row number group.

In this data, for each row number group, the connection information, the in-column number, and the character string indicating the column number are the number of Cw together with the dummy data. When the first connection information is “0”, it indicates that the check node of the row number and the message node indicated by the column number are connected. Further, if the row number is “i” and the column number is “j”, it corresponds to α _ij .
S9: The character string generated in S8 is used as address control data in the memory when the α calculation of the LDPC decoder is performed.

  Address control of the generated character string and the α storage memory and β storage memory at the time of α calculation will be described later.

FIG. 2 is a diagram showing the configuration of the LDPC decoder of the present invention. The LDPC decoder 1 includes a decoder basic unit 10 and a control data generation unit 20 for the given check matrix 2. The decoder basic unit 10 includes a λ storage memory 11, an α storage memory 12, a β storage memory 13, a β calculator 14, an α calculator 15, an α storage memory input / output control unit 16, a β storage memory input / output control unit 17, The received word (Q _n ) determining unit 18 is configured. Here, only the basic part is shown, and clocks and input / output interfaces necessary for the actual hardware configuration are omitted. For example, when configuring a characteristic tester for checking the characteristics of LDPC decoding for a parity check matrix, the control data generating unit may be configured together with the decoder basic unit.

lambda storing device 11 retains the y _n received as lambda _n, input to the β calculator. Each of the α storage memory 12 and the β storage memory 13 stores the data α _mn and β _mn generated by the above-described procedure, and writing and reading are performed in accordance with the sequential calculation.

The β calculator 14 performs an addition operation shown in (Equation 1) based on λ from the λ storage memory 11 and α _mn from the α storage memory 12.

The α calculator 15 performs (multiplication, absolute value conversion, minimum value selection) shown in (Expression 2) by β _mn from the β storage memory 13.

Further, assuming that the length of the received word is N, the capacity of the λ storage memory holds N data, and the capacity of the α storage memory 12 and the β storage memory 13 is secured from the number of N and the number of weights. The example of FIG. 2 shows an example in which the column weights of all the columns are Cw and the column numbers are stored in the ascending order α _mn and β _mn .

FIG. 3 is a diagram showing an example of an LDPC decoding arithmetic unit and memory control data generation according to the present invention. The figure shows a procedure for generating data to be input to an arithmetic unit and memory when a parity check matrix is set and LDPC decoding is performed by the Min-sum method. Below, the row number, column number, and in-column number are counted from “0” for convenience. The numbers corresponding to the step numbers in FIG.
1) A 5-by-10 check matrix with a row weight of 6 and a column weight of 3 is used. In this case, Cw = 6 and Rw = 3. (S1)
2) Since there is 1 in the 1st row, 2nd row and 4th row, the 0th column is (1, 2, 4), and the first column is (0, 1, 2). Further, since the fourth column has only 1 in the second row and the fourth row, dummy data D is added (2, 4, D). (S2, S3)
The 0 column indicates α ₁₀ , α ₂₀ , and α ₄₀ necessary for calculating β _m0 from (1, 2, 4).
3) For column number 0, an array of (0, 1), (1, 2), (2, 4) is obtained for three row numbers 1, 2, and 4. Similarly, column number 1 is (0 0), (1, 1), (2, 2). Since column number 3 has dummy data D, it becomes (02), (1, 4), (2, D). (S4)
4) When there is no dummy data: For the array generated in 4), for example, the array for column number 0 is (0, 0, 0), (0, 1, 0), (0, 2, 0). (S5 a)
5) When there is dummy data: 1 is added to the combination of (in-column number, column number) (1,2,3), (1,2,4), (1,2,6), (1, 2, 8) and (1, 2, 9) are generated. The description is omitted below. (A of S5)
6) For example, for the group with row number 0, (0, 0, 1), (0, 0, 2), (0, 0, 6), (0, 0, 8), (0, 0, 9) Since the original array is 5 and 1 is insufficient for Cw = 6, the dummy data (1, 2, 3) is added. The description is omitted below. (S6, S7)
7) Data read from the β storage memory at the time of α computation and data for writing control to the α storage memory, starting with “001” 002 ”006” 008 ”009” 123 ”,“ 025 ”027” Data ending with 129 'is obtained.

As can be seen in the generation procedure, for example, 1, 2, 6, 8, 9 of the last six character string final terms (c) are β ₀₁ , β ₀₂ , β ₀₆ , β necessary for the calculation of α _0n Dummy data that is deficient in ₀₈ and β ₀₉ and the last row weight Rw = 6 is shown. The relationship between the control data and the storage memory will be described later. (S8, S9)
FIG. 4 is a diagram showing a configuration example of an α calculator and a β calculator of the present invention. The configuration example of an α calculator and a β calculator assuming a maximum row weight Rw6 and a maximum column weight Cw = 3 of a check matrix is shown.
1) α calculator It is composed of a multiplier 120, a multiplier 221, an absolute value converter 22 and a minimum value converter 23, and calculates six αs from six βs. Six [beta] generated for each row of the parity check matrix are input to calculate six [alpha]. These six αs are read out from the β storage memory by two every three clocks, and multiplied by the six β multiplication results and the minimum value selected after the absolute value conversion of the six βs. Is calculated. For example, from β ₀₁ , β ₀₂ , β ₀₆ , β ₀₈ , β ₀₉ , dummy data,
α ₀₁ : β ₀₂ , β ₀₆ , β ₀₈ , β ₀₉
α ₀₂ : β ₀₁ , β ₀₆ , β ₀₈ , β ₀₉
α ₀₆ : β ₀₁ , β ₀₂ , β ₀₈ , β ₀₉
α ₀₈ : β ₀₁ , β ₀₂ , β ₀₆ , β ₀₉
α ₀₉ : β ₀₁ , β ₀₂ , β ₀₆ , β ₀₈
To obtain 6 α's. The six αs are stored in an α storage memory composed of three memories. The storage address is in the order of generation. The α storage memory will be described with reference to FIG.
2) β calculator An adder 24 is used to calculate three βs from three αs and one λ. Three βs are read from the β storage memory and λ is read from the λ storage memory in one clock, and β is calculated. For example, three βs of β ₁₀ , β ₂₀ , and β ₄₀ are obtained from α ₁₀ , α ₂₀ , α ₄₀ and λ. Store in one address of β storage memory. The β storage memory and storage method will be described with reference to FIG.

FIG. 5 is a diagram illustrating an example of generation control data and a storage memory in an example of a check matrix according to the present invention. The control data generated for the check matrix and the contents of the α storage memory and β storage memory are shown. As in the description of FIG. 3, the row and column counts are assumed to be 0 for convenience.
1) Check matrix This is a 5-by-10 check matrix of the check matrix (Rw = 6, Cw = 3) shown in FIG.
2) Generated control data The control data generated in step 5) in FIG. 3 is made into two systems, each of which is used for reading necessary β from the β storage memory and writing the calculation result to the α storage memory at the time of α calculation.

The two systems are port 1 and port 2, respectively, and three numerical values a, b, and c are processed as follows: a: presence or absence of β (β present = 0, β absent = 1)
b: RAM selection for RAM selection c: Address of storage memory In an actual hardware configuration, HEX conversion is performed in order to handle a character string in hexadecimal notation, but here it will be described as it is.
3) α storage memory Consists of three 1-port RAMs. The contents of each RAM are stored with α _mn determined at the position “1” of the check matrix as shown in 3) of FIG. For example, α starting with α _m0 , α ₀₁ , α ₀₂ and ending with α ₀₈ , α ₀₉ is stored in the RAM 1. The RAM 2 and RAM 3 are stored in the same manner. At the time of β calculation, data are sequentially read from address 0 of each RAM and input to the β calculator of FIG.
4) β storage memory It is composed of one RAM of two ports, one address is divided into three areas, and β _mn determined at the position “1” of the check matrix as shown in 4) of FIG. 5 is dummy data (as will be described later). Dummy data is stored including β maximum value 0). For example, in area 0, data starting with β ₁₀ , β ₀₁ , β ₀₂ and ending with β ₀₈ , β ₀₉ is stored in area 0. The storage in the area 1 and the area 2 is similarly performed.

  In the β calculation, three βs are calculated at the same time. Therefore, the βs are written in the RAM 1, RAM 2 and RAM 3 in the order in which the βs are calculated in order from the address 0.

Next, based on the generation control data shown in 2), the calculation procedure will be described focusing on reading of necessary β from the β storage memory at the time of α calculation and writing of the calculation result to the α storage memory.
1) β operation The β operation reads out the three RAMs of the α storage memory in the order of addresses, and calculates β connected to each message node. Here, since the initial values of α are all set to “0” as described above, the first β is the same as λ. For example:

Β ₁₀ , β ₂₀ , and β ₄₀ are calculated from α ₁₀ , α ₂₀ , and α _{40 at} the address “0” of the three RAMs, and written to the address “0” of the β storage RAM. The β calculation results are written in the order of the calculation results in the order of addresses.
2) α operation The α operation is calculated from 6 βs that read out two βs in one clock and are connected to one check node in three clocks. Six αs are calculated from six βs, and one is output per clock. For rows that do not satisfy the maximum row weight Rw = 6, the dummy data of the control data generated in FIG. 3 is set as the maximum value of β so that the selection of the minimum value is not affected. Similarly, for a column that does not satisfy the maximum column weight Cw = 3, the number 0 is set in the dummy data of the control data generated in FIG. 3 so that the addition operation is not affected.

Control data specifies the RAM address, data selection, and RAM selection (corresponding to the RAM area in the case of reading) necessary for this calculation. For example, the calculation of α _0j is as follows. Note that the control data in FIG. 5 is expressed from the 0th to the 14th in order from the top.
(1) Reading β from β storage memory 0th data = 001, 002
Port 0: as c = 1 from the address = 1, b = area 0 of the RAM from 0, reads the beta _01, a data-stored from the data "0" in the presence of beta. Hereinafter, it is expressed as (port 0, 1, 0, 0, β ₀₁ ) as (port number, address number, RAM area, β presence / absence “0” or “1”, β _ij ).

(Ports 1, 2, 0, 0, β ₀₂ )
I. First data = 006, 008
(Port 0, ₆ , ₀ , ₀ , β ₀₆ )
(Port 1, ₈ , ₀ , ₀ , β ₀₈ )
C. Second data = 009, 123
(Port 0, ₉ , ₀ , ₀ , β ₀₉ )
(Port 1, 3, 1, 2, maximum value) In this case, since the dummy data has no connection information, the maximum value is read out.

As a result, α ₀₁ , α ₀₂ , α ₀₆ , α ₀₈ , α ₀₉ are calculated from the read β ₀₁ , β ₀₂ , β ₀₆ , β ₀₈ , β ₀₉ .
(2) Writing α to the α storage memory 0th data = 001, 002
Α ₀₁ is written to address 1 (c = 1) of RAM 0 (b = 0). Hereinafter, it is expressed as (RAM0, ₁ , α ₀₁ ).

(RAM0,2, α ₀₂₎
I. First data = 006, 008
(RAM0, ₆ , α06)
(RAM1, ₈ , α08)
C. Second data = 009, 123
(RAM0, ₉ , α09)
In this case, since it is dummy data without connection information, the number 0 is written.

  Thereby, after β calculation, it is possible to read from each RAM of the α storage memory in the order of addresses.

  As described above, reading from the β storage memory and writing to the α storage memory from the data generated in FIG. 3 can be controlled by the control data generated in FIG.

It is a figure which shows the calculation procedure of the computing unit of LDPC decoding of this invention, and memory control data. It is a figure which shows the structure of the LDPC decoder of this invention. It is a figure which shows the calculator of LDPC decoding of this invention, and an example of memory control data generation. It is a figure which shows the structural example of the alpha calculator of this invention, and a beta calculator. It is a figure which shows the example of the production | generation control data and storage memory in an example of the check matrix of this invention. It is a figure which shows decoding of the LDPC code by Min-sum method. It is a figure which shows the decoding procedure of an LDPC code.

Explanation of symbols

1 LDPC decoder 2 parity check matrix 10 decoding basic unit 11 λ storage memory 12 α storage memory 13 β storage memory 14 β arithmetic unit 15 α arithmetic unit 16 α storage memory input / output control unit 17 β storage memory input / output control unit 18 (Q _n ) determination unit 20 multiplier 1
21 Multiplier 2
22 Absolute value conversion unit 23 Minimum value selection unit 24 Adder

Claims (3)

An arithmetic unit, an alpha storage memory, a beta arithmetic unit, and a beta storage memory are provided. Data for arithmetic unit control in an LDPC decoder that performs decoding by repeatedly performing alpha computation and beta computation on an input check matrix. A data generation method for operation control data of an LDPC decoder to be generated, comprising:
Extract one row for each column of the parity check matrix;
Generate row number data with dummy data added to column numbers where the number of extracted row numbers is insufficient for the maximum column weight,
As an in-column number with an order for the generated row number, an array in which connection information representing information connected to a combination having no dummy data is further combined with a combination of the column number and the in-column number is a dummy. Generate an array that combines connection information representing information that is not connected to the combination of the column number with data and the number in the column,
Search the array having the connected connection information in ascending order of row numbers to group the same row numbers;
If the number of grouped arrays is insufficient for the maximum number of row weights, add the number of combinations of column numbers and in-column numbers having connection information that are not connected, and add row numbers in ascending order, Within the line number group, generate a string with column numbers in ascending order,
A data generation method characterized in that the generated character string is read from the β storage memory at the time of α calculation, and is used as control data for writing storage data to the α storage memory of the α calculation result. A data generation method according to claim 1, wherein
2. The data generation method according to claim 1, wherein the generated character string is used as data for selecting the address and memory area of the β storage memory, the α storage memory. An LDPC decoder that has an α calculator, an α storage memory, a β calculator, and a β storage memory, and performs decoding by repeatedly performing α calculation and β calculation on an input check matrix,
Means for extracting one row for each column of the parity check matrix;
Means for generating row number data with dummy data attached to column numbers whose extracted row numbers are insufficient for the maximum column weight;
An array obtained by further combining connection information representing information connected to a combination having no dummy data with respect to a combination of the column number and the in-column number as an in-column number with an order for the generated row number, and a dummy Means for generating an array that combines connection information representing information that is not connected to a combination of a column number and a number in a column of data;
Means for searching the array having the connected connection information in ascending order of row numbers and grouping the same row numbers;
If the number of grouped arrays is insufficient for the maximum number of row weights, add the number of combinations of column numbers and in-column numbers having connection information that are not connected, and add row numbers in ascending order. In the group, a means for generating a string in which column numbers are arranged in ascending order,
Means for reading out the generated character string from the β storage memory at the time of α calculation, and as control data for writing stored data to the α storage memory of the α calculation result;
An LDPC decoder comprising:

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