CN111313912A - LDPC code encoder and encoding method - Google Patents

LDPC code encoder and encoding method Download PDF

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CN111313912A
CN111313912A CN202010137401.7A CN202010137401A CN111313912A CN 111313912 A CN111313912 A CN 111313912A CN 202010137401 A CN202010137401 A CN 202010137401A CN 111313912 A CN111313912 A CN 111313912A
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bit data
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bit
encoding
ldpc code
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CN111313912B (en
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陆连伟
刘斌彬
赵叶星
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Beijing HWA Create Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix

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Abstract

The application provides an LDPC code encoder and an encoding method, wherein the encoder comprises: the input format conversion module is used for converting input data to be encoded into first bit data with a first bit length; the information buffer module is used for ping-pong buffer of the first bit data; the encoding module is used for encoding the first bit data in parallel to determine encoded second bit data; the check buffering module is used for ping-pong buffering the second bit data; and the output format conversion module is used for converting the second bit data into data to be output with a second bit length. The information buffering module can ping-pong buffer the first bit data, the coding module can code the first bit data in parallel to obtain the second bit data, and the check buffering module can ping-pong buffer the second bit data. Therefore, the parallelism of the encoder can be effectively improved, and the encoding rate of the encoder is improved. And the encoder can also realize the functions of multi-stage pipeline encoding and parameter dynamic configuration.

Description

LDPC code encoder and encoding method
Technical Field
The present invention relates to the field of communications, and in particular, to an LDPC code encoder and an encoding method.
Background
With the development of broadband systems, data transmission rates are higher and higher, and from the previous several tens of Mbps (transmission rate unit, which refers to the number of bits transmitted per second) to the highest 20Gbps (switching bandwidth, which is a unit for measuring the total data exchange capacity of a switch and has a transmission speed of 1000 megabits per second) rate of a 5G system in the future, the requirements on the throughput rate of an encoder are higher and higher. The 5G system adopts LDPC (Low Density parity check Code) codes with a QC-Raptor-Like structure, and has two base maps and multiple promotion factors to support the requirements of different service data lengths and Code rates. Therefore, how to effectively increase the coding rate of the encoder is a problem to be solved.
Disclosure of Invention
An objective of the embodiments of the present application is to provide an LDPC code encoder and an encoding method, so as to effectively improve an encoding rate of the encoder.
In order to achieve the above object, embodiments of the present application are implemented as follows:
in a first aspect, an embodiment of the present application provides an LDPC code encoder, including: the input format conversion module is used for converting input data to be encoded into first bit data with a first bit length; the information buffer module is used for ping-pong buffer of the first bit data; the encoding module is used for encoding the first bit data in parallel to determine encoded second bit data; the check buffering module is used for ping-pong buffering the second bit data; and the output format conversion module is used for converting the second bit data into data to be output with a second bit length.
In this embodiment, the information buffering module may ping-pong buffer the first bit data, the encoding module may encode the first bit data in parallel to obtain the second bit data, and the check buffering module may ping-pong buffer the second bit data. Therefore, the parallelism of the encoder can be effectively improved, and the encoding rate of the encoder is improved.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the information buffering module includes two information buffers, and the check buffering module includes two check buffers.
In the implementation mode, the first bit data is cached by using two information Buffer ping-pong buffers, so that the parallelism of caching the first bit data can be improved, and the coding rate of the coder is improved; by using two check buffers to ping-pong Buffer the second bit data, the parallelism of buffering the second bit data can be improved, thereby improving the coding rate of the encoder.
With reference to the first aspect, in a second possible implementation manner of the first aspect, the encoding module includes: the device comprises a plurality of matrix multipliers, a memory and a calculation unit, wherein each matrix multiplier is used for determining a first parameter and a second parameter according to the first bit data; the memory is used for storing the first parameter; the calculating unit is used for determining a first check bit according to the first parameter; each matrix multiplier is further configured to determine a second parity bit according to the first parity bit and the second parameter, where the first parity bit and the second parity bit represent the encoded second bit data.
In this implementation, the encoding module includes a plurality of matrix multipliers, and in combination with the memory and the calculation unit, the parallelism of calculating the check bits (i.e., the first check bits and the second check bits) can be improved, thereby improving the encoding rate of the encoder.
With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the number of the matrix multipliers is two, and correspondingly, the memory is a dual-port memory.
In this implementation, the number of the matrix multipliers is two, and the memory adopts a dual-port memory, so that the parallelism of the coding module can be improved without increasing the memory, and the cost (design cost, production cost, etc.) can also be reduced.
With reference to the second possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, each matrix multiplier includes a circular right shifter and an accumulator.
In the implementation mode, the operation of the matrix is realized through the circulation right shifter and the accumulator, and the accuracy of the operation can be ensured, so that the reliability of the coding of the coder is ensured.
With reference to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, the LDPC code encoder further includes a control unit, a cyclic shift value memory, and an address memory, where the control unit is configured to control reading and writing of the cyclic shift value memory and the address memory, and control reading and writing of the information buffer module by the address memory; and the cyclic shift value memory is used for storing the cyclic shift value corresponding to the cyclic right shifter.
In this implementation, the control unit may control reading and writing of the cyclic shift value memory and the address memory, and may also control reading and writing of the information buffering module through the address memory, thereby providing a basis for the encoder to perform pipeline processing on data.
With reference to the fifth possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, the cyclic shift value memory and the address memory are both dual-port random access memories.
In the implementation mode, the double-port random access memory is adopted as the cyclic shift value memory and the address memory, so that the parallelism of the coding module can be improved and the cost (design cost, production cost and the like) can be reduced under the condition of not increasing the memory.
With reference to the first aspect or any one of the first to sixth possible implementation manners of the first aspect, in a seventh possible implementation manner of the first aspect, the LDPC code encoder further includes: the input buffer module is used for buffering the input data to be coded; and the output cache module is used for caching the data to be output.
In this implementation manner, the input buffer module may buffer the input data to be encoded, and the output buffer module may buffer the data to be output, so as to ensure the encoding reliability of the encoder.
With reference to the first aspect, or with reference to any one of the first to sixth possible implementation manners of the first aspect, in an eighth possible implementation manner of the first aspect, the information buffering module employs a first clock frequency, the encoding module employs a second clock frequency, and the check buffering module employs a third clock frequency.
In this implementation, a lower clock frequency (second clock frequency) is used in the core processing portion (encoding module) to improve the reliability of the circuit, and a higher clock frequency (first clock frequency and third clock frequency) is used in the simpler portion (information buffer module and check buffer module) to reduce the rate bottleneck. Therefore, the encoding rate can be improved as much as possible under the condition of ensuring the reliability of the encoder.
In a second aspect, an embodiment of the present application provides an LDPC code encoding method, which is applied to the LDPC code encoder described in any one of the first aspect or possible implementation manners of the first aspect, where the LDPC code encoding method includes: converting input data to be encoded into first bit data with a first bit length, and ping-pong buffering the first bit data; parallelly encoding the first bit data to determine encoded second bit data, and ping-pong caching the second bit data; and converting the second bit data into data to be output with a second bit length.
In the embodiment of the application, the input data to be encoded is converted into first bit data with a first bit length and subjected to ping-pong buffer, the first bit data is further encoded in parallel to determine encoded second bit data and subjected to ping-pong buffer, and the second bit data is converted into data to be output with a second bit length so as to be output by an encoder. Therefore, the method is favorable for realizing multi-level stream coding, thereby improving the parallelism degree during coding and improving the coding rate.
With reference to the second aspect, in a first possible implementation manner of the second aspect, the method includes: a first thread, a second thread and a third thread, the third thread running the steps of: converting input data to be encoded into first bit data with a first bit length, and performing ping-pong cache on the first bit data, wherein the second thread operates the following steps: parallelly encoding the first bit data to determine encoded second bit data, ping-pong caching the second bit data, and the first thread operating step: and converting the second bit data into data to be output with a second bit length.
In the implementation mode, the multi-thread parallel coding can be realized, and the coding efficiency of the LDPC code coder is greatly improved.
With reference to the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, when an information buffering module of the LDPC code encoder includes two dual-port information buffers, a check buffering module includes two dual-port check buffers, an encoding module includes a dual-port memory and two matrix multipliers, and a cyclic shift value memory and an address memory are both dual-port random access memories, the method further includes: and the fourth thread enables the encoding module to encode in parallel on the basis of the first thread, the second thread and the third thread so as to increase the parallelism of the LDPC code encoder.
In the implementation mode, a fourth thread is further added on the basis of the three threads to perform parallel coding processing, so that the parallelism of the encoder is improved, and the coding efficiency of the encoder can be further improved.
With reference to the second aspect, in a third possible implementation manner of the second aspect, when the LDPC code encoder includes a cyclic shift value memory and an address memory, and the cyclic shift value memory and the address memory are both random access memories, before the LDPC code encoder performs encoding, the method further includes: and configuring required parameters into the cyclic shift value memory and the address memory to support different LDPC codes and realize the dynamic configuration of the parameters.
In this implementation manner, parameters to be configured may be configured in a cyclic shift value memory and an address memory (both random access memories), so that different LDPC codes may be supported, and the parameters of the encoder may be dynamically configurable.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic diagram of a sub-matrix according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of an LDPC code encoder for implementing multiple stages of pipelining according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of another LDPC code encoder for implementing multi-level pipelining according to an embodiment of the present application.
Fig. 4 is a schematic port diagram of an LDPC code encoder according to an embodiment of the present application.
Fig. 5 is a flowchart of an LDPC code encoding method according to an embodiment of the present application.
Icon: a 100-LDPC code encoder; 101-input buffer module; 102-an input format conversion module; 103-an information buffering module; 1031. 1032-information Buffer; 104-an encoding module; 1041-a matrix multiplier; 1042 — a memory; 1043-a calculation unit; 105-a check buffer module; 1051. 1052-check Buffer; 106-output format conversion module; 107-output buffer module; 108-a control unit; 109-cyclic shift value memory; 110-address memory.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
For the purpose of facilitating an understanding of the technical solutions of the present application, the basic principles of the present solutions will be described herein.
Supporting multiple information block sizes is a design requirement for the practicality of LDPC codes. If the check matrix of the LDPC code is designed directly according to the size of the information block, a large number of check matrices are required to meet the requirement of information block granularity scheduled by the broadband system, which is not feasible for the description and coding/decoding implementation of the LDPC code. The problem is solved by the proposal of QC-LDPC Codes (Quasi-cyclic LowDensity Parity Check Codes).
QC-LDPC code is a kind of structured LDPC code, and its check matrix can be decomposed into Z x Z all-zero matrix and cyclic shift matrix. Wherein the cyclic shift matrix is obtained by cyclically shifting the zxz identity matrix to the right. The matrix before expansion is called a base matrix, and contains elements "0" and "1". And the position of "0" is replaced by an all-zero matrix of Z × Z, and the position of "1" is replaced by a matrix obtained by cyclic shifting an identity matrix of size Z × Z. Thus, the base matrix size is m × n, and the check matrix size of the extended QC-LDPC code may be mZ × nZ, i.e.:
Figure BDA0002396709030000071
wherein the content of the first and second substances,
Figure BDA0002396709030000072
is a shift Vi,jThe cyclic shift matrix of (2). For the sake of uniform expression, S is used-1Representing a Z × Z all-zero matrix. Thus, Vi,j∈{-1,0,1,...,Z-1}。
The Raptor-Like LDPC code can firstly design a check matrix with high code rate, then generates check bits in increments by expanding the check matrix to realize multi-code rate coding, and the support of IR-HARQ (Incremental Redundancy Hybrid Automatic Repeat Request) can be realized by retransmitting the expandable check bits. The check matrix structure of the Raptor-Like LDPC code is as follows:
Figure BDA0002396709030000073
wherein HcoreIs a high code rate part, HextIs the extension, 0 is the all-zero matrix and I is the identity matrix.
The 5G system adopts QC-Raptor-Like LDPC code, and the base matrix H thereofbaseHas the following structure:
Figure BDA0002396709030000074
wherein, [ A B ]]Corresponding to H in Raptor-Like LDPC codecoreIndicating a high code rate part; d corresponds to HextAnd indicates an extension portion. The sub-matrix A corresponds to systematic bits and has a size of LBX k; the sub-matrix B is a square matrix with a size LB×LBCorresponding to the first set of parity bits; the sub-matrix C is an all-zero matrix with a size LB×(n-k-LB) Corresponding to the second set of parity bits; the sub-matrix E is a unit matrix with the size of (n-k-L)B)×(n-k-LB) (ii) a The size of the sub-matrix D is (m-L)B)×(k+LB). According to the characteristics of the LDPC check matrix, the matrix [ B C]Is equal to HbaseThe number of rows of (c), i.e.: and m is n-k.
To reduce the encoding complexity, for example, the design of the sub-matrix B can be seen in fig. 1, that is:
(1) the first column weight is determined to be 3.
(2) The columns subsequent to the first column may employ a dual diagonal configuration.
(3) When the lifting factor is used to obtain the check matrix from the submatrix B, the cyclic shift value V for designing two elements in the first column may be usedi,jSame and other cyclic shift values V per columni,jIn the same manner.
The submatrix B designed in this way can effectively reduce the coding complexity. Of course, other manners may also be adopted to design the sub-matrix B, for example, one or a combination of the design manners (1) to (3) is adopted to design the sub-matrix B, so that the encoding complexity can also be reduced. Therefore, the present application should not be considered as limited herein.
And the check matrix after lifting the base matrix by the lifting factor Z is recorded as H, and the part corresponding to the sub-matrix A, B, C, D, E is recorded as HA、HB、HC、HD、HE. From the matrix characteristics, HCIs an all-zero matrix, HBIs a unit array.
Let the information bit input be
Figure BDA0002396709030000081
Wherein K ═ kZ is the information bit length; two sets of check bits are
Figure BDA0002396709030000082
L1、L2The lengths of the two groups of check bits; the code word after coding is
Figure BDA0002396709030000083
According to the characteristics of the LDPC check matrix, the following requirements are met:
Figure BDA0002396709030000084
please note that: unless otherwise specified, the multiplication and addition involved in the embodiments of the present application are performed in the binary domain.
Thus, it is possible to prevent the occurrence of,
Figure BDA0002396709030000091
Figure BDA0002396709030000092
after simplification, the following can be obtained:
Figure BDA0002396709030000093
Figure BDA0002396709030000094
Figure BDA0002396709030000095
according to the derivation, the calculation is firstly carried out to obtain
Figure BDA0002396709030000096
Is recalculated to obtain
Figure BDA0002396709030000097
The encoding process can be completed.
In the formula (8), H is to be calculatedBThe inverse matrix of (2) has a large operation amount. In order to improve the calculation efficiency, the following method can be used for realizing the following steps:
the front L in the formula (7)1＝LBXZ equations, one set of each Z equation, divided into LBAnd (3) correspondingly adding equations with the same number in each group to obtain a Z-group equation, namely:
Figure BDA0002396709030000098
wherein the content of the first and second substances,
Figure BDA0002396709030000099
represents a matrix HBZ lines per interval are divided into LBEach matrix is Z multiplied by L in size obtained by correspondingly adding rows with the same row number1A matrix of (a); in the same way, the method for preparing the composite material,
Figure BDA00023967090300000910
representing a matrix of size Z × K.
According to the characteristics of the submatrix B, the Z-set equation is obtained
Figure BDA00023967090300000911
The relevant terms can be eliminated and each equation contains only one p1,i(i∈[1,2,...,Z]). The value of i in each equation can be determined by a cyclic shift value left after excluding two identical cyclic shift values in the first column of the submatrix B, where the cyclic shift value can be denoted as VB。
Thus, equation (10) can be simplified as:
Figure BDA00023967090300000912
Figure BDA0002396709030000101
wherein the content of the first and second substances,
Figure BDA0002396709030000102
is a unit matrix circularly shifted to the right by VBA matrix obtained by the second time;
Figure BDA0002396709030000103
by
Figure BDA0002396709030000104
The characteristics of
Figure BDA0002396709030000105
Therefore, the temperature of the molten metal is controlled,
Figure BDA0002396709030000106
Svand multiplying by a matrix, namely obtaining the matrix by circularly shifting the matrix upwards for V times. Thus, the column vector
Figure BDA0002396709030000107
Cyclically shifted upwards by Z-VBThen obtaining
Figure BDA0002396709030000108
To obtain
Figure BDA0002396709030000109
Then, the calculation can be made by recursion according to the formula (10)
Figure BDA00023967090300001010
Thereby completing
Figure BDA00023967090300001011
And (4) calculating.
In this way, the computational efficiency can be improved as much as possible.
Referring again to fig. 1, an exemplary sub-matrix B designed in fig. 1 is illustrated. Wherein L isBCalculating as 4
Figure BDA00023967090300001012
The method comprises the following steps:
the first Z equations of equation (7) are taken to obtain:
Figure BDA00023967090300001013
wherein the content of the first and second substances,
Figure BDA00023967090300001014
represents taking HBA matrix composed of the 1 st to the Z th rows of,
Figure BDA00023967090300001015
represents taking HAAnd 1-Z rows of (a).
From the characteristics of the sub-matrix B, H is knownBThe first Z rows are non-zero in the 1 st to 2Z columns, and the other columns are all zero, so that the method is equivalent to the following steps:
Figure BDA00023967090300001016
wherein the content of the first and second substances,
Figure BDA00023967090300001017
is the cyclic shift value corresponding to the ith row and the jth column of the submatrix B.
Further comprising:
Figure BDA00023967090300001018
Figure BDA00023967090300001019
in the same way as above, the first and second,
Figure BDA0002396709030000111
Figure BDA0002396709030000112
thus, it is possible to prevent the occurrence of,
Figure BDA0002396709030000113
is calculated to obtain
Figure BDA0002396709030000114
Then, the calculation is carried out according to the formula (9) to obtain
Figure BDA0002396709030000115
The encoding process can be completed.
As can be seen from the above derivation process, equations (8) and (9) are the basis of coding, and two matrices and vectors need to be calculated as products, that is:
Figure BDA0002396709030000116
and
Figure BDA0002396709030000117
for example, the following are provided herein
Figure BDA0002396709030000118
For example, an exemplary calculation method is given.
By the characteristics of QC-LDPC codes, HACan be expressed as:
Figure BDA0002396709030000119
wherein the content of the first and second substances,
Figure BDA00023967090300001110
and indicating the cyclic shift value corresponding to the ith row and the jth column of the submatrix A.
Will be provided with
Figure BDA00023967090300001111
Dividing the number of each Z into one group, and obtaining the k groups
Figure BDA00023967090300001112
Figure BDA00023967090300001113
So that:
Figure BDA00023967090300001114
wherein the content of the first and second substances,
Figure BDA00023967090300001115
can be prepared by mixing
Figure BDA00023967090300001116
Cyclic shift upwards
Figure BDA00023967090300001117
And the calculation of the formula can be simplified into the operation of binary XOR after multiple times of cyclic shift, so that the method is very suitable for FPGA realization. And when
Figure BDA00023967090300001118
When the temperature of the water is higher than the set temperature,
Figure BDA00023967090300001119
no calculation is needed.
Through the introduction of the basic principle for implementing the scheme, it can be known that when the scheme is implemented, an appropriate encoder can be designed based on the principle, so that the technical scheme provided by the embodiment of the application can be operated and operated efficiently. In addition, in the description of the basic principle, there are many parts of calculation manners or design manners (for example, design manners of sub-matrices, calculation manners of codes, and the like), which are merely exemplary manners chosen for facilitating understanding, and therefore, these should not be construed as limitations of the present application. In other implementation manners, other design manners and/or calculation methods may be selected to achieve similar effects, and such manners are also within the protection scope of the present application as easily understood by those skilled in the art.
Hereinafter, an LDPC code encoder 100 provided in an embodiment of the present application will be described.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an LDPC code encoder 100 for implementing multi-stage pipelining according to an embodiment of the present application. In the present embodiment, the LDPC code encoder 100 may include: the device comprises an input buffer module 101, an input format conversion module 102, an information buffer module 103, an encoding module 104, a check buffer module 105, an output format conversion module 106, an output buffer module 107, a control unit 108, an address memory 110 and a cyclic shift value memory 109.
In this embodiment, the input buffer module 101 may be configured to buffer input data to be encoded. The input data bit width may be determined based on the throughput and operating frequency of the system. For example, assuming that the first clock frequency of the encoder is 200MHz (MegaHertz), if the throughput rate is to be 10Gbps, the parallel input bit width is at least: if 10G/200M is 50 bits, the input bit width to be selected is at least 50 bits.
In this embodiment, the input format conversion module 102 may be configured to convert input data to be encoded into first bit data of a first bit length. Illustratively, Z-tiling is taken as an example. As can be seen from the algorithm principle, when the input format conversion module 102 processes data to be encoded, the input format conversion module 102 may perform processing according to Z blocks, and splice or split the input data into a group of Z bits, and the input format conversion module 102 may implement the function of splicing and splitting the data.
In this embodiment, the information buffering module 103 may be configured to ping-pong buffer the first bit data converted by the input format conversion module 102. The bit width of the information buffer module 103 may be the maximum value Z of all the supported lifting factorsmaxThe depth may be the maximum value k of k among all codewords supported by the encodermax. Therefore, the parallelism of the first bit data buffered by the encoder can be improved as much as possible, and the encoding rate is improved.
For example, in order to further improve the parallelism of the encoder buffering the first bit data, the information buffering module 103 may include two information buffers, where the two information buffers may alternately Buffer the first bit data converted by the input format conversion module 102 (where the alternate buffering means that when one of the information buffers (reference numeral 1031) buffers the first bit data, the other information Buffer (reference numeral 1032) does not Buffer the data at this time, and the next first bit data converted by the input format conversion module 102 is buffered by the other information Buffer (reference numeral 1032), so as to alternately Buffer the first bit data). Of course, in general, the first bit data of the two information Buffer buffers are different (for example, two first bit data adjacent in time sequence may be used).
In this embodiment, the encoding module 104 may encode the first bit data buffered by the information buffering module 103, and may encode in parallel (of course, not limited thereto), so as to increase the parallelism of the encoder, thereby increasing the encoding rate, and thus determining the encoded second bit data.
Illustratively, the encoding module 104 may include a matrix multiplier 1041(s), a memory 1042, and a calculation unit 1043. The matrix multiplier 1041 may be configured to determine a first parameter and a second parameter according to the first bit data, the memory 1042 may be configured to store the first parameter, and the calculating unit 1043 may be configured to determine a first check bit according to the first parameter. Each matrix multiplier 1041 may further determine a second parity bit according to the first parity bit and the second parameter. The first parity bit and the second parity bit can represent the encoded second bit data. The plurality of matrix multipliers 1041, in combination with the memory 1042 and the calculating unit 1043, can increase the parallelism of calculating the check bits (i.e. the first check bits and the second check bits), thereby increasing the encoding rate of the encoder.
In particular, the matrix multiplier 1041 may be used for
Figure BDA0002396709030000131
(i.e., the first parameter) and
Figure BDA0002396709030000132
(i.e., the second parameter). The matrix multiplier 1041 may comprise two parts: cyclic shifter for implementing product of unit cyclic matrix and vector, e.g. in implementation (21)
Figure BDA0002396709030000133
An accumulator for implementing a binary addition operation, such as the binary addition operation in equation (21) (implemented by using an exclusive or in an FPGA, wherein the FPGA is a Field Programmable gate array).
The operation of the matrix is realized through the circulation right shifter and the accumulator, and the accuracy of the operation can be ensured, so that the encoding reliability of the encoder is ensured.
In particular, memory 1042 may be used for temporary storage
Figure BDA0002396709030000141
(i.e., the first parameter) may have a bit width of ZmaxThe depth may be the maximum number of rows L of BB,max。
And the calculation unit 1043 may be used for calculating
Figure BDA0002396709030000142
(i.e., the first parity bit). In addition, the matrix multiplier 1041 may further determine a second parity according to the first parity calculated by the calculating unit 1043
Figure BDA0002396709030000143
In this embodiment, the check buffering module 105 may be configured to ping-pong buffer the second bit data (the first check bit) encoded by the encoding module 104
Figure BDA0002396709030000144
And a second check bit
Figure BDA0002396709030000145
). The bit width of the check buffer module 105 may be ZmaxThe depth may be the maximum number of rows m of the base matrixmax. Therefore, the parallelism of the second bit data buffered by the encoder can be improved as much as possible, and the encoding rate is improved.
For example, to further improve the parallelism of the encoder buffering the second bit data, the check buffering module 105 may include two check buffers, and the two check buffers may alternately Buffer the second bit data encoded by the encoding module 104 (where the alternate buffering means that when one check Buffer (reference numeral 1051) buffers the second bit data, the other check Buffer (reference numeral 1052) does not Buffer the data at this time, and the second bit data encoded by the next encoding module 104 is buffered by the other check Buffer (reference numeral 1052), so as to alternately Buffer the second bit data). Of course, in general, the second bit data of the two information Buffer buffers are different (for example, two second bit data adjacent in time sequence may be used).
In this embodiment, the output format conversion module 106 may convert the second bit data ping-pong buffered by the verification buffer module 105 into the data to be output with the second bit length. That is, the output format conversion module 106 may also implement the data splicing and splitting functions. The second bit length and the first bit length are independent of each other, the first bit length may depend on the number of bits of the Z block, and the second bit length may be determined according to a required format, and there is no necessary connection between the two. The output bit width of the data to be output depends on the system requirements, for example, assuming that the second clock frequency of the encoder is 200MHz, the throughput rate is required to be 10Gbps, and k is 22, m is 46, then the parallel output bit width is at least: 10G × 46/22/200M ≈ 105 bits, the output bit width that should be selected is at least 105 bits.
In this embodiment, the output buffer module 107 may buffer the data to be output, waiting for output.
In this embodiment, address memory 110 may be used to store
Figure BDA0002396709030000151
The column number j of time, and
Figure BDA0002396709030000152
the column number j of (i) where,
Figure BDA0002396709030000153
and indicating the cyclic shift value corresponding to the ith row and the jth column of the submatrix D. The storage mode can be as follows: storing by rows, storing the submatrices A in each row
Figure BDA0002396709030000154
Column number j, and then in each row of the submatrix D
Figure BDA0002396709030000155
Column number j. When a plurality of base matrices are supported, corresponding column numbers may be sequentially stored according to the base matrices. The memory 1042 bit width may be the maximum number of columns n of the base matrix supported by allmaxBit width of
Figure BDA0002396709030000156
(wherein,
Figure BDA0002396709030000157
representing rounding up), the depth may be all of the basis matrices WA+WDIn which W isA、WDThe number of "1" in each sub-matrix A, D.
In this embodiment, the cyclic shift value storage 109 may store parameters required by the encoding module 104 during encoding, so as to cooperate with the encoding module 104 to complete encoding.
Illustratively, the cyclic shift value memory 109 may be used to store
Figure BDA0002396709030000158
Value of time shift
Figure BDA0002396709030000159
And
Figure BDA00023967090300001510
value of time shift
Figure BDA00023967090300001511
The storage order may correspond one-to-one to the column numbers in the address memory 110. When a plurality of base matrices are supported, corresponding column numbers may be sequentially stored according to the base matrices. The memory 1042 bit width may be the maximum number of columns n of the base matrix supported by allmaxBit width of
Figure BDA00023967090300001512
The depth may be all base matrices nZ×(WA+WD) Of (a) in which n isZThe number of lifting factors Z supported for one base matrix.
In this embodiment, the control unit 108 may be configured to control reading and writing of the cyclic shift value memory 109 and the address memory 110, and may control reading and writing of the information buffering module 103 through the address memory 110.
Based on the LDPC code encoder 100 (shown in fig. 2) for implementing multi-stage pipelining provided in the embodiment of the present application, a general description is provided herein for an encoding flow thereof.
First, the input buffer module 101 may buffer information with a fixed input bit width (i.e., input data to be encoded).
The input format conversion module 102 may perform format conversion on the cached information (to-be-encoded data) with a fixed bit width, splice or split the information into first bit data of one group of Z bits, and store the first bit data in the information Buffer (the information Buffer module 103).
The encoding module 104 may obtain the buffered first bit data from the information Buffer (the information buffering module 103) according to the set timing sequence, and encode the first bit data.
Specifically, the matrix multiplier 1041 of the encoding module 104 may calculate according to the first bit data
Figure BDA0002396709030000161
(first parameter) and will be calculated
Figure BDA0002396709030000162
Logging inA memory 1042. And the computing unit 1043 is readable
Figure BDA0002396709030000163
And grouped to calculate
Figure BDA0002396709030000164
Here, taking the reference design of the sub-matrix B shown in fig. 1 as an example, the calculation unit 1043 may calculate according to the equations (13), (17), (18) and (19)
Figure BDA0002396709030000165
To determine
Figure BDA0002396709030000166
(i.e., the first parity bit) and stored in the check Buffer (i.e., the check Buffer module 105).
The matrix multiplier 1041 can read the information bits from the information buffer (information buffer block 103) and the check buffer (check buffer block 105)
Figure BDA0002396709030000167
And check bit
Figure BDA0002396709030000168
Computing
Figure BDA0002396709030000169
(
Figure BDA00023967090300001610
As a second parameter) to obtain a second check bit
Figure BDA00023967090300001611
And stores the check buffer. Wherein the first check bit
Figure BDA00023967090300001612
And a second check bit
Figure BDA00023967090300001613
Representing the second bit of data.
The output format conversion module 106 may store the information (second bit data) of the group of Z bits in the check buffer into the output buffer module 107 in a format required by the output (i.e., the data to be output with the second bit length) through splitting or splicing. And the output buffer module 107 may output the encoded check bits (data to be output). Thus, the encoding can be completed.
The implementation of the multi-stage flowing water can be as follows: the encoding process of the encoder is divided into three parts, the input buffer and the input format are converted into a first part, encoding (namely calculation of check bits) is a second part, the output format is converted into a third part, and the three parts are used for realizing pipeline encoding. Illustratively, during the operation of multi-level pipeline coding, three threads are operated. When one thread runs to the first part, one thread runs to the second part, and meanwhile, the other thread runs to the third part, so that three-stage pipeline coding can be realized, and the coding rate of the coder can be effectively improved. Of course, the LDPC code encoder 100 provided in the embodiment of the present application may also improve the parallelism, for example, improve the parallelism of the encoding module 104, and may be implemented by parallel encoding (that is, the encoding module 104 may perform multi-thread encoding). In the following, an exemplary way will be given to achieve a higher degree of parallelism in the encoding of the encoder.
Referring to fig. 3, in order to further improve the parallelism of the LDPC code encoder 100, an embodiment of the present application further provides a schematic structural diagram of another LDPC code encoder 100 that implements multi-stage pipelining.
In the present embodiment, the structure of the LDPC code encoder 100 for implementing multi-level pipelining has many similarities with the structure of the LDPC code encoder 100 described above, and therefore, only different parts are described in detail herein, and similar parts can refer to the foregoing and are not described again.
In this embodiment, the LDPC code encoder 100 may also include: the device comprises an input buffer module 101, an input format conversion module 102, an information buffer module 103, an encoding module 104, a check buffer module 105, an output format conversion module 106, an output buffer module 107, a control unit 108, an address memory 110 and a cyclic shift value memory 109.
In contrast, the information buffering module 103 may include two dual-port information buffers, and the two information buffers perform ping-pong buffering, and each information Buffer may provide the first bit data for the two matrix adders 1041 in the encoder module 104 at the same time. This may further increase the buffering rate of the information buffering module 103.
And, two matrix multipliers 1041 may be included in the encoding module 104 for parallel encoding. Correspondingly, the memory 1042 may be a dual-port memory, so as to improve the parallelism of the coding module 104 and reduce the cost (design cost, production cost, etc.) without increasing the memory 1042. Of course, when the encoding module 104 includes two matrix multipliers 1041, two memories 1042 may also be used to improve the parallelism of encoding of the encoding module 104, where the selection of the memories 1042 and the number of the matrix multipliers 1041 should not be considered as limitations of the present application, and may be selected according to actual needs.
Correspondingly, the check Buffer module 105 may include two double-port check buffers, and the two check buffers perform ping-pong Buffer processing, and each check Buffer may receive the second bit data output by the two matrix adders 1041 in the encoder module 104 at the same time. This may further increase the buffering rate of the check buffer module 105.
In addition, the cyclic shift value memory 109 and the address memory 110 may both adopt a dual-port random access memory so as to correspond to the encoding module 104 for improving the parallelism, so that the parallelism of the encoder can be improved as a whole.
Other parts of the LDPC code encoder 100 can refer to the description of the encoder shown in fig. 2, and are not described herein again.
The LDPC code encoder 100 shown in fig. 3 can further improve the parallelism in encoding compared to the LDPC code encoder 100 shown in fig. 2, thereby improving the encoding rate of the LDPC code encoder 100.
Specifically, the LDPC code encoder 100 shown in fig. 3The encoding module 104 may calculate
Figure BDA0002396709030000182
And
Figure BDA0002396709030000181
the matrix multiplier 1041 can only realize the product calculation of the cyclic shift matrix and the vector once in one clock, so that at least W is neededA+WDA clock, wherein WA、WDIs the number of "1" in the submatrix A, D.
To reduce the number of computation clocks, the number of matrix multipliers 1041 may be increased, and thus the read information and the cyclic shift value may be increased accordingly. Under the condition of not increasing the Memory 1042, the characteristic that a dual-port RAM/ROM (RAM, Random Access Memory; ROM, Read-Only Memory) can be used for reading two groups of data at the same time can be fully utilized, and two matrix multiplications can be simultaneously carried out. In addition, the information Buffer, the address memory 110, the cyclic shift value memory 109, the memory 1042 and the check Buffer need to be changed from a single-port RAM to a dual-port RAM.
After adding a matrix multiplier 1041, the number of processing clocks can be up to WA+WDIs reduced to
Figure BDA0002396709030000191
Such an approach enables parallel encoding by the encoding module 104, thereby further increasing the encoding rate of the LDPC code encoder 100.
Taking the encoder of the LDPC base matrix of the 5G system as an example, the parameters corresponding to the base matrix are as follows:
m＝46，n＝68，k＝22，LB＝4，WA＝67，WDthere are multiple values for Z198, and when a maximum value of 384 is taken, the maximum throughput rate is reached.
The clock cycles required for the encoding module 104 to complete the check bit calculation (i.e., encoding) are as follows:
computing
Figure BDA0002396709030000192
Need to make sure that
Figure BDA0002396709030000193
One clock cycle;
computing
Figure BDA0002396709030000194
Requires LB4 clock cycles;
computing
Figure BDA0002396709030000195
Requires LB4 clock cycles;
computing
Figure BDA0002396709030000196
Need to make sure that
Figure BDA0002396709030000197
One clock cycle;
a total of about 141 clock cycles is required.
Taking the clock frequency f as 200MHz as an example, the throughput rate of the encoding module 104 is:
Figure BDA0002396709030000198
here, the throughput of the encoding module 104 is calculated, and to achieve the throughput of the entire LDPC code encoder 100 up to 10Gbps, the input bit width and the output bit width of the first-stage pipeline (i.e., the first part) and the third-stage pipeline (i.e., the third part) may be designed:
the input bit width is at least: 50 bits at 10Gbps/200 MHz;
the output bit width is at least: 10Gbps m/k/200MHz ≈ 105 bits.
In this way, a high throughput rate of the LDPC code encoder 100 can be achieved at a lower clock frequency.
Of course, this approach is the throughput obtained with the same clock frequency used for the entire encoder. In practical implementation, in order to reduce the bit width of the input/output (or to further increase the throughput of the encoder without changing the bit width) while ensuring the throughput, the processing clocks of the first-stage pipeline (i.e., the first part) and the third-stage pipeline (i.e., the third part) may use different clocks from the clock of the encoding module 104, so as to achieve the purpose.
Illustratively, the first stage of the pipeline (i.e., the first portion) may employ a first clock frequency, the second stage of the pipeline (i.e., the second portion) may employ a second clock frequency, and the third stage of the pipeline (i.e., the third portion) may employ a third clock frequency. The first clock frequency and the third clock frequency may be higher than the second clock frequency, and the first clock frequency and the third clock frequency may be the same or different, and are not limited herein.
Considering that the operation content of the core processing part (e.g. the second part) is complex, a lower clock frequency (e.g. 200MHz) can be used to improve the reliability of the circuit, while the parts with simpler operation content (e.g. the first part and the third part) can use a higher clock frequency (e.g. 400MHz) to reduce the rate bottleneck (by increasing the clock frequency, the number of clocks required for processing can be reduced without changing the bit width, and the rate is increased). By the method, the encoding rate of the whole encoder can be improved while the reliability of the encoder is ensured.
In addition, the LDPC code encoder 100 provided in the embodiment of the present application may further implement a function of dynamically configurable parameters. Illustratively, with the submatrix B and the corresponding cyclic shift value unchanged, parameters may be dynamically configured to support different LDPC codes. The address memory 110 and the cyclic shift value memory 109 are generally implemented by using ROM, the internal parameters cannot be modified, and in order to more flexibly support various different requirements, the ROM may be replaced by RAM (the RAM used in the address memory 110 and the cyclic shift value memory 109 described in the embodiment of the present application is not limited herein, but ROM may also be used when dynamic configuration parameters are not required). When the hardware is implemented, a set of parameters can be used for initialization, and if the encoder parameters to be implemented are not in the RAM, the required parameters can be configured into the RAM before encoding to support different LDPC codes, so as to implement the function of dynamically configurable parameters.
To implement the function of parameter configuration, the input data port and the input address port may be multiplexed. One exemplary way is: defining address space ADDRSPACE0 for writing to an input buffer, for example defining address space ADDRSPACE0 as: 0X0000 to 0X0 FFF. Alternatively, address space ADDRSPACE1 is defined for writing to address memory 110, for example, address space ADDRSPACE1 is defined as: 0X1000 to 0X1 FFF. Still alternatively, address space ADDRSPACE2 is defined for writing to address memory 110, for example, address space ADDRSPACE2 is defined as: 0X2000 to 0X2 FFF. In the case that the write enable is valid, it is determined in which address space the input address is located, and the input data may be stored in the corresponding memory 1042 according to the difference of the address spaces.
To facilitate understanding of the LDPC code encoder 100 provided in the embodiments of the present application, the LDPC code encoder 100 will be described herein from a specific example. Referring to fig. 4, fig. 4 is a schematic diagram of a port of the LDPC code encoder 100. In the present embodiment, the LDPC code encoder 100 may include:
input data port: for transmitting data to be encoded.
Inputting an address port: the method is used for indicating the address of the input data to be encoded stored in the input buffer.
First clock port: for inputting the clock frequency that implements the first stage of the flow.
A second clock port: the clock frequency used to input the pipeline implementing the second stage.
A third clock port: for inputting the clock frequency that implements the third stage of the pipeline.
Write enable port: indicating that the current input data port/output data port is valid and can be written into the input buffer.
Read enable port: for reading the indication to the output buffer.
Output address port: for reading the output buffer.
An output data port: for outputting the encoded check bits (data to be output).
Reset port: for resetting the encoder.
Of course, these ports are merely exemplary, and in other implementations, different ports and definitions may be adopted, and the ports may be designed according to actual needs, and are not limited herein.
In the above, several LDPC code encoders 100 provided in the embodiments of the present application are introduced, and hereinafter, LDPC code encoding methods provided in the embodiments of the present application will be described.
Referring to fig. 5, fig. 5 is a flowchart of an LDPC code encoding method according to an embodiment of the present application. In the present embodiment, the LDPC code encoding method may include step S10, step S20, and step S30.
The LDPC code encoding method can be performed by the LDPC code encoder provided in the embodiments of the present application. Step S10 may be performed when the LDPC code encoder needs to encode data to be encoded.
Step S10: converting input data to be encoded into first bit data with a first bit length, and ping-pong buffering the first bit data.
In this embodiment, the LDPC code encoder may buffer the input data to be encoded, convert the buffered data to be encoded into first bit data with a first bit length (for example, with a bit number of Z), and buffer the converted first bit data in a ping-pong buffer manner. For a specific manner of converting the data to be encoded into the first bit data and a manner of buffering the first bit data, reference may be made to the description in the foregoing, and details are not described here again.
Then, the LDPC code encoder may perform step S20.
Step S20: and parallelly encoding the first bit data to determine encoded second bit data, and ping-pong buffering the second bit data.
In order to increase the encoding rate and achieve high throughput of the LDPC code encoder, the LDPC code encoder may encode the first bit data in a parallel encoding manner to determine the encoded second bit data. For a specific process of encoding the first bit data, reference may be made to the foregoing description, and further description is omitted here. After the first bit data is encoded, the second bit data can be determined, and the LDPC code encoder may buffer the second bit data in a ping-pong buffer manner, which is not described herein again.
Then, the LDPC code encoder may perform step S30.
Step S30: and converting the second bit data into data to be output with a second bit length.
In this embodiment, the LDPC code encoder may convert the second bit data into the data to be output of the second bit length. And the data to be output can be cached and output is waited. The specific conversion method and the buffering method can be referred to above, and are not described herein again.
In addition, when the LDPC code encoder runs the LDPC code encoding method, a mode that a plurality of threads run simultaneously can be adopted to improve the encoding efficiency of the encoder. For example, a first thread, a second thread, and a third thread are used. While the third thread runs step S10, the second thread runs step S20, and at the same time, the first thread runs step S30 (i.e., the multi-stage pipeline coding method described above in the description of the LDPC code encoder, which is not described herein again). Of course, the steps executed by each thread are dynamically changed, and are not limited herein. By the method, multi-thread parallel coding can be realized, so that the coding efficiency of the LDPC code coder is greatly improved.
And when the information Buffer module of the LDPC code encoder comprises two double-port information buffers, the check Buffer module comprises two double-port check buffers, the encoding module comprises a double-port memory and two matrix multipliers, and the cyclic shift value memory and the address memory are both double-port random access memories, the LDPC code encoder can further increase the parallelism degree when the LDPC code encoding method is operated. For example, the fourth thread is used to enable the encoding module to perform parallel encoding on the basis of running the first thread, the second thread and the third thread, so as to increase the parallelism of the LDPC code encoder (which has been described above when describing the LDPC code encoder, and is not described here again). And a fourth thread is further added on the basis of the three threads to perform parallel coding processing, so that the parallelism of the encoder is improved, and the coding efficiency of the encoder can be further improved.
And when the LDPC encoder includes a cyclic shift value memory and an address memory, and both the cyclic shift value memory and the address memory are random access memories (may be a dual-port random access memory, but are not limited thereto), before the LDPC encoder operates the LDPC code encoding method to perform encoding, the LDPC encoder may further configure the required parameters into the cyclic shift value memory and the address memory to support different LDPC codes and implement dynamic configuration of the parameters (the foregoing has been introduced when the LDPC encoder is introduced, and is not described here again). Therefore, the encoder can flexibly use different LDPC codes during encoding, and the practicability of the encoder is improved. To sum up, the embodiment of the present application provides an LDPC code encoder and an encoding method, where the information buffering module may ping-pong buffer the first bit data, the encoding module may encode the first bit data in parallel to obtain the second bit data, and the check buffering module may ping-pong buffer the second bit data. Therefore, the parallelism of the encoder can be effectively improved, and the encoding rate of the encoder is improved. In addition, the reliable high throughput rate can be realized by adopting a mode of adopting different clock frequencies according to different implementation complexity through multistage pipeline processing and increased calculation parallelism and by using a lower clock frequency.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (13)

1. An LDPC code encoder, comprising:
the input format conversion module is used for converting input data to be encoded into first bit data with a first bit length;
the information buffer module is used for ping-pong buffer of the first bit data;
the encoding module is used for encoding the first bit data in parallel to determine encoded second bit data;
the check buffering module is used for ping-pong buffering the second bit data;
and the output format conversion module is used for converting the second bit data into data to be output with a second bit length.
2. The LDPC code encoder of claim 1, wherein the information buffering module comprises two information buffers and the check buffering module comprises two check buffers.
3. The LDPC code encoder of claim 1, wherein the encoding module comprises: a plurality of matrix multipliers, and a memory and computation unit,
each matrix multiplier is used for determining a first parameter and a second parameter according to the first bit data;
the memory is used for storing the first parameter;
the calculating unit is used for determining a first check bit according to the first parameter;
each matrix multiplier is further configured to determine a second parity bit according to the first parity bit and the second parameter, where the first parity bit and the second parity bit represent the encoded second bit data.
4. LDPC-code encoder according to claim 3 wherein the number of matrix multipliers is two, and correspondingly the memory is a dual port memory.
5. LDPC-code encoder according to claim 3, wherein each matrix multiplier comprises a cyclic right shifter and an accumulator.
6. The LDPC code encoder of claim 5, further comprising a control unit, a cyclic shift value memory, and an address memory,
the control unit is used for controlling the reading and writing of the cyclic shift value memory and the address memory and controlling the reading and writing of the information buffer module through the address memory;
and the cyclic shift value memory is used for storing the cyclic shift value corresponding to the cyclic right shifter.
7. LDPC-code encoder according to claim 6 wherein the cyclic shift value memory and the address memory are both dual-ported random access memories.
8. LDPC-code encoder according to any one of claims 1 to 7, further comprising:
the input buffer module is used for buffering the input data to be coded;
and the output cache module is used for caching the data to be output.
9. The LDPC code encoder according to any one of claims 1 to 7, wherein the information buffering module employs a first clock frequency, the encoding module employs a second clock frequency, and the check buffering module employs a third clock frequency, wherein the first clock frequency and the third clock frequency are higher than the second clock frequency.
10. An LDPC code encoding method applied to an LDPC code encoder as claimed in any one of claims 1 to 9, the method comprising:
converting input data to be encoded into first bit data with a first bit length, and ping-pong buffering the first bit data;
parallelly encoding the first bit data to determine encoded second bit data, and ping-pong caching the second bit data;
and converting the second bit data into data to be output with a second bit length.
11. The LDPC code encoding method of claim 10, wherein the method comprises: a first thread, a second thread and a third thread,
the third program operation step: converting input data to be encoded into first bit data with a first bit length, and performing ping-pong cache on the first bit data, wherein the second thread operates the following steps: parallelly encoding the first bit data to determine encoded second bit data, ping-pong caching the second bit data, and the first thread operating step: and converting the second bit data into data to be output with a second bit length.
12. The LDPC code encoding method of claim 11, wherein when the information Buffer module of the LDPC code encoder includes two dual-port information buffers, the check Buffer module includes two dual-port check buffers, the encoding module includes a dual-port memory and two matrix multipliers, and the cyclic shift value memory and the address memory are both dual-port random access memories, the method further comprises:
and the fourth thread is used for enabling the encoding module to encode in parallel on the basis of the first thread, the second thread and the third thread so as to increase the parallelism of the LDPC code encoder.
13. The LDPC code encoding method of claim 10, wherein when the LDPC code encoder includes a cyclic shift value memory and an address memory, and the cyclic shift value memory and the address memory are both random access memories, before the LDPC code encoder performs encoding, the method further comprises:
and configuring required parameters into the cyclic shift value memory and the address memory to support different LDPC codes and realize the dynamic configuration of the parameters.
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