JP4689168B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a technique for manufacturing an element formation layer including a semiconductor device including a plurality of thin film transistors (hereinafter referred to as TFTs) by peeling.

  In recent years, a technique for forming a TFT using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. TFTs are widely applied to electronic devices such as ICs and electro-optical devices.

  As a substrate on which these TFTs are formed, a glass substrate or a quartz substrate is currently used in many cases, but has a drawback that it is easily broken and heavy. In addition, these substrates are difficult to increase in size and are not suitable for mass production. Therefore, an attempt has been made to form an element composed of TFTs on a flexible substrate, typically a flexible plastic film.

  However, since the heat resistance of the plastic film is low, the maximum temperature of the process has to be lowered, and as a result, TFTs having better electrical characteristics cannot be formed than when formed on a glass substrate. Therefore, a semiconductor device, a display device, a light emitting device or the like obtained by directly forming a TFT on a plastic film has not been realized yet.

  On the other hand, a technique is disclosed in which after a thin film element is formed on a substrate such as glass or quartz, the thin film element is peeled off from the substrate and fixed to a substrate such as a plastic film (for example, see Patent Document 1). ).

   If a semiconductor device, a display device, a light-emitting device, or the like can be manufactured over a flexible substrate such as a plastic film in this way, in addition to being thin and lightweight, a flexible film having a curved surface. Can be used for a wide range of displays and the like, and the application range can be expanded.

Japanese Patent Laid-Open No. 10-125929

  Therefore, in the present invention, a thin film element is formed on various substrates by using a peeling technique, and space saving is achieved by forming the thin film element in a portion that is considered impossible by the conventional technique. Another object of the present invention is to provide a semiconductor device having excellent impact resistance and flexibility.

  The present invention is characterized in that a thin film element is formed on various substrates by fixing an element formation layer having a thickness of 50 μm or less once peeled from the substrate using a peeling technique onto the substrate. As the substrate to be fixed, various materials can be selected depending on the application, but a thin film element excellent in impact resistance and flexibility can be formed by fixing on a flexible substrate. it can. Here, as the TFT included in the element formation layer, an amorphous silicon TFT (a-Si TFT) formed using an amorphous semiconductor layer as an active layer, or a polysilicon TFT formed using a crystalline semiconductor layer as an active layer. (P-Si TFT).

  In the present invention, it can be directly fixed on the substrate by a peeling technique, but once it is fixed on the auxiliary substrate by a peeling technique to form a chip, the chip can be attached to a desired position on the substrate. it can.

  Note that it is more preferable to use a flexible substrate such as plastic as a substrate to which the thin film element is fixed because the merit of the peeling technique that the element can be formed without selecting the substrate can be utilized. Further, the thin film element can be further highly integrated by repeatedly stacking and fixing the element forming layer having a thickness of 50 μm or less peeled off from another substrate on the previously formed element forming layer.

  In the present invention, the element forming layer to be peeled has a film thickness of 50 μm or less, and the element is easily deteriorated by heat generated from the element forming layer. Therefore, heat can be effectively released to the substrate. The heat conductive material which can be used can also be used. Further, when another element forming layer is fixed on the already formed element forming layer, it is preferable to form a heat conductive thin film on the fixing surface (on the already fixed element forming layer).

The present invention includes a panel having a pixel portion and a driver circuit formed over a substrate and an FPC connected to the panel, and the FPC includes an element formation layer including a plurality of TFTs on a flexible substrate. An integrated circuit formed by being fixed is provided.
As another structure of the present invention, a panel having a pixel portion and a driver circuit formed on a substrate and an FPC connected to the panel are included, and the FPC includes an element formation layer including a plurality of TFTs. An integrated circuit formed by directly adhering to each other is provided.
Note that the FPC here refers to a flexible printed circuit board, which means a flexible circuit board.

The present invention has a pixel portion and a driving circuit on a substrate, and the driving circuit is formed of an integrated circuit formed by fixing an element formation layer including a plurality of TFTs to a flexible substrate. .
As another configuration, the pixel unit and the drive circuit are provided on a substrate, and the drive circuit includes an integrated circuit formed by directly fixing an element formation layer including a plurality of TFTs on the substrate. It is a feature.
That is, in the above structure, the driving circuit is not formed on the substrate in the same manner as the pixel portion, but is formed separately and then fixed to a desired position of the panel by a peeling technique. . At this time, the driving circuit can be directly fixed on the panel. For example, after fixing the driving circuit on the auxiliary substrate on which the wiring is formed in advance, the driving circuit is attached to a desired position on the panel via the solder ball. You can also.

The present invention includes a panel having a pixel portion and a driver circuit formed on a substrate, and an integrated circuit formed by fixing an element formation layer including a plurality of TFTs to a flexible substrate on the back surface of the panel. It is characterized by being.
As another structure, a panel having a pixel portion and a driver circuit formed on a substrate and an integrated circuit formed by directly fixing an element formation layer including a plurality of TFTs to the back surface of the panel are provided. It is characterized by having.
Note that the above structure is characterized in that, unlike a structure in which an integrated circuit formed by a peeling technique on a flexible substrate is attached to a panel, the integrated circuit is directly fixed to the back surface of the panel.

  In the above configuration, the integrated circuit includes at least one of a controller, a CPU (Central Processing Unit), and a memory. The integrated circuit is characterized in that its film thickness is 50 μm or less.

  The present invention is an electronic device characterized by using the semiconductor device having the above-described structure.

  In each of the above-described configurations, the semiconductor device includes a CPU, an MPU (Micro Processor Unit), a memory, a microcomputer, and an image processor, and in addition to a module in which these are mounted, the panel and an external power source are electrically connected. The module to which the FPC is attached is also included. Display devices include liquid crystal, EL, PDP, electronic paper, and the like. The panel may be an active matrix type or a passive matrix type.

  As described above, by forming a thin film element using a peeling technique, it becomes possible to form a thin film element in a portion that was considered impossible by the conventional technique, and thus space saving can be achieved. In addition, a semiconductor device having excellent impact resistance and flexibility can be provided.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.
(Embodiment 1)
In the first embodiment, a module (semiconductor module) including an integrated circuit formed by using a peeling technique on an FPC (Flexible Printed Circuit) for electrically connecting the panel 100 to the outside is shown in FIG. It explains using.

  1A is a top view of the semiconductor module, and FIG. 1B is a cross-sectional view of the semiconductor module. The panel 100 is provided with a pixel portion 105 and driving circuits (a signal line driving circuit 107 and a scanning line driving circuit 106). These driving circuits and an external power source (not shown) provided outside are provided. An FPC 108 for electrical connection is attached on the panel 100 with an adhesive 109.

  An integrated circuit (controller 101, CPU (Central Processing unit) 102, memory 103) is formed on the FPC 108 by a peeling technique.

  Note that these integrated circuits (the controller 101, the CPU (Central Processing unit) 102, and the memory 103) can be formed with a film thickness of 50 μm or less by using a peeling technique. Therefore, an integrated circuit can be formed over a flexible film such as the FPC 108. Further, as shown in FIG. 1B, even when the shape of the FPC 108 is curved and a physical force is applied, the integrated circuit formed by the peeling technique itself can cope with a flexible shape change. It can be used without impairing its function.

  FIG. 1C illustrates an enlarged view of the CPU 102 which is a part of the integrated circuit formed over the FPC 108 in FIG.

  An element formation layer 112 composed of a plurality of TFTs 111 is fixed on a flexible auxiliary substrate 113 by a peeling technique (in this case, twice peeling), and further electrically connected to the wiring 115 on the FPC 108 via bumps 114. Connected. Note that here, a case where the element formation layer 112 is fixed onto the auxiliary substrate 113 and then electrically connected to the wiring 115 on the FPC 108 by the bump 114 is shown; however, the present invention is not limited to this, A structure in which the element formation layer 112 is directly electrically connected to the wiring 115 without using the auxiliary substrate 113 and the bump 114 can also be employed. Note that the two-time peeling method will be described in detail in Embodiment 5.

  As another variation in the case of forming an integrated circuit on the FPC, the integrated circuit fixed to the FPC 208 may be enlarged as shown in FIGS.

  Note that the integrated circuit in this case is formed by forming an integrated circuit 210 in which a controller, a CPU, a memory, and the like are fixed on a large and flexible auxiliary substrate as shown in FIG. As shown in FIG. 2B, an integrated circuit 215 including a controller 211, a CPU 212, a memory 213, and the like is fixed to the auxiliary substrate 214 and then attached to the FPC 216. Also good.

  By increasing the size of the integrated circuit fixed on the FPC in this way, a large fixing (bonding) margin can be obtained, so that alignment at the time of fixing (bonding) can be easily performed.

  Further, as the peeling method of the present invention, the element forming layer 222 formed on the substrate is electrically connected to the wiring 225 on the substrate (here, the FPC 228) via the bump 224 instead of the above-described two-time peeling. It is also possible to adopt a one-time peeling configuration in which the substrate is peeled after being fixed to the position connected to the substrate, and in this case, the shape shown in FIG. 2C is obtained.

(Embodiment 2)
In the second embodiment, a module (semiconductor module) in which a driving circuit on a panel is formed by a peeling technique will be described with reference to FIG.

  FIG. 3A shows a top view of the semiconductor module. The panel 300 is provided with a pixel portion 305 and driving circuits (a signal line driving circuit 307 and a scanning line driving circuit 306), and these are electrically connected to an external power source (not shown) provided outside. An FPC 308 for connection is attached to the panel 300 with an adhesive 309.

  In this embodiment mode, these driver circuits (the signal line driver circuit 307 and the scan line driver circuit 306) are formed by a separation technique, so that it is easy even when a panel is formed using a flexible substrate. Can be formed on the substrate.

  FIG. 3B is an enlarged view of a driver circuit (a signal line driver circuit 307 and a scan line driver circuit 306) formed over the panel. Here, a structure of a chip in which the element formation layer 312 is fixed on the auxiliary substrate 314 will be described in detail.

  As shown in FIG. 3B, an element formation layer 312 including a plurality of TFTs 311 is formed over a flexible auxiliary substrate 314 by a peeling technique. Note that a wiring 315 is formed in advance on the auxiliary substrate 314, and the peeled element formation layer 312 is electrically connected to the wiring 315 through the bump 313. Further, by attaching the solder ball 316 electrically connected to the wiring 315 to the panel 300, a wiring (not shown) on the panel 300 and a driving circuit can be electrically connected.

  An enlarged view of 323 in FIG. 3B is shown in FIG. A plurality of wirings included in the element formation layer 312 are drawn out by lead-out wirings 321 as shown in FIG. 3C, and bumps 313 formed in contact with the wirings 321 are provided via anisotropic conductive adhesive layers 317. The wiring 315 on the auxiliary substrate 314 is electrically connected.

  Here, as the material used for the anisotropic conductive adhesive layer 317, anisotropic conductive particles 325 in which metal particles such as Ag, Au, and Al are covered with an insulating coating, a reactive curable adhesive, and a thermosetting adhesive are used. And an adhesive 324 such as a photocurable adhesive such as an ultraviolet curable adhesive and various curable adhesives such as an anaerobic adhesive. In the anisotropic conductive adhesive layer 317, the bump 313 and the wiring 315 on the auxiliary substrate 314 are electrically connected with the anisotropic conductive particles 325 interposed therebetween.

  As described above, the drive circuit formed by adhering the chip formed by fixing the drive circuit on the flexible auxiliary substrate 314 to the panel 300 via the solder balls 316 has a substrate shape. Even when a physical force is applied by bending, it can respond to a flexible shape change and can be used without impairing its function.

  Further, even when a defect is found in one chip, only the defective chip needs to be replaced with a normal chip, so that the yield can be improved.

  Note that although the case where each of the signal line driver circuit 307 and the scan line driver circuit 306 is formed by attaching a plurality of semiconductor chips is described in this embodiment mode, the present invention is not limited thereto. Each may be formed of one chip.

(Embodiment 3)
In Embodiment Mode 3, a case where an integrated circuit (a controller 401, a CPU 402, a memory 403) formed on a flexible substrate by a peeling technique is attached to the back surface of the panel together with the flexible substrate will be described with reference to FIG. To do.

  4A shows a top view of the semiconductor module, and FIG. 4B shows a cross-sectional view of the semiconductor module. The panel 400 is provided with a pixel portion 405 and a driving circuit (a signal line driving circuit 407, a scanning line driving circuit 406), and these are electrically connected to an external power source (not shown) provided outside. An FPC 408 for connection is attached to the panel 400 with an adhesive 409.

  Further, a flexible substrate 412 on which an integrated circuit (a controller 401, a CPU 402, and a memory 403) is formed by a peeling technique (twice peeling) as shown in FIG. 413 is pasted.

  Note that these integrated circuits (the controller 401, the CPU 402, and the memory 403) are formed on a flexible substrate 412 by a peeling technique and have a flexible shape, and thus are attached to a substrate 411 that forms a panel. Becomes easier.

  FIG. 4C is an enlarged view of the pixel portion 405 and the CPU 402 in 410 of FIG. 4B.

  That is, on the panel 400, an element formation layer 425 that includes a TFT and elements and constitutes a pixel is fixed, and a pixel portion 405 is formed. Note that although not shown here, an element formation layer which forms a driver circuit is fixed to the same surface, and a driver circuit (a signal line driver circuit 407 and a scanning line driver circuit 406) is formed.

  In the pixel portion 405 shown here, since a liquid crystal element is formed, a substrate 414 including a counter electrode 417 is provided on the element formation layer 425 forming the pixel portion 405 with the liquid crystal 416 interposed therebetween. Yes.

  On the other hand, an integrated circuit 415 such as a CPU 402 formed on the flexible substrate 412 by a peeling technique (twice peeling) is formed on the opposite surface of the panel 400 (the surface where the pixel portion 405 is not formed). Has been. Note that a surface of the integrated circuit 415 from which the wiring is exposed is attached to the panel 400 with an adhesive 413. Examples of the material used for the adhesive 413 include a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and various curable adhesives such as an anaerobic adhesive.

  In this embodiment, the wiring of the integrated circuit 415 is electrically connected to the FPC 408 in 420 of FIG. 4B.

  Note that in this embodiment mode, an integrated circuit can be formed on the back surface of the panel and there is no need to provide an integrated circuit outside, so that space saving can be realized and the semiconductor device can be downsized. it can.

(Embodiment 4)
In the fourth embodiment, unlike the third embodiment, by attaching a chip formed by peeling the integrated circuit on the auxiliary substrate to the back surface of the substrate to which the element formation layer constituting the pixel is fixed, A module (semiconductor module) in which an integrated circuit is formed on the back surface of a substrate on which a pixel portion and a driver circuit are formed will be described with reference to FIG.

  5A shows a top view of the front surface of the semiconductor module, FIG. 5B shows a top view of the back surface, and FIG. 5C shows a cross-sectional view of the semiconductor module. Note that in this embodiment mode, an element formation layer can be easily formed over a flexible substrate by forming a panel using a flexible substrate having a flexible shape as illustrated in FIG. Since the merit of the fixation which can be formed can be utilized, it is more preferable.

  The panel 500 is provided with a pixel portion 505 and a driving circuit (a signal line driving circuit 507 and a scanning line driving circuit 506), and these, an external power source (not shown), and an external circuit (not shown). FPC 508 for electrically connecting the two is attached to panel 500 with adhesive 509.

  Further, a chip on which an integrated circuit 512 (controller 501, CPU 502, memory 503) is formed by a separation technique (two-time separation) is attached to the back surface of the panel 500 as shown in FIG.

  Note that these integrated circuits 512 (the controller 501, the CPU 502, and the memory 503) are fixed on a flexible auxiliary substrate and then attached to the panel 500. Therefore, the panel 500 is a flexible substrate, and the panel Even when the shape of 500 is curved and a physical force is applied, the shape itself can cope with a change in the shape of the flexible shape, so that it can be used without impairing its function.

  As shown in FIG. 5C, a pixel portion and a driver circuit formed on the front surface of the panel and an integrated circuit (controller 501, CPU 502, memory 503) formed on the back surface of the panel are electrically connected by an auxiliary wiring 513. Connected. Note that Au, Cu, Al, Al—Si, an Au alloy, or the like can be used as a material for forming the auxiliary wiring 513.

  In this embodiment mode, the FPC 508 is attached to the back surface of the panel with an adhesive 509 and is electrically connected to the integrated circuit 512 (controller 501, CPU 502, memory 503) attached to the back surface of the panel. Further, a wiring (not shown) formed on the back surface, a pixel portion 505 formed on the front surface via an auxiliary wiring 513, and a driving circuit (signal line driving circuit 507, scanning line driving circuit 506) are also electrically connected. Connected to.

  Note that in this embodiment mode, an integrated circuit can be formed on the back surface of the panel and there is no need to provide an integrated circuit outside, so that space saving can be realized and the semiconductor device can be downsized. it can.

(Embodiment 5)
In the fifth embodiment, the peeling technique (two-time peeling) used in the present invention will be described in detail with reference to FIGS.

  6A, a metal layer 601, a metal oxide layer 602, and an oxide layer 603 are sequentially stacked over a first substrate 600, and an element formation layer 604 including a plurality of TFTs and wirings is formed thereover. The formed state is shown.

  As the first substrate 600, a glass substrate, a quartz substrate, a plastic substrate, a ceramic substrate, a silicon substrate, a metal substrate, or a stainless steel substrate can be used. In this embodiment, the AN100 that is a glass substrate is used. To do.

  The materials used for the metal layer 601 formed on the first substrate 600 include W, Ti, Ta, Mo, Nd, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, Ir, and Pt. Or a single layer made of an alloy material or a compound material containing the element as a main component, or a laminate thereof, or a nitride thereof such as titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride. A single layer or a stacked layer thereof may be used. Note that the thickness of the metal layer 601 may be 10 nm to 200 nm, preferably 50 nm to 75 nm.

  Here, when the metal layer 601 is formed by a sputtering method, the first substrate 600 is fixed, and thus the film thickness in the vicinity of the peripheral portion of the first substrate 600 tends to be nonuniform. Therefore, it is preferable to remove only the peripheral edge portion by dry etching. At that time, an insulating film made of a silicon oxynitride film is formed between the substrate 600 and the metal layer 601 so that the first substrate 600 is not etched. It can also be formed to the extent.

  A metal oxide layer 602 and an oxide layer 603 are formed over the metal layer 601, but in this embodiment, after the oxide layer 603 is formed first, a part of the metal layer 601 is formed in a later step. A case where the metal oxide layer 602 is oxidized is described.

  That is, a layer made of tungsten (film thickness: 10 nm to 200 nm, preferably 50 nm to 75 nm) is formed as the metal layer 601 here, and the oxide layer 603, here a silicon oxide layer (film thickness 150 nm), without being exposed to the atmosphere. To 200 nm). It is desirable that the thickness of the oxide layer 603 be at least twice that of the metal layer 601. For example, the thickness of the silicon oxide film is preferably 150 nm to 200 nm by a sputtering method using a silicon oxide target.

  The element formation layer 604 formed over the oxide layer 603 includes a semiconductor device, a display device, or a light-emitting device including elements formed by appropriately combining TFTs (p-channel TFTs or n-channel TFTs). This refers to the layer to be formed. The TFT shown here includes an impurity region 606 and a channel formation region 607 formed in part of the semiconductor film over the base film 605, a gate insulating film 620, and a gate electrode 608, and is electrically connected by a wiring 609. ing. Furthermore, an electrode pad 610 that enables connection to the outside later is also formed.

  Further, when the element formation layer 604 is formed, a heat treatment for diffusing hydrogen contained in the material film containing hydrogen is performed after forming a material film (semiconductor film or metal film) containing at least hydrogen. This heat treatment may be performed at 420 ° C. or higher, and may be performed separately from the formation process of the element formation layer 604, or may be omitted. For example, if an amorphous silicon film containing hydrogen is formed as a material film containing hydrogen by a CVD method and then subjected to a heat treatment at 500 ° C. or higher for crystallization, a polysilicon film can be formed by heating and simultaneously hydrogen diffusion. It can be carried out.

  Note that by performing this heat treatment, a metal oxide layer 602 having a crystal structure is formed between the metal layer 601 and the oxide layer 603. Note that when the metal layer 601 and the oxide layer 603 are stacked, an amorphous metal oxide layer (tungsten oxide film) formed between about 2 nm to 5 nm between the metal film 601a and the silicon oxide film 602 is formed. Is also included in the metal oxide layer 602 because a crystal structure is formed by this heat treatment.

  In this embodiment mode, the case where the metal oxide layer 602 is formed in the step of forming part of the element formation layer is described; however, the present invention is not limited to this method, and the metal layer 601 is formed. After that, the metal oxide layer 602 may be formed and the oxide layer 603 may be formed.

  Next, as illustrated in FIG. 6B, an organic resin layer 611 is formed over the element formation layer 604. As a material used for the organic resin layer 611, an organic material soluble in water or alcohols is used, and this is formed by applying and curing the entire surface. The composition of the organic material may be any material such as epoxy, acrylate, or silicon. Specifically, a water-soluble resin (manufactured by Toagosei Co., Ltd .: VL-WSHL10) (film thickness 30 μm) is applied by spin coating, exposure is performed for 2 minutes to temporarily cure, and then UV light is applied from the back surface 2 The organic resin layer 611 is formed by performing exposure for 5 minutes and exposure for a total of 12.5 minutes for 10 minutes from the surface.

  Note that in order to facilitate subsequent peeling, treatment for partially reducing the adhesion in the metal oxide layer 602 is performed. The treatment for partially decreasing the adhesion is performed by partially irradiating the metal layer 601 or the oxide layer 603 with laser light along the periphery of the region to be peeled, or on the periphery of the region to be peeled. A process of damaging the inside of the oxide layer 603 or a part of the interface by locally applying a pressure along the outside. Specifically, a hard needle may be pressed vertically with a diamond pen or the like to move under a load. Preferably, a scriber device is used, the pushing amount is 0.1 mm to 2 mm, and the pressure is applied. In this way, it is important to create a part where peeling phenomenon is likely to occur before peeling, that is, a trigger, and by performing a pretreatment that selectively (partially) decreases adhesion, peeling is performed. Defects are eliminated and the yield is improved.

  Next, the second substrate 613 can be attached to the organic resin layer 611 through the first adhesive layer 612 by forming the first adhesive layer 612. Note that as a material for forming the first adhesive layer 611, a known material that can weaken adhesiveness by performing a predetermined treatment in a later step can be used. A case where a photosensitive double-sided tape whose adhesive strength is reduced by light irradiation in a later step will be described.

  Further, the second adhesive layer 614 is similarly formed on the exposed surface of the first substrate 600, and the third substrate 615 is attached through the second adhesive layer 614. Note that as a material for forming the second adhesive layer 614, a double-sided tape is used as in the case of the first adhesive layer 612. The third substrate 615 attached here prevents the first substrate 601 from being damaged in a subsequent peeling step. As the second substrate 613 and the third substrate 615, a substrate having higher rigidity than the first substrate 600, for example, a quartz substrate or a semiconductor substrate is preferably used.

  Next, the first substrate 600 provided with the metal layer 601 is peeled off by physical means from the region side where the adhesion is partially reduced. In the case of this embodiment, the metal layer 601 and the substrate 600 are applied to the metal oxide layer 602 with a relatively small force (for example, a human hand, the wind pressure of a gas blown from a nozzle, an ultrasonic wave, etc.). Can be peeled off. Specifically, separation can be performed in the tungsten oxide film, at the interface between the tungsten oxide film and the silicon oxide film, or at the interface between the tungsten oxide film and the tungsten film. Thus, the element formation layer 604 formed over the oxide layer 603 can be separated from the first substrate 600. The state at the time of peeling is shown in FIG.

  In addition, a part of the metal oxide layer 602 remains on the surface exposed by peeling, and this causes a decrease in adhesion when the exposed surface is bonded to a substrate or the like in a later step. Therefore, it is preferable to perform a process of removing a part of the metal oxide layer 602 remaining on the exposed surface. In order to remove them, an alkaline aqueous solution such as an aqueous ammonia solution or an acidic aqueous solution can be used. In addition, the subsequent steps may be performed at a temperature (430 ° C.) or less at which part of the metal oxide layer 602 is easily peeled off.

  Next, a third adhesive layer 616 is formed, and the fourth substrate 617 and the oxide layer 603 (and the element formation layer 604) are bonded to each other through the third adhesive layer 616 (FIG. 7A). . Note that the oxide layer 603 (and the element formation layer 604) bonded by the third bonding layer 616 is more preferable than the adhesion between the second substrate 613 bonded by the first bonding layer 612 and the organic resin layer 611. It is important that the adhesion between the substrate and the fourth substrate 617 is higher.

  As the fourth substrate 617, a glass substrate, a quartz substrate, a ceramic substrate, a flexible substrate (plastic substrate), a silicon substrate, a metal substrate, a stainless steel substrate, or the like can be used; however, in this embodiment mode, a flexible substrate is used. It is preferable to use a substrate having a property. Note that a wiring for obtaining electrical connection with the attached element formation layer needs to be formed over the fourth substrate 617. Note that, as a method of forming a wiring, a known method used in the case of forming a wiring on a substrate (also referred to as a die) to which a chip is attached in the field of LSI can be used, and thus description thereof is omitted.

  Furthermore, since the element formation layer in the present invention is a thin film having a thickness of 50 μm or less, the fourth substrate 617 has a fourth surface so as not to cause element breakdown, connection breakdown, or the like included in the element formation layer 604 due to unevenness on the surface of the fourth substrate 617. A planarization film may be formed on the surface of the substrate 617.

  The material used for the third adhesive layer 616 includes various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive. Is mentioned. More preferably, it is more preferable to provide high thermal conductivity by including powder or filler made of silver, nickel, aluminum, aluminum nitride.

  Next, the adhesive force of the double-sided tape used for the first adhesive layer 612 is reduced by irradiating ultraviolet rays from the second substrate 613 side, and the second substrate 613 is separated from the element formation layer 604 ( FIG. 7 (B)). Further, by washing the exposed surface with water, the first adhesive layer 612 and the organic resin layer 611 can be dissolved and removed (FIG. 7C).

  Note that in the case where the element formation layer 604 is a pixel portion and a driver circuit, the element formation layer 604 is formed as illustrated in FIG. (However, in the case of the pixel portion, after obtaining the shape of FIG. 7C, an element electrically connected to the TFT is formed.) On the other hand, the element formation layer 604 includes an integrated circuit (controller, In the case of a CPU or a memory), the separation technique described in this embodiment mode can be used. That is, as the fourth substrate 617 illustrated in FIG. 7A, a flexible auxiliary substrate on which wiring is formed in advance may be used, and a substrate on which a pixel portion and a driver circuit are formed through bumps. What is necessary is just to affix on the back surface.

  As described above, Embodiments 1 to 4 can be performed by using the peeling technique described in this embodiment.

(Embodiment 6)
In Embodiment Mode 6, a method for simultaneously manufacturing an n-channel TFT and a p-channel TFT over the same substrate will be described with reference to FIGS.

  As the substrate 800, a quartz substrate, a semiconductor substrate, a ceramic substrate, a metal substrate, or the like can be used. In this embodiment, a glass substrate (# 1737) is used.

Next, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%) formed from a source gas SiH ₄ and N ₂ O by a plasma CVD method as a base insulating film 804 on the substrate 800 is formed. N = 7%, H = 2%) are laminated to a thickness of 100 nm, and further have an amorphous structure with a film forming temperature of 300 ° C. and a film forming gas of SiH ₄ by plasma CVD without being released to the atmosphere. A semiconductor layer (here, an amorphous silicon layer) is formed with a thickness of 54 nm. This amorphous silicon layer contains hydrogen, and can be peeled off in the oxide layer or at the interface by physical means by diffusing hydrogen by a subsequent heat treatment.

  Next, a nickel acetate salt solution containing 10 ppm of nickel in terms of weight is applied with a spinner. Instead of coating, a method of spreading nickel element over the entire surface by sputtering may be used. Next, heat treatment is performed for crystallization, so that a semiconductor film having a crystal structure (here, a polysilicon layer) is formed. Here, after heat treatment for dehydrogenation (500 ° C., 1 hour), heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a silicon film having a crystal structure. The heat treatment for dehydrogenation (500 ° C., 1 hour) also serves as a heat treatment for diffusing hydrogen contained in the amorphous silicon film to the interface between the W film and the silicon oxide film. Although a crystallization technique using nickel as a metal element for promoting crystallization of silicon is used here, other known crystallization techniques such as a solid phase growth method and a laser crystallization method may be used.

Next, after removing the oxide film on the surface of the silicon film having a crystal structure with dilute hydrofluoric acid or the like, laser light (XeCl: wavelength 308 nm) for increasing the crystallization rate and repairing defects left in the crystal grains Irradiation is performed in air or in an oxygen atmosphere. As the laser light, excimer laser light having a wavelength of 400 nm or less, and second harmonic and third harmonic of YAG laser are used. Here, a pulsed laser beam having a repetition frequency of about 10 to 1000 Hz is used, the laser beam is condensed to 100 to 500 mJ / cm ² by an optical system, and irradiated with an overlap rate of 90 to 95%, and the silicon film surface May be scanned. Here, laser light irradiation is performed in the atmosphere at a repetition frequency of 30 Hz and an energy density of 470 mJ / cm ² .

Note that since the reaction is performed in the air or in an oxygen atmosphere, an oxide film is formed on the surface by laser light irradiation. Although an example using a pulsed laser is shown here, a continuous wave laser may be used, and in order to obtain a crystal with a large grain size when crystallizing an amorphous semiconductor film, continuous wave is possible. It is preferable to apply a second to fourth harmonic of the fundamental wave using a solid-state laser. Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied. In the case of using a continuous wave laser, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method of emitting harmonics by putting a YVO ₄ crystal and a nonlinear optical element in a resonator. Preferably, the laser beam is shaped into a rectangular or elliptical shape on the irradiation surface by an optical system, and the object to be processed is irradiated. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.

  Next, in addition to the oxide film formed by the laser beam irradiation, the surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total thickness of 1 to 5 nm. In this embodiment mode, a barrier layer is formed using ozone water. However, a method of oxidizing a surface of a semiconductor film having a crystal structure by irradiation with ultraviolet rays in an oxygen atmosphere or a surface of a semiconductor film having a crystal structure by oxygen plasma treatment A barrier layer may be formed by depositing an oxide film having a thickness of about 1 to 10 nm by a method such as oxidation, plasma CVD, sputtering, or vapor deposition. Further, the oxide film formed by laser light irradiation may be removed before forming the barrier layer.

Next, an amorphous silicon film containing an argon element serving as a gettering site is formed with a thickness of 10 to 400 nm, here 100 nm, over the barrier layer by a sputtering method. In this embodiment, the amorphous silicon film containing an argon element is formed in an atmosphere containing argon using a silicon target. In the case where an amorphous silicon film containing an argon element is formed using a plasma CVD method, the film formation conditions are a monosilane / argon flow rate ratio (SiH ₄ : Ar) of 1:99 and a film formation pressure of 6.665 Pa. (0.05 Torr), RF power density is 0.087 W / cm ^2, and film forming temperature is 350 ° C.

  After that, heat treatment is performed for 3 minutes in a furnace heated to 650 ° C., and gettering is performed to reduce the nickel concentration in the semiconductor film having a crystal structure. A lamp annealing apparatus may be used instead of the furnace.

  Next, the amorphous silicon film containing an argon element which is a gettering site is selectively removed using the barrier layer as an etching stopper, and then the barrier layer is selectively removed with dilute hydrofluoric acid. Note that during gettering, nickel tends to move to a region with a high oxygen concentration, and thus it is desirable to remove the barrier layer made of an oxide film after gettering.

  Next, after forming a thin oxide film with ozone water on the surface of the obtained silicon film having a crystal structure (also called a polysilicon film), a mask made of resist is formed and etched into a desired shape to form islands. The separated semiconductor layers 805 and 806 are formed. After the semiconductor layers 805 and 806 are formed, the resist mask is removed (FIG. 8A).

  Next, the oxide film is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the silicon film is washed, and then an insulating film containing silicon as a main component to be the gate insulating film 807 is formed. In this embodiment, a silicon oxide film is formed with a thickness of 115 nm by a plasma CVD method (FIG. 8B).

  Further, a first conductive film 808 with a thickness of 20 to 100 nm and a second conductive film 809 with a thickness of 100 to 400 nm are stacked over the gate insulating film 807. In this embodiment, a tantalum nitride film with a thickness of 50 nm and a tungsten film with a thickness of 370 nm are sequentially stacked over the gate insulating film 807.

  As a conductive material for forming the first conductive film 808 and the second conductive film 809, an element selected from Ta, W, Ti, Mo, Al, Cu, or an alloy material or compound containing the element as a main component Form with material. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive film 808 and the second conductive film 809. Further, the present invention is not limited to the two-layer structure. For example, a three-layer structure in which a 50 nm-thickness tungsten film, a 500 nm-thickness aluminum and silicon alloy (Al-Si) film, and a 30 nm-thickness titanium nitride film are sequentially stacked. Also good. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient.

Next, as shown in FIG. 8C, resist masks 810 and 811 are formed by a light exposure process, and a first etching process is performed to form gate electrodes and wirings. The first etching process is performed under the first and second etching conditions. For etching, an ICP (Inductively Coupled Plasma) etching method may be used. Using the ICP etching method, the film is formed into a desired taper shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) Can be etched. As an etching _{gas, Cl 2, BCl 3, SiCl} 4, CCl 4 chlorine gas or CF ₄ to the typified like, SF _6, fluorine-based gas NF ₃ and the like typified, or O ₂ as appropriate Can be used.

In this embodiment, 150 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil-type electrode area size (here, the quartz disk provided with the coil) is a disk having a diameter of 25 cm. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered. Under the first etching conditions, the etching rate with respect to W is 200.39 nm / min, the etching rate with respect to TaN is 80.32 nm / min, and the selection ratio of W with respect to TaN is about 2.5. Further, the taper angle of W is about 26 ° under this first etching condition. Thereafter, the resist masks 810 and 811 are not removed and the second etching conditions are changed, CF ₄ and Cl ₂ are used as etching gases, and the respective gas flow ratios are set to 30/30 (sccm). Etching was performed for about 30 seconds by applying 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa to generate plasma. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching conditions is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.

  In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of the tapered portion may be 15 to 45 °.

  Thus, the first shape conductive layers 812 and 813 (the first conductive layers 812a and 813a and the second conductive layers 812b and 813b) formed of the first conductive layer and the second conductive layer by the first etching treatment. Form. The insulating film 807 to be a gate insulating film is etched by about 10 to 20 nm to be a gate insulating film 811 in which a region not covered with the first shape conductive layers 812 and 813 is thinned.

Next, as shown in FIG. 8D, a second etching process is performed without removing the resist mask. Here, SF ₆ , Cl _2, and O ₂ are used as etching gases, the gas flow ratios are 24/12/24 (sccm), and 700 W of RF ( 13.56 MHz) Electric power is applied to generate plasma, and etching is performed for 25 seconds. 10 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. In the second etching process, the etching rate with respect to W is 227.3 nm / min, the etching rate with respect to TaN is 32.1 nm / min, the selection ratio of W with respect to TaN is 7.1, and the gate insulating film 811 is formed. The etching rate with respect to SiON is 33.7 nm / min, and the selection ratio of W with respect to SiON is 6.83. As described above, when SF ₆ is used as the etching gas, the selectivity with respect to the gate insulating film 811 is high, so that film loss can be suppressed. The thickness reduction of the gate insulating film 811 in this embodiment is about 8 nm.

  By this second etching process, the taper angle of W can be set to 70 °. By this second etching process, second conductive layers 814b and 815b are formed. At this time, the first conductive layer is hardly etched and becomes the first conductive layers 814a and 815a. Note that the first conductive layers 814a and 815a have substantially the same size as the first conductive layers 812a and 813a. Actually, the width of the first conductive layer may be about 0.3 μm, that is, the entire line width may be receded by about 0.6 μm as compared with that before the second etching process, but the size is hardly changed.

In place of the two-layer structure, a three-layer structure in which a 50-nm-thick tungsten film, a 500-nm-thick aluminum and silicon alloy (Al-Si) film, and a 30-nm-thick titanium nitride film are sequentially stacked, As the first etching condition in the first etching process, BCl ₃ , Cl _2, and O ₂ are used as source gases, the respective gas flow ratios are set to 65/10/5 (sccm), and the substrate side (sample stage). ) 300W RF (13.56MHz) power is applied to the coil-type electrode at a pressure of 1.2Pa and 450W RF (13.56MHz) power is generated to generate plasma and perform etching for 117 seconds. Ebayoku, as the second etching conditions of the first etching treatment, CF ₄ and using a Cl ₂ and O _2, a ratio of respective gas flow rates is 25/25/10 (scc ), And 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma. The second etching process uses BCl ₃ and Cl ₂ , the gas flow ratio is 20/60 (sccm), and the substrate side (sample stage) is 100 W. RF (13.56 MHz) power is applied, 600 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa, plasma is generated, and etching is performed.

  Next, after removing the resist mask 810, a resist mask 818 is formed as shown in FIG. 9A, and a first doping process is performed. The doping process may be performed by ion doping or ion implantation. Note that the mask 818 is a mask for protecting a semiconductor film forming a p-channel TFT and a peripheral region thereof.

The conditions of the ion doping method in the first doping process are that the dose is 1.5 × 10 ¹⁵ atoms / cm ² , the acceleration voltage is 60 to 100 keV, and phosphorus (P) is doped. Note that phosphorus (P) or arsenic (As) can be typically used as the impurity element imparting n-type conductivity. Here, impurity regions are formed in a self-aligned manner in the respective semiconductor layers using the second conductive layers 814b and 815b as a mask. Of course, it is not added to the region covered with the mask 818. Thus, a first impurity region 819 and a second impurity region 820 are formed. An impurity element imparting n-type conductivity is added to the first impurity region 819 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Here, a region having the same concentration range as the first impurity region is also referred to as an n ⁺ region.

The second impurity region 820 is formed by the first conductive layer 815a at a lower concentration than the first impurity region 819 and imparts n-type in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ^3. Impurity elements to be added are added. Note that the second impurity region 820 has a concentration gradient in which the impurity concentration increases toward the end of the tapered portion because doping is performed by passing the portion of the first conductive layer 815a having a tapered shape. ing. Here, a region having the same concentration range as the second impurity region 820 is also referred to as an n ⁻ region.

  Next, after removing the resist mask 818, a new resist mask 821 is formed, and a second doping process is performed as shown in FIG. 9B.

  Through the second doping process, a third impurity region 822 and a fourth impurity region 823 to which an impurity element imparting p-type conductivity is added are formed in the semiconductor layer for forming the p-channel TFT.

Further, an impurity element imparting p-type conductivity is added to the third impurity region 822 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Note that the third impurity region 822 region in the preceding step phosphorus (P) has been added ^- is a (n region), the concentration thereof 1.5-3 times the impurity element imparting p-type The conductivity type is p-type. Here, a region having the same concentration range as the third impurity region 822 is also referred to as a p ⁺ region.

The fourth impurity region 823 is formed in a region overlapping with the tapered portion of the first conductive layer 815a and imparts p-type in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3. Impurity elements are added. Here, a region having the same concentration range as the fourth impurity region 823 is also referred to as a p ⁻ region.

  Through the above steps, an impurity region having n-type or p-type conductivity is formed in each semiconductor layer. The conductive layers 814 and 815 become TFT gate electrodes.

  Next, a step of activating the impurity element added to each semiconductor layer is performed. This activation step may be a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination thereof. By different methods.

  Next, a first insulating film 824 is formed. Note that in this embodiment, a 50-nm-thick silicon nitride oxide film formed by a plasma CVD method is used. Needless to say, this insulating film is not limited to a silicon nitride oxide film, and an insulating film such as silicon nitride, silicon oxynitride, or silicon oxide may be used as a single layer or a stacked structure.

  Next, a second insulating film 825 is formed over the first insulating film 824. As the second insulating film 825 formed here, an insulating film such as silicon nitride, silicon nitride oxide, or silicon oxide can be used; in this embodiment, a film thickness of 50 nm formed by a plasma CVD method is used. This silicon nitride film is used.

  Next, after a second insulating film 825 made of a silicon nitride film is formed, heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) is performed to perform a step of hydrogenating the semiconductor layer (FIG. 9C )). This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the second insulating film 825. As other means for hydrogenation, heat treatment at about 350 ° C. or plasma hydrogenation (using hydrogen excited by plasma) can be performed in a hydrogen atmosphere.

  Next, a third insulating film 826 made of an organic insulating material is formed over the second insulating film 825. Here, an acrylic resin film having a thickness of 1.6 μm is formed. Next, contact holes 827 that reach the impurity regions are formed.

  Note that since the acrylic resin used in this embodiment mode is photosensitive acrylic, a desired position can be opened by exposure and development. Further, a part of the first insulating film 824 and the second insulating film 825 is etched by a dry etching method, and the second insulating film 825 is etched using the first insulating film 824 as an etching stopper. Then, the first insulating film 824 is etched. As a result, a contact hole 827 is obtained.

  Note that although the case where a contact hole is formed after the third insulating film 826 formed using an organic resin film is described in this embodiment mode, the second insulating film 826 is formed before the third insulating film 826 is formed. The insulating film 825 and the first insulating film 824 can be dry-etched. Note that in this case, it is preferable that the substrate be heat-treated (300 to 550 ° C. for 1 to 12 hours) after the etching process and before the third insulating film 826 is formed.

  Then, as shown in FIG. 9D, by forming the wiring 828 using Al, Ti, Mo, W, or the like, the n-channel TFT 901 and the p-channel TFT 902 can be formed over the same substrate.

(Embodiment 7)
In this Embodiment 7, the process in the case of mass-producing a semiconductor device with the peeling technique in this invention is demonstrated using FIG.

  FIG. 10A shows a process for manufacturing an element formation layer fixed on a large flexible substrate, and FIG. 10B shows a process performed on the large flexible substrate. It shows about a process.

  Since the element formation layer manufacturing steps (a to e) in FIG. 10A are the same as those described in Embodiment Mode 5, detailed description of materials, processing conditions, and the like is omitted.

  That is, in the process a, the element formation layer 930 including the TFT 932 is formed on the first substrate 931, and in the process b, the organic resin layer 933 is formed on the TFT 932. Next, in step c, the second substrate 935 is attached via the adhesive layer 934, and then in step d, the first substrate 931 is peeled off. Note that, when the state obtained in the step d includes a plurality of circuits, the circuit is divided in the step e.

  In FIG. 10B, a flexible substrate 900 is wound around a roll 901, and processing is performed while sequentially moving the flexible substrate 900 to the right in the figure by a feed roll 911.

  First, in the first step, the pressure-sensitive adhesive film 902 is attached to the flexible substrate 900 by the pressure-bonding rolls (903, 904). When the pressure-sensitive adhesive film 902 is formed, the element formation layer formed in the step e of FIG.

  Next, in the third step, the adhesive force of the adhesive layer 934 is reduced by irradiating the flexible substrate with the element formation layer attached thereto in the UV irradiation chamber 905, and the peeling means 906 performs the second step. After the substrate 935 is removed, the upper surface of the substrate is washed in the washing chamber 907 and the organic resin layer 933 is removed.

  Further, in this embodiment, a protective film is formed as the fourth step. Note that here, an organic material such as an ultraviolet curable resin is used, and coating is performed using the coating unit 908. Thereafter, the protective film can be formed by irradiating UV in the UV irradiation chamber 909 and curing the organic material.

  Finally, in the fifth step, each of the fixed element forming layers is divided by the cutter 910.

  As described above, by sticking a plurality of element formation layers on a large flexible substrate, continuous processing is possible and mass production is possible, improving throughput and reducing production costs. Can be achieved.

(Embodiment 8)
In the eighth embodiment, the function and configuration when a CPU is formed by a peeling technique will be described with reference to FIG.

  First, when the operation code is input to the data bus interface 1101, the analysis circuit 1103 (also referred to as instruction decoder) decodes the code, and the signal is input to the control signal generation circuit 1104 (CPU Timing Control). When a signal is input, a control signal is output from the control signal generation circuit 1104 to the arithmetic circuit 1109 (hereinafter referred to as ALU) and the storage circuit 1110 (hereinafter referred to as Register).

  The control signal generation circuit 1104 includes an ALU controller 1105 that controls the ALU 1109 (hereinafter referred to as ACON), a circuit 1106 that controls the Register 1110 (hereinafter referred to as RCON), and a timing controller 1107 that controls timing (hereinafter referred to as TCON). And an interrupt controller 1108 (hereinafter referred to as ICON) for controlling interrupts.

  On the other hand, when the operand is input to the data bus interface 1101, it is output to the ALU 1109 and the Register 1110. Then, processing (for example, a memory read cycle, a memory write cycle, an I / O read cycle, an I / O write cycle, or the like) based on a control signal input from the control signal generation circuit 1104 is performed.

  The Register 1110 includes a general-purpose register, a stack pointer (SP), a program counter (PC), and the like.

  An address controller 1111 (hereinafter referred to as ADRC) outputs a 16-bit address.

  Note that the configuration of the CPU described in this embodiment is an example of a CPU included in the semiconductor chip of the present invention, and does not limit the configuration of the present invention. Therefore, the semiconductor chip of the present invention can be completed using a known CPU having a structure other than that shown in this embodiment mode.

Further, FIG. 12 shows a timing chart in the operation of the CPU having the configuration described in FIG. As an input signal to the CPU shown in FIG. 12, there is CLK (clock signal), which is a signal inputted as System Clock in FIG. In addition, RESET (reset signal) input to the control signal generation circuit 1104 in FIG. 11 and signals (D _{0 to} D ₇ ) (opcode and operand) input to the data bus interface 1101 are input. In addition, MREQ (memory request), RD (read signal), and WD (write signal) are output as output signals from the CPU. In this case, the operating frequency is 5 MHz.

  Next, FIGS. 13 and 14 show photographs of the CPU described in this embodiment. FIG. 13A is a photograph showing a state in which a plurality of CPUs are formed on the same substrate. Note that the CPU shown here can be formed by using the method described in Embodiment Mode 5. In addition, since the fourth substrate 617 illustrated in FIG. 7 is formed using a flexible substrate, a curved shape illustrated in FIG. FIG. 13B illustrates a state in which a plurality of CPUs formed over the same substrate in FIG. 13A are separated into one and an FPC is connected.

  Further, FIG. 14A is a photograph showing a part of the CPU, and FIG. 14B is a photograph showing a state in which the CPU formed according to the present invention is incorporated in a part of the audio device. is there. That is, the CPU formed according to the present invention can be driven in the same manner as a conventional CPU.

(Embodiment 9)
In the ninth embodiment, as shown in the first to fourth embodiments, various electronic devices can be completed by incorporating integrated circuits formed by using a peeling technique in various portions of the module.

  These electronic devices include video cameras, digital cameras, head-mounted displays, (goggles type displays), car navigation systems, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, portable game consoles or electronic A device provided with a display device capable of reproducing a recording medium such as a book and displaying an image thereof. Specific examples of these electronic devices are shown in FIGS.

  FIG. 15A illustrates a display device, which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. Note that the module of the display portion 2003 includes an integrated circuit formed using a separation technique. The display device includes all information display devices such as a personal computer, a TV broadcast reception, and an advertisement display.

  FIG. 15B shows a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. Note that the module of the display portion 2203 includes an integrated circuit formed using a separation technique.

  FIG. 15C illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. Note that the module of the display portion 2302 includes an integrated circuit formed using a peeling technique.

  FIG. 15D shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet.

  FIG. 15E illustrates a portable book (electronic book) which includes a main body 2501, a display portion 2502, a storage medium 2503, operation switches 2504, an antenna 2505, and the like. Note that the module of the display portion 2502 includes an integrated circuit formed using a peeling technique.

  FIG. 15F illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control reception portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and an eyepiece. Part 2610 and the like. Note that the module of the display portion 2602 includes an integrated circuit formed using a peeling technique.

  Here, FIG. 15G shows a cellular phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. Note that the module of the display portion 2703 includes an integrated circuit formed using a separation technique.

  As described above, the application range of the module including an integrated circuit manufactured according to the present invention is extremely wide and can be applied to application products in various fields.

2A and 2B illustrate a structure of the present invention shown in Embodiment 1. FIG. 2A and 2B illustrate a structure of the present invention shown in Embodiment 1. FIG. FIG. 6 illustrates a configuration of the present invention shown in a second embodiment. FIG. 6 illustrates a configuration of the present invention shown in a third embodiment. FIG. 6 illustrates a configuration of the present invention shown in a fourth embodiment. The figure explaining the peeling method. The figure explaining the peeling method. 10A and 10B illustrate a manufacturing process of a TFT. 10A and 10B illustrate a manufacturing process of a TFT. The figure explaining a mass-production process. The figure explaining the structure of CPU. The timing chart of CPU. The photograph of CPU formed by this invention. The photograph of CPU formed by this invention. 8A and 8B each illustrate an electronic device formed using the present invention.

Claims (5)

A metal layer, a metal oxide layer, and an oxide layer are sequentially formed on the substrate,
Forming an element formation layer including a thin film transistor on the oxide layer;
The substrate and the element formation layer are separated at the interface between the metal oxide and the oxide layer, or at the interface between the metal oxide layer and the metal layer, in the metal oxide layer,
Adhering the element forming layer on a flexible substrate made of plastic,
A method for manufacturing a semiconductor device, comprising: attaching a flexible substrate on a flexible printed wiring board having wiring; and electrically connecting the wiring and the element formation layer. A metal layer, a metal oxide layer, and an oxide layer are sequentially formed on the substrate,
Forming an element formation layer including a thin film transistor on the oxide layer;
The substrate and the element after performing a process of partially irradiating a laser beam along the periphery of the region to be peeled or a process of locally applying pressure from the outside along the periphery of the region to be peeled The forming layer is peeled off in the metal oxide layer, at the interface between the metal oxide and the oxide layer, or at the interface between the metal oxide layer and the metal layer,
Adhering the element forming layer on a flexible substrate made of plastic,
A method for manufacturing a semiconductor device, comprising: attaching a flexible substrate on a flexible printed wiring board having wiring; and electrically connecting the wiring and the element formation layer. In claim 1 or 2,
A method for manufacturing a semiconductor device, wherein the flexible substrate is attached to the flexible printed wiring board through bumps. In any one of Claims 1 thru | or 3,
The metal layer is a layer made of tungsten,
The metal oxide layer is a layer made of tungsten oxide,
The method for manufacturing a semiconductor device, wherein the oxide layer is a layer made of silicon oxide. In any one of Claims 1 thru | or 4,
A method for manufacturing a semiconductor device, wherein the element formation layer has a thickness of 50 μm or less.