JP4267394B2 - Peeling method and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for peeling a layer to be peeled, and particularly to a method for peeling a layer to be peeled including various elements. In addition, the present invention relates to a semiconductor device having a circuit including a thin film transistor (hereinafter referred to as TFT) in which a peeled layer to be peeled is attached to a substrate and transferred, and a manufacturing method thereof. For example, the present invention relates to an electro-optical device typified by a liquid crystal module, a light-emitting device typified by an EL module, and an electronic apparatus in which such a device is mounted as a component.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.

  Various applications using such an image display device are expected, but the use for portable devices is attracting attention. Currently, many glass substrates and quartz substrates are used, but they have the disadvantage of being easily broken and heavy. Further, in mass production, it is difficult to increase the size of a glass substrate or a quartz substrate, which is not suitable. Therefore, attempts have been made to form TFT elements on a flexible substrate, typically a flexible plastic film.

  However, since the heat resistance of the plastic film is low, the maximum temperature of the process has to be lowered, and as a result, TFTs having better electrical characteristics cannot be formed when formed on a glass substrate. Therefore, a high-performance liquid crystal display device or light emitting element using a plastic film has not been realized.

  Further, a peeling method has already been proposed in which a layer to be peeled existing on a substrate via a separation layer is peeled from the substrate. For example, in the techniques described in Patent Document 1 and Patent Document 2, a separation layer made of amorphous silicon (or polysilicon) is provided, and the substrate is passed through the substrate and irradiated with laser light to be included in the amorphous silicon. By releasing hydrogen, voids are generated and the substrate is separated. In addition, using this technique, Patent Document 3 also describes that a layer to be peeled (referred to as a layer to be transferred in the publication) is attached to a plastic film to complete a liquid crystal display device.

However, in the above method, it is essential to use a substrate with high translucency, which gives a sufficient energy to pass through the substrate and to release hydrogen contained in amorphous silicon. There is a problem that light irradiation is required and damages the peeled layer. In addition, in the above method, when an element is manufactured on the separation layer, if high-temperature heat treatment or the like is performed in the element manufacturing process, hydrogen contained in the separation layer is diffused and reduced, and the separation layer is irradiated with laser light. However, there is a risk that peeling will not be performed sufficiently. Therefore, in order to maintain the amount of hydrogen contained in the separation layer, there is a problem that the process after the formation of the separation layer is limited. In addition, the above publication describes that a light shielding layer or a reflective layer is provided in order to prevent damage to the layer to be peeled, but in that case, it is difficult to manufacture a transmissive liquid crystal display device. In addition, with the above method, it is difficult to peel off a layer to be peeled having a large area.
Japanese Patent Laid-Open No. 10-125929 Japanese Patent Laid-Open No. 10-125931 Japanese Patent Laid-Open No. 10-125930

  The present invention has been made in view of the above-mentioned problems, and the present invention provides a peeling method that does not damage the peeled layer, and not only peels off the peeled layer having a small area, but also provides a large area. It is an object to make it possible to peel the layer to be peeled over the entire surface.

  Another object of the present invention is to provide a peeling method that does not limit the heat treatment temperature, the type of the substrate, and the like in the formation of the layer to be peeled.

  It is another object of the present invention to provide a lightweight semiconductor device and a manufacturing method thereof by attaching a layer to be peeled to various base materials. In particular, a light-weight semiconductor device and a manufacturing method thereof are provided by attaching various elements such as TFT (a thin film diode, a photoelectric conversion element made of a silicon PIN junction or a silicon resistance element) to a flexible film. Is an issue.

  While many experiments and studies have been made by the present inventors, a metal layer provided on a substrate, an oxide layer provided in contact with the metal layer, and an insulating film provided on the oxide layer, When a layer containing hydrogen, typically an amorphous silicon film containing hydrogen, is formed on the insulating film and then subjected to heat treatment at 410 ° C. or higher, no process abnormality such as film peeling (peeling) occurs. Can be easily separated at the interface of the oxide layer (the interface between the oxide layer and the metal layer) easily by applying physical means, typically mechanical force (for example, peeling by human hand) A peeling method was found.

  That is, the bonding force between the metal layer and the oxide layer is strong enough to withstand thermal energy, while the heat treatment causes hydrogen to diffuse and react between the metal layer and the oxide layer. The film stress of the oxide layer or the amorphous silicon film changes, and the mechanical energy between the metal layer and the oxide layer becomes weak. As a result, peeling is likely to occur when a mechanical force is applied. Note that the semiconductor film is not limited to an amorphous silicon film, and may be a semiconductor film that can be formed by a PCVD method, for example, a germanium film, an alloy film of silicon and germanium, or an amorphous silicon film containing phosphorus or boron.

  Further, when the oxide layer is formed on the metal layer, the surface of the metal layer is oxidized, so that the adhesion between the metal layer and the oxide layer is improved. And it is thought that the adhesiveness of a metal layer and an oxide layer falls by diffusing hydrogen contained in the layer containing hydrogen at 410 degreeC or more, and reacting (for example, reduction reaction) with the oxidized metal layer surface. In addition, since the layer containing hydrogen changes to the tensile stress side when heated, distortion occurs at the interface between the metal layer and the oxide layer, and peeling easily occurs.

Note that in this specification, the internal stress of a film (referred to as film stress) means that when an arbitrary cross section is considered inside a film formed on a substrate, one side of the cross section exerts on the other side. This is the force per unit cross-sectional area. It can be said that the internal stress is more or less necessarily present in a thin film formed by vacuum deposition, sputtering, vapor phase growth or the like. The value reaches a maximum of 10 ⁹ N / m ² . The internal stress value varies depending on the material of the thin film, the substance of the substrate, the formation conditions of the thin film, and the like. Further, the internal stress value also changes by performing heat treatment.

  Also, the state in which the force acting on the other party is pulled through the unit cross-sectional area perpendicular to the substrate surface is called the tensile state, the internal stress at that time is called the tensile stress, and the state in the pushing direction is called the compressed state. Internal stress is called compressive stress.

Configuration 1 of the invention relating to the peeling method disclosed in the present specification is:
A peeling method for peeling a layer to be peeled from a substrate,
A step of sequentially forming a metal layer on the substrate, an oxide layer in contact with the metal layer, an insulating film, and a semiconductor film containing hydrogen and having an amorphous structure on the insulating film;
Performing a heat treatment for diffusing hydrogen;
After the support is bonded to the layer to be peeled including the oxide layer, the insulating film, and the semiconductor film, the layer to be peeled bonded to the support is removed from the substrate provided with the metal layer by physical means. A peeling method characterized by comprising a peeling step.

Moreover, the structure 2 of this invention regarding another peeling method is as follows.
A peeling method for peeling a layer to be peeled from a substrate,
A step of sequentially forming a metal layer on the substrate, an oxide layer in contact with the metal layer, an insulating film, and a semiconductor film containing hydrogen and having an amorphous structure on the insulating film;
Performing a heat treatment for diffusing hydrogen;
Forming a TFT having the semiconductor film as an active layer and an element connected to the TFT;
After a support is bonded to a layer to be peeled including the oxide layer, the insulating film, the TFT, and the element, the layer to be peeled bonded to the support is physically separated from the substrate provided with the metal layer. And a step of peeling by means.

In the above structure, the order of the step of performing heat treatment for diffusing hydrogen and the step of forming a TFT using the semiconductor film as an active layer and an element connected to the TFT is not particularly limited. In the case where heat treatment at 410 ° C. or higher is performed in the step of forming the TFT having the semiconductor film as an active layer and an element connected to the TFT, it is not necessary to separately perform heat treatment for diffusing hydrogen.

  In each of the above structures, the heat treatment is characterized in that the temperature at which hydrogen in the film is released or diffused, that is, 410 ° C. or higher.

  In each of the above structures, the metal layer is an element selected from Ti, Ta, W, Mo, Cr, Nd, Fe, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, Ir, and Pt. Or a single layer made of an alloy material or a compound material containing the element as a main component, or a laminate of these metals or a mixture thereof.

In this specification, the physical means is a means recognized not by chemistry but by physics, and specifically by mechanical means or mechanical means having a process that can be applied to the laws of mechanics. It means a means for changing some mechanical energy (mechanical energy).

However, in any of the above-described configurations, it is necessary to make the bonding force between the oxide layer and the metal layer smaller than the bonding force with the support when peeling by physical means.

Further, instead of the semiconductor film containing hydrogen, a metal film containing hydrogen may be formed.
A peeling method for peeling a layer to be peeled from a substrate,
A step of sequentially forming a metal layer, an oxide layer in contact with the metal layer, an insulating film, and a metal layer containing hydrogen over the insulating film on the substrate;
Performing a heat treatment for diffusing hydrogen;
Forming a TFT and an element connected to the TFT;
After a support is bonded to a layer to be peeled including the oxide layer, the insulating film, the TFT, and the element, the layer to be peeled bonded to the support is physically separated from the substrate provided with the metal layer. And a step of peeling by means.

In addition, a metal layer containing hydrogen may be used as the metal layer.
A peeling method for peeling a layer to be peeled from a substrate,
A step of sequentially stacking a metal layer containing hydrogen on the substrate, an oxide layer in contact with the metal layer, an insulating film, and a semiconductor film having an amorphous structure on the insulating film;
Performing a heat treatment for diffusing hydrogen;
Forming a TFT having the semiconductor film as an active layer and an element connected to the TFT;
After a support is bonded to a layer to be peeled including the oxide layer, the insulating film, the TFT, and the element, the layer to be peeled bonded to the support is physically separated from the substrate provided with the metal layer. And a step of peeling by means.

  In each of the above structures, the oxide layer is a silicon oxide film formed by sputtering.

  In each of the above structures, the insulating film is a silicon oxide film, a silicon oxynitride film, or a stacked layer thereof.

  In each of the above structures, the thickness of the oxide layer is greater than the thickness of the metal layer.

  In each of the above structures, the element provided over the insulating film is a light-emitting element, a semiconductor element, or a liquid crystal element.

Further, as the metal layer containing hydrogen, a W film or a Ni film using a CVD method (such as a remote plasma method) can be used. For example, silicon that becomes the nucleus of the W film is deposited with SiH ₄ gas, or the surface of the silicon oxide film (or silicon nitride film) is exposed to rare gas plasma to break the Si—O bond (or Si—N bond). When W is deposited and then WF ₆ / H ₂ gas is allowed to flow, a W film can be deposited by a reduction reaction. A film forming method for depositing a W film by a reduction reaction is a kind of CVD method also called a blanket W method. Further, as the metal layer containing hydrogen, an AB ₂ type hydrogen storage alloy containing hydrogen (where A is Ti or Zr, B is Ni, V, Cr, Co, Fe, Mn), or AB ₅ type hydrogen storage alloy. (However, M may be used as A, and Ni, Co, Mn, Al, and Mo may be used as B).

  In each of the above structures, the metal layer may be provided with another layer between the substrate and the metal layer, for example, an insulating layer. However, in order to simplify the process, the metal layer is in contact with the substrate. It is preferable to form.

  In the present invention, not only a light-transmitting substrate but any substrate, for example, a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or a metal substrate can be used, and a layer to be peeled provided on the substrate Can be peeled off.

  Note that in this specification, the transfer body is to be bonded to the layer to be peeled after being peeled, and is not particularly limited, and may be a base material having any composition such as plastic, glass, metal, ceramics and the like. Further, in the present specification, the support is for adhering to the layer to be peeled when peeling by physical means, and is not particularly limited, and any composition such as plastic, glass, metal, ceramics, etc. A substrate may be used. Further, the shape of the transfer body and the shape of the support are not particularly limited, and may be a flat surface, a curved surface, a bendable shape, or a film shape. If weight reduction is the top priority, a film-like plastic substrate such as polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), nylon, polyetherether Plastic substrates such as ketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), and polyimide are preferable.

  In each of the above structures related to the method for manufacturing the semiconductor device, when a liquid crystal display device is manufactured, the support body may be bonded to the layer to be peeled using the support body as a counter substrate and a sealing material as an adhesive. In this case, the element provided in the peeling layer has a pixel electrode, and a liquid crystal material is filled between the pixel electrode and the counter substrate.

  In each of the above structures related to the method for manufacturing a semiconductor device, when a light-emitting device typified by a light-emitting device having an EL element is manufactured, an organic compound layer such as moisture or oxygen is externally used as a support. It is preferable to completely block the light emitting element from the outside so as to prevent a substance that promotes deterioration from entering. Further, if weight reduction is the top priority, a film-like plastic substrate is preferable. However, since the effect of preventing the entry of substances that promote deterioration of the organic compound layer such as moisture and oxygen from the outside is weak, for example, a support If the first insulating film, the second insulating film, and the third insulating film are provided on the top to sufficiently prevent a substance that promotes deterioration of the organic compound layer such as moisture and oxygen from entering from the outside. Good. However, the second insulating film (stress relieving film) sandwiched between the first insulating film (barrier film) and the third insulating film (barrier film) includes the first insulating film and the first insulating film. The film stress is made smaller than that of the third insulating film.

In the case of manufacturing a light-emitting device typified by a light-emitting device having an EL element, not only the support but also the transfer body similarly includes the first insulating film, the second insulating film, and the third insulating film. It is preferable to prevent the invasion of substances that promote the deterioration of the organic compound layer such as moisture and oxygen from the outside.

Since the present invention peels from the substrate by physical means, the reliability of the element can be improved without damage to the semiconductor layer.

  Further, according to the present invention, not only the layer to be peeled having a small area but also the layer to be peeled having a large area can be peeled over the entire surface with a high yield.

  In addition, the present invention is a process suitable for mass production because it can be easily peeled off by physical means, for example, peeled off by a human hand. Further, in the case where a manufacturing apparatus for peeling off a layer to be peeled is manufactured in mass production, a large manufacturing apparatus can be manufactured at low cost.

The best mode for carrying out the invention will be described below.

    In FIG. 1A, 10 is a substrate, 11 is a nitride layer or metal layer, 12 is an oxide layer, and 13 is a layer to be peeled.

  In FIG. 1A, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used as the substrate 10. Further, a silicon substrate, a metal substrate, or a stainless steel substrate may be used.

  First, as shown in FIG. 1A, a nitride layer or a metal layer 11 is formed on a substrate 10. A typical example of the nitride layer or the metal layer 11 is an element selected from W, Ti, Ta, Mo, Nd, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, Ir, and Pt, or Single layer made of an alloy material or compound material containing the element as a main component, or a laminate thereof, or a nitride thereof, for example, a single layer made of titanium nitride, tungsten nitride, tantalum nitride, molybdenum nitride, or these A stacked layer may be used. The film thickness of the nitride layer or metal layer 11 is 10 nm to 200 nm, preferably 50 nm to 75 nm.

  Further, since the substrate is fixed by the sputtering method, the film thickness in the vicinity of the peripheral edge of the substrate tends to be non-uniform. For this reason, it is preferable to remove only the peripheral portion by dry etching. At this time, an insulating film made of a silicon oxynitride film is formed between the substrate 10 and the nitride layer or the metal layer 11 so that the substrate is not etched. You may form.

Next, an oxide layer 12 is formed on the nitride layer or metal layer 11. As the oxide layer 12, a layer made of silicon oxide, silicon oxynitride, or a metal oxide material may be formed by a sputtering method. The film thickness of the oxide layer 12 is desirably about twice or more that of the nitride layer or the metal layer 11. Here, the silicon oxide film is formed to a thickness of 150 nm to 200 nm by a sputtering method using a silicon oxide target. The stress of the silicon oxide film obtained by the sputtering method was measured to be −3.97 × 10 ⁸ (Dyne / cm ² ), and the hydrogen concentration by SIMS measurement was 4 × 10 ²⁰ atoms / cm ³ . is there. However, these measured values are measured values with a single film and not with stacked layers.

  Next, a layer to be peeled 13 is formed on the oxide layer 12. When forming the layer 13 to be peeled, a material film (semiconductor film or metal film) containing at least hydrogen is formed, and then heat treatment for diffusing hydrogen contained in the material film containing hydrogen is performed. This heat treatment may be performed at 410 ° C. or higher, and may be performed separately from the formation process of the layer to be peeled 13, or may be combined to omit the process. For example, when an amorphous silicon film containing hydrogen is used as a material film containing hydrogen and a polysilicon film is formed by heating, if a heat treatment at 500 ° C. or higher is performed for crystallization, the polysilicon film is formed and hydrogen is simultaneously formed. Diffusion can be performed. Note that the layer 13 to be peeled is formed by various elements typified by TFTs (thin film diodes, photoelectric conversion elements made of silicon PIN junctions, silicon resistance elements, and sensor elements (typically pressure-sensitive fingerprint sensors using polysilicon). ).

  Next, a second substrate 15 serving as a support for fixing the layer to be peeled 13 is attached with the first adhesive 14. (FIG. 1B) Note that the second substrate 15 is preferably a substrate having higher rigidity than the first substrate 10. As the first adhesive 14, an adhesive or a double-sided tape may be used.

  Next, the substrate 10 provided with the nitride layer or the metal layer 11 is peeled off by physical means. (FIG. 1C) Since the film stress of the oxide layer 12 and the film stress of the nitride layer or the metal layer 11 are different, the oxide layer 12 can be peeled off with a relatively small force. In this example, it is assumed that the mechanical strength of the peelable layer 13 is sufficient. However, when the mechanical strength of the peelable layer 13 is insufficient, the peelable layer 13 is fixed. It is preferable to peel off after attaching a support (not shown).

  Thus, the layer to be peeled 13 formed on the oxide layer 12 can be separated from the substrate 10. The state after peeling is shown in FIG.

  Next, a third substrate to be a transfer body is attached with the second adhesive 16 to the peeled layer 13 to be peeled off. (Figure 1 (E))

  Next, the second substrate 15 is peeled off by removing or peeling off the first adhesive material 14. (Fig. 1 (F))

  Next, the EL layer 20 is formed, and the fourth substrate 18 serving as the sealing material is sealed with the third adhesive 19. Note that the fourth substrate 18 is not particularly required if the third adhesive 19 is a material that can sufficiently block substances (moisture and oxygen) that promote the deterioration of the organic compound layer. Here, an example of manufacturing a light-emitting device using an EL element has been described; however, there is no particular limitation, and various semiconductor devices can be completed.

  In the case of manufacturing a liquid crystal display device, the support may be attached to the layer to be peeled using the support as a counter substrate and a sealant as an adhesive. In this case, an element provided in the layer to be peeled has a pixel electrode, and a liquid crystal material is filled between the pixel electrode and the counter substrate. The order in which the liquid crystal display device is manufactured is not particularly limited, and a counter substrate as a support may be attached, and after injecting liquid crystal, the substrate may be peeled off and a plastic substrate as a transfer member may be attached. After the pixel electrode is formed, the substrate may be peeled off, a plastic substrate as a first transfer body may be attached, and then a counter substrate as a second transfer body may be attached.

The order of manufacturing the light-emitting device is not particularly limited, and after forming the light-emitting element, a plastic substrate as a support may be attached, the substrate may be peeled off, and a plastic substrate as a transfer member may be attached. After the light emitting element is formed, the substrate may be peeled off and a plastic substrate as a first transfer body may be attached, and then a plastic substrate as a second transfer body may be attached.

  In the present invention, the heat treatment at 410 ° C. or higher causes hydrogen to diffuse at the interface between the nitride layer or the metal layer 11 and the oxide layer 12 to cause a reaction, and further the film stress of the oxide layer 12 and the nitride It is important to change the film stress of the layer or metal layer 11 or all the stress stacked on the substrate. However, since peeling occurs when the film stress is changed too much, it is preferable to carefully perform film formation and other processes.

  Further, even when heat treatment at 500 ° C. or higher or laser light irradiation is performed, film peeling (peeling) does not occur in the process. Then, it can be easily separated cleanly within the oxide layer or at the interface by physical means.

In the experiments by the present inventors, even when the metal layer 11 is a tungsten film 10 nm and the oxide layer 12 is a silicon oxide film 200 nm by a sputtering method, the peeling can be confirmed by the peeling method of the present invention. Even if the oxide layer 12 is a silicon oxide film 100 nm by the sputtering method, peeling can be confirmed by the peeling method of the present invention. Even when the metal layer 11 is a tungsten film of 50 nm and the oxide layer 12 is a silicon oxide film of 400 nm by a sputtering method, peeling can be confirmed by the peeling method of the present invention.

  Further, in the experiments by the present inventors, it has been confirmed that the nitride layer 11 is also peeled off by the peeling method of the present invention even when a tungsten nitride film or a titanium nitride film is used.

  Moreover, the following experiment was conducted.

(Experiment 1)
After forming an amorphous silicon film containing hydrogen on a glass substrate by a PCVD method (film formation temperature 300 ° C., film formation gas SiH ₄ ), heat treatment under different conditions was performed, and each stress was measured. is there. The heat treatment conditions are 350 ° C. for 1 hour, 400 ° C. for 1 hour, 410 ° C. for 1 hour, 430 ° C. for 1 hour, and 450 ° C. for 1 hour.

Regardless of the conditions, the stress value immediately after film formation (−8 × 10 ⁹ (Dyne / cm ² ) to −6 × 10 ⁹ (Dyne / cm ² )) is changed to the tensile stress side by heat treatment. It can be read from FIG. The stress value after the heat treatment is in the range of −6 × 10 ⁹ (Dyne / cm ² ) to 2 × 10 ⁹ (Dyne / cm ² ).

In addition, a tungsten film, a silicon oxide film formed by sputtering, a base insulating film, and an amorphous silicon film containing hydrogen by PCVD are sequentially stacked on a glass substrate and subjected to heat treatment under the above conditions, respectively, and a peeling experiment using a tape. As a result, peeling was confirmed by heat treatment at 410 ° C. or higher.

(Experiment 2)
Here, when the hydrogen concentration of the amorphous silicon film containing hydrogen obtained by the PCVD method under the same conditions as in Experiment 1 was measured by FT-IR, Si-H was 1.06 × 10 ²² (atoms / cm ³ ), Si—H ₂ was 8.34 × 10 ¹⁹ (atoms / cm ³ ), and the hydrogen concentration in the composition ratio was calculated to be 21.5%. Further, when the hydrogen concentration was calculated in the same manner while changing the film formation conditions of the PCVD method, the hydrogen concentration in the composition ratio was 16.4%, 17.1%, and 19.0%.

Further, a tungsten film, a silicon oxide film by sputtering, a base insulating film, and an amorphous silicon film containing hydrogen by PCVD (a film having a hydrogen concentration of 16.4% to 21.5% in a composition ratio) are formed over a glass substrate. When the layers were sequentially formed, heat treatment was performed at 410 ° C. for 1 hour, and a peeling experiment using a tape was performed, peeling was confirmed under all conditions. On the other hand, the amorphous silicon film obtained by the sputtering method instead of the PCVD method could not be peeled off in a peeling experiment using a tape.

Further, a tungsten film on a glass substrate, a silicon oxide film by sputtering, a base insulating film, a silicon nitride film containing hydrogen by PCVD (stress value is −2.4 × 10 ⁸ (Dyne / cm ² )), Si—H Are 8.9 × 10 ²¹ (atoms / cm ³ ) and N—H is 6.6 × 10 ²¹ (atoms / cm ³ ) in this order, and heat treatment is performed at 410 ° C. for 1 hour. As a result of peeling experiments using tape, peeling was confirmed. Therefore, the present invention is not particularly limited to the amorphous silicon film, and similar results can be obtained as long as the film contains hydrogen.

(Experiment 3)
Here, a W film (100 nm) and a silicon oxide film (100 nm) formed on a silicon wafer are stacked and then heat treated (350 ° C. for 1 hour, 400 ° C. for 1 hour, 410 ° C. for 1 hour, 430 FIG. 3 shows the result of measuring the stress change for each treatment after etching the silicon oxide film for 1 hour at 450 ° C. and 1 hour at 450 ° C.).

  The film formation conditions for the W film were a sputtering method using a tungsten target, a film formation pressure of 0.2 Pa, a film formation power of 3 kW, and an argon flow rate = 20 sccm.

  The silicon oxide film is formed by using an RF sputtering apparatus, using a silicon oxide target (diameter: 30.5 cm), flowing a heated argon gas at a flow rate of 30 sccm, and heating the substrate temperature. 300 ° C., film forming pressure 0.4 Pa, film forming power 3 kW, argon flow rate / oxygen flow rate = 10 sccm / 30 sccm.

  It can be seen from FIG. 3 that the stress changes greatly after the formation of the silicon oxide film and after the etching of the silicon oxide film.

As a comparison, the stress change in the lamination of the W film (100 nm) and the silicon oxide film (20 nm) formed on the silicon wafer was measured, but almost no change was observed even when all the above treatments were performed. From this, it is clear that the stress after the formation of the silicon oxide film depends on the thickness of the silicon oxide film. When the thickness of the silicon oxide film is large, the stress changes greatly, so that the interface between the W film and the silicon oxide film is likely to be distorted, and a peeling phenomenon occurs. Therefore, in the present invention, the film thickness of the silicon oxide film and the film thickness ratio of the W film and the silicon oxide film are important, and at least the film thickness of the silicon oxide film is larger than the W film, and more preferably 2 Double or more.

(Experiment 4)
In addition, a tungsten film, a silicon oxide film by sputtering, a base insulating film, and an amorphous silicon film containing hydrogen by PCVD are sequentially stacked on a glass substrate, and after heat treatment at 410 ° C. or higher for diffusing hydrogen, etching is performed. When the tape test was conducted after removing the amorphous silicon film by the above, peeling was confirmed. Further, when a tungsten film, a silicon oxide film formed by sputtering, and a base insulating film were sequentially stacked on a glass substrate and subjected to a heat treatment at 410 ° C. or higher, a tape test was performed, and peeling was not possible. Therefore, it is considered that the presence of the amorphous silicon film, which is a layer formed on the base film, is caused by the peeling phenomenon.

The result of these experiments, that is, whether or not peeling is possible is determined at 410 ° C. In addition, since the change in stress is not seen so much, the inventors are not only concerned with the peeling of the laminated film, but the amorphous silicon film and the hydrogen contained in the film are also caused by the peeling phenomenon. Is found.

  FIG. 11 is a graph showing the relationship between the density of hydrogen desorbed from the amorphous silicon film formed on the glass substrate and the substrate surface temperature (° C.) by temperature programmed desorption gas analysis (TDS). FIG. 11 shows that hydrogen desorbed from the amorphous silicon film tends to increase as the substrate temperature rises. From the obtained data, the temperature reaching the peak of the desorbed hydrogen amount is 382 ° C. to 411 ° C. I found out. Therefore, FIG. 11 shows data related to the above experimental results (experimental results in which whether or not peeling is possible at 410 ° C. is determined), and the heating temperature sufficient to easily cause the peeling phenomenon is about 410 ° C. or higher. It can be said that.

  The inventors have also found that the film thickness ratio between the W film and the silicon oxide film is also caused by the peeling phenomenon. Further, the inventors consider that the combination of the material of the metal layer or nitride layer and the material of the oxide layer, and the interface state such as adhesion are also caused by the peeling phenomenon.

  The present invention having the above-described configuration will be described in more detail with the following examples.

  An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT) of a driver circuit provided around the pixel portion on the same substrate will be described in detail. Note that an example of manufacturing an active matrix substrate for manufacturing a reflective liquid crystal display device is shown here, but the invention is not particularly limited. If an arrangement of TFTs and a material of a pixel electrode are appropriately changed, a transmissive liquid crystal Needless to say, a display device can be manufactured, and a light-emitting device having a light-emitting layer containing an organic compound can also be manufactured.

A glass substrate (# 1737) was used as the substrate. First, a silicon oxynitride layer was formed to a thickness of 100 nm on the substrate by PCVD.

  Next, a tungsten layer was formed as a metal layer with a thickness of 50 nm by a sputtering method, and a silicon oxide layer was formed as an oxide layer with a thickness of 200 nm by a sputtering method continuously without being released to the atmosphere. The silicon oxide layer was formed by using an RF sputtering apparatus, using a silicon oxide target (diameter 30.5 cm), flowing argon gas heated to heat the substrate at a flow rate of 30 sccm, a substrate temperature of 300 ° C., The film forming pressure was 0.4 Pa, the film forming power was 3 kW, and the argon flow rate / oxygen flow rate was 10 sccm / 30 sccm.

Next, the tungsten layer is removed from the peripheral edge or the end surface of the substrate by O ₂ ashing.

Next, a silicon oxynitride film produced from a plasma CVD method using a film formation temperature of 300 ° C. and source gases SiH ₄ and N ₂ O (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) A semiconductor layer (here, an amorphous silicon layer having an amorphous structure with a film-forming temperature of 300 ° C. and a film-forming gas of SiH ₄ continuously by a plasma CVD method without being released to the atmosphere. ) With a thickness of 54 nm. This amorphous silicon layer contains hydrogen, and can be peeled off in the oxide layer or at the interface by physical means by diffusing hydrogen by a subsequent heat treatment.

  Next, a nickel acetate salt solution containing 10 ppm of nickel by weight is applied by a spinner. Instead of coating, a method of spreading nickel element over the entire surface by sputtering may be used. Next, heat treatment is performed for crystallization, so that a semiconductor film having a crystal structure (here, a polysilicon layer) is formed. Here, after heat treatment for dehydrogenation (500 ° C., 1 hour), heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a silicon film having a crystal structure. The heat treatment for dehydrogenation (500 ° C., 1 hour) also serves as heat treatment for diffusing hydrogen contained in the amorphous silicon layer to the interface between the W film and the silicon oxide layer. Although a crystallization technique using nickel as a metal element for promoting crystallization of silicon is used here, other known crystallization techniques such as a solid phase growth method and a laser crystallization method may be used.

Next, after removing the oxide film on the surface of the silicon film having a crystal structure with dilute hydrofluoric acid or the like, irradiation with laser light (XeCl: wavelength 308 nm) for increasing the crystallization rate and repairing defects left in the crystal grains In the air or in an oxygen atmosphere. As the laser light, excimer laser light having a wavelength of 400 nm or less, and second harmonic and third harmonic of a YAG laser are used. Here, a pulsed laser beam having a repetition frequency of about 10 to 1000 Hz is used, and the laser beam is condensed to 100 to 500 mJ / cm ² by an optical system, and irradiated with an overlap rate of 90 to 95%. May be scanned. Here, laser light irradiation was performed in the air at a repetition frequency of 30 Hz and an energy density of 470 mJ / cm ² . Note that since the reaction is performed in the air or in an oxygen atmosphere, an oxide film is formed on the surface by laser light irradiation. Although an example using a pulsed laser is shown here, a continuous wave laser may be used, and in order to obtain a crystal with a large grain size when crystallizing an amorphous semiconductor film, continuous wave is possible. It is preferable to use a solid-state laser and apply the second to fourth harmonics of the fundamental wave. Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied. In the case of using a continuous wave laser, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method of emitting harmonics by putting a YVO ₄ crystal and a nonlinear optical element in a resonator. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system, and irradiated to the object to be processed. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.

Next, in addition to the oxide film formed by the laser light irradiation, the surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total thickness of 1 to 5 nm. In this embodiment, ozone water is used to form the barrier layer. However, the surface of the semiconductor film having a crystal structure is oxidized by a method of oxidizing the surface of the semiconductor film having a crystal structure by irradiation with ultraviolet rays in an oxygen atmosphere, or by oxygen plasma treatment. The barrier layer may be formed by depositing an oxide film of about 1 to 10 nm by an oxidation method, a plasma CVD method, a sputtering method, an evaporation method, or the like. Further, the oxide film formed by laser light irradiation may be removed before forming the barrier layer.

Next, an amorphous silicon film containing an argon element serving as a gettering site is formed with a thickness of 10 nm to 400 nm, here 100 nm, over the barrier layer by a sputtering method. In this embodiment, the amorphous silicon film containing an argon element is formed in an atmosphere containing argon using a silicon target. In the case where an amorphous silicon film containing an argon element is formed using a plasma CVD method, the film formation conditions are a monosilane / argon flow rate ratio (SiH ₄ : Ar) of 1:99 and a film formation pressure of 6.665 Pa. (0.05 Torr), RF power density is 0.087 W / cm ^2, and film forming temperature is 350 ° C.

After that, heat treatment is performed for 3 minutes in a furnace heated to 650 ° C., and gettering is performed to reduce the nickel concentration in the semiconductor film having a crystal structure. A lamp annealing apparatus may be used instead of the furnace.

Next, the amorphous silicon film containing an argon element as a gettering site is selectively removed using the barrier layer as an etching stopper, and then the barrier layer is selectively removed with dilute hydrofluoric acid. Note that during gettering, nickel tends to move to a region with a high oxygen concentration, and thus it is desirable to remove the barrier layer made of an oxide film after gettering.

  Next, after forming a thin oxide film with ozone water on the surface of the obtained silicon film having a crystal structure (also called a polysilicon film), a mask made of resist is formed and etched into a desired shape to form islands. A separated semiconductor layer is formed. After the semiconductor layer is formed, the resist mask is removed.

  Through the above steps, a nitride layer or a metal layer 101, an oxide layer 102, and a base insulating film 103 are formed over the substrate 100 to obtain a semiconductor film having a crystal structure, and then etched into a desired shape to form an island shape. The separated semiconductor layers 104 to 108 can be formed.

  Next, the oxide film is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the silicon film is washed, and then an insulating film containing silicon as a main component and serving as the gate insulating film 109 is formed. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) is formed to a thickness of 115 nm by plasma CVD.

  Next, as illustrated in FIG. 4A, a first conductive film 110 a with a thickness of 20 to 100 nm and a second conductive film 110 b with a thickness of 100 to 400 nm are stacked over the gate insulating film 109. In this embodiment, a tantalum nitride film with a thickness of 50 nm and a tungsten film with a thickness of 370 nm are sequentially stacked on the gate insulating film 109.

  The conductive material for forming the first conductive film and the second conductive film is an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Form. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive film and the second conductive film. Further, the present invention is not limited to the two-layer structure. For example, a three-layer structure in which a 50 nm-thickness tungsten film, a 500 nm-thickness aluminum and silicon alloy (Al-Si) film, and a 30 nm-thickness titanium nitride film are sequentially stacked. Also good. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient.

Next, as shown in FIG. 4B, resist masks 112 to 117 are formed by a light exposure process, and a first etching process is performed to form gate electrodes and wirings. The first etching process is performed under the first and second etching conditions. For etching, an ICP (Inductively Coupled Plasma) etching method may be used. Using the ICP etching method, the film is formed into a desired taper shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) Can be etched. As an etching _{gas, Cl 2, BCl 3, SiCl} 4, CCl 4 chlorine gas or CF ₄ to the typified like, SF _6, fluorine-based gas NF ₃ and the like typified, or O ₂ as appropriate Can be used.

In this embodiment, 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The electrode area size on the substrate side is 12.5 cm × 12.5 cm, and the coil-type electrode area size (here, the quartz disk provided with the coil) is a disk having a diameter of 25 cm. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered. Under the first etching conditions, the etching rate with respect to W is 200.39 nm / min, the etching rate with respect to TaN is 80.32 nm / min, and the selection ratio of W with respect to TaN is about 2.5. Further, the taper angle of W is about 26 ° under this first etching condition. Thereafter, the masks 112 to 117 made of resist are changed to the second etching conditions without removing them, CF ₄ and Cl ₂ are used as etching gases, and the respective gas flow ratios are set to 30/30 (sccm). Etching was performed for about 30 seconds by applying 500 W RF (13.56 MHz) power to the coil electrode at a pressure of 1 Pa to generate plasma. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching conditions is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.

  In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of the tapered portion may be 15 to 45 °.

  Thus, the first shape conductive layers 119 to 123 (first conductive layers 119 a to 123 a and second conductive layers 119 b to 123 b) composed of the first conductive layer and the second conductive layer by the first etching process. Form. The insulating film 109 to be a gate insulating film is etched by about 10 to 20 nm to become a gate insulating film 118 in which a region not covered with the first shape conductive layers 119 to 123 is thinned.

Next, a second etching process is performed without removing the resist mask. Here, SF ₆ , Cl _2, and O ₂ are used as the etching gas, the gas flow ratios are 24/12/24 (sccm), and a 700 W RF ( 13.56 MHz) Electric power was applied to generate plasma, and etching was performed for 25 seconds. 10 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. In the second etching process, the etching rate with respect to W is 227.3 nm / min, the etching rate with respect to TaN is 32.1 nm / min, the selection ratio of W with respect to TaN is 7.1, and the SiON that is the insulating film 118 The etching rate with respect to is 33.7 nm / min, and the selective ratio of W to SiON is 6.83. Thus, when SF ₆ is used as the etching gas, the selectivity with respect to the insulating film 118 is high, so that the film loss can be suppressed. In this embodiment, the insulating film 118 is reduced only by about 8 nm.

  By this second etching process, the taper angle of W became 70 °. The second conductive layers 126b to 131b are formed by this second etching process. On the other hand, the first conductive layer is hardly etched and becomes the first conductive layers 126a to 131a. Note that the first conductive layers 126a to 131a are approximately the same size as the first conductive layers 119a to 124a. Actually, the width of the first conductive layer may be about 0.3 μm, that is, the entire line width may be receded by about 0.6 μm as compared with that before the second etching process, but the size is hardly changed.

In place of the two-layer structure, a three-layer structure in which a 50-nm-thick tungsten film, a 500-nm-thick aluminum and silicon alloy (Al-Si) film, and a 30-nm-thick titanium nitride film are sequentially stacked, As the first etching condition in the first etching process, BCl ₃ , Cl _2, and O ₂ are used as source gases, the respective gas flow ratios are set to 65/10/5 (sccm), and the substrate side (sample stage). ) 300W RF (13.56MHz) power is applied to the coil-type electrode at a pressure of 1.2Pa and 450W RF (13.56MHz) power is generated to generate plasma and perform etching for 117 seconds. Ebayoku, as the second etching conditions of the first etching treatment, CF ₄ and using a Cl ₂ and O _2, a ratio of respective gas flow rates is 25/25/10 (scc ) And 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma. The second etching process uses BCl ₃ and Cl ₂ , each gas flow ratio is 20/60 (sccm), and the substrate side (sample stage) is 100 W. RF (13.56 MHz) power is applied, 600 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa, plasma is generated, and etching is performed.

Next, after removing the resist mask, a first doping process is performed to obtain the state of FIG. The doping process may be performed by ion doping or ion implantation. The conditions of the ion doping method are a dose amount of 1.5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60 to 100 keV. Typically, phosphorus (P) or arsenic (As) is used as the impurity element imparting n-type conductivity. In this case, the first conductive layer and the second conductive layers 126 to 130 serve as a mask for the impurity element imparting n-type, and the first impurity regions 132 to 136 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the first impurity regions 132 to 136 in a concentration range of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . Here, a region having the same concentration range as the first impurity region is also referred to as an n ⁻ region.

  In this embodiment, the first doping process is performed after removing the resist mask, but the first doping process may be performed without removing the resist mask.

  Next, as shown in FIG. 5A, masks 137 to 139 made of resist are formed, and a second doping process is performed. The mask 137 is a mask for protecting the channel formation region of the semiconductor layer for forming the p-channel TFT of the driver circuit and its peripheral region, and the mask 138 is for the semiconductor layer for forming one of the n-channel TFT of the driver circuit. The mask 139 is a mask for protecting the channel formation region and its peripheral region, and the mask 139 is a mask for protecting the channel formation region of the semiconductor layer forming the TFT of the pixel portion, its peripheral region, and the region serving as a storage capacitor.

The condition of the ion doping method in the second doping process is that the dose is 1.5 × 10 ¹⁵ atoms / cm ² , the acceleration voltage is 60 to 100 keV, and phosphorus (P) is doped. Here, impurity regions are formed in a self-aligned manner in each semiconductor layer using the second conductive layers 126b to 128b as masks. Of course, it is not added to the region covered with the masks 137 to 139. Thus, second impurity regions 140 to 142 and a third impurity region 144 are formed. An impurity element imparting n-type conductivity is added to the second impurity regions 140 to 142 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Here, a region having the same concentration range as the second impurity region is also referred to as an n ⁺ region.

The third impurity region is formed by the first conductive layer at a lower concentration than the second impurity region and imparts n-type in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ^3. Will be added. Note that the third impurity region has a concentration gradient in which the impurity concentration increases toward the end portion of the tapered portion because doping is performed by passing the portion of the first conductive layer having a tapered shape. . Here, a region having the same concentration range as the third impurity region is also referred to as an n ⁻ region. In addition, the regions covered with the masks 138 and 139 become the first impurity regions 146 and 147 without being doped with the impurity element in the second doping process.

  Next, after removing the resist masks 137 to 139, new resist masks 148 to 150 are formed, and a third doping process is performed as shown in FIG. 5B.

In the driver circuit, a fourth impurity region 151 in which an impurity element imparting p-type conductivity is added to the semiconductor layer forming the p-channel TFT and the semiconductor layer forming the storage capacitor by the third doping process. , 152 and fifth impurity regions 153, 154 are formed.

In addition, an impurity element imparting p-type conductivity is added to the fourth impurity regions 151 and 152 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ . Incidentally, in the fourth impurity regions 151 and 152 regions in the preceding step phosphorus (P) has been added ^- is a (n region), the 1.5 the concentration of the impurity element imparting p-type Three times as much is added and the conductivity type is p-type. Here, a region having the same concentration range as the fourth impurity region is also referred to as a p ⁺ region.

The fifth impurity regions 153 and 154 are formed in a region overlapping with the tapered portion of the second conductive layer 127a, and have a p-type in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3. An impurity element to be added is added. Here, a region having the same concentration range as the fifth impurity region is also referred to as a p ⁻ region.

  Through the above steps, impurity regions having n-type or p-type conductivity are formed in each semiconductor layer. The conductive layers 126 to 129 become TFT gate electrodes. The conductive layer 130 serves as one electrode forming a storage capacitor in the pixel portion. Further, the conductive layer 131 forms a source wiring in the pixel portion.

  Next, an insulating film (not shown) that covers substantially the entire surface is formed. In this example, a 50 nm-thickness silicon oxide film was formed by plasma CVD. Of course, this insulating film is not limited to the silicon oxide film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

  Next, a step of activating the impurity element added to each semiconductor layer is performed. This activation process is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination thereof. By different methods.

  Further, in this embodiment, an example in which an insulating film is formed before the activation is shown, but an insulating film may be formed after the activation.

  Next, a first interlayer insulating film 155 made of a silicon nitride film is formed and subjected to a heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) to hydrogenate the semiconductor layer. (FIG. 5C) This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the first interlayer insulating film 155. The semiconductor layer can be hydrogenated regardless of the presence of an insulating film (not shown) made of a silicon oxide film. However, in this embodiment, since the material containing aluminum as a main component is used as the second conductive layer, it is important to set the heat treatment conditions that the second conductive layer can withstand in the hydrogenation step. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

  Next, a second interlayer insulating film 156 made of an organic insulating material is formed on the first interlayer insulating film 155. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed. Next, a contact hole reaching the source wiring 131, a contact hole reaching the conductive layers 129 and 130, and a contact hole reaching each impurity region are formed. In this embodiment, a plurality of etching processes are sequentially performed. In this embodiment, after etching the second interlayer insulating film using the first interlayer insulating film as an etching stopper, the first interlayer insulating film is etched using the insulating film (not shown) as an etching stopper, and then the insulating film (illustrated). Not etched).

Thereafter, wirings and pixel electrodes are formed using Al, Ti, Mo, W, or the like. As materials for these electrodes and pixel electrodes, it is desirable to use a highly reflective material made of a film mainly composed of Al or Ag, or a laminated film thereof. Thus, the source or drain electrodes 157 to 162, the gate wiring 164, the connection wiring 163, and the pixel electrode 165 are formed.

  As described above, the pixel portion 207 including the driving circuit 206 including the n-channel TFT 201, the p-channel TFT 202, and the n-channel TFT 203, the pixel TFT 204 including the n-channel TFT, and the storage capacitor 205 is formed over the same substrate. Can be formed. (FIG. 6) In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the pixel portion 207, the pixel TFT 204 (n-channel TFT) includes a channel formation region 169, a first impurity region (n ⁻ region) 147 formed outside the conductive layer 129 forming the gate electrode, and a source region. Alternatively, second impurity regions (n ⁺ regions) 142 and 171 functioning as drain regions are provided. A fourth impurity region 152 and a fifth impurity region 154 are formed in the semiconductor layer functioning as one electrode of the storage capacitor 205. The storage capacitor 205 is formed of the second electrode 130 and the semiconductor layers 152, 154, and 170 using the insulating film (the same film as the gate insulating film) 118 as a dielectric.

In the driver circuit 206, the n-channel TFT 201 (first n-channel TFT) includes a third impurity region (a first n-channel TFT) that overlaps with a channel formation region 166 and part of the conductive layer 126 forming a gate electrode with an insulating film interposed therebetween. n ⁻ region) 144 and a second impurity region (n ⁺ region) 140 functioning as a source region or a drain region.

In the driver circuit 206, the p-channel TFT 202 includes a channel formation region 167, a fifth impurity region (p ⁻ region) 153 that overlaps with a part of the conductive layer 127 forming the gate electrode through an insulating film, and a source region or A fourth impurity region (p ⁺ region) 151 that functions as a drain region is provided.

In the driver circuit 206, the n-channel TFT 203 (second n-channel TFT) has a channel formation region 168 and a first impurity region (n ⁻ region) 146 outside the conductive layer 128 for forming the gate electrode. And a second impurity region (n ⁺ region) 141 functioning as a source region or a drain region.

  A driving circuit 206 may be formed by appropriately combining these TFTs 201 to 203 to form a shift register circuit, a buffer circuit, a level shifter circuit, a latch circuit, and the like. For example, in the case of forming a CMOS circuit, an n-channel TFT 201 and a p-channel TFT 202 may be complementarily connected.

In particular, the structure of the n-channel TFT 203 is suitable for a buffer circuit having a high driving voltage in order to prevent deterioration due to the hot carrier effect.

  In addition, the structure of the n-channel TFT 201 having a GOLD structure is suitable for a circuit in which reliability is given the highest priority.

  In addition, since the reliability can be improved by improving the planarization of the surface of the semiconductor film, it is sufficient to reduce the area of the impurity region overlapping with the gate electrode and the gate insulating film in the GOLD structure TFT. Reliability can be obtained. Specifically, sufficient reliability can be obtained even if the size of the portion that becomes the tapered portion of the gate electrode is reduced in the GOLD structure TFT.

  Further, in the GOLD structure TFT, the parasitic capacitance increases as the gate insulating film becomes thin. However, if the parasitic capacitance is reduced by reducing the size of the portion that becomes the tapered portion of the gate electrode (first conductive layer), the f characteristic ( (Frequency characteristics) is improved, and a higher speed operation is possible, and a TFT having sufficient reliability is obtained.

  Note that also in the pixel TFT of the pixel portion 207, reduction of off-state current and variation are realized by irradiation with the second laser light.

In this embodiment, an example of manufacturing an active matrix substrate for forming a reflective display device is shown. However, when a pixel electrode is formed of a transparent conductive film, a photomask is increased by one, but a transmissive display is provided. A device can be formed.

  Further, although a glass substrate is used in this embodiment, it is not particularly limited, and a quartz substrate, a semiconductor substrate, a ceramic substrate, or a metal substrate can be used.

  Further, after obtaining the state of FIG. 6, the substrate 100 may be peeled off if the mechanical strength of the layer including the TFT (the layer to be peeled) provided over the oxide layer 102 is sufficient. In this example, since the mechanical strength of the layer to be peeled is insufficient, it is preferable to peel off after attaching a support (not shown) for fixing the layer to be peeled.

In Example 1, an example of a reflective display device in which a pixel electrode is formed of a reflective metal material is shown. However, in this embodiment, a transmissive display in which a pixel electrode is formed of a light-transmitting conductive film. An example of an apparatus is shown.

Since the steps up to the formation of the interlayer insulating film are the same as those in the first embodiment, they are omitted here. After an interlayer insulating film is formed according to Embodiment 1, a pixel electrode 601 made of a light-transmitting conductive film is formed. As the light-transmitting conductive film, ITO (indium tin oxide alloy), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like may be used.

Thereafter, contact holes are formed in the interlayer insulating film 600. Next, a connection electrode 602 which overlaps with the pixel electrode is formed. The connection electrode 602 is connected to the drain region through a contact hole. In addition, the source electrode or drain electrode of another TFT is formed simultaneously with this connection electrode.

  Although an example in which all the drive circuits are formed on the substrate is shown here, several ICs may be used as part of the drive circuit.

  An active matrix substrate is formed as described above. When this active matrix substrate is used and the substrate is peeled off, a plastic substrate is attached to manufacture a liquid crystal module, and a backlight 604 and a light guide plate 605 are provided and covered with a cover 606. FIG. An active matrix liquid crystal display device as shown in FIG. Note that the cover and the liquid crystal module are bonded together using an adhesive or an organic resin. In addition, when the plastic substrate and the counter substrate are bonded to each other, the organic resin may be filled between the frame and the substrate by being surrounded by a frame and bonded. Further, since it is a transmissive type, the polarizing plate 603 is attached to both the plastic substrate and the counter substrate.

In this embodiment, an example of manufacturing a light-emitting device including a light-emitting element using an organic compound layer formed over a plastic substrate as a light-emitting layer is shown in FIG.

8A is a top view illustrating the light-emitting device, and FIG. 8B is a cross-sectional view taken along line A-A ′ in FIG. 8A. Reference numeral 1101 indicated by a dotted line denotes a source signal line driver circuit, 1102 denotes a pixel portion, and 1103 denotes a gate signal line driver circuit. Reference numeral 1104 denotes a sealing substrate, 1105 denotes a sealing agent, and the inside surrounded by the first sealing agent 1105 is filled with a transparent second sealing material 1107.

  Reference numeral 1108 denotes a wiring for transmitting signals input to the source signal line driver circuit 1101 and the gate signal line driver circuit 1103. A video signal and a clock signal are received from an FPC (flexible printed circuit) 1109 serving as an external input terminal. receive. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The light-emitting device in this specification includes not only a light-emitting device body but also a state in which an FPC or a PWB is attached thereto.

  Next, a cross-sectional structure is described with reference to FIG. A driver circuit and a pixel portion are formed over the substrate 1110. Here, a source signal line driver circuit 1101 and a pixel portion 1102 are shown as the driver circuits. Note that the substrate 1110 is bonded to the base film with the adhesive layer 1100 by using the peeling method described in Embodiment Mode 1 or Example 1.

  Note that as the source signal line driver circuit 1101, a CMOS circuit in which an n-channel TFT 1123 and a p-channel TFT 1124 are combined is formed. The TFT forming the driving circuit may be formed by a known CMOS circuit, PMOS circuit or NMOS circuit. Further, in this embodiment, a driver integrated type in which a drive circuit is formed on a substrate is shown, but this is not always necessary, and it can be formed outside the substrate.

  The pixel portion 1102 is formed by a plurality of pixels including a switching TFT 1111, a current control TFT 1112, and a first electrode (anode) 1113 electrically connected to the drain thereof. Although an example in which two TFTs are used for one pixel is shown here, three or more TFTs may be used as appropriate.

  Here, since the first electrode 1113 is in direct contact with the drain of the TFT, the lower layer of the first electrode 1113 is a material layer that can be in ohmic contact with the drain made of silicon, and a layer containing an organic compound. It is desirable to use a material layer having a high work function on the surface in contact. For example, when a three-layer structure of a titanium nitride film, a film containing aluminum as a main component, and a titanium nitride film is used, the resistance as a wiring is low, a good ohmic contact can be obtained, and the film can function as an anode. . In addition, the first electrode 1113 may be a single layer of a titanium nitride film, or a stack of three or more layers may be used.

In addition, insulators (referred to as banks, partition walls, barriers, banks, or the like) 1114 are formed on both ends of the first electrode (anode) 1113. The insulator 1114 may be formed using an organic resin film or an insulating film containing silicon. Here, as the insulator 1114, a positive-type photosensitive acrylic resin film is used to form the insulator having the shape shown in FIG.

In order to improve the coverage, it is preferable that a curved surface having a curvature be formed at the upper end portion or the lower end portion of the insulator 1114. For example, when positive photosensitive acrylic is used as a material for the insulator 1114, it is preferable that only the upper end portion of the insulator 1114 have a curved surface with a curvature radius (0.2 μm to 3 μm). As the insulator 1114, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used.

  Further, the insulator 1114 may be covered with a protective film formed of an aluminum nitride film, an aluminum nitride oxide film, or a silicon nitride film. This protective film is an insulating film mainly containing silicon nitride or silicon nitride oxide obtained by sputtering (DC method or RF method), or a thin film mainly containing carbon. If a silicon target is used and formed in an atmosphere containing nitrogen and argon, a silicon nitride film can be obtained. A silicon nitride target may be used. Further, the protective film may be formed using a film forming apparatus using remote plasma. Further, in order to allow light emission to pass through the protective film, it is preferable to make the protective film as thin as possible.

  Further, a layer 1115 containing an organic compound is selectively formed over the first electrode (anode) 1113 by an evaporation method using an evaporation mask or an inkjet method. Further, a second electrode (cathode) 1116 is formed over the layer 1115 containing an organic compound. Thus, a light-emitting element 1118 including the first electrode (anode) 1113, the layer 1115 containing an organic compound, and the second electrode (cathode) 1116 is formed. Here, since the light-emitting element 1118 emits white light, a color filter including a colored layer 1131 and a BM 1132 (for the sake of simplicity, an overcoat layer is not shown here) is provided.

  Further, if each layer containing an organic compound capable of emitting R, G, and B is selectively formed, a full color display can be obtained without using a color filter.

  In order to seal the light emitting element 1118, the sealing substrate 1104 is attached to the first sealing material 1105 and the second sealing material 1107. Note that an epoxy resin is preferably used as the first sealing material 1105 and the second sealing material 1107. The first sealing material 1105 and the second sealing material 1107 are preferably materials that do not transmit moisture and oxygen as much as possible.

  Further, in this embodiment, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, acrylic, or the like is used as a material constituting the sealing substrate 1104 in addition to a glass substrate or a quartz substrate. be able to. Further, after the sealing substrate 1104 is bonded using the first sealing material 1105 and the second sealing material 1107, it is also possible to seal with a third sealing material so as to cover the side surface (exposed surface).

  By enclosing the light emitting element in the first sealing material 1105 and the second sealing material 1107 as described above, the light emitting element can be completely blocked from the outside, and deterioration of the organic compound layer such as moisture and oxygen from the outside can be performed. It can prevent the urging substance from entering. Therefore, a highly reliable light-emitting device can be obtained.

  In addition, when a transparent conductive film is used as the first electrode 1113, a double-sided light-emitting device can be manufactured.

  In this embodiment, an example in which a layer containing an organic compound is formed on the anode and a cathode that is a transparent electrode is formed on the layer containing the organic compound (hereinafter referred to as a top emission structure) is shown. However, the organic compound layer is formed on the anode made of the transparent conductive film, and the cathode is formed on the organic compound layer. The light generated in the organic compound layer is transmitted from the anode that is the transparent electrode to the TFT. It is good also as a structure of taking out (henceforth a bottom emission structure).

  This embodiment can be freely combined with the above-described best mode or embodiment 1.

By implementing the present invention, various modules (active matrix liquid crystal module, active matrix EL module, active matrix EC module) can be completed. That is, by implementing the present invention, all electronic devices incorporating them are completed.

  Such electronic devices include video cameras, digital cameras, head mounted displays (goggles type displays), car navigation systems, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples of these are shown in FIGS.

FIG. 9A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like.

FIG. 9B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, an image receiving portion 2106, and the like.

FIG. 9C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, an operation switch 2204, a display unit 2205, and the like.

FIG. 9D shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet.

  FIG. 9E shows a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, an operation switch 2504, an image receiving portion (not shown), and the like.

  FIG. 10A shows a mobile phone, which includes a main body 2901, an audio output portion 2902, an audio input portion 2903, a display portion 2904, operation switches 2905, an antenna 2906, an image input portion (CCD, image sensor, etc.) 2907, and the like.

  FIG. 10B illustrates a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006, and the like.

  FIG. 10C illustrates a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like.

  Incidentally, the display shown in FIG. 10C is a medium or small size display, for example, a screen size of 5 to 20 inches. Further, in order to form a display portion having such a size, it is preferable to use a substrate having a side of 1 m and perform mass production by performing multiple chamfering.

  As described above, the applicable range of the present invention is so wide that the present invention can be applied to methods for manufacturing electronic devices in various fields. In addition, the electronic apparatus of this embodiment can be realized by freely combining with any one of the above-described best modes and Embodiments 1 to 3.

In the present invention, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface with a high yield. Therefore, when applied to a display device, a large screen and a thin display can be provided.

The figure which shows embodiment. The graph which shows the relationship between the heat processing temperature and stress in an amorphous silicon film single layer. The graph which shows the stress change in lamination | stacking. It is a figure which shows the manufacturing process of an active matrix substrate. Example 1 It is a figure which shows the manufacturing process of an active matrix substrate. Example 1 It is a figure which shows the manufacturing process of an active matrix substrate. Example 1 It is a figure which shows sectional drawing of a liquid crystal display device. (Example 2) It is a figure which shows the top view or sectional drawing of a light-emitting device. (Example 3) FIG. 14 illustrates an example of an electronic device. (Example 4) FIG. 14 illustrates an example of an electronic device. (Example 4) The graph which shows the result by TDS.

Explanation of symbols

10: First substrate 11: Nitride layer or metal layer 12: Oxide layer 13: Peeled layer 14: First adhesive or double-sided tape 15: Second substrate (support)
16: 2nd adhesive material 17: 3rd board | substrate (transfer body)

Claims (18)

A metal layer, an oxide layer in contact with the metal layer, an insulating film, and a semiconductor film containing hydrogen over the insulating film are sequentially stacked over the substrate,
Performing a heat treatment for diffusing the hydrogen at least between the metal layer and the oxide layer ;
After a support is bonded to a layer to be peeled including the oxide layer, the insulating film, and the semiconductor film, the layer to be peeled bonded to the support is removed from a substrate provided with the metal layer by a human hand or A peeling method characterized by peeling by using an apparatus for peeling off an element . In claim 1,
The peeling method, wherein the heat treatment is performed at 410 ° C. or higher. In claim 1 or 2,
The metal layer is an element selected from W, Ti, Ta, Mo, Cr, Nd, Fe, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, Ir, and Pt, or the element as a main component. A peeling method characterized by being a single layer made of an alloy material or a compound material, or a laminate of these metals or a mixture thereof. In any one of Claims 1 thru | or 3,
The peeling method, wherein the oxide layer is a silicon oxide film formed by sputtering. In any one of Claims 1 thru | or 4,
The peeling method, wherein the insulating film is a silicon oxide film, a silicon oxynitride film, or a laminate thereof. In any one of Claims 1 thru | or 5,
The peeling method, wherein the oxide layer is thicker than the metal layer. In any one of Claims 1 thru | or 6,
The peeling method, wherein the semiconductor film containing hydrogen has an amorphous structure. A metal layer, an oxide layer in contact with the metal layer, an insulating film, and a semiconductor film containing hydrogen over the insulating film are sequentially stacked over the substrate,
Performing a heat treatment for diffusing the hydrogen at least between the metal layer and the oxide layer ;
Forming a TFT having the semiconductor film;
After a support is bonded to the layer to be peeled including the oxide layer, the insulating film, and the TFT, the layer to be peeled bonded to the support is removed from a substrate provided with the metal layer by a human hand or an element. A method for manufacturing a semiconductor device, wherein the semiconductor device is separated by using a device for peeling off the semiconductor. A metal layer, an oxide layer in contact with the metal layer, an insulating film, and a metal layer containing hydrogen over the insulating film are sequentially stacked on the substrate,
Performing a heat treatment for diffusing the hydrogen at least between the metal layer and the oxide layer ;
TFT is formed,
After a support is bonded to the layer to be peeled including the oxide layer, the insulating film, and the TFT, the layer to be peeled bonded to the support is removed from a substrate provided with the metal layer by a human hand or an element. A method for manufacturing a semiconductor device, wherein the semiconductor device is separated by using a device for peeling off the semiconductor. A metal layer containing hydrogen on the substrate, an oxide layer in contact with the metal layer, an insulating film, and a semiconductor film are sequentially stacked on the insulating film;
Performing a heat treatment for diffusing the hydrogen at least between the metal layer and the oxide layer ;
Forming a TFT having the semiconductor film;
After a support is bonded to the layer to be peeled including the oxide layer, the insulating film, and the TFT, the layer to be peeled bonded to the support is removed from a substrate provided with the metal layer by a human hand or an element. A method for manufacturing a semiconductor device, wherein the semiconductor device is separated by using a device for peeling off the semiconductor. In any one of Claims 8 thru | or 10,
The method for manufacturing a semiconductor device, wherein the heat treatment is performed at 410 ° C. or higher. In any one of Claims 8 thru | or 11,
The metal layer is an element selected from W, Ti, Ta, Mo, Cr, Nd, Fe, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, Ir, and Pt, or the element as a main component. A method for manufacturing a semiconductor device, comprising: a single layer made of an alloy material or a compound material, or a laminate of these metals or a mixture thereof. In any one of Claims 8 thru | or 12,
The method for manufacturing a semiconductor device, wherein the oxide layer is a silicon oxide film formed by a sputtering method. In any one of Claims 8 thru | or 13,
The method for manufacturing a semiconductor device, wherein the insulating film is a silicon oxide film, a silicon oxynitride film, or a stacked layer thereof. In any one of Claims 8 thru | or 14,
The method for manufacturing a semiconductor device, wherein the oxide layer is thicker than the metal layer. In any one of Claims 8 and 11 thru | or 15,
The method for manufacturing a semiconductor device, wherein the semiconductor film containing hydrogen has an amorphous structure. In claim 16,
A method for manufacturing a semiconductor device, wherein the semiconductor film having an amorphous structure is crystallized by the heat treatment. In any one of Claims 8 thru | or 17,
A method for manufacturing a semiconductor device, comprising an element connected to the TFT, wherein the element is a light-emitting element, a semiconductor element, or a liquid crystal element.

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