JP4653192B2 - A computer that dynamically determines interrupt delay. - Google Patents

Description

  The present invention relates to an interrupt control system in a computer system. More specifically, for example, after an interrupt event is input from the outside, an interrupt request output unit in the computer system outputs an interrupt request to the processor according to the load state of the processor. The present invention relates to a computer system that dynamically determines the delay time until.

  When an interrupt event that requires interrupt processing by the processor is input to the computer system, for example, an interrupt (request) signal is received from the input / output (I / O) device that received the interrupt event to the processor. And the corresponding interrupt processing is executed by the processor. For example, when the I / O device is a network interface, an interrupt signal is output from the I / O device to the processor when communication data such as a packet arrives.

  FIG. 16 is a block diagram showing the configuration of a computer system targeted by the present invention. In the figure, the computer system includes a processor 50, a main memory 51, an I / O bus bridge 53, and a plurality of I / O devices 54 and 55.

  In FIG. 16, an I / O bus bridge 53 is a mechanism for connecting a processor 50, a main memory 51, and an I / O bus 52, and provides an access function from the processor 50 to the main memory 51 and the I / O bus 52. . The I / O devices 54 and 55 are connected to the I / O bus 52, and serve as interfaces between various devices such as networks and disks and the computer system.

  For example, in the case of a network interface, an interrupt (request) signal is output to the processor 50 when communication data arrives at the I / O device. For example, the contents of the interrupt factor register are checked.

  Here, the prior art will be described by taking PCI (Peripheral Component Interconnect) type buses and PCI bus devices, which are currently used as the mainstream of high-speed buses for personal computers, as an example. It can also be applied to the system.

  In the system as shown in FIG. 16, the timing and frequency at which the I / O device issues an interrupt (request) signal to the processor greatly affects the performance of the system. For example, when the I / O device is an interface compatible with Gigabit Ethernet®, a transmission performance of 125 MB / sec is realized for both transmission and reception, but the minimum length of the packet is about 60 bytes, When a reception interrupt is notified to the processor every time it is received, the processor is interrupted at a rate of once every 0.5 μs.

  FIG. 17 is an explanatory diagram of a conventional example of interrupt processing in such a case. In the figure, for example, an interrupt event 1 is given from the outside to the computer system, the interrupt processing is immediately performed by the processor, an interrupt event k is then given from the outside, and an interrupt event is immediately performed by the processor.

The interrupt processing by the processor requires at least a certain processing load such as saving and restoring the current processing state and specifying the interrupt factor. If the frequency of interrupts becomes high and the interrupt interval becomes short, the interrupt processing load on the processor increases, which may reduce the performance of the system.

  In order to avoid an increase in the load on the processor due to such frequent occurrence of interrupts, a conventional technique called interrupt calling is used. In interrupt calling, a process for delaying an event that should generate an interrupt, that is, a time from when an interrupt event occurs until an interrupt request is actually made to the processor, according to a certain condition is performed. For example, since a plurality of interrupt events are collected and interrupted, the processing load such as saving and restoring the current processing state and specifying the interrupt factor can be collected at one time, and the processing load of the processor can be reduced.

  FIG. 18 is an explanatory diagram of such interrupt coalescing. In the figure, a plurality of interrupts from the occurrence of interrupt event 1 to the occurrence of interrupt event K are collected, and an interrupt request is given from the I / O device to the processor.

  As a typical condition up to the interrupt request in interrupt calling, a condition such as “a certain time elapses” or “a certain number of interrupt events occur” is used. For example, in the case of a network interface, an interrupt request is made after a certain time has elapsed since the packet was received. By using this method, when a total of K packets are received while the interrupt is delayed, the number of interrupts to the processor can be reduced to 1 / K. Even if the condition for the number of interrupt events is used, the number of interrupts can be similarly reduced.

  Next, a conventional apparatus configuration of an interrupt request circuit in an I / O device will be described. FIG. 19 is a block diagram of the configuration. In the figure, for example, an interrupt request circuit 58 is provided inside the I / O device 54, and an interrupt factor register 59 is further provided therein.

  The interrupt request circuit 58 outputs an interrupt (request) signal to the processor 50 via the I / O bus 52 and the I / O bus bridge 53 when an interrupt event occurs due to arrival of a packet from the outside, for example. At the same time, the interrupt factor register 59 is set with information for determining the contents of the interrupt event.

  The contents of the interrupt factor register 59 can be read from and written to the processor 50 via the I / O bus 52. The processor 50 examines the contents of the interrupt factor register 59 to determine the contents of the interrupt event. Identify. Further, the processor 50 can notify the interrupt request circuit 58 of the end of the interrupt processing by clearing the contents of the interrupt factor register 59. In response to this, the interrupt request circuit 58 generates an interrupt signal, and all processes corresponding to the interrupt are completed.

FIG. 20 is an explanatory diagram of the flow of interrupt processing in FIG. (Note that the circled numbers in the drawings described below are shown as parenthesized numbers in this specification.) As soon as an interrupt event is given to an I / O device, an interrupt signal is output to the processor. In (1) , the interrupt factor is inspected according to the contents of the interrupt factor register 59 and interrupt processing is started. In (2) , the interrupt processing is basically ended and the contents of the interrupt factor register 59 are cleared. For example, for interrupt processing Perform processing such as releasing the work area of, and end interrupt processing in (3) .

  FIG. 21 is a block diagram of another configuration example of the conventional I / O device, and FIG. 22 is an explanatory diagram of the flow of interrupt processing in FIG. In FIG. 21, the interrupt request circuit 58 includes a condition register 61 that stores a predetermined fixed delay condition. The interrupt delay circuit 62 generates an interrupt event according to the contents of the condition register 61. Then, the delay time from when the interrupt signal is output to the processor is determined. The content stored in the condition register 61 may be the above-described fixed time or a fixed number of interrupt events, but the interrupt delay circuit 62 determines the delay time from the occurrence of the interrupt event corresponding to the content, Output an interrupt signal.

In FIG. 22, an interrupt signal is output to the processor after a fixed delay time after an interrupt event is given to the I / O device. After that, as in FIG. 20, (1) checks the interrupt factor, (2) The interrupt factor is cleared, and interrupt processing ends in (3) .

  There are three problems with the interrupt calling as the prior art described above. The first problem is that, since an interrupt is always delayed according to a certain condition after the occurrence of the interrupt event, the response after the occurrence of the interrupt event is always delayed. For example, in the case of a network interface, even if only one packet is received, interrupt processing is not executed unless a certain time has elapsed since the packet was actually received.

  The second problem is that since the processor load state is not taken into consideration, an adaptive process such as immediately interrupting when the processor load is low and delaying the interrupt when the processor load is high cannot be performed. is there.

  The third problem is that, for example, a card or the like is often inserted into an I / O device, but the optimum condition for interrupt delay between such a card and the processor differs depending on the card or the like. Nevertheless, the conventional technique uses a fixed delay condition and cannot be adjusted.

  The object of the present invention is to delay from the occurrence of an interrupt event until the I / O device actually outputs an interrupt request signal to the processor, depending on the performance of the processor, the state of the load, and the frequency of occurrence of the interrupt event. It is to provide a computer that can dynamically determine conditions.

  FIG. 1 is a block diagram showing the principle of the present invention. In the figure, an interrupt request output unit 1 corresponds to the I / O device of FIG. 16, and outputs an interrupt request to the processor 2 in response to the occurrence of an interrupt event.

  In FIG. 1, the interrupt request output unit 1 includes delay condition determining means 3. The delay condition determining means 3 dynamically determines a delay condition, for example, a delay time from when an interrupt event occurs until the interrupt request output unit 1 outputs an interrupt request to the processor 2.

  In the embodiment of the invention, the interrupt request output unit 1 further includes delay condition determination factor output means 4. The delay condition determining factor output means 4 obtains a delay condition determining factor from when an interrupt event occurs until an interrupt request is output to the processor. The delay condition determining means 3 corresponds to the determined factor. Determine the conditions until an interrupt request is output.

In this case, the interrupt request output unit 1 further includes an interrupt factor storage unit that stores an interrupt factor corresponding to the interrupt event that has occurred, and the processor stores the interrupt factor after the delay condition determination factor output unit 4 outputs the interrupt request. The time until the stored contents of the means are read can be obtained as a delay condition determining factor corresponding to the next and subsequent interrupts, or until the stored contents of the interrupt factor storing means are cleared by the processor after the interrupt request is output. Can be obtained as a delay condition determining factor corresponding to the next and subsequent interrupts.

  In the embodiment, the delay condition determination factor output means 4 has a plurality of times from when the interrupt request is output until the stored contents of the interrupt factor storage means are read by the processor, or until the stored contents are cleared. The delay condition factor corresponding to the next and subsequent interruptions can also be obtained based on the measurement values obtained a plurality of times.

  Furthermore, in the embodiment, the delay condition determining means 3 determines the delay time as the delay condition by multiplying the time as the determining factor obtained by the delay condition determining factor output means 4 by a predetermined coefficient. You can also.

  The computer of the present invention further comprises an interrupt cycle setting means and an interrupt time point determination means. The interrupt cycle setting means sets a cycle for outputting an interrupt request to the processor 2 in response to the interrupt event generated by the interrupt request output unit 1, and the interrupt time determining means sets an interrupt event based on the set interrupt cycle. Determine when to output the corresponding interrupt request.

  In the embodiment of the invention, the interrupt request output unit 1 further includes interrupt factor storage means for storing an interrupt factor corresponding to the generated interrupt event, and the processor sets the interrupt factor after the interrupt request is output by the cycle setting means. The interrupt cycle can also be set based on the time until the stored contents of the means are read or the time until the stored contents of the interrupt factor storage means are cleared.

In the embodiment, the interrupt cycle setting means can set the interrupt cycle in response to an instruction from the processor 2.
The computer according to the present invention further includes an interrupt request output unit 1 for the processor 2. The interrupt request output unit 1 is dynamically determined by the processor and is a delay from when an interrupt event occurs until the interrupt request is output to the processor. Delay condition storage means for storing conditions, for example, a condition register is provided .

  As described above, according to the present invention, the delay condition from when an interrupt event occurs until the interrupt request output unit outputs an interrupt request to the processor is dynamically determined.

FIG. 2 is a block diagram showing the configuration of the interrupt request circuit according to the first embodiment of the present invention, and FIG. 3 is an explanatory diagram of the processing flow in FIG.
In FIG. 2, the condition register 13 is similar to the condition register 61 in the conventional example of FIG. The delay condition until an interrupt (request) signal is output is stored. This delay condition is dynamically determined on the processor side according to the load state of the processor, and the condition is stored in the condition register 13. The

  That is, the I / O device 11 side explicitly indicates the delay condition of the interrupt by the processor, that is, the delay time from when the interrupt event occurs until the interrupt delay circuit 12 outputs the interrupt signal, or the number of interrupt events occurring during that time. The I / O device 11 delays the interrupt based on this condition.

The determination of the interrupt delay condition on the processor side is dynamically executed according to the load state of the processor at that time, and is adapted to the load state of the processor by rewriting the contents of the condition register 13 at a certain time interval, for example. The interrupt delay can be realized dynamically. Any known technique can be used as a method of measuring the load state on the processor side, and detailed description thereof is omitted.

In the processing flow of FIG. 3, in (1) , the processor side sets an interrupt delay condition for the condition register 13, and the I / O device side sets, for example, a plurality of interrupts according to the designation of the condition, for example, the delay time. Even if the event occurs during the delay time, an interrupt signal is output from the interrupt delay circuit 12 to the processor after a delay of a specified time after the occurrence of the first interrupt event. The processor checks the interrupt factor by reading the contents of the interrupt factor register 14 in (2) , and when the interrupt processing is basically completed, clears the interrupt factor stored in the interrupt factor register 14 in (3). In step (4) , all interrupt processing ends.

  FIG. 4 is a flowchart of interrupt delay condition setting processing by the processor according to the first embodiment. In the figure, the interrupt delay condition is first dynamically determined in step S1 on the processor side, and the delay condition is set in the condition register 13 in the I / O device 11 in step S2. Thus, on the I / O device 11 side, after an interrupt event occurs, an interrupt request signal is output in step S3 corresponding to the set interrupt delay condition, and interrupt processing is executed on the processor side in step S4.

  FIG. 5 is a block diagram of a configuration example of the interrupt delay circuit 12 in the first embodiment. Here, it is assumed that an interrupt delay time is set in the condition register 13 as an interrupt delay condition.

  In FIG. 5, in response to the occurrence of an interrupt event, the counter 16 is given the value of the interrupt delay time set in the condition register 13, and for example, the countdown of the counter is started. When the counter times out, a time-out signal is given to one input terminal of the AND gate 17. An interrupt (request) signal corresponding to the occurrence of an interrupt event is input to the other input terminal of the AND gate 17, and an interrupt (request) signal is output from the AND gate 17 to the processor via the I / O bus 15. The

  FIG. 6 is an example of a flowchart of interrupt delay processing when the interrupt delay circuit 12 is realized by software. In the figure, after the occurrence of an interrupt event, the value of the interrupt delay time set in the condition register 13 is set in the timer in step S5, the timer value is decremented in step S6, and the timer times out in step S7. If it has not yet occurred, the processes after step S6 are repeated. If a timeout has occurred, it is determined whether or not there is an interrupt factor in step S8. If there is no interrupt factor, the processing from step S5 is repeated, and if there is an interrupt factor, interrupt processing is executed in step S9. .

  FIG. 7 shows a configuration block diagram of the interrupt request circuit in the second embodiment, and FIG. 8 shows the flow of processing in FIG. In the second embodiment, unlike the first embodiment, an interrupt delay condition, for example, an interrupt delay time is dynamically determined on the I / O device side.

  As described above, the interrupt factor register 14 in the interrupt request circuit 11 stores a factor corresponding to the generated interrupt event, and the processor checks the interrupt factor by reading the contents via the I / O bus 15. When the interrupt processing is basically completed, the interrupt factor is cleared.

In the second embodiment, by measuring the time from when an interrupt signal for an interrupt event that occurred at a certain point in time is output until the interrupt factor stored in the interrupt factor register 14 is cleared, for example, The load state is estimated, and the interrupt delay time for the next interrupt event is determined based on the estimated time.

  In FIG. 7, for example, when an interrupt event occurs and an interrupt signal is output immediately, an interrupt factor is stored in the interrupt factor register 14, a timer 21 is started, and the contents of the interrupt factor register 14 are cleared by the processor. The time to complete is measured. The time is given to the delay time determination circuit 20 and used to determine the interrupt delay time corresponding to the occurrence of the next interrupt event.

  In the determination of the delay time, the measurement value of the timer 21 can be used as it is. However, coefficients such as 2, 4,..., 1/2, 1/4,. The delay time can also be determined by multiplying the coefficients. As a result of experiments, it has been found that, in some systems, the overall processing performance is improved by multiplying, for example, by 4 instead of using the timer measurement value as it is.

In the processing flow of FIG. 8, when an interrupt event occurs at a certain point in time, for example, the I / O device immediately outputs an interrupt signal to the processor via the I / O bus 15 and starts time measurement (1) . To do. The processor checks the interrupt factor stored in the interrupt factor register 14 in (2) , and clears the interrupt factor in (3) when the interrupt processing is basically ended. On the I / O device side, the measured value of the time from when the interrupt signal is output until the interrupt factor is cleared (3) is used to determine the interrupt delay time corresponding to the occurrence of the next interrupt event. That is, an interrupt signal is output with a delay of the determined delay time from the occurrence of the next interrupt event, and time measurement is performed again in preparation for the occurrence of the next interrupt event.

  In FIG. 9, in the second embodiment, the timer 21 measures not the time until the interrupt factor is cleared by the processor from the output of the interrupt signal but the time until the interrupt factor test is performed, and based on the measured time. It is explanatory drawing of the flow of a process in the case of determining the interruption delay time with respect to the next interruption.

In FIG. 8, as in FIG. 8, for example, an interrupt signal is immediately output to the processor when an interrupt event occurs, and time measurement by the timer 21 is started in (1) . In processor side checks the contents of the interrupt factor register 14 (2), (3) the cause is cleared, although the interrupt processing is terminated (4), the point of time measurement interrupt factor check (1) The measurement result is used to determine the interrupt delay time corresponding to the next interrupt event.

  That is, in FIG. 9, the time measured by the timer 21 reflects the time from when the interrupt (request) signal is received until the processor actually enters interrupt processing, and this time also corresponds to the load state of the processor. is there.

  Thus, in the second embodiment, the processor does not specify the interrupt delay condition, but the I / O device side substantially detects the processing load state of the processor and determines the interrupt delay condition. That is, the time from when the I / O device makes an interrupt request to the processor until the processor starts or ends the corresponding interrupt processing is measured, and the interrupt delay condition is determined based on this time. The main feature of this embodiment is that the processor does not need to set a delay condition.

FIG. 10 is a detailed block diagram of the second embodiment, that is, the timer and delay time determination circuit in FIG. In the figure, the timer 21 is activated and starts counting when an interrupt event occurs, the interrupt factor is stored in the interrupt factor register 14, and an interrupt signal is output from the interrupt delay circuit 12 to the processor.

  In FIG. 8, when the contents of the interrupt factor register 14 are cleared by the processor, for example, when 0 is written as data, a stop signal is input to the timer 21 in response to the write signal of this data. The measured value is output to the multiplier 26. A coefficient to be multiplied by the timer measurement value is output from the coefficient unit 25 to the multiplier 26, and a multiplication result by the multiplier 26 is given to the interrupt delay circuit 12. The configuration of the interrupt delay circuit is the same as that in FIG. 5 in the first embodiment.

  In FIG. 9, the time from when the timer 21 starts counting until the processor reads the contents of the interrupt factor register 14, that is, until the read signal is output, is measured. At this point, the timer 21 is given a stop signal. The measured value of the timer is supplied to the multiplier 26 in the same manner as described above, multiplied by the coefficient output from the coefficient unit 25, and output to the interrupt delay circuit 12.

  FIG. 11 is a flowchart of the interrupt delay time determination process corresponding to FIG. In FIG. 7, an interrupt request signal is output to the processor on the I / O device side in step S10, and the timer 21 in FIG. 7 is started.

  On the processor side, the interrupt request is received in step S11, and after the time corresponding to the load processing state at that time has elapsed, the contents of the interrupt factor register 14 are read in step S12. Then, the processor executes interrupt processing in step S13, and clears the contents of the interrupt factor register in step S14.

  The I / O device side detects clearing of the interrupt factor register by the processor, stops the timer in step S15, and determines the delay time based on the value of the timer in step S16.

  FIG. 12 is a flowchart of the delay time determination process corresponding to FIG. Compared with FIG. 11, the only difference is that the I / O device side stops the timer in step S17 in response to the processing in step S12 by the processor, that is, reading the interrupt factor, and determines the interrupt delay time in step S18. ing.

  FIG. 13 shows a plurality of times of measurement of the time from when the interrupt signal is output until the contents of the interrupt factor register 14 are read or cleared by the processor in the second embodiment. It is a block diagram of the structural example of the delay time determination circuit which sets the interrupt delay condition corresponding to the next interrupt based on it.

  In the figure, a stop signal is output to the timer 21 when the contents of the interrupt factor register 14 are cleared or read by the processor as in FIG. The timer 21 first counts the time from the output of the interrupt signal corresponding to the occurrence of the first interrupt event, and the measured value is stored in the register 31a. In this measurement value storage, a timer value confirmation signal is given from the timer 21 to the counter 30, the count value of the counter 30 is incremented in response to this signal, and the output of the counter 30 is given to the register 31a as a write enable signal. Executed by.

  The time from the interrupt signal output corresponding to the occurrence of the second interrupt event until the contents of the interrupt factor register 14 is read or cleared by the processor is measured by the timer 21, and the count value is output by the counter 30. The write enable signal is supplied to the register 31b and stored in the register 31b.

  Similarly, after all n count values are stored in the respective registers, the count values are supplied to the average value calculation circuit 32, and the calculated average value is output to the multiplier 26 in FIG. Thus, a measurement value corresponding to a plurality of interrupt events is obtained and used to determine an interrupt delay time corresponding to the occurrence of the next interrupt event.

  FIG. 14 is a configuration block diagram of the interrupt request circuit 11 in the third embodiment, and FIG. 15 is an explanatory diagram of the processing flow in FIG. In the third embodiment, the I / O device 10 periodically outputs an interrupt (request) signal to the processor, and even if an interrupt event occurs, the delay of the interrupt until the timing of the next interrupt cycle occurs. Done. Since the occurrence points of the interrupt events are randomly distributed within the period, the delay time from the occurrence of the interrupt event to the actual output of the interrupt signal becomes half of the period on average.

  In FIG. 14, the cycle timer 35 generates this interrupt cycle, the delay time determination circuit 34 determines the delay time so as to synchronize with this cycle, and the interrupt delay circuit 12 receives the interrupt signal at the time synchronized with the timing of this cycle. It will output to the processor.

In FIG. 15, an interrupt signal is output to the processor at the timing of the next fixed period corresponding to the occurrence of the first interrupt event, the interrupt factor is checked by the processor in (1) , the interrupt factor is cleared in (2) , Interrupt processing ends at (3) .

  The interrupt signal output is delayed until the timing determined by the cycle for the next interrupt event. Even if other interrupt events occur during this time, interrupt (request) signals are output collectively for these interrupt events.

  As the period generated by the period timer 35, when the first is fixed, secondly, as in the first embodiment, when the processor specifies according to the load state, the second second is implemented. As in the embodiment, there are three cases where the I / O device makes a decision based on the measured value of the time until the processor reads the contents of the interrupt factor register 14 or clears it.

  The method of making an interrupt request at periodic timing as in the third embodiment is effective in a system using TCP / IP (Transmission Control Protocol / Internet Protocol), and UDP / IP (User Datagram). In a system using (Protocol / Internet Protocol), it has been experimentally proved that the method of multiplying the measured value of the timer by a certain coefficient as described in FIG. 7 for the second embodiment is effective.

  In the above description, the embodiment of the invention has been mainly described in the case where the delay time is used as the interrupt delay condition. However, it is naturally possible to use the number of occurrences of the interrupt event as the delay condition. For example, in the second embodiment, instead of measuring the time until the processor reads or clears the interrupt factor, the number of interrupt events occurring during that time is measured, and the delay condition is determined based on the number. You can also.

  As described above in detail, according to the present invention, it is possible to determine the processing load state of the processor from the past processing state corresponding to the interrupt event, and to adaptively set the interrupt delay condition corresponding to the result. it can.

As a result, interrupts can be interrupted immediately after an interrupt event occurs when the processor load is low, and interrupts can be delayed according to the degree of load when the processor load is high. The effect of automatically optimizing the delay time until output can be obtained.

  In addition, even when a card is inserted into the I / O device, the optimum conditions for interrupt delay between the card and the processor can be automatically adjusted, improving interrupt processing performance. The place that contributes to

  As described above, in the computer according to the present invention, the delay condition from the occurrence of the interrupt event until the interrupt request is given to the processor is adaptively determined according to the processor load and the like. It can be used in all industries that use computers that can execute.

The circled numbers in the drawings described below are shown as numbers in parentheses in this specification.
1 is a block diagram illustrating the principle configuration of the present invention. It is a block diagram which shows the structure of the interrupt request circuit in 1st Embodiment. It is a figure which shows the flow of the interruption process in FIG. It is a flowchart of the delay condition setting process by the processor in 1st Embodiment. It is a block diagram which shows the structure of the interruption delay circuit in 1st Embodiment. 6 is a flowchart of interrupt delay processing in the first embodiment. FIG. 5 is a block diagram illustrating a configuration of an interrupt request circuit according to a second embodiment. It is a figure which shows the flow of the interruption process in FIG. It is a figure which shows the flow of a process in the case of determining delay time based on the time until interruption factor reading in 2nd Embodiment. It is a block diagram which shows the structure of the timer and delay time determination circuit in 2nd Embodiment. It is a 1st example of the flowchart of the interruption delay time determination process in 2nd Embodiment. It is a 2nd example of the flowchart of the interruption delay time determination process in 2nd Embodiment. It is a block diagram of the example of a structure of the delay time determination circuit which determines delay time from several time measurement value in 2nd Embodiment. FIG. 10 is a configuration block diagram of an interrupt request circuit according to a third embodiment. It is a figure which shows the flow of the process in FIG. It is a block diagram which shows the structural example of a computer system. It is a figure explaining the relationship between an interruption interval and interruption processing load. It is a figure explaining the process of the interrupt calling as a prior art. It is a configuration block diagram of a conventional example of an interrupt request circuit when there is no interrupt delay. It is a figure which shows the flow of the process in FIG. It is a block diagram of a conventional example of an interrupt request circuit when there is an interrupt delay. It is a figure which shows the flow of the process in FIG.

Claims (3)

In a computer having an interrupt main Motomede force unit to the processor,
The interrupt request output unit determines an interval for outputting an interrupt request to the processor in response to the occurrence of an interrupt event;
A interrupt time determining means for determining when to output an interrupt request corresponding to the interrupt event based on the interrupt period is the set,
The interrupt request output unit includes an interrupt factor storage means for storing an interrupt factor corresponding to an interrupt event that has occurred,
Said period setting means, based on the time until the stored data is read out of該割interrupt factor storage means by the processor from the output of the interrupt request corresponding to the interrupt event that the generated feature that you set the period A computer that dynamically determines the interrupt delay. In a computer having an interrupt request output unit for a processor,
The interrupt request output unit determines an interval for outputting an interrupt request to the processor in response to the occurrence of an interrupt event;
Interrupt time determination means for determining a time to output an interrupt request corresponding to the interrupt event based on the set interrupt cycle,
The interrupt request output unit includes an interrupt factor storage means for storing an interrupt factor corresponding to an interrupt event that has occurred,
It said period setting means, based on the time from the output of the interrupt request corresponding to the interrupt event that the generated until the stored contents of該割interrupt factor storage means is cleared by the processor, that you set the period computer to dynamically determine the interrupt delay shall be the feature. Said interrupt period setting means, computer for dynamically determining an interrupt delay according to claim 1 or 2, in response to an instruction from said processor and said Rukoto can set the period.

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