JP4583529B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a circuit formed of a thin film transistor over a substrate having an insulating surface and a manufacturing method thereof. For example, the present invention relates to an electro-optical device typified by a liquid crystal display device and a configuration of an electronic apparatus equipped with the electro-optical device. Note that in this specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics, and includes the above-described electro-optical device and electronic devices in which the electro-optical device is mounted.
[0002]
[Prior art]
Since thin film transistors (hereinafter referred to as TFTs) can be manufactured on a transparent glass substrate, application development to active matrix liquid crystal display devices has been actively promoted. A TFT having a semiconductor film having a crystal structure as an active layer (hereinafter referred to as a crystalline TFT) can obtain high mobility, so that a high-definition image display can be realized by integrating functional circuits on the same substrate. It became possible.
[0003]
In the specification of the present application, the semiconductor film having the crystal structure includes a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor, and further includes Japanese Patent Application Laid-Open Nos. H7-130652, H8-78329, and H10. -135468 or the semiconductor disclosed in Japanese Patent Application Laid-Open No. 10-135469.
[0004]
In order to construct an active matrix type liquid crystal display device, it is necessary to provide one to two million crystalline TFTs with only a pixel matrix circuit, and if a functional circuit provided in the periphery is further added, a larger number of crystalline TFTs are required. Was necessary. In order to stably operate the liquid crystal display device, it is necessary to ensure the reliability of each crystalline TF.
[0005]
The characteristics of a field effect transistor such as a TFT are ideal for a linear region where the drain current and drain voltage increase proportionally, a saturation region where the drain current saturates even when the drain voltage increases, and a drain voltage applied Can be divided into a cut-off region where no current flows. In this specification, the linear region and the saturation region are referred to as the TFT on region, and the blocking region is referred to as the off region. For convenience, the drain current in the on region is referred to as on-current, and the current in the off region is referred to as off-current.
[0006]
The pixel matrix circuit of the active matrix liquid crystal display device is composed of n-channel TFTs (hereinafter referred to as pixel TFTs), and a gate voltage having an amplitude of about 15 to 20 V is applied thereto. It was necessary to satisfy both characteristics. On the other hand, the peripheral circuit provided for driving the pixel matrix circuit is configured based on a CMOS circuit, and the on-region characteristics are mainly important. However, the crystalline TFT has a problem that the off-current tends to increase. When the crystalline TFT is driven for a long period of time, deterioration phenomena such as a decrease in mobility, an on-current, and an increase in off-current are often observed. One of the causes is considered to be a hot carrier injection phenomenon that occurs due to a high electric field near the drain.
[0007]
In the LSI technical field, a lightly doped drain (LDD) structure is known as a method for reducing the off-current of a MOS transistor and further mitigating a high electric field in the vicinity of the drain. In this structure, a low concentration impurity region is provided between a drain region and a channel formation region, and this low concentration impurity region is called an LDD region.
[0008]
Similarly, it has been known that a crystalline TFT forms an LDD structure. In the conventional technique, a low-concentration impurity region that becomes an LDD region is formed by adding a first impurity element using a gate electrode as a mask, and then an anisotropic etching technique is used on both sides of the gate electrode. In this method, sidewalls are formed, and a high concentration impurity region to be a source region and a drain region is formed by adding a second impurity element using the gate electrode and the sidewall as a mask.
[0009]
However, the LDD structure has a drawback in that, even if the off-current can be reduced, the series resistance component increases structurally, and as a result, the on-current of the TFT also decreases. It was. Moreover, the deterioration of the on-current could not be prevented completely. As a method for compensating for this drawback, a structure is known in which the LDD region is overlapped with a gate electrode through a gate insulating film. There are several methods for forming this structure. For example, it is known as GOLD (Gate-drain Overlapped LDD) or LATID (Large-tilt-angle implanted drain). With such a structure, the high electric field in the vicinity of the drain was relaxed to increase the hot carrier resistance, and at the same time, a decrease in on-current could be prevented.
[0010]
Also, in the case of a crystalline TFT, compared to a crystalline TFT having a simple structure formed only from a source region, a drain region, and a channel region, by providing an LDD structure, resistance to hot carriers is improved, and furthermore, a GOLD structure is adopted. It was confirmed that an extremely excellent effect was obtained ("A Novel Self-aligned Gate-overlapped LDD Poly-Si TFT with High Reliability and Performance", Mutsuko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM97-523).
[0011]
[Problems to be solved by the invention]
In a crystalline TFT, it is an effective means to form an LDD structure in order to suppress the hot carrier injection phenomenon. Further, when the GOLD structure is used, it is possible to prevent a decrease in on-current observed in the LDD structure. Also, good results are obtained from the viewpoint of reliability.
[0012]
As described above, in order to achieve high reliability with the crystalline TFT, it is necessary to study from the structure side of the element. For this reason, it is desirable to form a GOLD structure. However, in the conventional method, the LDD region can be formed in a self-aligning manner. However, the step of forming the sidewall film by anisotropic etching is to process a large-area glass substrate like a liquid crystal display device. Was unsuitable. In addition, since the length of the LDD region is determined by the width of the side wall, the degree of freedom in device design is extremely limited.
[0013]
A first object of the present invention is to provide a technique for overcoming such problems, and a crystal having a structure in which a gate electrode and an LDD region are overlapped by a simpler method than the conventional technique. The object is to provide a technique for producing a quality TFT.
[0014]
Although the GOLD structure can prevent the on-current from deteriorating, the off-current may increase when a high gate voltage is applied in the off region, particularly in the case of an n-channel TFT constituting a pixel matrix circuit. is there. When the off-current increases in the pixel TFT of the pixel matrix circuit, there arises a problem that power consumption increases and abnormality appears in image display. This is considered to be because an inversion layer is formed in the LDD region which is formed in the off region so as to overlap the gate electrode, thereby creating a hole passage. In such a case, the operating range of the TFT becomes narrow and limited.
[0015]
A second object of the present invention is to provide a structure for preventing an increase in off-current so that the operating range can be expanded in a crystalline TFT having a structure in which a gate electrode and an LDD region overlap each other, and a method for manufacturing the same. The second purpose is to provide the above.
[0016]
[Means for Solving the Problems]
FIG. 17 schematically shows the structure of the TFT and the Vg-Id (gate voltage-drain current) characteristics obtained at that time, based on the knowledge thus far. FIG. 17A-1 illustrates the simplest TFT structure in which a semiconductor layer includes a channel formation region, a source region, and a drain region. (B-1) shows the characteristics of this TFT. The + Vg side is the on region of the TFT and the -Vg side is the off region. The solid line indicates the initial characteristics, and the broken line indicates the deterioration characteristics due to the hot carrier injection phenomenon. In this structure, both the on-current and the off-current are high and the deterioration is large, so that it cannot be used as it is, for example, in the pixel TFT of the pixel matrix circuit.
[0017]
FIG. 17A-2 illustrates a structure in which a low-concentration impurity region serving as an LDD region is provided in (A-1) and does not overlap with the gate electrode. FIG. 2B-2 shows the characteristics of this TFT, which can suppress the off current to some extent, but cannot prevent the deterioration of the on current. FIG. 17A-3 shows a structure in which the LDD region completely overlaps with the gate electrode, which is also called a GOLD structure. FIG. 5B-3 shows characteristics corresponding to this, and the degradation can be suppressed to a level that does not cause a problem, but the off-current is increased on the −Vg side as compared with the structure of (A-2).
[0018]
On the other hand, the structure shown in FIG. 17A-4 can prevent deterioration and suppress an increase in off-state current as shown in FIG. 17B-4. This is an LDD region divided into two regions, a region overlapping with the gate electrode and a region not overlapping, suppressing the hot carrier injection phenomenon in the LDD region overlapping with the gate electrode, and The LDD region that does not overlap with the gate electrode also has an effect of preventing an increase in off current.
[0019]
In the present invention, in order to realize a TFT having a structure as shown in FIG. 17A-3 or A-4, an LDD region overlaps with a gate electrode in an n-channel TFT. Therefore, a gate electrode is formed from a first conductive layer and a second conductive layer, and after forming the first conductive layer, an impurity element imparting the n-type for the first time is added to form an LDD region. After the first impurity region is formed and the second conductive layer is formed, a second step of adding an impurity element imparting n-type is performed to form a second impurity region as a source region and a drain region To do. In this way, a structure in which the LDD region overlaps with the gate electrode is realized. Further, in order to provide an LDD region that does not overlap with the gate electrode, part of the second conductive layer may be removed.
[0020]
On the other hand, a p-channel TFT similarly has a gate electrode formed of a first conductive layer and a second conductive layer, but has a structure in which part of a third impurity region serving as a source region and a drain region overlaps with the gate electrode. And
[0021]
The first conductive layer is formed using one or more elements selected from titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or a material containing the element as a component. In the structure, at least one conductive layer (A) made of the above material and formed in contact with the gate insulating film, and one or more selected from aluminum (Al) and copper (Cu) on the conductive layer (A) It is preferable to form the conductive layer (B) made of the above element or a material containing the element as a component.
[0022]
The second conductive layer is formed of one or more elements selected from titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or an alloy material containing the element as a component.
[0023]
Further, in the structure of the pixel matrix circuit, a semiconductor layer that is provided in contact with the second impurity region of the pixel TFT and includes the impurity element at the same concentration as the first impurity region, and the same layer as the gate insulating film are formed. A storage capacitor is formed from the insulating layer and the capacitor wiring formed on the insulating layer. Alternatively, a semiconductor layer provided in contact with the second impurity region of the pixel TFT and containing the impurity element at the same concentration as the third impurity region, an insulating layer formed of the same layer as the gate insulating film, and the insulating layer A storage capacitor is formed from the capacitor wiring formed on the layer.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
An embodiment of the present invention will be described with reference to FIG. The substrate 301 is a substrate having an insulating surface. For example, a glass substrate, a stainless steel substrate, a plastic substrate, a ceramic substrate, or a silicon substrate provided with a silicon oxide film can be used. In addition, a quartz substrate may be used.
[0025]
The semiconductor layer formed on the substrate 301 is a crystalline semiconductor obtained by crystallizing an amorphous semiconductor film formed by a film forming method such as a plasma CVD method, a low pressure CVD method, or a sputtering method by a laser annealing method or a thermal annealing method. It is desirable to form with a film. Alternatively, a microcrystalline semiconductor formed by the above film formation method can be used. The semiconductor material that can be applied here is silicon, germanium, silicon and germanium alloy, or silicon carbide. In addition, a compound semiconductor material such as gallium arsenide can also be used.
[0026]
Alternatively, the semiconductor layer formed over the substrate 301 may be an SOI (Silicon On Insulators) substrate in which a single crystal silicon layer is formed. Several types of SOI substrates are known depending on their structures and manufacturing methods. Typically, SIMOX (Separation by Implanted Oxygen), ELTRAN (Epitaxial Layer Transfer: registered trademark of Canon Inc.) substrate, Smart- Cut (registered trademark of SOITEC) or the like can be used. Of course, other SOI substrates can also be used.
[0027]
FIG. 28 shows a cross-sectional structure of n-channel and p-channel TFTs formed on the substrate 301. The gate electrodes of the n-channel TFT and the p-channel TFT are composed of a first conductive layer and a second conductive layer. The first conductive layer includes conductive layers (A) 313 and 316 provided in contact with the gate insulating film 312, and conductive layers (B) 314 and 317 provided in contact with the conductive layers (A) 313 and 316. Consists of. The second conductive layers 315 and 318 are provided in contact with the conductive layers (A) 313 and 316 and the first conductive layers (B) 314 and 317 of the first conductive layer and the gate insulating film 312.
[0028]
The conductive layers (A) 313 and 316 constituting the first conductive layer are elements such as titanium (Ti), tantalum (Ta), molybdenum (Mo), tungsten (W), or a material containing these elements as components. Form. The conductive layers (B) 314 and 317 may be made of aluminum (Al) or copper (Cu) with low resistivity. Here, the conductive layer (B) is provided in consideration of forming the TFT of the present invention on a large-area substrate such as a liquid crystal display device, and is provided for the purpose of reducing the resistance of the gate electrode and the gate wiring. . Therefore, depending on the application, the first conductive layer may be formed of only the conductive layer (A), or another conductive layer may be stacked on the conductive layer (B).
[0029]
The second conductive layers 315 and 318 are formed so as to be in contact with the first conductive layer and extend from the first conductive layer to the gate insulating film 312. As shown in FIG. 31, when the lengths in the channel length direction of the first conductive layer and the second conductive layer are L1 and L2, respectively, it is sufficient that the relationship of L1 <L2 is maintained, and the present invention is implemented. The length should be set appropriately. However, as described below, the first conductive layer and the second conductive layer function as a mask for forming a source region, a drain region, and an LDD region by adding impurities to the semiconductor layer in the TFT manufacturing process. Therefore, it is necessary to determine the values of L1 and L2 in consideration of this point.
[0030]
The semiconductor layer of the n-channel TFT includes a channel formation region 302, first impurity regions 303 and 304 provided in contact with both sides of the channel formation region, a source region 305 provided in contact with the first impurity region 303, The drain region 306 is provided in contact with the first impurity region 304. The first impurity regions 303 and 304 are provided so as to overlap with a region where the second conductive layer 315 is in contact with the gate insulating film with the gate insulating film 312 interposed therebetween.
[0031]
The length of the first impurity regions 303 and 304 in the channel length direction is 0.5 to 3 μm, typically 1.5 μm, and the concentration of the impurity element imparting n-type is 1 × 10 6. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three , Typically 1 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three It is. The impurity concentration of the source region 305 and the drain region 306 is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three , Typically 1 × 10 ²⁰ ~ 5x10 ²⁰ atoms / cm ^Three And
[0032]
In the channel formation region 302, 1 × 10 3 is previously provided. ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three Boron may be added at a concentration of This boron is added to control the threshold voltage, and other elements can be substituted if the same effect can be obtained.
[0033]
On the other hand, an impurity element imparting p-type conductivity is added to the first impurity regions 308 and 309, the source region 310, and the drain region 311 of the p-channel TFT at the same concentration. Then, an impurity element imparting p-type is added at a concentration of 1.5 to 3 times the impurity concentration added to the source region 305 and the drain region 306 of the n-channel TFT.
[0034]
As described above, in the present invention, in the TFT structure, the gate electrode is provided with the first conductive layer, and the second conductive layer is provided thereon. As shown in FIG. 28, the gate insulating film and the second conductive layer are provided. The first conductive layer located between the conductive layers has an end formed inside the end of the second conductive layer. In addition, the structure in which the first impurity region provided in the semiconductor layer and the second conductive layer are provided to overlap each other has a feature, and the manufacturing method has a feature.
[0035]
The TFT shown in FIG. 28 has a structure in which first low-concentration impurity regions 303 and 304 functioning as so-called LDD regions are provided so as to overlap with a gate electrode through a gate insulating film, particularly in an n-channel TFT. Therefore, advantages such as the GOLD structure and LATID structure of the MOS transistor can be obtained.
[0036]
On the other hand, the p-channel TFT is not provided with such a low concentration impurity region having an LDD structure. Of course, a structure in which a low-concentration impurity region is provided may be used. However, since the p-channel TFT is originally highly reliable, it is preferable to gain on-current and balance the characteristics with the n-channel TFT. When the present invention is applied to a CMOS circuit as shown in FIG. 28, it is particularly important to balance this characteristic. However, there is no problem even if the structure of the present invention is applied to a p-channel TFT.
[0037]
When the n-channel TFT and the p-channel TFT are thus completed, the source electrodes 320 and 322 and the drain electrode 321 which are covered with the first interlayer insulating film 319 and are in contact with the source regions 305 and 311 and the drain regions 306 and 310 are provided. . In the structure of FIG. 28, after providing these, a silicon nitride film is provided as the passivation film 323. Further, a second interlayer insulating film 324 made of a resin material is provided.
The second interlayer insulating film need not be limited to a resin material. For example, when applied to a liquid crystal display device, it is preferable to use a resin material in order to ensure surface flatness.
[0038]
In FIG. 28, a CMOS circuit formed by complementary combination of an n-channel TFT and a p-channel TFT is shown as an example. However, the present invention is applied to an NMOS circuit using an n-channel TFT or a pixel matrix circuit of a liquid crystal display device. The invention can also be applied.
[0039]
[Embodiment 2]
An embodiment of the present invention will be described with reference to FIG. The substrate 101 has an insulating surface. For example, in addition to a glass substrate or a plastic substrate, a stainless steel substrate, a ceramic substrate, or a silicon substrate provided with an insulating film on the surface can be used. In addition, a quartz substrate may be used.
[0040]
A base film 102 is formed on the surface of the substrate 101 where the TFT is formed. The base film 102 is formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like, and is provided to prevent impurities from diffusing from the substrate 101 to the semiconductor layer.
[0041]
The semiconductor layer formed on the base film 102 is an amorphous semiconductor film formed by a film formation method such as a plasma CVD method, a low pressure CVD method, or a sputtering method by a solid phase growth method using a laser crystallization method or a heat treatment. It is desirable to form a crystallized crystalline semiconductor. Alternatively, a microcrystalline semiconductor formed by the above film formation method can be used. The semiconductor material applicable here is silicon, germanium, a silicon germanium alloy, or a silicon carbide alloy. In addition, a compound semiconductor material such as gallium arsenide can also be used. In addition, an SOI substrate may be used as in the first embodiment.
[0042]
FIG. 1 shows cross-sectional structures of an n-channel TFT and a p-channel TFT. The gate electrodes of the n-channel TFT and the p-channel TFT are composed of a first conductive layer and a second conductive layer. The first conductive layer has a three-layer structure. Conductive layers (A) 111 and 115 provided in contact with the gate insulating film 103 and conductive layers (B) 112 and 116 stacked thereon are provided. , Conductive layers (C) 113 and 117. The second conductive layers 114 and 118 are provided in contact with the first conductive layer and the gate insulating film 103.
[0043]
The conductive layers (A) 111 and 115 constituting the first conductive layer are formed of an element such as Ti, Ta, Mo, W, or an alloy material containing these elements as a main component. Alternatively, a nitride, oxide, or silicide of these elements may be used. The conductive layers (B) 112 and 116 are preferably made of Al or Cu having a low resistivity. Similarly to the conductive layer (A), the conductive layers (C) 113 and 117 are formed of an element such as Ti, Ta, Mo, W, or an alloy material containing these elements as a main component. Here, the conductive layer (B) is used for the purpose of reducing the resistance of the gate electrode and the gate wiring connected to the gate electrode in consideration of forming the TFT of the present invention on a large-area substrate such as a liquid crystal display device. It is provided. Depending on the application, the first conductive layer may be formed of only the conductive layer (A), or three or more layers may be laminated.
[0044]
The second conductive layers 114 and 118 are electrically connected to the first conductive layer and are provided in contact with the gate insulating film 103. Here, as shown in FIG. 16, the second conductive layer is formed with a length of L3 at first in the channel length direction, and then is removed by the length of L5 by an etching process, and finally the length of L2 is reached. Is done. Therefore, when the first conductive layer is L1, the length that the second conductive layer extends to the gate insulating film can be represented by L4.
[0045]
Here, in the present invention, the length L1 of the first conductive layer is 0.2 to 10 μm, preferably 0.4 to 5 μm, and the length L2 of the second conductive layer is 1.2 to 16 μm, preferably 2 It is desirable to form with a length of 2 to 11 μm. Here, the length L5 for removing the second conductive layer is 0.5 to 3 μm, preferably 1.0 to 2.0 μm.
[0046]
The first conductive layer and the second conductive layer function as a mask in the first step of adding the first conductive type impurity element and the second step of adding the first conductive type impurity element. It is necessary to determine the lengths of L1 and L3 and L2 and L5 in consideration of the points. The length of the LDD region of the n-channel TFT is formed by the length of the difference between L3 and L1. In order to obtain the configuration of the present invention, the second conductive layer is formed in advance with a length of L3, and then the length of L2 is removed by etching to remove the length of L2. This is because the region where the first impurity region 1605 to be a region overlaps with the second conductive layer through the gate insulating film has a length of L4, and a region which does not overlap has a length of L5.
[0047]
In FIG. 1, a semiconductor layer of an n-channel TFT is provided in contact with a channel formation region 104, a first impurity region 105 provided in contact with both sides of the channel formation region, and the first impurity region 105. The second impurity regions 106 and 107 are formed. The second impurity region 106 functions as a source region, and the second impurity region 107 functions as a drain region. The first impurity region 105 is provided so as to overlap with a region where the second conductive layer 114 is in contact with the gate insulating film with the gate insulating film 103 interposed therebetween.
[0048]
The length of the first impurity region 105 corresponding to L6 in FIG. 16 is 1.0 to 6 μm, preferably 2.0 to 4 μm (for example, 3 μm), and an impurity element imparting n-type conductivity Concentration of 1 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three , Typically 5 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three Is added. The length L5 at which the first impurity region does not overlap with the second conductive layer is 0.5 to 3 μm, preferably 1.0 to 2 μm as described above. The impurity concentration of the source region 105 and the drain region 106 is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three , Typically 2 × 10 ²⁰ ~ 5x10 ²⁰ atoms / cm ^Three What should I do?
[0049]
At this time, the channel formation region 104 is preliminarily set to 1 × 10 6. ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three Boron may be added at a concentration of. This boron is added to control the threshold voltage, and other elements can be substituted as long as the same effect can be obtained.
[0050]
On the other hand, the third impurity regions 109, 110, 130, and 131 of the p-channel TFT form a source region and a drain region. The third impurity regions 130 and 131 contain an impurity element imparting n-type in the same concentration as the source region 106 and the drain region 107 of the n-channel TFT. An impurity element imparting p-type at a concentration is added.
[0051]
As described above, the TFT of the present invention has a structure in which the gate electrode is provided with the first conductive layer and the second conductive layer. As shown in FIG. The conductive layer is in contact with the gate insulating film. At least in the n-channel TFT, there is a feature in a structure in which a part of the first impurity region is provided so as to overlap with a region in contact with the gate insulating film of the second conductive layer.
[0052]
In the structure shown in FIG. 1, a first impurity region that becomes an LDD region is formed using the first conductive layer as a mask, and a second impurity that becomes a source region and a drain region using the second conductive layer as a mask. After forming the region, it can be realized by retracting the second conductive layer by an etching process. Therefore, as shown in FIG. 16, the length of the LDD region is determined by the length L1 of the first conductive layer and the length L3 of the second conductive layer, and the LDD region does not overlap with the second conductive layer. The length can be determined by the length L5 for etching the second conductive layer. Such a method can increase the degree of freedom in designing or manufacturing a TFT, and is very effective.
[0053]
On the other hand, the third impurity regions 109, 110, 130, and 131 are formed in the p-channel TFT, and a region having an LDD structure is not provided. In the third impurity region, source regions 109 and 130 and drain regions 110 and 131 are formed. A part of the source region 109 and the drain region 110 overlaps with the second conductive layer. Of course, the LDD structure of the present invention may be provided. However, since the p-channel TFT is originally highly reliable, it is preferable to obtain an on-current and balance the characteristics with the n-channel TFT. When the present invention is applied to a CMOS circuit as shown in FIG. 1, it is particularly important to balance this characteristic. However, there is no problem even if the structure of the present invention is applied to a p-channel TFT.
[0054]
When the n-channel TFT and the p-channel TFT are thus completed, the source electrode 120 and the drain electrode 122 are provided by covering with the first interlayer insulating film 119. In the structure of FIG. 1, after providing these, a silicon nitride film is provided as the passivation film 123. Further, a second interlayer insulating film 124 made of a resin material is provided. The second interlayer insulating film need not be limited to a resin material. For example, when applied to a liquid crystal display device, it is preferable to use a resin material in order to ensure surface flatness.
[0055]
In FIG. 1, a CMOS circuit formed by complementary combination of an n-channel TFT and a p-channel TFT is shown as an example. However, the present invention is applied to an NMOS circuit using an n-channel TFT or a pixel matrix circuit of a liquid crystal display device. The invention can also be applied.
[0056]
The configuration of the present invention described above will be described in more detail in the following examples.
[0057]
[Example 1]
In this embodiment, an example in which the structure of the present invention is applied to a liquid crystal display device is shown, and a method of simultaneously manufacturing a pixel matrix circuit and a CMOS circuit which is a basic form of a driver circuit provided in the periphery thereof is shown in FIGS. Will be described.
[0058]
In FIG. 29A, an alkali-free glass substrate typified by a Corning 1737 glass substrate is used as the substrate 401, for example. Then, a base film 402 formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like is formed to a thickness of 200 nm on the surface of the substrate 401 where the TFT is formed.
[0059]
Next, an amorphous silicon film having a thickness of 50 nm is formed on the base film 402 by a plasma CVD method. Although depending on the amount of hydrogen contained in the amorphous silicon film, the dehydrogenation treatment is preferably performed by heating to 400 to 500 ° C., and the amount of hydrogen contained in the amorphous silicon film is set to 5 atomic% or less, and the crystallization step is performed. A crystalline silicon film is obtained.
[0060]
For this crystallization step, a laser annealing technique or a thermal annealing technique may be used. In this embodiment, a pulsed oscillation type KrF excimer laser beam is condensed into a linear shape and irradiated to an amorphous silicon film to form a crystalline silicon film.
[0061]
The configuration of the laser annealing apparatus used here is shown in FIG. The pulsed laser beam irradiated from the laser oscillation device 3201, changed in direction by the reflection mirror 3202, and changed in optical path by the optical system 3203 is reflected by the mirror 3207 and condensed by the optical system 3208 using a cylindrical lens. Thus, the substrate 3209 on which the amorphous silicon film is formed has a function of irradiating. As the laser oscillation device 3201, a XeCl excimer laser or a KrF excimer laser may be used. The substrate 3209 is set on the stage 3205.
[0062]
In this embodiment, the crystalline silicon film is formed from the amorphous silicon film. However, the microcrystalline silicon film may be crystallized by a laser annealing method, or the crystalline silicon film may be directly formed. .
[0063]
The crystalline silicon film thus formed is patterned to form island-like semiconductor layers 403, 404, and 405.
[0064]
Next, a gate insulating film 406 containing silicon oxide or silicon nitride as a main component is formed so as to cover the semiconductor layers 403, 404, and 405. Here, a silicon oxynitride film is formed to a thickness of 100 nm by a plasma CVD method. Then, although not illustrated in the drawing, a first conductive layer is formed on the surface of the gate insulating film 406. The first conductive layer is formed by sputtering with a thickness of Ta of 10 to 200 nm, for example, 50 nm as the conductive layer (A), and Al of 100 to 1000 nm, for example, 200 nm of the conductive layer (B). Then, conductive layers (A) 407, 408, 409, and 410 constituting the first conductive layer and conductive layers (B) 412, 413, 414, and 415 are formed by a known patterning technique. At this time, the first conductive layer shown in FIG. 31 is patterned to have a length L1 of 3 μm.
[0065]
When Al is used as the conductive layer (B) constituting the first conductive layer, pure Al may be used, and an element selected from Ti, Si, and Sc is added in an amount of 0.1 to 5 atomic%. Al alloy may also be used. In the case of using Cu, although not shown, it is preferable to provide a silicon nitride film on the surface of the gate insulating film 406.
[0066]
In FIG. 29, a storage capacitor is provided on the drain side of the pixel TFT of the pixel matrix circuit. At this time, the capacitor wirings 411 and 416 are formed using the same material as the first conductive layer.
[0067]
When the structure shown in FIG. 29A is thus formed, a first step of adding an impurity element imparting n-type conductivity is performed. Phosphorus (P), arsenic (As), antimony (Sb), and the like are known as impurity elements that impart n-type to crystalline conductor materials. Here, phosphine (PH) _Three Phosphorus is added by an ion doping method using In this step, in order to add phosphorus to the semiconductor layer thereunder through the gate insulating film 406, the acceleration voltage is set as high as 80 keV. Further, the impurity region thus formed is to form first impurity regions 434 and 442 of an n-channel TFT, which will be described later, and functions as an LDD region. Therefore, the concentration of phosphorus in this region is 1 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three In this embodiment, 1 × 10 is preferable. ¹⁸ atoms / cm ^Three And
[0068]
The impurity element added to the semiconductor layer needs to be activated by a laser annealing method or a thermal annealing method. This step may be performed after the step of adding the impurity element for forming the source region and the drain region, but it is effective to activate at this stage by a laser annealing method.
[0069]
In this step, the conductive layers (A) 407, 408, 409, and 410 and the conductive layers (B) 412, 413, 414, and 415 constituting the first conductive layer function as a mask against the addition of phosphorus. As a result, no or almost no phosphorus is added to the region immediately below the first conductive layer of the semiconductor layer existing through the gate insulating film. Then, as shown in FIG. 29B, impurity regions 417, 418, 419, 420, 421, 422, and 423 to which phosphorus is added are formed. In this specification, this impurity region is referred to as a first impurity region.
[0070]
Next, using the photoresist as a mask, the region for forming the n-channel TFT is covered with resist masks 424 and 425, and an impurity element imparting p-type is added only to the region where the p-channel TFT is formed. . Boron (B), aluminum (Al), and gallium (Ga) are known as impurity elements imparting p-type. In this embodiment, diborane (B ₂ H ₆ ) To add boron (B). Again, the acceleration voltage is 80 keV and 2 × 10 ²⁰ atmos / cm ^Three Boron is added to the concentration of. Then, as shown in FIG. 29C, regions 426 and 427 to which boron (B) is added at a high concentration are formed. In this specification, this region is referred to as a third impurity region, which will later be referred to as a source region and a drain region of a p-channel TFT.
[0071]
Then, after removing the resist masks 424 and 425, a step of forming a second conductive layer is performed. Here, Ta is used as the material of the second conductive layer, and is formed to a thickness of 100 to 1000 nm, for example, 200 nm. Then, patterning is performed by a known technique to form second conductive layers 428, 429, 430, and 431. At this time, patterning is performed so that the length L2 of the second conductive layer shown in FIG. 31 is 6 μm. As a result, in the second conductive layer, regions in contact with the gate insulating film are formed on both sides of the first conductive layer with a length of 1.5 μm.
[0072]
In addition, a storage capacitor is provided on the drain side of the pixel TFT of the pixel matrix circuit, and the storage capacitor wiring 432 is formed simultaneously with the second conductive layer.
[0073]
Then, a second step of adding an impurity element imparting n-type conductivity is performed using the second conductive layers 428, 429, 430, and 431 as masks. Phosphine (PH _Three In order to add phosphorus (P) to the underlying semiconductor layer through the gate insulating film 406, the acceleration voltage is set as high as 80 keV. Here, the region to which phosphorus (P) is added functions as source regions 435 and 443 and drain regions 434, 444 and 447 by n-channel TFTs, and the concentration of phosphorus in this region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atmos / cm ^Three Is preferred, here 1 × 10 ²⁰ atmos / cm ^Three (FIG. 29D).
[0074]
Although not shown here, the gate insulating film covering the source regions 435 and 443 and the drain regions 436, 444 and 447 may be removed, and the semiconductor layer in the regions may be exposed to add phosphorus directly. By this treatment, the acceleration voltage of the ion doping method can be lowered to 10 keV, and phosphorus can be added efficiently.
[0075]
Further, phosphorus is added to the source region 439 and the drain region 440 of the p-channel TFT at the same concentration, but the conductivity type is not reversed because boron is added at twice the concentration in the previous step. There is no problem in the operation of the p-channel TFT.
[0076]
Since the impurity element imparting n-type or p-type added at each concentration is not activated as it is and does not act effectively, it is necessary to perform an activation process. This step can be performed by a thermal annealing method using an electric heating furnace, a laser annealing method using the above-described excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp.
[0077]
In the thermal annealing method, activation is performed by heating at 550 ° C. for 2 hours in a nitrogen atmosphere. In this embodiment, Al is used for the conductive layer (B) constituting the first conductive layer, but the conductive layer (A) formed of Ta and the second conductive layer are formed so as to cover the Al. , Ta functions as a blocking layer, and Al atoms can be prevented from diffusing into other regions. In the laser annealing method, activation is performed by condensing and irradiating a pulse oscillation type KrF excimer laser beam in a line with an apparatus having the same configuration as that shown in FIG. Further, better results can be obtained when the thermal annealing method is performed after the laser annealing method. This process also has the effect of annealing a region where the crystallinity is destroyed by ion doping, and can improve the crystallinity of the region.
[0078]
Through the above steps, the gate electrode is provided with the first conductive layer and the second conductive layer is provided so as to cover the first conductive layer. In the n-channel TFT, the source region is formed on both sides of the second conductive layer. And a drain region are formed. In addition, a structure in which the first impurity region provided in the semiconductor layer through the gate insulating film overlaps with the region in contact with the gate insulating film of the second conductive layer is formed in a self-aligned manner. . On the other hand, in the p-channel type TFT, a part of the source region and the drain region overlaps with the second conductive layer, but there is no problem in practical use.
[0079]
When the state of FIG. 29D is obtained, a first interlayer insulating film 449 is formed to a thickness of 1000 nm. As the first interlayer insulating film 449, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used. In this embodiment, although not shown, a two-layer structure is formed in which a silicon nitride film is first formed to 50 nm and a silicon oxide film is further formed to 950 nm.
[0080]
The first interlayer insulating film 449 forms contact holes that reach the source region and the drain region of each TFT by patterning. Then, source wirings 450, 452, and 453 and drain wirings 451 and 454 are formed. Although not shown, in this embodiment, this electrode is formed by patterning a film having a three-layer structure in which a Ti film of 100 nm, an Al film containing Ti of 300 nm, and a Ti film of 150 nm are successively laminated by sputtering.
[0081]
Thus, as shown in FIG. 29E, a CMOS circuit and a pixel matrix circuit are formed over the substrate 401. A storage capacitor is simultaneously formed on the drain side of the n-channel TFT of the pixel matrix circuit. As described above, an active matrix substrate can be manufactured.
[0082]
Next, a process of manufacturing an active matrix liquid crystal display device based on a CMOS circuit and a pixel matrix circuit manufactured on the same substrate by the above process will be described with reference to FIGS. First, a passivation film 455 is formed on the substrate in the state of FIG. 29E so as to cover the source wirings 450, 452, 453, the drain wirings 451, 454, and the first interlayer insulating film 445. The passivation film 455 is a silicon nitride film with a thickness of 50 nm. Further, a second interlayer insulating film 456 made of an organic resin is formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. An organic resin film other than those described above can also be used. Here, it is formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate (FIG. 30A).
[0083]
Next, a light shielding layer 457 is formed in part of the pixel region of the second interlayer insulating film 456. The light shielding layer 457 may be formed of a metal film or an organic resin film containing a pigment. Here, a Ti film is formed by sputtering to form a light shielding film.
[0084]
After the light shielding film 457 is formed, a third interlayer insulating film 458 is formed. The third interlayer insulating film 458 is preferably formed using an organic resin film in the same manner as the second interlayer insulating film 456. Then, a contact hole reaching the drain wiring 454 is formed in the second interlayer insulating film 456 and the third interlayer insulating film 458, and a pixel electrode 459 is formed. The pixel electrode 459 may be a transparent conductive film in the case of a transmissive liquid crystal display device, and a metal film in the case of a reflective liquid crystal display device. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by a sputtering method, and a pixel electrode 459 is formed.
[0085]
Etching treatment of the material of the transparent conductive film is performed with a hydrochloric acid based solution. However, since etching of ITO tends to generate residues, an indium oxide-zinc oxide alloy (In ₂ O _Three —ZnO) may also be used. Indium zinc oxide alloy is characterized by excellent surface smoothness and thermal stability compared to ITO. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to further increase the transmittance and conductivity of visible light can be used.
[0086]
When the state of FIG. 30A is formed, an alignment film 460 is formed. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A transparent conductive film 472 and an alignment film 473 are formed on the opposite substrate 471. The alignment film is then subjected to a rubbing process so that the liquid crystal molecules are aligned in parallel with a certain pretilt angle.
[0087]
Through the above steps, the substrate on which the pixel matrix circuit and the CMOS circuit are formed and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown) and the like by a known cell assembling process. Thereafter, a liquid crystal material 474 is injected between both the substrates and completely sealed with a sealant (not shown). Thus, the active matrix liquid crystal display device shown in FIG. 30B is completed.
[0088]
[Example 2]
In this embodiment, the structure of the present invention will be described as a method for simultaneously manufacturing a CMOS circuit which is a basic form of a pixel matrix circuit and a driver circuit provided in the periphery thereof.
[0089]
In FIG. 2, as the substrate 201, for example, a non-alkali glass substrate typified by Corning 1737 glass substrate is used. Then, a base film 202 is formed on the surface of the substrate 201 on which the TFT is formed. As the base film 202, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like is used.
[0090]
The base film 202 may be formed of one layer of the above material or a stacked structure of two or more layers. In any case, it is formed to have a thickness of about 100 to 300 nm. For example, SiH by plasma CVD method _Four , NH _Three , N ₂ A first silicon oxynitride film made of O is formed to a thickness of 10 to 100 nm, and SiH _Four , N ₂ The base film 102 is formed as a two-layer structure in which a second silicon oxynitride film manufactured from O is stacked to a thickness of 100 to 200 nm.
[0091]
The first silicon oxynitride film is formed by using a conventional parallel plate type plasma CVD method. The silicon oxynitride film is SiH _Four 10SCCM, NH _Three To 100 SCCM, N ₂ O was introduced into the reaction chamber as 20 SCCM, the substrate temperature was 325 ° C., the reaction pressure was 40 Pa, and the discharge power density was 0.41 W / cm. ² The discharge frequency was 60 MHz. On the other hand, the second silicon oxynitride film is made of SiH. _Four 4SCCM, N ₂ O was introduced into the reaction chamber as 400 SCCM, the substrate temperature was 400 ° C., the reaction pressure was 40 Pa, and the discharge power density was 0.41 W / cm. ² The discharge frequency was 60 MHz. These films can be formed continuously only by changing the substrate temperature and switching the reaction gas. The first silicon oxynitride film is formed so that the internal stress becomes a tensile stress with the substrate as the center. The second silicon oxynitride film is also given an internal stress in the same direction, but the stress is smaller than the first silicon oxynitride film in terms of absolute value.
[0092]
Next, an amorphous silicon film having a thickness of 30 to 80 nm, for example 50 nm, is formed on the base film 202 by plasma CVD. Thereafter, although depending on the amount of hydrogen contained in the amorphous silicon film, it is desirable to perform a dehydrogenation treatment by heating to 400 to 500 ° C., and to perform a crystallization step with the amount of hydrogen contained being 5 atomic% or less. .
[0093]
The step of crystallizing the amorphous silicon film is performed by a laser annealing method or a thermal annealing method. In this embodiment, a pulse oscillation type KrF excimer laser beam is condensed into a linear shape and irradiated to an amorphous silicon film to form a crystalline silicon film.
[0094]
In this embodiment, an amorphous silicon film is used. However, a microcrystalline silicon film may be used, or a crystalline silicon film may be directly formed.
[0095]
The crystalline silicon film thus formed is patterned to form island-shaped semiconductor layers 204, 205, and 206.
[0096]
Next, a gate insulating film 203 containing silicon oxide or silicon nitride as a main component is formed so as to cover the semiconductor layers 204, 205, and 206. For example, a silicon oxynitride film is formed to a thickness of 100 nm by plasma CVD. Although not illustrated in the figure, a Ta film is formed as a conductive layer (A) constituting a first conductive layer of the gate electrode on the surface of the gate insulating film 203 to a thickness of 10 to 200 nm, for example, 50 nm, and a conductive layer. As (B), an Al film was formed by sputtering at a thickness of 100 to 1000 nm, for example, 200 nm. Then, conductive layers (A) 207, 208, 209 and 210 and conductive layers (B) 212, 213, 214 and 215 constituting the first conductive layer are formed by a known patterning technique. At this time, the length L1 of the first conductive layer shown in FIG. 16 may be determined as appropriate, and patterning is performed with a length of 0.2 to 10 μm, here 3 μm (FIG. 2A).
[0097]
When Al is used as the conductive layer (B) constituting the first conductive layer, pure Al may be used, and an element selected from Ti, Si, and Sc is added in an amount of 0.1 to 5 atomic%. Al alloy may also be used. In the case of using copper, although not shown, it is preferable to provide a silicon nitride film with a thickness of 30 to 100 nm on the surface of the gate insulating film 203.
[0098]
When a Ta film is used for the conductive layers (A) 207, 208, 209, and 210, they can be similarly formed by sputtering. The Ta film uses Ar as a sputtering gas. In addition, when an appropriate amount of Xe or Kr is added to these sputtering gases, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used as a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for a gate electrode. However, since the TaN film has a crystal structure close to an α phase, an α phase Ta film can be easily obtained by forming a Ta film thereon. Therefore, although not shown, a TaN film having a thickness of 10 to 50 nm may be formed under the conductive layers (A) 207, 208, 209, and 210. Similarly, although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A). This improves adhesion and prevents oxidation of the conductive film formed thereon, and at the same time, the alkali metal element contained in a trace amount in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 203. Can be prevented. In any case, the conductive layer (A) preferably has a resistivity in the range of 10 to 50 μΩcm.
[0099]
In addition, it is also possible to use a W film for the conductive layers (A) 207, 208, 209, and 210, in which case argon (Ar) gas and nitrogen (N ₂ ) Gas is introduced to form the conductive layer (A) with a W film to a thickness of 200 nm. In addition, W film is made of tungsten hexafluoride (WF ₆ Can also be formed by a thermal CVD method. In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less.
The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in the W film, the crystallization is hindered and the resistance is increased. Therefore, in the case of sputtering, the resistivity is obtained by using a W target with a purity of 99.9999% and forming a W film with sufficient consideration so that impurities are not mixed in the gas phase during film formation. 9-20 μΩcm can be realized.
[0100]
In FIG. 2, a storage capacitor is provided on the drain side of the pixel TFT of the pixel matrix circuit. At this time, wirings 211 and 216 having storage capacitors are formed using the same material as the first conductive layer.
[0101]
After the structure shown in FIG. 2A is formed in this manner, a first impurity region imparting n-type conductivity is added to form a first impurity region. Phosphorus (P), arsenic (As), antimony (Sb), and the like are known as impurity elements that impart n-type to crystalline semiconductor materials. For example, phosphorous is used to form phosphine (PH _Three ) Using an ion doping method. In this step, the acceleration voltage was set as high as 80 keV in order to add phosphorus to the underlying semiconductor layer through the gate insulating film 203. The first impurity region formed in this way forms the first impurity regions 229, 236, and 240 of the n-channel TFT described later and functions as an LDD region. Therefore, the concentration of phosphorus in this region is 1 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three In the range of 1 × 10 ¹⁸ atoms / cm ^Three (FIG. 2B).
[0102]
The impurity element added to the semiconductor layer needs to be activated by a laser annealing method or a thermal annealing method. This step may be performed after the step of adding an impurity element for forming a source region and a drain region, but it is effective to activate at this stage by a laser annealing method.
[0103]
In this step, the conductive layers (A) 207, 208, 209, and 210 and the conductive layers (B) 212, 213, 214, and 215 included in the first conductive layer function as a mask with respect to the addition of phosphorus. As a result, no or almost no phosphorus is added to the region of the semiconductor layer overlapping the first conductive layer. Here, as shown in FIG. 2B, first impurity regions 218, 219, 220, 221, and 222 to which phosphorus is added are formed.
[0104]
Next, using the photoresist film as a mask, the region for forming the n-channel TFT is covered with the resist masks 225 and 226, and an impurity addition step for imparting p-type is performed only on the region where the p-channel TFT is formed. . Known impurity elements imparting p-type include boron (B), aluminum (Al), and gallium (Ga). Here, boron is used as the impurity element, and diborane (B ₂ H ₆ To the semiconductor layer by ion doping. The acceleration voltage is 80 keV and 2 × 10 ²⁰ atoms / cm ^Three Boron is added to the concentration of. Then, as shown in FIG. 2C, third impurity regions 227 and 228 to which boron is added at a high concentration are formed. This third impurity region will later become the source region and drain region of the p-channel TFT (FIG. 2C).
[0105]
Then, after removing the resist masks 225 and 226, a step of forming a second conductive layer is performed. Ta is used as the material, and is formed to a thickness of 100 to 1000 nm (for example, 200 nm). Then, patterning is performed by a known technique to form second conductive layers 243, 244, 245, and 246. At this time, as shown in FIG. 16, patterning is performed so that the length L3 of the second conductive layer in the channel length direction is 1.3 to 20 μm, for example, 9 μm. As a result, in the second conductive layer, regions (L6) in contact with the gate insulating film with a length of 3 μm are formed on both sides of the first conductive layer.
[0106]
In addition, a storage capacitor is provided on the drain side of the n-channel TFT (pixel TFT) constituting the pixel matrix circuit, and the electrode 247 of the storage capacitor is formed simultaneously with the second conductive layer.
[0107]
Then, using the second conductive layers 243, 244, 245, and 246 as masks, a second impurity element imparting n-type conductivity is added to form second impurity regions. At this time, as shown in FIG. 3A, the resist masks 283, 284, 285, 286, and 287 provided when the second conductive layer is patterned may be left as they are. Impurity elements are added using phosphine (PH _Three ) Using an ion doping method. Also in this step, in order to add phosphorus to the semiconductor layer thereunder through the gate insulating film 203, the acceleration voltage was set as high as 80 keV. Since the second impurity region formed here functions as the source region 230, 237 and the drain region 231, 238, 241 of the n-channel TFT, the phosphorus concentration in this region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three In this embodiment, 1 × 10 is preferable. ²⁰ atoms / cm ^Three (FIG. 3A).
[0108]
Although not shown here, the gate insulating film covering the source regions 230, 237, and 289 and the drain regions 231, 238, 241, and 288 is removed, the semiconductor layers in the regions are exposed, and phosphorus is added directly. May be. When this step is added, the acceleration voltage of the ion doping method can be reduced to 10 keV, and phosphorus can be efficiently added.
[0109]
Further, phosphorus is added to the third impurity regions 288 and 289 of the p-channel TFT at the same concentration. However, since boron is added at twice that concentration, the conductivity type is not reversed. There is no problem in the operation of the p-channel TFT. In the p-channel TFT, the third impurity regions 234, 289, 233 and 288 form source regions 234 and 289 and drain regions 233 and 288, respectively. At this time, the source region 234 and the drain region 233 are formed so as to overlap with the second conductive layer 244.
[0110]
When the state of FIG. 3A is obtained, the resist masks 283, 284, 285, 286, and 287 are removed, a photoresist film is formed again, and a resist mask is formed by exposure from the back surface. At this time, as shown in FIG. 3B, resist masks 248, 249, 250, 256, and 257 are formed in a self-aligning manner using the first and second conductive layers as masks. Exposure from the back surface is performed using direct light and scattered light. By overexposure, a resist mask can be provided inside the second conductive layer as shown in FIG.
[0111]
Then, the unmasked region of the second conductive layer is removed by etching.
Etching may be performed using ordinary dry etching technology, and CF _Four And O ₂ Use gas. Then, as shown in FIG. 3C, the length L5 is removed. The length of L5 may be appropriately adjusted in the range of 0.5 to 3 μm, and here it is 1.5 μm. As a result, in the n-channel TFT, a region overlapping with the second conductive layer is formed with a length of 1.5 μm (L4) out of the length of 3 μm of the first impurity region serving as the LDD region, and 1.5 μm. A region which does not overlap with the second conductive layer with a length of (L5) could be formed.
[0112]
Since the impurity element imparting n-type or p-type added at each concentration is not activated as it is and does not act effectively, it is necessary to perform an activation process. This step can be performed by a thermal annealing method using an electric heating furnace, a laser annealing method using the above-described excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp.
[0113]
In the thermal annealing method, activation is performed by heat treatment in a nitrogen atmosphere at 300 to 700 ° C., preferably 350 to 550 ° C., for example, 450 ° C. for 2 hours. In this embodiment, Al is used for the conductive film (B) constituting the first conductive layer, and the conductive film (A) made of Ta and the second conductive layer are formed to cover Al. Therefore, Ta functions as a blocking layer, and Al atoms can be prevented from diffusing into other regions. In the laser annealing method, activation is performed by converging and irradiating pulse oscillation type KrF excimer laser light in a linear shape. Further, better results can be obtained when the thermal annealing method is performed after the laser annealing method. This step also has the effect of annealing the region where the crystallinity is destroyed by the ion doping method, and the crystallinity of the region can be improved.
[0114]
Through the above steps, the gate electrode is provided with the first conductive layer, the second conductive layer is provided in contact with the first conductive layer, and the semiconductor layers 204 and 206 include the first impurity region serving as the LDD region, A second impurity region to be a source region and a drain region is formed. In the first impurity region, a region that does not overlap with the region overlapping with the second conductive layer is formed through the gate insulating film. On the other hand, in a p-channel TFT, a channel formation region, a source region, and a drain region are formed.
[0115]
When the steps up to FIG. 3B are completed, the resist masks 248, 249, 250, 256, and 257 are removed, and a first interlayer insulating film 263 is formed to a thickness of 500 to 1500 nm. As the first interlayer insulating film 263, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used. In this embodiment, although not shown, a two-layer structure is formed in which a silicon nitride film is first formed to 50 nm and a silicon oxide film is further formed to 950 nm. Or SiH _Four And N ₂ A silicon oxynitride film formed from O may be formed to a thickness of 1000 nm.
[0116]
Thereafter, contact holes reaching the source region and the drain region of the respective semiconductor layers are formed in the first interlayer insulating film 263. Then, source wirings 264, 265, 266 and drain wirings 267, 268 are formed. Although not shown, in this embodiment, this wiring has a three-layer structure, and is continuously formed by sputtering with a thickness of a Ti film of 100 nm, an Al film containing Ti of 300 nm, and a Ti film of 150 nm.
[0117]
Then, a passivation film 269 is formed so as to cover the source electrodes 264, 265, 266, the drain electrodes 267, 268, and the first interlayer insulating film 263. The passivation film 269 is a silicon nitride film formed with a thickness of 50 nm. Further, a second interlayer insulating film 270 made of an organic resin is formed with a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Organic resin films other than those described above can also be used. Here, after applying to the substrate, a thermal polymerization type polyimide is used and baked at 300 ° C.
[0118]
Thus, as shown in FIG. 3C, an active matrix substrate in which a CMOS circuit and a pixel TFT of a pixel matrix circuit are formed over a substrate 201 is manufactured.
Further, a storage capacitor is simultaneously formed on the drain side of the pixel TFT of the pixel matrix circuit.
[0119]
[Example 3]
In this embodiment, after the state shown in FIG. 3A is obtained in the same process as that of Embodiment 1, a part of the second conductive layer is removed by another method so that the first impurity region is the second impurity region. An example in which a region overlapping with a conductive layer and a region not overlapping with the conductive layer are formed will be described.
[0120]
First, as shown in FIG. 3A, the resist masks 283, 284, 285, 286, and 287 used in the patterning process of the second conductive layer are used as they are, and one of the second conductive layers is etched. The part is removed by the length of L5 as shown in FIG.
[0121]
This step can be performed by dry etching. Although it depends on the material of the second conductive layer, isotropic etching proceeds basically by using a fluorine (F) gas, and the second conductive layer material under the resist mask can be removed. it can. For example, in the case of Ta, CF _Four Gas is possible, and in the case of Ti, CF _Four And CCl _Four It is possible with gas, and in the case of Mo, SF ₆ And NF _Three Is possible.
[0122]
Then, as shown in FIG. 4A, the length of L5 is removed here by 1.5 μm. As a result, in the n-channel TFT, the first impurity region serving as the LDD region is formed with a length (L6) of 3 μm and overlaps with the second conductive layer with a length (L4) of 1.5 μm. A region that does not overlap with the second gate electrode can be formed with a length (L5) of 1.5 μm.
[0123]
Then, the resist masks 283, 284, 285, 286, and 287 are removed, and an activation process is performed in the same manner as in the first embodiment, so that the first interlayer insulating film 263, the source wirings 264, 265, 266, the drain wiring 267, An active matrix substrate shown in FIG. 4B can be formed by forming 268, a passivation film 269, and a second interlayer insulating film 270.
[0124]
[Example 4]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate formed in Embodiments 1 to 3 and Embodiment 5 will be described.
[0125]
A contact hole reaching the drain electrode 268 is formed in the second interlayer insulating film 270 in the active matrix substrate in the state of FIG. 3C or FIG. 4B, and the pixel electrode 271 is formed. As the pixel electrode 271, a transparent conductive film is used when a transmissive liquid crystal display device is used, and a metal film may be used when a reflective liquid crystal display device is used. Here, in order to obtain a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by a sputtering method, and a pixel electrode 271 is formed.
[0126]
After the state shown in FIG. 5A is formed, an alignment film 272 is formed over the second interlayer insulating film 270 and the pixel electrode 271. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A transparent conductive film 274 and an alignment film 275 are formed on the opposite substrate 273. After the alignment film is formed, a rubbing process is performed so that the liquid crystal molecules are aligned in parallel with a certain pretilt angle.
[0127]
Through the above steps, the pixel matrix circuit, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are bonded to each other via a sealing material, a spacer (both not shown), or the like by a known cell assembly process. Thereafter, a liquid crystal material 276 is injected between both substrates and completely sealed with a sealant (not shown). Thus, the active matrix liquid crystal display device shown in FIG. 5B is completed.
[0128]
Next, the structure of the active matrix liquid crystal display device of this embodiment will be described with reference to FIGS. FIG. 7 is a perspective view of the active matrix substrate of this embodiment.
The active matrix substrate includes a pixel matrix circuit 701 formed on the glass substrate 201, a scanning (gate) line side driving circuit 702, and a data (source) line side driving circuit 703. A pixel TFT 700 of the pixel matrix circuit is an n-channel TFT, and a driving circuit provided in the periphery is configured based on a CMOS circuit. The scanning (gate) line side driving circuit 702 and the data (source) line side driving circuit 703 are connected to the pixel matrix circuit 701 by a gate wiring 802 and a source wiring 803, respectively.
[0129]
FIG. 8A is a top view of the pixel matrix circuit 701, which is a top view of almost one pixel. The pixel matrix circuit is provided with a pixel TFT. A gate electrode 820 formed continuously with the gate wiring 802 intersects the semiconductor layer 801 thereunder via a gate insulating film (not shown). Although not shown, a source region, a drain region, and a first impurity region are formed in the semiconductor layer. On the drain side of the pixel TFT, a storage capacitor 807 is formed from a semiconductor layer, a gate insulating film, and a capacitor wiring 821 formed of the same material as the first and second conductive layers. 8A corresponds to the cross-sectional view of the pixel TFT of the pixel matrix circuit shown in FIG. 3C or FIG. 4C.
[0130]
On the other hand, in the CMOS circuit shown in FIG. 8B, the gate electrodes 813 and 814 extending from the gate wiring 815 intersect with the semiconductor layers 810 and 812 thereunder through a gate insulating film (not shown). Yes. Although not shown, similarly, a source region, a drain region, and a first impurity region are formed in the semiconductor layer 810 of the n-channel TFT. A source region and a drain region are formed in the semiconductor layer 812 of the p-channel TFT. A cross-sectional structure along the line BB ′ corresponds to the cross-sectional view of the pixel matrix circuit shown in FIG. 3C or 4C.
[0131]
In this embodiment, the pixel TFT 700 has a double gate structure, but may have a single gate structure or a multi-gate structure with a triple gate. The structure of the active matrix substrate of this embodiment is not limited to the structure of this embodiment. The structure of the present invention is characterized by the structure of the gate electrode, and the structure of the source region, drain region, and other impurity regions of the semiconductor layer provided via the gate insulating film. The practitioner should make a proper decision.
[0132]
[Example 5]
The present embodiment is the same process as the second embodiment, but shows an example in which the structure of the second conductive layer is different between the pixel TFT of the pixel matrix circuit and the n-channel TFT and the p-channel TFT of the CMOS circuit. At this time, as shown in FIG. 6A, the second conductive layers 290 and 291 are in contact with the first conductive layer and extend only to the drain side of each TFT. In the CMOS circuit, even when the second conductive layer of the n-channel TFT has such a shape, the high electric field region formed on the drain side of the TFT can be relaxed. On the other hand, the second conductive layers 292 and 293 and the capacitor wiring 294 of the pixel TFT are formed in the same manner as in the first embodiment.
[0133]
The steps of this embodiment may basically follow the steps shown in Embodiment 2, and the shape of the second conductive layer is changed only by changing the photomask used in the patterning step, and other steps are changed. There is no need. However, the first impurity region of the n-channel TFT is formed only on the drain region side.
[0134]
Then, as shown in FIG. 6B, the resist masks 223, 224, 225, 226, and 227 are removed, a photoresist film is formed again, and patterning is performed by exposure from the back surface. At this time, as shown in FIG. 6B, resist masks 248, 249, 250, 256, and 257 are formed in a self-aligning manner using the first and second conductive layers as masks. Exposure from the back surface is performed using direct light and scattered light. By overexposure, a resist mask can be provided inside the second conductive layer as shown in FIG. 6B.
[0135]
Then, the unmasked region of the second conductive layer is removed by etching.
Etching may be performed using ordinary dry etching technology, and CF _Four And O ₂ Use gas. Then, as shown in FIG. 6C, the length L5 is removed. The length of L5 may be appropriately adjusted in the range of 0.5 to 3 μm, and here it is 1.5 μm. As a result, in the n-channel TFT, a region overlapping with the second conductive layer is formed with a length of 1.5 μm (L4) out of the length of 3 μm of the first impurity region serving as the LDD region, and 1.5 μm. A region which does not overlap with the second gate electrode with a length of (L5) can be formed. The subsequent steps are performed in the same manner as in Example 1, so that the active matrix substrate shown in FIG. 6C is formed.
[0136]
[Example 6]
In this example, an example in which a crystalline semiconductor film used as a semiconductor layer in Embodiments 1 and 2 and Examples 1, 2, 3, and 5 is formed by a thermal annealing method using a catalytic element is shown. In the case of using a catalyst element, it is desirable to use the techniques disclosed in Japanese Patent Application Laid-Open Nos. 7-130652 and 8-78329.
[0137]
Here, FIG. 9 shows an example in which the technique disclosed in Japanese Patent Laid-Open No. 7-130652 is applied to the present invention. First, a silicon oxide film 902 was provided over a substrate 901, and an amorphous silicon film 903 was formed thereon. Further, a nickel acetate salt solution containing 10 ppm of nickel by weight is applied to form a nickel-containing layer 904 (FIG. 9A).
[0138]
Next, after a dehydrogenation step at 500 ° C. for 1 hour, a heat treatment is performed at 500 to 650 ° C. for 4 to 12 hours, for example, 550 ° C. for 8 hours to form a crystalline silicon film 905. The crystalline silicon film 905 thus obtained has extremely excellent crystallinity (FIG. 9B).
[0139]
Further, the technique disclosed in Japanese Patent Laid-Open No. 8-78329 enables selective crystallization of an amorphous semiconductor film by selectively adding a catalytic element. The case where this technology is applied to the present invention will be described with reference to FIG.
[0140]
First, a silicon oxide film 1002 is provided over a glass substrate 1001, and an amorphous silicon film 1003 and a silicon oxide film 1004 are successively formed thereon. At this time, the thickness of the silicon oxide film 1004 is 150 nm.
[0141]
Next, the silicon oxide film 1004 is patterned to selectively form the opening 1005, and then a nickel acetate salt solution containing 10 ppm of nickel in terms of weight is applied. Thus, a nickel-containing layer 1006 is formed, and the nickel-containing layer 1006 is in contact with the amorphous silicon film 1002 only at the bottom of the opening portion 1005 (FIG. 10A).
[0142]
Next, heat treatment is performed at 500 to 650 ° C. for 4 to 24 hours, for example, 570 ° C. for 14 hours to form a crystalline silicon film 1007. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is crystallized first, and then proceeds laterally from there. The crystalline silicon film 1007 formed in this way is formed by a collection of rod-like or needle-like crystals, and each crystal grows in a specific direction as viewed macroscopically, and therefore has a uniform crystallinity. (FIG. 10B).
[0143]
In addition to nickel (Ni), the catalyst elements that can be used in the above two technologies are iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt). ), Copper (Cu), gold (Au), or the like may be used.
[0144]
A crystalline TFT semiconductor layer can be formed by forming a crystalline semiconductor film (including a crystalline silicon film and a crystalline silicon germanium film) using the above-described technique and performing patterning. A TFT manufactured from a crystalline semiconductor film by using the technique of this embodiment can provide excellent characteristics, but is required to have high reliability. However, by adopting the TFT structure of the present invention, it is possible to manufacture a TFT that makes the best use of the technique of this embodiment.
[0145]
[Example 7]
In this example, as a method for forming a semiconductor layer used in Embodiments 1, 2, and Examples 1, 2, 3, 5, a crystalline semiconductor film using an amorphous semiconductor film as an initial film and the catalyst element is used. An example of performing a process of removing the catalytic element from the crystalline semiconductor film after forming the substrate is shown. In this embodiment, as the method, the technique described in JP-A-10-247735, JP-A-10-135468, or JP-A-10-135469 is used.
[0146]
The technique described in the publication is a technique for removing a catalytic element used for crystallization of an amorphous semiconductor film by using a gettering action of phosphorus after crystallization. By using this technique, the concentration of the catalytic element in the crystalline semiconductor film can be reduced to 1 × 10. ¹⁷ atoms / cm ^Three Or less, preferably 1 × 10 ¹⁶ atoms / cm ^Three It can be reduced to.
[0147]
The configuration of this embodiment will be described with reference to FIG. As the glass substrate 1101, a non-alkali glass substrate typified by Corning 1737 substrate is used. FIG. 11A shows a state in which a base 1102 and a crystalline silicon film 1103 are formed by using the crystallization technique shown in Embodiment 5. A silicon oxide film 1104 for masking is formed to a thickness of 150 nm on the surface of the crystalline silicon film 1103, an opening is provided by patterning, and a region where the crystalline silicon film is exposed is provided. Then, a step of adding phosphorus is performed to provide a region 1105 in which phosphorus is added to the crystalline silicon film.
[0148]
In this state, when heat treatment is performed in a nitrogen atmosphere at 550 to 800 ° C. for 5 to 24 hours, for example, 600 ° C. for 12 hours, the region 1105 in which phosphorus is added to the crystalline silicon film functions as a gettering site, The catalytic element remaining in the porous silicon film 1103 can be segregated in the region 1105 to which phosphorus is added.
[0149]
Then, the silicon oxide film 1104 for mask and the region 1105 to which phosphorus is added are removed by etching, so that the concentration of the catalytic element used in the crystallization step is 1 × 10 6. ¹⁷ atoms / cm ^Three A crystalline silicon film reduced to the following can be obtained. This crystalline silicon film can be used as it is as the semiconductor layer of the TFT of the present invention shown in Examples 1, 2, and 4.
[0150]
[Example 8]
In this example, another example of forming a semiconductor layer and a gate insulating film in the process of manufacturing the TFT of the present invention shown in Embodiment Modes 1 and 2 and Examples 1, 2, 3, and 5 will be described. The configuration of this embodiment will be described with reference to FIG.
[0151]
Here, a substrate having heat resistance of at least about 700 to 1100 ° C. is necessary, and a quartz substrate 1201 is used. Then, a crystalline semiconductor is formed using the technique shown in the fifth embodiment. In order to make this a semiconductor layer of a TFT, semiconductor layers 1202 and 1203 are formed by patterning into island shapes. Then, the gate insulating film 1204 was formed using a film containing silicon oxide as a main component so as to cover the semiconductor layers 1202 and 1203. In this embodiment, a silicon oxynitride film is formed with a thickness of 70 nm by a plasma CVD method (FIG. 12A).
[0152]
Then, heat treatment is performed in an atmosphere containing halogen (typically chlorine) and oxygen.
In this embodiment, the temperature is 950 ° C. and 30 minutes. The treatment temperature may be selected in the range of 700 to 1100 ° C., and the treatment time may be selected from 10 minutes to 8 hours (FIG. 12B).
[0153]
As a result, under the conditions of this embodiment, a thermal oxide film is formed at the interface between the semiconductor layers 1202 and 1203 and the gate insulating film 1204, and the gate insulating film 1207 is formed.
In addition, in the process of oxidation in a halogen atmosphere, a metal impurity element, in particular, impurities contained in the gate insulating film 1204 and the semiconductor layers 1202 and 1203 can form a compound with halogen and can be removed in the gas phase.
[0154]
The gate insulating film 1207 manufactured through the above steps has high withstand voltage, and the interface between the semiconductor layers 1205 and 1206 and the gate insulating film 1207 is very good.
In order to obtain the structure of the TFT of the present invention, the subsequent steps may follow the first, second, and fourth embodiments.
[0155]
[Example 9]
In this embodiment, an example in which a crystalline TFT is manufactured in a process order different from that in Embodiment 2 is shown in FIG. First, in Example 2, a crystalline silicon film manufactured by the method shown in Example 6 is used for the semiconductor layers 204, 205, and 206 shown in FIG. At this time, a small amount of the catalyst element used in the crystallization process remains in the semiconductor layer. Subsequent steps are performed up to the step of adding an impurity imparting p-type as shown in FIG. Then, the resist masks 258 and 259 are removed.
[0156]
At this time, as shown in FIG. 13, the source regions 230 and 237 of the n-channel TFT, the drain regions 231, 238 and 241, the source regions 234 and 289 of the p-channel TFT, and the drain regions 233 and 288 are formed. In either case, phosphorus added in the step of FIG. 3 (A) is present. According to Example 1, the phosphorus concentration is 1 × 10 at this time ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three Met.
[0157]
In this state, a heat treatment step is performed in a nitrogen atmosphere at 400 to 800 ° C. for 1 to 24 hours, for example, 550 ° C. for 4 hours. By this step, the added impurity element imparting n-type and p-type can be activated. Further, the region to which phosphorus is added becomes a gettering site, and the catalytic element remaining after the crystallization step can be segregated. As a result, the catalytic element can be removed from the channel formation region.
[0158]
After the process of FIG. 13 is completed, the subsequent process is the same as that of the first embodiment, and an active matrix substrate can be manufactured by forming the state of FIG. 3C.
[0159]
[Example 10]
In this embodiment, an example of the configuration of the gate electrode in the TFT of the present invention is shown in FIG. The gate electrode includes a first conductive layer and a second conductive layer formed in contact with the first conductive layer. The first conductive layer is formed from one or a plurality of conductive layers.
[0160]
In FIG. 14A, a conductive layer (A) 1701 formed in contact with the gate insulating film of the first conductive layer of the gate electrode is formed using a Mo—Ti film and stacked on the conductive layer (A). The conductive layer (B) 1702 is formed of a Ti film, the conductive layer (C) 1703 is formed of a film containing Al as a main component, and the conductive layer (D) 1704 is formed of a Ti film. Yes. Here, the thickness of the conductive layer (A) is preferably 30 to 200 nm, and the thickness of the conductive layer (B) to conductive layer (D) is preferably 50 to 100 nm.
[0161]
The conductive layer (A) in contact with the gate insulating film serves as a barrier layer that prevents the constituent elements of the conductive layer formed thereon from penetrating into the gate insulating film. Ti, Ta, W, Mo It is desirable to use a high melting point metal such as In addition, the conductive layer (C) 1703 formed in FIG. 14A is a film containing Al as a main component, and is provided to reduce the resistivity of the gate electrode. In order to improve the flatness of the Al film to be formed, it is desirable to use an Al alloy film containing elements such as Sc, Ti, and Si at a ratio of 0.1 to 5 atomic%. In any case, when the present invention is applied to a 10-inch class or higher liquid crystal display device, in order to reduce the resistance of the gate electrode, a material having a low resistivity mainly composed of Al or Cu should be used. Is desirable. Further, the second conductive layer 1705 formed in contact with the first conductive layer and the gate insulating film is a refractory metal such as Ti, Ta, W, Mo, or an alloy material thereof in order to improve heat resistance. It is desirable to use
[0162]
FIG. 14B shows another configuration example, in which the conductive layer (A) 1706 is formed of one layer made of a Mo—W alloy film or a W film, and the second conductive layer 1707 is formed of a Ti film. . In addition, the second conductive layer 1707 may be formed of Ta, Mo, or W. The conductive layer (A) 1706 may have a thickness of 50 to 100 nm.
[0163]
In FIG. 14C, the conductive layer (A) 1708 included in the first conductive layer of the gate electrode is formed using a Ti film, and the conductive layer (B) 1709 is formed using a film containing copper (Cu) as a main component. Then, the conductive layer (C) 1710 is formed of a Ti film. Even when a Cu film is used as in the case of the Al film, the resistivity of the gate electrode and the gate wiring can be lowered.
The second conductive layer 1711 is formed using a film of Ti, Mo, W, Ta, or the like.
[0164]
In FIG. 14D, the conductive layer (A) 1712 included in the first conductive layer is formed using a Ti film, the conductive layer (B) 1713 is formed using a film containing Al as a main component, and the conductive layer (C ) 1714 is formed of a Ti film. The second conductive layer 1715 is formed using a film of Ti, Mo, W, Ta, or the like.
[0165]
In FIG. 14E, a conductive layer (A) 1716 that constitutes the first conductive layer of the gate electrode is formed using a Ti film, and a titanium nitride (TiN) film 1720 is provided by nitriding the surface. The thickness of the TiN film may be 10 to 100 nm with respect to the thickness of 30 to 200 nm of the Ti film, and here it is 20 nm. When the TiN film is formed by sputtering, the Ti film of the conductive layer (A) 1716 may be added with about 10 to 30% nitrogen gas at a flow rate ratio in the argon gas. It may be 50 atomic%, preferably 40 atomic%. Then, the conductive layer (B) 1717 is formed using a film containing Al as a main component, and the conductive layer (C) 1718 is formed using a Ti film. At this time, the TiN film 1721 may be formed before the Ti film is formed. Then, the second conductive layer 1719 is formed using a Ti film. Also at this time, the TiN film 1722 may be formed before the Ti film is formed.
[0166]
By providing the TiN film at the interface with the conductive layer (B) 1717 as shown in FIG. 14E, Ti and Al can be prevented from reacting directly. Such a structure of the gate electrode is effective for the heat activation step of Example 1 and the heat treatment step of Example 8, and is in the range of 300 to 700 ° C., preferably 350 to 550 ° C. The process can be carried out in the range of.
[0167]
In FIG. 14F, a conductive layer (A) 1723 included in the first conductive layer of the gate electrode is formed using a Ti film, a conductive layer (B) 1724 is formed using a film containing Al as a main component, The second conductive layer 1725 is formed of a Ta film. Here, similarly, a TiN film 1726 and a TaN film 1727 are formed on the surface in contact with the conductive layer (B) 1724. Similarly, the TaN film may be sputtered by adding nitrogen to the argon gas at a flow rate ratio of 1 to 10%. At this time, the amount of nitrogen contained in the TaN film is 35 to 60 atomic%, preferably 45 to 50 atomic%. And good. With such a structure, heat resistance can be increased as in the structure example in FIG.
[0168]
Such a structure of the gate electrode can be suitably combined with the TFTs of Embodiments 1 and 2 and Examples 1, 2, 3, and 5.
[0169]
[Example 11]
In this embodiment, an example in which L4 shown in FIG. 16 is different on the semiconductor layer and its periphery will be described with reference to FIG.
[0170]
In FIG. 18, a first conductive layer 1841 and a second conductive layer 1842 of a gate electrode are formed over a semiconductor layer 1840. At this time, the second conductive layer 1842 is formed so as to cover the first conductive layer 1841. In this specification, the length of the portion that does not overlap with the first conductive layer 1841 is defined as L4. Yes.
[0171]
In the case of the present embodiment, the length of L4 (represented here as WDDD) on the semiconductor layer is set to 0.5 to 3 μm. In the wiring portion (peripheral portion other than the top of the semiconductor layer), the length of L4 ′ (here, expressed as WL) is set to 0.1 to 1.5 μm.
[0172]
That is, this embodiment is characterized in that the line width of the second conductive layer is narrower in the wiring portion than on the semiconductor layer. This is because an area corresponding to L4 is not necessary in the wiring portion, and it becomes a factor that hinders the high-density integration of the wiring. Therefore, it is preferable to make the line width as narrow as possible.
[0173]
Therefore, by using the configuration of this embodiment, high-density integration of wiring is facilitated, and as a result, high-density integration of semiconductor devices becomes possible. In addition, the structure of a present Example can be freely combined with any structure of Examples 1-10.
[0174]
[Example 12]
In this embodiment, another example of a process for forming a storage capacitor provided on the active matrix substrate of Embodiments 1 and 2 will be described. A region in which the n-channel TFT is formed is covered with a resist mask 225, 295 using the photoresist film as a mask on the substrate in the state of FIG. An impurity adding step for imparting p-type is performed on the region to be formed. Here, as in Example 1, 2 × 10 ²⁰ atoms / cm ^Three Boron is added to the concentration of. Then, as shown in FIG. 19, third impurity regions 227, 228 and 296 to which boron is added at a high concentration are formed.
[0175]
By adding high-concentration boron (B) to the semiconductor layer in the region where the storage capacitor is formed, the resistivity can be lowered, which is a preferable state. The subsequent steps may be performed according to the first embodiment.
[0176]
[Example 13]
In this example, the validity of the configuration of the present invention was verified using computer simulation. Here, an integrated system engineering AG (ISE) semiconductor device simulator integrated package was used.
[0177]
The structure of the TFT used for the calculation is shown in FIG. The TFT has a channel length of 10 μm and a channel width of 10 μm, and the low-concentration impurity region (LDD) length is fixed at 2.5 μm. Other conditions include a low concentration impurity region (n ^- ) Concentration of 4.2 × 10 ¹⁷ Piece / cm ^Three , Source region and drain region (n ⁺ ) Phosphorus concentration of 2 × 10 ²⁰ Piece / cm ^Three The thickness of the semiconductor layer was 50 nm, the thickness of the gate insulating film was 150 nm, and the thickness of the gate electrode was 400 nm. In the calculation, the low concentration impurity region (n ^- ), The case of the GOLD structure completely overlapping with the gate electrode and the case of the structure partially overlapped by shifting to the outside at a pitch of 0.5 μm (GOLD + LDD) were investigated.
[0178]
FIG. 21 shows the calculation result of the electric field intensity distribution on the drain side with the center of the channel formation region as a reference. Here, the calculation was performed assuming that the gate voltage Vg = −8V and the drain voltage Vds = 16V. As a result, the low concentration impurity region (n ^- ) Is completely overlapped with the gate electrode, the electric field strength at the gate-drain end is the strongest, and the low concentration impurity region (n ^- ) By shifting the region to the drain side and reducing the amount of overlap, the electric field strength was reduced.
[0179]
FIG. 22 shows the result of calculating the Vg-Id (gate voltage-drain current) characteristics with the drain voltage Vds = 16V constant. In the case of the GOLD structure, there is an increase in off-current, but a low concentration impurity region (n ^- ) When the region is shifted to the drain side and the overlap amount is reduced, an increase in off current can be prevented.
[0180]
23 and 24 show a low concentration impurity region (n ^- ) In the case of a GOLD structure that completely overlaps with the gate electrode and a structure (GOLD + LDD) that is shifted outward by 0.5 μm and partially overlaps, the electrons in the channel formation region, the source region, and the drain region The calculation results for the concentration distribution and hole concentration distribution are shown. In the figure, the concentration distribution is indicated by contour lines. In FIG. 23, the low concentration impurity region (n ^- It can be seen that the hole concentration is high in the region where the surface of () overlaps the gate electrode. At this time, an increase in off-current due to the high hole concentration is expected. This can be seen as the hole current in FIG. On the other hand, in FIG. 24, since the electric field strength at the gate electrode and the drain end is relaxed by the GOLD + LDD structure, the hole concentration is not high.
In addition, the distribution of the electron concentration becomes gentle and the tunnel current is blocked due to the presence of the LDD region, so that the increase in off current is also eliminated. Similarly, in FIG. 26, both the electron current and the hole current are reduced.
[0181]
The results of the above computer simulation fully explain the phenomenon of the GOLD structure, which is the problem of the present invention. And it has shown that the increase of an off-current can be prevented by taking the structure of this invention.
[0182]
[Example 14]
In this embodiment, a semiconductor device incorporating an active matrix liquid crystal display device using a TFT circuit of the present invention will be described with reference to FIGS.
[0183]
Examples of such a semiconductor device include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a still camera, a personal computer, a television, and the like. Examples of these are shown in FIGS. 15, 40, and 41.
[0184]
FIG. 15A illustrates a mobile phone, which includes a main body 9001, an audio output portion 9002, an audio input portion 9003, a display device 9004, operation switches 9005, and an antenna 9006. The present invention can be applied to a display device 9004 including an audio output unit 9002, an audio input unit 9003, and an active matrix substrate.
[0185]
FIG. 15B illustrates a video camera which includes a main body 9101, a display device 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 9106. The present invention can be applied to the audio input portion 9103, the display device 9102 including the active matrix substrate, and the image receiving portion 9106.
[0186]
FIG. 15C illustrates a mobile computer, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, operation switches 9204, and a display device 9205. The present invention can be applied to an image receiving portion 9203 and a display device 9205 including an active matrix substrate.
[0187]
FIG. 15D illustrates a head mounted display which includes a main body 9301, a display device 9302, and an arm portion 9303. The present invention can be applied to the display device 9302. Although not shown, it can also be used for other signal control circuits.
[0188]
FIG. 15E illustrates a portable book, which includes a main body 9501, display devices 9502 and 9503, a storage medium 9504, an operation switch 9505, and an antenna 9506. Data stored in a minidisc (MD) or DVD, The data received by the antenna is displayed. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to the display devices.
[0189]
FIG. 40A illustrates a personal computer which includes a main body 9601, an image input portion 9602, a display device 9603, and a keyboard 9604.
[0190]
FIG. 40B shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The player includes a main body 9701, a display device 9702, a speaker portion 9703, a recording medium 9704, and operation switches 9705. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet.
[0191]
FIG. 40C illustrates a digital camera, which includes a main body 9801, a display device 9802, an eyepiece unit 9803, an operation switch 9804, and an image receiving unit (not illustrated).
[0192]
FIG. 27A illustrates a front type projector which includes a display device 2601 and a screen 2602. The present invention can be applied to display devices and other signal control circuits.
[0193]
FIG. 27B illustrates a rear projector, which includes a main body 2701, a display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to display devices and other signal control circuits.
[0194]
Note that FIG. 27C illustrates an example of the structure of the display devices 2601 and 2702 in FIGS. 27A and 27B. The display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a retardation plate 2809, and a projection optical system 2810. The optical system includes a projection optical system 2810 and a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like in the optical path indicated by an arrow in FIG. Good.
[0195]
FIG. 27D illustrates an example of the structure of the light source optical system 2810 in FIG. In this embodiment, the light source optical system 2810 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 27D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system. In addition, the present invention can also be applied to image sensors and EL display elements. Thus, the applicable range of the present invention is extremely wide and can be applied to electronic devices in all fields.
[0196]
[Example 15]
In this example, an example in which an EL (electroluminescence) display device is manufactured using the present invention will be described.
[0197]
FIG. 33A is a top view of an EL display device using the present invention. In FIG. 33A, reference numeral 4010 denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, and 4013 denotes a gate side driver circuit. Connected.
[0198]
At this time, a cover material 6000, a sealing material (also referred to as a housing material) 7000, and a sealing material (second sealing material) 7001 are provided so as to surround at least the pixel portion, preferably the drive circuit and the pixel portion.
[0199]
FIG. 33B shows a cross-sectional structure of the EL display device of this embodiment. A driving circuit TFT (here, an n-channel TFT and a p-channel TFT are combined on a substrate 4010 and a base film 4021). And a pixel portion TFT 4023 (however, only the TFT for controlling the current to the EL element is shown here). These TFTs may have a known structure (top gate structure or bottom gate structure).
[0200]
The present invention can be used for the driving circuit TFT 4022 and the pixel portion TF 4023.
[0201]
When the driver circuit TFT 4022 and the pixel portion TFT 4023 are completed using the present invention, a transparent conductive film electrically connected to the drain of the pixel portion TFT 4023 is formed on the interlayer insulating film (planarization film) 4026 made of a resin material. A pixel electrode 4027 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (referred to as ITO) or a compound of indium oxide and zinc oxide can be used.
Then, after the pixel electrode 4027 is formed, an insulating film 4028 is formed, and an opening is formed over the pixel electrode 4027.
[0202]
Next, an EL layer 4029 is formed. The EL layer 4029 may have a stacked structure or a single-layer structure by freely combining known EL materials (a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer). A known technique may be used to determine the structure. EL materials include low-molecular materials and high-molecular (polymer) materials. When a low molecular material is used, a vapor deposition method is used. When a high molecular material is used, a simple method such as a spin coating method, a printing method, or an ink jet method can be used.
[0203]
In this embodiment, the EL layer is formed by vapor deposition using a shadow mask. Color display is possible by forming a light emitting layer (a red light emitting layer, a green light emitting layer, and a blue light emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask. In addition, there are a method in which a color conversion layer (CCM) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, but either method may be used.
Needless to say, an EL display device emitting monochromatic light can also be used.
[0204]
After the EL layer 4029 is formed, a cathode 4030 is formed thereon. It is desirable to remove moisture and oxygen present at the interface between the cathode 4030 and the EL layer 4029 as much as possible. Therefore, it is necessary to devise such that the EL layer 4029 and the cathode 4030 are continuously formed in a vacuum, or the EL layer 4029 is formed in an inert atmosphere and the cathode 4030 is formed without being released to the atmosphere. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.
[0205]
In this embodiment, a stacked structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used as the cathode 4030. Specifically, a 1 nm-thick LiF (lithium fluoride) film is formed on the EL layer 4029 by evaporation, and a 300 nm-thick aluminum film is formed thereon. Of course, you may use the MgAg electrode which is a well-known cathode material. The cathode 4030 is connected to the wiring 4016 in the region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and is connected to the FPC 4017 through a conductive paste material 4032.
[0206]
In order to electrically connect the cathode 4030 and the wiring 4016 in the region indicated by 4031, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These may be formed when the interlayer insulating film 4026 is etched (when the pixel electrode contact hole is formed) or when the insulating film 4028 is etched (when the opening before the EL layer is formed). In addition, when the insulating film 4028 is etched, the interlayer insulating film 4026 may be etched all at once. In this case, if the interlayer insulating film 4026 and the insulating film 4028 are the same resin material, the shape of the contact hole can be improved.
[0207]
A passivation film 6003, a filler 6004, and a cover material 6000 are formed so as to cover the surface of the EL element thus formed.
[0208]
Further, a sealing material is provided inside the cover material 7000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.
[0209]
At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because the moisture absorption effect can be maintained.
[0210]
In addition, a spacer may be included in the filler 6004. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic.
[0211]
In the case where a spacer is provided, the passivation film 6003 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.
[0212]
As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 6004, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0213]
However, the cover material 6000 needs to have translucency depending on the light emission direction (light emission direction) from the EL element.
[0214]
The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 7000 and the sealing material 7001 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are electrically connected to the FPC 4017 through the sealing material 7000 and the sealing material 7001 in the same manner.
[0215]
[Example 16]
In this embodiment, an example of manufacturing an EL display device having a different form from that of Embodiment 15 using the present invention will be described with reference to FIGS. The same reference numerals as those in FIGS. 33A and 33B indicate the same parts, and the description thereof is omitted.
[0216]
FIG. 34A is a top view of the EL display device of this example, and FIG. 34B is a cross-sectional view taken along line AA ′ of FIG.
[0217]
According to the fifteenth embodiment, a passivation film 6003 is formed to cover the surface of the EL element.
[0218]
Further, a filler 6004 is provided so as to cover the EL element. The filler 6004 also functions as an adhesive for bonding the cover material 6000. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because the moisture absorption effect can be maintained.
[0219]
In addition, a spacer may be included in the filler 6004. At this time, the spacer may be a granular material made of BaO or the like, and the spacer itself may be hygroscopic.
[0220]
In the case where a spacer is provided, the passivation film 6003 can relieve the spacer pressure. In addition to the passivation film, a resin film for relaxing the spacer pressure may be provided.
[0221]
As the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic film can be used. Note that when PVB or EVA is used as the filler 6004, it is preferable to use a sheet having a structure in which an aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.
[0222]
However, the cover material 6000 needs to have translucency depending on the light emission direction (light emission direction) from the EL element.
[0223]
Next, after the cover material 6000 is bonded using the filler 6004, the frame material 6001 is attached so as to cover the side surface (exposed surface) of the filler 6004. The frame material 6001 is bonded by a sealing material (functioning as an adhesive) 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used if the heat resistance of the EL layer permits. Note that the sealing material 6002 is desirably a material that does not transmit moisture and oxygen as much as possible. Further, a desiccant may be added inside the sealing material 6002.
[0224]
The wiring 4016 is electrically connected to the FPC 4017 through a gap between the sealing material 6002 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner.
[0225]
[Example 17]
The present invention can be used in an EL display panel configured as in Embodiments 15 and 16. FIG. 35 shows a detailed cross-sectional structure of the pixel portion, FIG. 36A shows a top structure, and FIG. 36B shows a circuit diagram. 35, 36 (A), and 36 (B) use common reference numerals and may be referred to each other.
[0226]
In FIG. 35, a switching TFT 3502 provided on a substrate 3501 is formed using an n-channel TFT of the present invention (see Examples 1 to 12).
In this embodiment, a double gate structure is used. However, there is no significant difference in structure and manufacturing process, and thus description thereof is omitted. However, the double gate structure substantially has a structure in which two TFTs are connected in series, and there is an advantage that the off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure may be used, and a triple gate structure or a multi-gate structure having more gates may be used. Alternatively, the p-channel TFT of the present invention may be used.
[0227]
The current control TFT 3503 is formed using the n-channel TFT of the present invention. At this time, the drain wiring 35 of the switching TFT 3502 is electrically connected to the gate electrode 37 of the current control TFT by the wiring 36. A wiring indicated by 38 is a gate wiring for electrically connecting the gate electrodes 39a and 39b of the switching TFT 3502.
[0228]
At this time, it is very important that the current control TFT 3503 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows, and it is also an element with a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the LDD region is provided on the drain side of the current control TFT so as to overlap the gate electrode through the gate insulating film is extremely effective.
[0229]
In this embodiment, the current control TFT 3503 is illustrated as a single gate structure, but a multi-gate structure in which a plurality of TFTs are connected in series may be used. Further, a structure may be employed in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of portions so that heat can be emitted with high efficiency. Such a structure is effective as a countermeasure against deterioration due to heat.
[0230]
Further, as shown in FIG. 36A, the wiring that becomes the gate electrode 37 of the current control TFT 3503 overlaps with the drain wiring 40 of the current control TFT 3503 through an insulating film in a region indicated by 3504. At this time, a capacitor is formed in a region indicated by 3504. This capacitor 3504 functions as a capacitor for holding the voltage applied to the gate of the current control TFT 3503. The drain wiring 40 is connected to a current supply line (power supply line) 3506, and a constant voltage is always applied.
[0231]
A first passivation film 41 is provided on the switching TFT 3502 and the current control TFT 3503, and a planarizing film 42 made of a resin insulating film is formed thereon. It is very important to flatten the step due to the TFT using the flattening film 42. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0232]
Reference numeral 43 denotes a pixel electrode (EL element cathode) made of a highly reflective conductive film, which is electrically connected to the drain of the current control TFT 3503. As the pixel electrode 43, it is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a laminated film thereof. Of course, a laminated structure with another conductive film may be used.
[0233]
A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) may be formed separately. A π-conjugated polymer material is used as the organic EL material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV), polyvinyl carbazole (PVK), and polyfluorene.
[0234]
There are various types of PPV organic EL materials such as “H. Shenk, H. Becker, O. Gelsen, E. Kluge, W. Kreuder, and H. Spreitzer,“ Polymers for Light Emitting ”. Materials such as those described in “Diodes”, Euro Display, Proceedings, 1999, p. 33-37 ”and Japanese Patent Laid-Open No. 10-92576 may be used.
[0235]
As a specific light emitting layer, cyanopolyphenylene vinylene may be used for a light emitting layer that emits red light, polyphenylene vinylene may be used for a light emitting layer that emits green light, and polyphenylene vinylene or polyalkylphenylene may be used for a light emitting layer that emits blue light. The film thickness may be 30 to 150 nm (preferably 40 to 100 nm).
[0236]
However, the above example is an example of an organic EL material that can be used as a light emitting layer, and is not necessarily limited to this. An EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer.
[0237]
For example, in this embodiment, an example in which a polymer material is used as the light emitting layer is shown, but a low molecular weight organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.
[0238]
In this embodiment, the EL layer has a laminated structure in which a hole injection layer 46 made of PEDOT (polythiophene) or PAni (polyaniline) is provided on the light emitting layer 45.
An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of the present embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (upward of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used, but it is possible to form after forming a light-emitting layer or hole injection layer with low heat resistance. What can form into a film at low temperature as much as possible is preferable.
[0239]
When the anode 47 is formed, the EL element 3505 is completed. Note that the EL element 3505 here refers to a capacitor formed by the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 46, and the anode 47. As shown in FIG. 36A, since the pixel electrode 43 substantially matches the area of the pixel, the entire pixel functions as an EL element. Therefore, the use efficiency of light emission is very high, and a bright image display is possible.
[0240]
By the way, in the present embodiment, a second passivation film 48 is further provided on the anode 47. The second passivation film 48 is preferably a silicon nitride film or a silicon nitride oxide film. This purpose is to cut off the EL element from the outside, and has both the meaning of preventing deterioration due to oxidation of the organic EL material and the meaning of suppressing degassing from the organic EL material. This increases the reliability of the EL display device.
[0241]
As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 35, and includes a switching TFT having a sufficiently low off-current value and a current control TFT resistant to hot carrier injection. Have. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.
[0242]
In addition, the structure of a present Example can be implemented in combination freely with Examples 1-12 structure. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic apparatus of Embodiment 14.
[0243]
[Example 18]
In this embodiment, a structure in which the structure of the EL element 3505 is inverted in the pixel portion described in Embodiment 17 will be described. FIG. 37 is used for the description. Note that the only difference from the structure of FIG. 35 is the EL element portion and the current control TFT, and other descriptions are omitted.
[0244]
In FIG. 37, a current control TFT 3503 is formed using the p-channel TFT of the present invention. Examples 1 to 12 may be referred to for the manufacturing process.
[0245]
In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film made of a compound of indium oxide and zinc oxide is used. Of course, a conductive film made of a compound of indium oxide and tin oxide may be used.
[0246]
Then, after banks 51a and 51b made of insulating films are formed, a light emitting layer 52 made of polyvinylcarbazole is formed by solution coating. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 3701 is formed.
[0247]
In the case of the present embodiment, the light generated in the light emitting layer 52 is emitted toward the substrate on which the TFT is formed, as indicated by the arrows.
[0248]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-12. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic apparatus of Embodiment 14.
[0249]
[Example 19]
In this embodiment, FIGS. 38A to 38C show an example of a pixel having a structure different from that of the circuit diagram shown in FIG. In this embodiment, 3801 is a source wiring of the switching TFT 3802, 3803 is a gate wiring of the switching TFT 3802, 3804 is a current control TFT, 3805 is a capacitor, 3806 and 3808 are current supply lines, and 3807 is an EL element. .
[0250]
FIG. 38A shows an example in which the current supply line 3806 is shared between two pixels. In other words, the two pixels are formed so as to be symmetrical about the current supply line 3806. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0251]
FIG. 38B illustrates an example in which the current supply line 3808 is provided in parallel with the gate wiring 3803. Note that in FIG. 38B, the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, since the exclusive area can be shared by the power supply line 3808 and the gate wiring 3803, the pixel portion can be further refined.
[0252]
In FIG. 38C, a current supply line 3808 is provided in parallel with the gate wiring 3803 similarly to the structure of FIG. 38B, and two pixels are symmetrical with respect to the current supply line 3808. It is characterized in that it is formed. It is also effective to provide the current supply line 3808 so as to overlap with any one of the gate wirings 3803. In this case, since the number of power supply lines can be reduced, the pixel portion can be further refined.
[0253]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Example 1-12, 15 or 16. In addition, it is effective to use the EL display panel having the pixel structure of this embodiment as the display unit of the electronic device of Embodiment 14.
[0254]
[Example 20]
In FIGS. 36A and 36B shown in Embodiment 17, the capacitor 3504 is provided to hold the voltage applied to the gate of the current control TFT 3503; however, the capacitor 3504 may be omitted. . In the case of Example 17, since the n-channel TFT of the present invention as shown in Examples 1 to 12 is used as the current control TFT 3503, the LDD region provided to overlap the gate electrode through the gate insulating film have. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region, but this embodiment is characterized in that this parasitic capacitance is positively used in place of the capacitor 3504.
[0255]
Since the capacitance of the parasitic capacitance varies depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.
[0256]
Similarly, in the structure of FIGS. 38A, 38B, and 38C shown in Embodiment 19, the capacitor 3805 can be omitted.
[0257]
In addition, the structure of a present Example can be implemented in combination freely with the structure of Examples 1-12, 15-19. In addition, it is effective to use the EL display panel having the pixel structure of this embodiment as the display unit of the electronic device of Embodiment 14.
[0258]
[Example 21]
In addition to the nematic liquid crystal, various liquid crystals can be used for the liquid crystal display device described in Embodiment 1 or Embodiment 4. For example, 1998, SID, "Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability" by H. Furue et al., 1997, SID DIGEST, 841, "A Full -Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time "by T. Yoshida et al., 1996, J. Mater. Chem. 6 (4), 671-673," Thresholdless antiferroelectricity in liquid crystals and its application to The liquid crystal disclosed in "displays" by S. Inui et al. or US Pat. No. 5,945,569 can be used.
[0259]
Ferroelectric liquid crystal (FLC) showing an isotropic phase-cholesteric phase-chiral smectic C phase transition series is used to cause a cholesteric phase-chiral smectic C phase transition while applying a DC voltage, and the cone edge is almost in the rubbing direction. The electro-optic characteristics of the matched monostable FLC are shown in FIG. The display mode using the ferroelectric liquid crystal as shown in FIG. 39 is called “Half-V-shaped switching mode”. The vertical axis of the graph shown in FIG. 39 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage.
Regarding “Half-V-shaped switching mode”, Terada et al., “Half-V-shaped switching mode FLCD”, Proceedings of the 46th Joint Physics Related Conference, March 1999, p. 1316, and Yoshihara et al. "Time-division full-color LCD using ferroelectric liquid crystal", Liquid Crystal, Vol. 3, No. 3, page 190.
[0260]
As shown in FIG. 39, it can be seen that when such a ferroelectric mixed liquid crystal is used, low voltage driving and gradation display are possible. For the liquid crystal display device of the present invention, ferroelectric liquid crystal exhibiting such electro-optical characteristics can also be used.
[0261]
A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). Among mixed liquid crystals having antiferroelectric liquid crystals, there is a so-called thresholdless antiferroelectric mixed liquid crystal that exhibits electro-optic response characteristics in which transmittance continuously changes with respect to an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optic response characteristic, and a drive voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) is also found. Has been.
[0262]
In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization, and the dielectric constant of the liquid crystal itself is high. For this reason, when a thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device, a relatively large storage capacitor is required for the pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.
[0263]
In addition, since such a thresholdless antiferroelectric mixed liquid crystal is used for the liquid crystal display device of the present invention, low voltage driving is realized, so that low power consumption is realized.
[0264]
【The invention's effect】
By implementing the present invention, a stable operation can be obtained even if a gate voltage of 15 to 20 V is applied to the pixel TFT of the pixel matrix circuit and driven. As a result, the reliability of a semiconductor device including a CMOS circuit made of crystalline TFT, specifically, a pixel matrix circuit such as a liquid crystal display device or an EL display device, and a drive circuit provided in the periphery thereof is improved. A liquid crystal display device and an EL display device that can withstand long-term use can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a TFT according to an embodiment.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 3 is a cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 6 is a cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 7 is a perspective view of an active matrix substrate.
FIG. 8 is a top view of a pixel matrix circuit and a CMOS circuit.
FIGS. 9A and 9B are diagrams illustrating a manufacturing process of a crystalline silicon film. FIGS.
FIGS. 10A and 10B are diagrams illustrating a manufacturing process of a crystalline silicon film. FIGS.
FIGS. 11A and 11B are diagrams illustrating a manufacturing process of a crystalline silicon film. FIGS.
FIGS. 12A and 12B are diagrams illustrating a manufacturing process of a crystalline silicon film. FIGS.
13 is a cross-sectional view illustrating a manufacturing process of a TFT. FIG.
FIG 14 illustrates a structure of a gate electrode.
FIG 15 illustrates an example of an electronic device.
FIG 16 illustrates a structure of a gate electrode.
FIGS. 17A and 17B illustrate a structure and electrical characteristics of a TFT. FIGS.
FIG 18 illustrates a structure of a gate electrode.
FIG. 19 is a cross-sectional view illustrating a manufacturing process of a TFT.
FIG. 20 is a diagram showing a basic structure of simulation.
FIG. 21 is a diagram of a simulation result of electric field intensity distribution in the channel length direction.
FIG. 22 shows a simulation result of gate voltage-drain current characteristics.
FIG. 23 is a diagram of a simulation result of electron / hole concentration distribution.
FIG. 24 is a diagram of a simulation result of electron / hole concentration distribution.
FIG. 25 is a diagram of a simulation result of electron / hole current density distribution.
FIG. 26 is a diagram of a simulation result of electron / hole current density distribution.
FIG. 27 is a diagram illustrating a configuration of a projector.
FIG. 28 is a cross-sectional view of the TFT of this embodiment.
29 is a cross-sectional view showing a manufacturing process of a TFT. FIG.
30 is a cross-sectional view illustrating a manufacturing process of a TFT. FIG.
FIG 31 shows a structure of a gate electrode.
FIG. 32 is a diagram illustrating a configuration of a laser annealing apparatus.
FIG. 33 illustrates a structure of an active matrix EL display device.
FIG. 34 illustrates a structure of an active matrix EL display device.
35 is a cross-sectional view illustrating a structure of a pixel portion of an active matrix EL display device.
36A and 36B are a top view and a circuit diagram illustrating a structure of a pixel portion of an active matrix EL display device.
FIG. 37 is a cross-sectional view illustrating a structure of a pixel portion of an active matrix EL display device.
FIG. 38 is a circuit diagram illustrating a structure of a pixel portion of an active matrix EL display device.
FIG. 39 is a diagram showing an example of light transmittance characteristics of an antiferroelectric mixed liquid crystal.
FIG 40 illustrates an example of an electronic device.

Claims (27)

A semiconductor device including a CMOS circuit formed of an n-channel TFT and a p-channel TFT,
The gate electrodes of the n-channel TFT and the p-channel TFT are formed in contact with the first conductive layer formed in contact with the gate insulating film, the top surface and the side surface of the first conductive layer, and A second conductive layer extending on the gate insulating film,
The semiconductor layer of the n-channel TFT is formed in contact with a channel formation region, a pair of first impurity regions to be an LDD region formed in contact with the channel formation region, and a pair of the first impurity regions. A pair of second impurity regions to be a source region and a drain region,
The semiconductor layer of the p-channel TFT has a channel formation region and a pair of third impurity regions that are a source region and a drain region formed in contact with the channel formation region,
The channel formation region of the n-channel TFT is provided to overlap the first conductive layer ,
The channel formation region of the p-channel TFT is provided to overlap the first conductive layer ,
The pair of first impurity regions of the n-channel TFT are provided so as to partially overlap the second conductive layer,
A pair of the third impurity regions of the p-channel TFT is provided so as to partially overlap the second conductive layer. A semiconductor device including a CMOS circuit formed by a pixel TFT, an n-channel TFT, and a p-channel TFT,
The gate electrodes of the pixel TFT, the n-channel TFT, and the p-channel TFT are formed in contact with a first conductive layer formed in contact with a gate insulating film, and an upper surface and a side surface of the first conductive layer. And a second conductive layer provided extending on the gate insulating film,
The semiconductor layer of the pixel TFT and the n-channel TFT includes a channel formation region, a pair of first impurity regions that are LDD regions formed in contact with the channel formation region, and a pair of the first impurity regions. A pair of second impurity regions to be a source region and a drain region formed in contact with each other,
The semiconductor layer of the p-channel TFT has a channel formation region and a pair of third impurity regions that are a source region and a drain region formed in contact with the channel formation region,
The channel formation regions of the pixel TFT and the n-channel TFT are provided so as to overlap the first conductive layer ,
The channel formation region of the p-channel TFT is provided to overlap the first conductive layer ,
The pair of first impurity regions of the pixel TFT and the n-channel TFT are provided so as to partially overlap the second conductive layer,
A pair of the third impurity regions of the p-channel TFT is provided so as to partially overlap the second conductive layer. A semiconductor device having an n-channel TFT and a p-channel TFT in one pixel,
Gate electrodes of the n-channel TFT and the p-channel TFT are formed in contact with the first conductive layer formed in contact with the gate insulating film, the upper surface and the side surface of the first conductive layer, and A second conductive layer provided extending on the gate insulating film,
The semiconductor layer of the n-channel TFT is formed in contact with a channel formation region, a pair of first impurity regions to be an LDD region formed in contact with the channel formation region, and a pair of the first impurity regions. A pair of second impurity regions to be a source region and a drain region, and the pair of first impurity regions are provided to partially overlap the second conductive layer,
The semiconductor layer of the p-channel TFT has a channel formation region and a pair of third impurity regions that are a source region and a drain region formed in contact with the channel formation region, and a pair of the third impurity regions The region is provided so as to partially overlap the second conductive layer,
The channel formation region of the n-channel TFT is provided to overlap the first conductive layer ,
The semiconductor device, wherein the channel formation region of the p-channel TFT is provided so as to overlap the first conductive layer . In any one of Claims 1 thru | or 3,
The length of the pair of first impurity regions is 1.0 μm or more and 6 μm or less,
The semiconductor device, wherein a length of the pair of the first impurity regions so as not to overlap with the second conductive layer is 0.5 μm or more and 3 μm or less.   5. The semiconductor device according to claim 1, wherein the n-channel TFT has a multi-gate structure. 6.   6. The semiconductor device according to claim 1, wherein an element having a light emitting layer is connected to the p-channel TFT. In any one of Claims 1 thru | or 6,
The semiconductor device is characterized in that the concentration of the impurity element imparting n-type in the pair of first impurity regions is 1 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ . In any one of Claims 1 thru | or 7,
A semiconductor layer provided in contact with the pair of second impurity regions and including the same impurity element as the pair of first impurity regions or the same impurity element as the pair of third impurity regions; A semiconductor device comprising: an insulating layer formed of the same layer as the film; and a storage capacitor including a capacitor wiring formed over the insulating layer. In any one of Claims 1 thru | or 8,
The first conductive layer includes one or more elements selected from titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or an alloy containing the element as a main component. A semiconductor device characterized by the above. In any one of Claims 1 thru | or 9,
The semiconductor device, wherein the first conductive layer is a stacked conductive layer. In any one of Claims 1 to 10,
The first conductive layer is formed in contact with the gate insulating film, and includes one or more elements selected from titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or A conductive layer (A) having an alloy containing an element as a main component;
A conductive layer (B) formed on the conductive layer (A) and having one or a plurality of elements selected from aluminum (Al) and copper (Cu), or an alloy containing the element as a main component; A semiconductor device including at least the semiconductor device. In Claim 11, the nitride film of said conductive layer (A) is provided in the interface of said conductive layer (A) and said conductive layer (B),
A semiconductor device, wherein a nitride film of the second conductive layer is provided at an interface between the conductive layer (B) and the second conductive layer. In any one of Claims 1 to 12,
The second conductive layer has one or more elements selected from titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or an alloy containing the element as a main component. A semiconductor device characterized by the above. In any one of Claims 1 thru / or Claim 13,
The n-channel TFT and the p-channel TFT are provided on a glass substrate, a stainless steel substrate, or a plastic substrate. In any one of Claims 1 thru | or 14,
The semiconductor device is an organic electroluminescence display device, a transmissive liquid crystal display device, or a reflective liquid crystal display device. In any one of Claims 1 thru | or 14,
The semiconductor device is any one selected from a mobile phone, a personal computer, a video camera, a portable information terminal, a digital camera, a player using a recording medium storing a program, a goggle type display, an electronic book, and a projector. A semiconductor device. Forming a first semiconductor layer and a second semiconductor layer;
Forming a gate insulating film in contact with said second semiconductor layer and the first semiconductor layer,
Wherein the first conductive layer is formed on the second semiconductor layer and the first semiconductor layer in contact with the gate insulating film,
Using the first conductive layer as a mask, an element belonging to Group 15 of the periodic table is added to the first semiconductor layer and the second semiconductor layer to form a pair of first layers that form LDD regions in the first semiconductor layer. An impurity region of
Forming a photoresist on the first semiconductor layer;
Using the photoresist and the first conductive layer as a mask, an element belonging to Group 13 of the periodic table is added to the second semiconductor layer to form a pair of third impurity regions to be a source region and a drain region,
Removing the photoresist,
Forming a second conductive layer in contact with the first conductive layer and the gate insulating film on the first semiconductor layer and the second semiconductor layer;
Using the second conductive layer as a mask, an element belonging to Group 15 of the periodic table is added to the first semiconductor layer and the second semiconductor layer to form a source region and a drain region in the first semiconductor layer. Forming a second impurity region of
A method for manufacturing a semiconductor device, wherein part of the second conductive layer is removed. In claim 17,
A third photoresist having a narrower width than the second conductive layer is formed on the second conductive layer by exposing from the back surface using the first conductive layer and the second conductive layer as a mask. ,
A method for manufacturing a semiconductor device, wherein part of the second conductive layer is removed using the third photoresist as a mask. Forming a first semiconductor layer and a second semiconductor layer;
Forming a gate insulating film in contact with said second semiconductor layer and the first semiconductor layer,
Wherein the first conductive layer is formed on the second semiconductor layer and the first semiconductor layer in contact with the gate insulating film,
Using the first conductive layer as a mask, an element belonging to Group 15 of the periodic table is added to the first semiconductor layer and the second semiconductor layer to form a pair of first layers that form LDD regions in the first semiconductor layer. An impurity region of
Forming a first photoresist on the first semiconductor layer;
Using the first photoresist and the first conductive layer as a mask, an element belonging to Group 13 of the periodic table is added to the second semiconductor layer to form a pair of third impurity regions to be a source region and a drain region. Forming,
Removing the first photoresist;
Forming a second conductive layer in contact with the first conductive layer and the gate insulating film on the first semiconductor layer and the second semiconductor layer using a second photoresist as a mask;
Using the second photoresist and the second conductive layer as a mask, an element belonging to Group 15 of the periodic table is added to the first semiconductor layer and the second semiconductor layer, and a source is added to the first semiconductor layer. Forming a pair of second impurity regions to be a region and a drain region;
Removing a portion of the second conductive layer under the second photoresist;
A method for manufacturing a semiconductor device, wherein the second photoresist is removed. In any one of claims 17 to 19,
Forming a capacitor wiring formed of the same layer as the second conductive layer in contact with the first conductive layer and the first conductive layer on the semiconductor layer extending from the pair of second impurity regions; A method for manufacturing a semiconductor device.   21. The element belonging to Group 15 of the same periodic table as the element added to the pair of first impurity regions or the pair of third elements in the semiconductor layer extending from the pair of second impurity regions. A method for manufacturing a semiconductor device, comprising adding an element belonging to the same group 13 of the periodic table as an element to be added to the impurity region. In any one of Claims 17 to 21,
The first conductive layer has one or more elements selected from titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or an alloy containing the element as a main component. A method for manufacturing a semiconductor device. In any one of Claim 17 thru | or Claim 22,
The first conductive layer is formed in contact with the gate insulating film, and one or more elements selected from titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or the A conductive layer (A) having an alloy containing an element as a main component, one or a plurality of elements selected from aluminum (Al) and copper (Cu) on the conductive layer (A), or the main component of the element And a conductive layer (B) having an alloy as described above. 24. In any one of claims 17 to 23,
The second conductive layer has one or more elements selected from titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or an alloy containing the element as a main component. A method for manufacturing a semiconductor device. 25. In any one of claims 17 to 24,
A method for manufacturing a semiconductor device, wherein an element belonging to Group 15 of the periodic table is added to the pair of first impurity regions at 1 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ . In any one of Claims 17 to 25,
The method for manufacturing a semiconductor device, wherein the semiconductor device is an organic electroluminescence display device, a transmissive liquid crystal display device, or a reflective liquid crystal display device. In any one of Claims 17 to 25,
The semiconductor device is any one selected from a mobile phone, a personal computer, a video camera, a portable information terminal, a digital camera, a player using a recording medium storing a program, a goggle type display, an electronic book, and a projector. A method for manufacturing a semiconductor device.

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