JP4550957B2 - Photodetector - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a photodetector that outputs a signal corresponding to the amount of received light as a digital signal.
[0002]
[Prior art]
The light detection device outputs a current signal according to the amount of received light, accumulates charge according to the current signal output from the light reception element, and outputs an integration signal according to the amount of the charge And an integrating circuit. If this photodetection device is used, the amount of light received by the light receiving element can be obtained based on the integration signal output from the integration circuit. In some cases, the photodetection device performs A / D conversion on an integration signal (analog signal) output from the integration circuit by an A / D conversion circuit and outputs a digital signal. One of the problems with such a light detection device is to increase the dynamic range (number of bits of the digital signal) for light detection.
[0003]
For example, the photodetector disclosed in Japanese Patent Laid-Open No. 5-215607 employs a Δ modulation method to improve the dynamic range. This photodetection device compares the value of the integration signal with a reference voltage value by a comparison circuit provided at the subsequent stage of the integration circuit, and when the former is determined to be greater than the latter, it is input from the light receiving element to the integration circuit. This event is counted while dumping the charge. And based on this count value (digital signal), the light quantity of the light which the light receiving element received is calculated | required.
[0004]
In addition, the photodetection device disclosed in Japanese Patent Laid-Open No. 9-298690 employs the ΣΔ modulation method to improve the dynamic range. This photodetection device compares the value of the integration signal with the reference voltage value by a comparison circuit provided at the subsequent stage of the integration circuit, and based on the current signal output from the light receiving element so that they are equal. A certain amount of charge is added to or subtracted from the charge accumulated in the integration circuit, and an event of adding this certain amount of charge is counted. And based on this count value (digital signal), the light quantity of the light which the light receiving element received is calculated | required.
[0005]
[Problems to be solved by the invention]
However, any of the above prior arts has the following problems. That is, switching noise is easily generated during the operation of the switching circuit used to dump the electric charge accumulated in the integration circuit, so that the light detection accuracy is poor and it is not suitable for detecting the amount of weak light. The scale of the circuit required for dumping the electric charge accumulated in the integrating circuit is large, so that the cost is high and the power consumption is large.
[0006]
The present invention has been made to solve the above problems, and an object of the present invention is to provide a photodetection device having a large dynamic range for photodetection, excellent photodetection accuracy, and a small circuit scale.
[0007]
[Means for Solving the Problems]
  The first photodetecting device according to the present invention includes (1) a light receiving element that outputs a current signal according to the amount of received light, and (2) a charge element according to the current signal output from the light receiving element. Output the integration signal corresponding to the amount of charge accumulated in the capacitor element, and reset the charge accumulated in the capacitor element based on the control signal input from the outside. An integration circuit that outputs the first reference voltage value indicating the reset level as an integration signal when (3), and (3) comparing the value of the integration signal with the second reference voltage value, the value of the integration signal is the second A comparison circuit that outputs a saturation signal indicating that if it is equal to or higher than the reference voltage value, and (4) the capacitance of the integration circuit when the value of the integration signal is equal to or higher than the second reference voltage value based on the saturation signal. Just cancel the charge accumulated in the deviceA certain amountResetting means for resetting the charge accumulated in the capacitive element of the integrating circuit by injecting the charge into the capacitive element; and (5) based on the saturation signal, the value of the integral signal is greater than or equal to the second reference voltage value. A counting circuit that counts the generated event and outputs the counted value as a first digital signal; and (6) a third reference voltage value obtained by subtracting the first reference voltage value from the second reference voltage value. An A / D conversion circuit that performs A / D conversion of the integrated signal as an A / D conversion range and outputs a result of the A / D conversion as a second digital signal of lower bits than the first digital signal; It is characterized by providing.
  Further, the reset means includes a reset capacitance element, and based on the saturation signal, the constant amount of charge is accumulated in the reset capacitance element before the value of the integration signal reaches the second reference voltage value. When the signal value becomes equal to or higher than the second reference voltage value, the fixed amount of charge accumulated in the reset capacitor element is injected into the capacitor element of the integration circuit.
[0008]
  According to this photodetection device, the current signal output from the light receiving element in accordance with the amount of received light is input to the integration circuit, and in this integration circuit, the electric charge corresponding to the current signal isCapacitance elementAccumulated, thatCapacitance elementAn integrated signal corresponding to the amount of accumulated charge is output.Further, in this integrating circuit, the charge accumulated in the capacitive element is reset based on a control signal input from the outside, and the first reference voltage value indicating the reset level when in the reset state is used as the integration signal. Is output.In the comparison circuit, the value of the integration signal output from the integration circuit andSecondThe reference voltage value is compared in magnitude, and the integrated signal value isSecondIf it is equal to or higher than the reference voltage value, a saturation signal indicating that is output. Then, based on the saturation signal output from the comparison circuit by the reset means, the value of the integral signal isSecondWhen it is above the reference voltage value,By injecting into the capacitive element enough charge to cancel the charge accumulated in the capacitive element of the integrating circuit,Integration circuitCapacitance elementThe electric charge accumulated in is reset. Based on this saturation signal, the value of the integral signal is calculated by the counting circuit.SecondEvents that exceed the reference voltage value are counted, and the counted value is output as a first digital signal. The integration signal output from the integration circuit isA third obtained by subtracting the first reference voltage value from the second reference voltage value;A / D conversion is performed by an A / D conversion circuit having a reference voltage value as an A / D conversion range, and the result of the A / D conversion isThe lower bits of the first digital signalIt is output as a second digital signal. The first and second digital signals are output signals of the photodetection device.
[0009]
The first photodetecting device according to the present invention comprises (1) a plurality of sets of light receiving elements, integrating circuits, comparison circuits, reset means and counting circuits, and one A / D conversion circuit is provided for the plurality of sets. (2) It further includes a hold circuit that is provided in each of the plurality of sets and holds the integration signal output from each integration circuit and sequentially outputs it to the A / D conversion circuit. In this case, since the first and second digital signals corresponding to the amount of light received by the light receiving elements of each group are sequentially output, a one-dimensional or two-dimensional light image can be captured. .
[0010]
  The second photodetecting device according to the present invention includes (1) a light receiving element that outputs a current signal according to the amount of received light, and (2) a charge element according to the current signal output from the light receiving element. An integration circuit that outputs an integration signal corresponding to the amount of electric charge accumulated in the capacitive element and resets the electric charge accumulated in the capacitive element based on a control signal input from the outside; (3) A CDS signal having a value corresponding to the amount of change in the value of the integral signal is output, and a reset state is entered based on a control signal input from the outside, and the first reference voltage value indicating the reset level is used as the CDS signal. (4) Compare the value of the CDS signal with the second reference voltage value, and if the value of the CDS signal is greater than or equal to the second reference voltage value, output a saturation signal indicating that effect Based on the comparison circuit and (5) saturation signal When the value of the CDS signal is a second reference voltage value or more, enough to offset the charge stored in the capacitor of the integration circuitA certain amountA reset means for resetting the charge accumulated in the capacitive element of the integrating circuit by injecting the charge into the capacitive element; and (6) based on the saturation signal, the value of the CDS signal is greater than or equal to the second reference voltage value. A counting circuit that counts the generated event and outputs the counted value as a first digital signal; and (7) a third reference voltage value obtained by subtracting the first reference voltage value from the second reference voltage value. An A / D conversion circuit that performs A / D conversion on the CDS signal as an A / D conversion range, and outputs a result of the A / D conversion as a second digital signal of lower bits than the first digital signal; It is characterized by providing.
  Further, the reset means includes a reset capacitance element, and based on the saturation signal, the constant amount of charge is accumulated in the reset capacitance element before the value of the integration signal reaches the second reference voltage value. When the signal value becomes equal to or higher than the second reference voltage value, the fixed amount of charge accumulated in the reset capacitor element is injected into the capacitor element of the integration circuit.
[0011]
  According to this photodetection device, the current signal output from the light receiving element in accordance with the amount of received light is input to the integration circuit, and in this integration circuit, the electric charge corresponding to the current signal isCapacitance elementAccumulated, thatCapacitance elementAn integrated signal corresponding to the amount of accumulated charge is output.In the integration circuit, the charge accumulated in the capacitor element is reset based on a control signal input from the outside.A CDS (Correlated Double Sampling) circuit outputs a CDS signal having a value corresponding to the amount of change in the value of the integrated signal.In the CDS circuit, the first reference voltage value indicating the reset level is output as the CDS signal in a reset state based on a control signal input from the outside.In the comparison circuit, the value of the CDS signal output from the CDS circuit andSecondThe reference voltage value is compared in magnitude, and the CDS signal value isSecondIf it is equal to or higher than the reference voltage value, a saturation signal indicating that is output. Based on the saturation signal output from the comparison circuit by the reset means, the value of the CDS signal isSecondIntegration circuit when the reference voltage value is exceededCapacitance elementThe electric charge accumulated in is reset. Based on this saturation signal, the value of the CDS signal is calculated by the counting circuit.SecondEvents that exceed the reference voltage value are counted, and the counted value is output as a first digital signal. The CDS signal output from the CDS circuit isA third obtained by subtracting the first reference voltage value from the second reference voltage value;A / D conversion is performed by an A / D conversion circuit having a reference voltage value as an A / D conversion range, and the result of the A / D conversion isThe lower bits of the first digital signalIt is output as a second digital signal. The first and second digital signals are output signals of the photodetection device.
[0012]
The second photodetection device according to the present invention comprises (1) a plurality of sets of light receiving elements, integration circuits, CDS circuits, comparison circuits, reset means and counting circuits, and an A / D conversion circuit for these sets. (2) It further includes a hold circuit that is provided in each of a plurality of sets, holds a CDS signal output from each CDS circuit, and sequentially outputs it to the A / D conversion circuit. In this case, since the first and second digital signals corresponding to the amount of light received by the light receiving elements of each group are sequentially output, a one-dimensional or two-dimensional light image can be captured. .
[0013]
In the first or second photodetecting device according to the present invention, the reset unit resets the charge accumulated in the integration circuit by injecting charge sufficient to cancel the charge accumulated in the integration circuit. It is characterized by that. In this case, since the integration operation is resumed immediately after the reset operation of the integration circuit, the light detection time can be shortened, or a highly sensitive light detection result can be obtained.
[0014]
  In the first photodetection deviceReceiveDepending on the mode of connection between the optical element and the integrating circuit, when the light receiving element receives light, the value of the integrated signal may decrease. In this case, the decrease width of the integrated signal and the reference voltage value may be reduced. The comparison circuit compares the size.
[0015]
  Similarly, in the second photodetection deviceReceiveDepending on the mode of connection between the optical element and the integrating circuit, the value of the CDS signal may decrease when the light receiving element receives light. In this case, the decrease width of the CDS signal and the reference voltage value are different. The comparison circuit compares the size.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.
[0017]
(First embodiment)
First, a first embodiment of the photodetecting device according to the present invention will be described. FIG. 1 is a circuit diagram of the photodetecting device 1 according to the first embodiment. The photodetector 1 according to the first embodiment includes a photodiode (light receiving element) PD, an integration circuit 10, a CDS circuit 20, a comparison circuit 30, a counting circuit 40, an A / D conversion circuit 50, and an OR circuit (reset means). 61).
[0018]
The photodiode PD has a cathode terminal at the power supply potential Vdd and an anode terminal connected to the input terminal of the integrating circuit 10. The photodiode PD outputs a current signal corresponding to the amount of received light from the anode terminal to the input terminal of the integrating circuit 10.
[0019]
The integrating circuit 10 includes an amplifier A in parallel between the input terminal and the output terminal.₁, Capacitive element C₁And switch element SW₁Is connected. Amplifier A₁The inverting input terminal is connected to the anode terminal of the photodiode PD, and the non-inverting input terminal is set to the reference voltage value Vinp1. Capacitance element C₁And switch element SW₁Amplifier A₁Between the inverting input terminal and the output terminal. The integrating circuit 10 includes a switch element SW₁Is closed, the capacitive element C₁Is discharged and initialized. On the other hand, the integrating circuit 10 includes a switch element SW.₁Is open, the charge input from the photodiode PD to the input terminal is transferred to the capacitive element C.₁And a voltage signal corresponding to the accumulated charge (referred to as an integration signal) is output from the output terminal. This integration signal is in accordance with the amount of light received by the photodiode PD, and the amplifier A₁The reference voltage value Vinp1 input to the non-inverting input terminal is indicated as the reset level. Switch element SW₁Is opened and closed based on a signal output from the OR circuit 61.
[0020]
The CDS circuit 20 includes a capacitive element C in order between the input terminal and the output terminal._{twenty one}And amplifier A₂have. Amplifier A₂Switch element SW between input and output₂And capacitive element C_{twenty two}Are connected in parallel to each other. Amplifier A₂The inverting input terminal is a capacitive element C_{twenty one}And the non-inverting input terminal is set to the reference voltage value Vinp2.
Capacitance element C_{twenty two}And switch element SW₂Amplifier A₂Between the inverting input terminal and the output terminal. The CDS circuit 20 includes a switch element SW₂Is closed, the capacitive element C_{twenty two}Is discharged and initialized. On the other hand, the CDS circuit 20 includes a switch element SW.₂Is open from the input terminal to the capacitive element C_{twenty one}The charge input through the capacitor element C_{twenty two}And a voltage signal corresponding to the accumulated charge (referred to as a CDS signal) is output from the output terminal. This CDS signal corresponds to the amount of change in the integration signal output from the integration circuit 10, and is the amplifier A₂The reference voltage value Vinp2 input to the non-inverting input terminal is indicated as the reset level. Switch element SW₂Opens and closes based on the Vclamp control signal.
[0021]
The comparison circuit 30 inputs the CDS signal output from the CDS circuit 20 to the inverting input terminal, inputs the reference voltage value (Vinp2 + Vmax) to the non-inverting input terminal, compares both values in magnitude, and compares the value of the CDS signal. Is equal to or higher than the reference voltage value (Vinp2 + Vmax), a saturation signal having a logical value H indicating that is output. If the value of the CDS signal is less than the reference voltage value (Vinp2 + Vmax), the saturation signal is a logical value L. The reference voltage value (Vinp2 + Vmax) input to the non-inverting input terminal of the comparison circuit 30 is the amplifier A of the CDS circuit 20.₂Is the sum of the reference voltage value Vinp2 (that is, the reset level of the CDS signal) input to the non-inverting input terminal and the reference voltage value Vmax that defines the A / D conversion range of the A / D conversion circuit 50.
[0022]
The counting circuit 40 receives the saturation signal output from the comparison circuit 30, counts an event in which the saturation signal changes from the logical value L to the logical value H, and outputs the count value as a first digital signal. The A / D conversion circuit 50 uses the reference voltage value Vmax as the A / D conversion range, inputs the CDS signal output from the CDS circuit 20, performs A / D conversion on the CDS signal, and performs the A / D conversion. The result is output as a second digital signal. Here, if the first digital signal output from the counting circuit 40 is M bits and the second digital signal output from the A / D conversion circuit 50 is N bits, the counting circuit 40 and A / D conversion circuit 50 receives the first digital signal (D_{M + N-1}~ D_N) And the second N-bit second digital signal (D_N-1~ D₀(M + N) -bit digital signal (D_{M + N-1}~ D₀) Is output as an output signal of the light detection apparatus 1.
[0023]
The OR circuit 61 inputs the saturation signal output from the comparison circuit 30 and the Vreset control signal, and outputs a logic signal indicating the OR of both, and the switch signal SW of the integrating circuit 10 is output based on the logic signal.₁Controls the opening and closing of. The Vreset control signal, the Vclamp control signal, the control signal for resetting the counting operation of the counting circuit 40, and the control signal for instructing the A / D conversion operation of the A / D conversion circuit 50 are detected by this light detection. It is output at a predetermined timing from a timing control circuit (not shown) that controls the operation of the circuit 1.
[0024]
Next, the operation of the photodetecting device 1 according to the first embodiment will be described. FIG. 2 is a timing chart for explaining the operation of the photodetecting device 1 according to the first embodiment. FIG. 3 is a timing chart in which the time axis is enlarged in order to explain the operation particularly near the time t2. In the following description, it is assumed that the number of bits M of the first digital signal is 4, and the number of bits N of the second digital signal is 4.
[0025]
First, at time t0, the switching element SW of the integrating circuit 10₁Closes and capacitive element C₁Is discharged, and the value of the integration signal output from the integration circuit 10 is set to the reset level Vinp1. At this time t0, the switch element SW of the CDS circuit 20₂Closes and capacitive element C_{twenty two}Are discharged, and the value of the integration signal output from the CDS circuit 20 is set to the reset level Vinp2. At this time t0, the counting operation of the counting circuit 40 is reset, and the first digital signal has a value of 0000.₂It becomes.
[0026]
At time t1, the switch element SW of the integration circuit 10₁Opens, and the switch element SW of the CDS circuit 20₂Also open. After this time t1, in the integration circuit 10, the charge output from the photodiode PD is converted into the capacitive element C.₁And this capacitive element C₁An integrated signal corresponding to the charge accumulated in the output is output. In the CDS circuit 20, the electric charge corresponding to the change amount of the integration signal output from the integration circuit 20 is converted into the capacitive element C._{twenty two}And this capacitive element C_{twenty two}A CDS signal corresponding to the electric charge accumulated in is output. That is, after the time t1, the value of the integral signal gradually decreases from the reset level Vinp1 at the beginning of the time t1, and the value of the CDS signal gradually increases from the reset level Vinp2 at the beginning of the time t1.
[0027]
When the value of the CDS signal eventually becomes equal to or higher than the reference voltage value (Vinp2 + Vmax) in the comparison circuit 30 at time t2, the saturation signal output from the comparison circuit 30 changes from the previous logical value L to the logical value H. Further, based on the event that the saturation signal has changed from the logical value L to the logical value H, the first digital signal output from the counting circuit 40 is incremented by 1 to the value 0001.₂It becomes.
[0028]
As shown in FIG. 3, when the saturation signal becomes a logic value H at time t <b> 2, the logic signal output from the OR circuit 61 also becomes the logic value H, and the switch element SW of the integration circuit 10.₁Closes and capacitive element C₁, The value of the integration signal output from the integration circuit 10 becomes the reset level Vinp1, and the value of the CDS signal output from the CDS circuit 20 becomes the reset level Vinp2. At a time t <b> 2 ′, the saturation signal output from the comparison circuit 30 becomes a logical value L, and the logical signal output from the OR circuit 61 also becomes a logical value L. Then, again, the switching element SW of the integrating circuit 10₁Opens, and the charge output from the photodiode PD is converted into the capacitive element C.₁Newly stored in the capacitor element C₁An integrated signal corresponding to the charge accumulated in the output is output.
[0029]
At each of the times t3, t4, and t5, an operation similar to the operation at the above time t2 occurs. That is, at each of these times, the first digital signal output from the counting circuit 40 increases by 1 and the switch element SW of the integrating circuit 10₁Is once closed and opened, the value of the integration signal output from the integration circuit 10 gradually decreases from the reset level Vinp1, and the value of the CDS signal output from the CDS circuit 20 gradually increases from the reset level Vinp2. Go. When the value of the CDS signal becomes equal to or higher than the reference voltage value (Vinp2 + Vmax) in the comparison circuit 30, the same operation is repeated again.
[0030]
In the timing chart shown in FIG. 2, the first digital signal output from the counting circuit 40 when time t5 has elapsed is 0100.₂It has become. If the predetermined integration period ends at time t6, the first digital signal (D₇, D₆, D_Five, D_Four), And a second digital signal (D) that is a result of A / D conversion of the CDS signal output from the CDS circuit 20 at the time t6 by the A / D conversion circuit 50._Three, D₂, D₁, D₀) Is output as an output signal of the photodetector 1. The output signal output from the photodetector 1 is a first digital signal (D₇, D₆, D_Five, D_Four) As the upper 4 bits and the second digital signal (D_Three, D₂, D₁, D₀) As the lower 4 bits, a total of 8 bits of digital signal (D₇, D₆, D_Five, D_Four, D_Three, D₂, D₁, D₀).
[0031]
As described above, in the photodetecting device 1 according to the present embodiment, the upper M bits as a digital signal having a value corresponding to the amount of light received by the photodiode PD over the integration period (time t1 to time t6). Is output from the counting circuit 40 as a first digital signal, and the lower N bits are output from the A / D conversion circuit 50 as a second digital signal. Therefore, as compared with the case where only the A / D conversion circuit 50 is provided, in the present embodiment in which the comparison circuit 30 and the counting circuit 40 are provided in addition to the A / D conversion circuit 50, the dynamic range of light detection (digital signal The number of bits) can be increased.
[0032]
Further, in the light detection device 1 according to the present embodiment, the charge accumulated in the integration circuit 10 is not dumped, so that the problem of switching noise does not occur, the light detection accuracy is excellent, and the amount of weak light is detected. It is also suitable to do. Further, the circuit scales of the comparison circuit 30, the counting circuit 40, and the OR circuit 61 are small, so that the cost is low and the power consumption is small. Furthermore, the photodetection device 1 according to the present embodiment includes the CDS circuit 20, thereby removing the influence of offset fluctuation included in the integration signal output from the integration circuit 10.
[0033]
(Second Embodiment)
Next, a second embodiment of the photodetecting device according to the present invention will be described. FIG. 4 is a circuit diagram of the photodetecting device 2 according to the second embodiment. The photodetector 2 according to the second embodiment includes a reset circuit (reset means) 62 instead of the OR circuit 61 as compared with the photodetector 1 according to the first embodiment (FIG. 1). It is different in point.
[0034]
The reset circuit 62 includes a switch element SW₆₁~ SW₆₄, Capacitive element C₆And a logic inversion element INV. Switch element SW₆₁, Capacitive element C₆And switch element SW₆₂Are connected in series in this order, and the switch element SW₆₁Is connected to the input terminal of the integrating circuit 10, and the switch element SW₆₂The other end is set to a reference voltage value Vmax. Switch element SW₆₁And capacitive element C₆Is connected to the switch element SW₆₃Is grounded through the capacitor element C.₆And switch element SW₆₂Is connected to the switch element SW₆₄Is grounded. Switch element SW₆₁And SW₆₄Each opens and closes based on a saturation signal output from the comparison circuit 30. The switch element SW₆₂And SW₆₃Each opens and closes based on a signal obtained by logically inverting the saturation signal output from the comparison circuit 30 by the logic inverting element INV.
[0035]
The operation of the photodetector 2 according to the present embodiment is substantially the same as the operation of the photodetector 1 according to the first embodiment (FIG. 2). However, the reset operation of the integration circuit 10 is different at times t2, t3, t4, and t5. FIG. 5 is a timing chart in which the time axis is expanded in order to explain the operation in the vicinity of the time t2 of the photodetecting device according to the second embodiment. In the present embodiment, after time t1, the switch element SW of the integrating circuit 10 is used.₁Remains open.
[0036]
After the time t1 and before the time t2, the saturation signal output from the comparison circuit 30 is the logical value L, so that the switch element SW of the reset circuit 62₆₁And SW₆₄Opens, switch element SW₆₂And SW₆₃Is closed. During this period, the capacitive element C of the reset circuit 62₆The charge is accumulated in.
[0037]
When the saturation signal output from the comparison circuit 30 changes to a logical value H at time t2, the switch element SW of the reset circuit 62₆₁And SW₆₄Closed and switch element SW₆₂And SW₆₃Will open. Thereby, the capacitive element C of the integrating circuit 10₁The charge accumulated in the capacitor element C of the reset circuit 62₆The value of the integration signal output from the integration circuit 10 becomes the reset level Vinp1 and the value of the CDS signal output from the CDS circuit 20 becomes the reset level Vinp2. Immediately thereafter, the charge output from the photodiode PD is converted into the capacitive element C.₁Newly stored in the capacitor element C₁An integrated signal corresponding to the charge accumulated in the output is output.
[0038]
When the saturation signal output from the comparison circuit 30 changes to the logical value L at time t <b> 2 ′, the switch element SW of the reset circuit 62.₆₁And SW₆₄Opens, switch element SW₆₂And SW₆₃Is closed and the capacitive element C of the reset circuit 62₆The charge is accumulated in the.
[0039]
At each of the times t3, t4, and t5, an operation similar to the operation at the above time t2 occurs. That is, at each of these times, the first digital signal output from the counting circuit 40 increases by 1 and the capacitive element C of the integrating circuit 10₁Is initialized, and immediately thereafter, the value of the integration signal output from the integration circuit 10 gradually decreases from the reset level Vinp1, and the value of the CDS signal output from the CDS circuit 20 gradually increases from the reset level Vinp2. To go. When the value of the CDS signal becomes equal to or higher than the reference voltage value (Vinp2 + Vmax) in the comparison circuit 30, the same operation is repeated again.
[0040]
The light detection device 2 according to the present embodiment has the same effect as the light detection device 1 according to the first embodiment, and also has the following effects. That is, in the present embodiment, at each of the times t2, t3, t4, and t5, the switch element SW of the integrating circuit 10₁Is open and the capacitive element C of the integrating circuit 10₆The charge accumulated in is canceled out by the charge from the reset circuit 62, whereby the reset operation of the integration circuit 10 is performed. That is, in the light detection device 1 according to the first embodiment, while a certain time (time from time t2 to time t2 ′ in FIG. 3) is required from the reset operation of the integration circuit 10 to the start of the integration operation, In the light detection device 2 according to the present embodiment, the integration operation is restarted immediately after the reset operation of the integration circuit 10. Therefore, in the first embodiment, the integration action is paused in the period from time t2 to time t2 ′ in FIG. 3, whereas in the second embodiment, there is no such integration action pause period. Instead, integration can be performed continuously.
[0041]
(Third embodiment)
Next, a third embodiment of the photodetecting device according to the present invention will be described. FIG. 6 is a circuit diagram of the photodetecting device 3 according to the third embodiment. The photodetector 3 according to the third embodiment is different from the photodetector 2 according to the second embodiment (FIG. 4) in that the CDS circuit 20 is not provided.
[0042]
In the present embodiment, the comparison circuit 30 inputs the integration signal output from the integration circuit 10 to the inverting input terminal, inputs the reference voltage value (Vinp1 + Vmax) to the non-inverting input terminal, and compares both values in magnitude. . When the connection state between the photodiode PD and the integration circuit 10 is as shown in the figure, the value of the integration signal decreases when the photodiode PD receives light. Therefore, in this embodiment, if the decrease width of the integrated signal from the reset level Vinp1 is equal to or greater than the value Vmax, a saturation signal having a logical value H indicating that is output. Otherwise, the saturation signal is a logical value L. The reference voltage value (Vinp1 + Vmax) input to the non-inverting input terminal of the comparison circuit 30 is the amplifier A of the integration circuit 10.₁Is the sum of the reference voltage value Vinp1 (that is, the reset level of the integration signal) input to the non-inverting input terminal and the reference voltage value Vmax that defines the A / D conversion range of the A / D conversion circuit 50. The A / D conversion circuit 50 uses the reference voltage value Vmax as an A / D conversion range, inputs an integration signal output from the integration circuit 10, performs A / D conversion on the integration signal, and outputs the A / D signal. The conversion result is output as a second digital signal.
[0043]
The light detection device 3 according to the present embodiment operates in substantially the same manner as the operation of the light detection device 2 according to the second embodiment, and substantially the same effect as the effect exhibited by the light detection device 2 according to the second embodiment. Play. However, in this embodiment, since the CDS circuit 20 is not provided, even if an offset variation is included in the integration signal output from the integration circuit 10, this influence cannot be removed. , Small cost, and low power consumption.
[0044]
(Fourth embodiment)
Next, a fourth embodiment of the photodetecting device according to the present invention will be described. FIG. 7 is a circuit diagram of the photodetecting device 4 according to the fourth embodiment. The light detection device 4 according to the fourth embodiment is an array of the light detection devices 2 (FIG. 4) according to the second embodiment except for the A / D conversion circuit 50.
[0045]
The light detection device 4 according to the present embodiment includes L units (L ≧ 2) of units 100.₁~ 100_LThe shift register 200 and the A / D conversion circuit 50 are provided. Each unit 100₁~ 100_LEach includes a photodiode PD, an integration circuit 10, a CDS circuit 20, a comparison circuit 30, a counting circuit 40, a reset circuit 62, a hold circuit 70, and a switch element array 80.
[0046]
As shown in the circuit diagram of FIG. 8, the hold circuit 70 includes a switch element SW in order between the input terminal and the output terminal.₇And amplifier A₇Switch element SW₇And amplifier A₇Is a capacitive element C₇Is grounded. The hold circuit 70 includes a switch element SW.₇The CDS signal input to the input terminal when is closed is the capacitive element C₇And switch element SW₇After the capacitor opens, the capacitive element C₇The CDS signal stored in is stored in the amplifier A.₇To output from the output terminal.
[0047]
The switch element array 80 is provided with a number of switch elements obtained by adding a value 1 to the number of bits M of the first digital signal output from the counting circuit 40 in parallel, and these (M + 1) pieces of switch elements are provided. The switch elements open and close simultaneously. When the switch element array 80 is closed, the switch element array 80 outputs an M-bit first digital signal output from the counting circuit 40, and A / D converts the CDS signal held and output by the hold circuit 70. Output to the circuit 50.
[0048]
The shift register 200 includes L sets of units 100.₁~ 100_LEach switch element row 80 is closed sequentially. The A / D conversion circuit 50 includes L sets of units 100.₁~ 100_LThe CDS signal output from one of the units is input, the CDS signal is A / D converted, and the result of the A / D conversion is output as an N-bit second digital signal.
[0049]
In the light detection device 4 according to the present embodiment, L sets of units 100 are provided.₁~ 100_LEach photodiode PD, integration circuit 10, CDS circuit 20, comparison circuit 30, counting circuit 40, and reset circuit 62 operate in the same manner until time t6 in the timing chart shown in FIG.
[0050]
In this embodiment, L sets of units 100₁~ 100_LIn each, the switch element SW of the hold circuit 70₇Is closed once before time t6 and opened at time t6, so that the CDS signal output from the CDS circuit 20 at time t6 becomes the capacitive element C of the hold circuit 70.₇And after time t6, this CDS signal is supplied to the amplifier A.₇Is output from the output terminal.
[0051]
After time t6, first, the first unit 100₁Only the switch element array 80 is closed under the control of the shift register 200. And the first unit 100₁The first digital signal of M bits output from the counting circuit 40 is the first unit 100.₁Is output. Also, the first unit 100₁The CDS signal held and output by the hold circuit 70 is A / D converted by the A / D conversion circuit 50, and an N-bit second digital signal is output from the A / D conversion circuit 50. That is, the first unit 100₁While the switch element array 80 of the first unit 100 is closed,₁A digital signal (first M signal of upper M bits + second digital signal of lower N bits) corresponding to the amount of light received by the photodiode PD is output as an output signal of the photodetection device 4.
[0052]
Subsequently, the second unit 100₂Only the switch element array 80 is closed under the control of the shift register 200. And the second unit 100₂The first digital signal of M bits output from the counting circuit 40 is the second unit 100.₂Is output. Also, the second unit 100₂The CDS signal held and output by the hold circuit 70 is A / D converted by the A / D conversion circuit 50, and an N-bit second digital signal is output from the A / D conversion circuit 50. That is, the second unit 100₂While the switch element array 80 of the second unit 100 is closed,₂A digital signal (first M signal of upper M bits + second digital signal of lower N bits) corresponding to the amount of light received by the photodiode PD is output as an output signal of the photodetection device 4.
[0053]
In the same manner, the unit 100_Three~ 100_LA digital signal corresponding to the amount of light received by each photodiode PD (first M signal of upper M bits + second digital signal of lower N bits) is sequentially output as an output signal of this photodetection device 4. The
[0054]
The photodetecting device 4 according to the present embodiment has the same effects as the effects exhibited by the photodetecting device 2 according to the second embodiment, and also has the following effects. That is, the photodetector 4 according to the present embodiment can capture a one-dimensional or two-dimensional light image by arranging a plurality of photodiodes PD in a one-dimensional or two-dimensional array. In addition, since the dynamic range (number of bits of the digital signal) of light detection by each photodiode PD is large, the number of gradations of the captured optical image can be increased.
[0055]
The present invention is not limited to the above embodiment, and various modifications can be made.
For example, in the fourth embodiment, the A / D conversion circuit 50 is not included in each unit in the fourth embodiment but is common, but the A / D conversion circuit 50 may be included in each unit to form an array. Good. Considering integration on a semiconductor chip, an A / D conversion circuit with high resolution can be realized in the former case, but the imaging speed is sacrificed, whereas in the latter case Although high-speed imaging is possible, the resolution of the A / D conversion circuit cannot be increased.
[0056]
In the fourth embodiment, the photodetectors according to the second embodiment are arrayed. However, the photodetectors according to the first or third embodiment may be arrayed. In the third embodiment, the OR circuit 61 in the first embodiment may be provided instead of the reset circuit 62.
[0057]
【The invention's effect】
As described above in detail, according to the present invention, the current signal output from the light receiving element according to the amount of received light is input to the integrating circuit, and in this integrating circuit, the electric charge corresponding to the current signal is The accumulated signal is output according to the amount of the accumulated charge. In the comparison circuit, the value of the integration signal output from the integration circuit is compared with the reference voltage value, and if the value of the integration signal is greater than or equal to the reference voltage value, a saturation signal indicating that is output. The reset means resets the charge accumulated in the integration circuit when the value of the integration signal is equal to or higher than the reference voltage value based on the saturation signal output from the comparison circuit. Based on the saturation signal, the counting circuit counts an event in which the value of the integrated signal is equal to or higher than the reference voltage value, and outputs the counted value as a first digital signal. The integration signal output from the integration circuit is A / D converted by the A / D conversion circuit having the reference voltage value as the A / D conversion range, and the result of the A / D conversion is used as the second digital signal. Is output. The first and second digital signals are output signals of the photodetection device.
[0058]
Therefore, by providing a comparison circuit and a counting circuit in addition to the A / D conversion circuit, the dynamic range of light detection (the number of bits of the output digital signal) can be increased. In addition, since the charge accumulated in the integration circuit is not dumped, the problem of switching noise does not occur, the light detection accuracy is excellent, and it is suitable for detecting the amount of weak light. Further, the circuit scales of the comparison circuit, the counting circuit, and the reset means are small, so that the cost is low and the power consumption is small.
[0059]
Further, by providing the CDS circuit at the subsequent stage of the integration circuit, the influence of the offset variation included in the integration signal output from the integration circuit can be removed by the CDS circuit.
[0060]
In addition, by providing a plurality of sets of light receiving elements, integrating circuits, comparison circuits, reset means and counting circuits, first and second digital signals corresponding to the amount of light received by each light receiving element of each set are sequentially output. Therefore, a one-dimensional or two-dimensional light image can be taken with a large number of gradations.
[0061]
  In addition, the reset means preferably resets the charge accumulated in the integration circuit by injecting a charge sufficient to cancel the charge accumulated in the integration circuit. Since the integration operation is resumed immediately after the reset operation, the integration action is not required for resetting.InterruptionSince it does not, integration can be performed continuously.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a photodetection device according to a first embodiment.
FIG. 2 is a timing chart for explaining the operation of the photodetecting device according to the first embodiment.
FIG. 3 is a timing chart in which the time axis is enlarged to explain the operation in the vicinity of time t2 of the photodetecting device according to the first embodiment.
FIG. 4 is a circuit diagram of a photodetecting device according to a second embodiment.
FIG. 5 is a timing chart in which the time axis is enlarged to explain the operation in the vicinity of time t2 of the photodetecting device according to the second embodiment.
FIG. 6 is a circuit diagram of a photodetecting device according to a third embodiment.
FIG. 7 is a circuit diagram of a photodetecting device according to a fourth embodiment.
FIG. 8 is a circuit diagram of a hold circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1-4 ... Photodetection device, 10 ... Integration circuit, 20 ... CDS circuit, 30 ... Comparison circuit, 40 ... Count circuit, 50 ... A / D conversion circuit, 61 ... OR circuit, 62 ... Reset circuit, 70 ... Hold Circuit, 80 ... switch element array, 200 ... shift register.

Claims (4)

A light receiving element that outputs a current signal according to the amount of light received;
In accordance with the current signal output from the light receiving element, electric charge is accumulated in the capacitive element, and an integrated signal corresponding to the amount of electric charge accumulated in the capacitive element is output, and based on a control signal input from the outside An integration circuit that resets the charge accumulated in the capacitive element and outputs a first reference voltage value indicating a reset level as the integration signal when in the reset state;
A comparison circuit that compares the value of the integral signal with a second reference voltage value and outputs a saturation signal indicating that if the value of the integral signal is equal to or greater than the second reference voltage value;
Based on the saturation signal, when the value of the integration signal is greater than or equal to the second reference voltage value, a certain amount of charge that only cancels the charge accumulated in the capacitance element of the integration circuit Resetting means for resetting the electric charge accumulated in the capacitive element of the integrating circuit,
A counting circuit that counts an event in which the value of the integrated signal is equal to or greater than the second reference voltage value based on the saturation signal, and outputs the counted value as a first digital signal;
The integrated signal is A / D converted using the third reference voltage value obtained by subtracting the first reference voltage value from the second reference voltage value as an A / D conversion range, and the result of the A / D conversion is obtained. An A / D conversion circuit that outputs a second digital signal of lower bits than the first digital signal;
Bei to give a,
The reset means includes a reset capacitance element, and based on the saturation signal, accumulates the fixed amount of charge in the reset capacitance element before the value of the integration signal reaches the second reference voltage value. When the value of the integration signal becomes equal to or higher than the second reference voltage value, the fixed amount of charge accumulated in the reset capacitor element is injected into the capacitor element of the integrator circuit.
An optical detection device characterized by that. A plurality of sets of the light receiving element, the integration circuit, the comparison circuit, the reset means, and the counting circuit, and one A / D conversion circuit for the plurality of sets,
A hold circuit that is provided in each of the plurality of sets, holds an integration signal output from each integration circuit, and sequentially outputs the integration signal to the A / D conversion circuit;
The photodetection device according to claim 1. A light receiving element that outputs a current signal according to the amount of light received;
In accordance with the current signal output from the light receiving element, electric charge is accumulated in the capacitive element, and an integrated signal corresponding to the amount of electric charge accumulated in the capacitive element is output, and based on a control signal input from the outside An integrating circuit for resetting the charge accumulated in the capacitive element;
A CDS signal having a value corresponding to the amount of change in the value of the integral signal is output, and a first reference voltage value indicating a reset level is output as the CDS signal based on a control signal input from the outside. A CDS circuit to
A comparison circuit that compares the value of the CDS signal with a second reference voltage value and outputs a saturation signal indicating that if the value of the CDS signal is greater than or equal to the second reference voltage value;
Based on the saturation signal, when the value of the CDS signal is greater than or equal to the second reference voltage value, a certain amount of charge that only cancels the charge accumulated in the capacitive element of the integrating circuit Resetting means for resetting the electric charge accumulated in the capacitive element of the integrating circuit,
A counting circuit for counting an event in which the value of the CDS signal is equal to or higher than the second reference voltage value based on the saturation signal, and outputting the counted value as a first digital signal;
The CDS signal is A / D converted using the third reference voltage value obtained by subtracting the first reference voltage value from the second reference voltage value as an A / D conversion range, and the result of the A / D conversion is obtained. An A / D conversion circuit that outputs a second digital signal of lower bits than the first digital signal;
Bei to give a,
The reset means includes a reset capacitance element, and based on the saturation signal, accumulates the fixed amount of charge in the reset capacitance element before the value of the integration signal reaches the second reference voltage value. When the value of the integration signal becomes equal to or higher than the second reference voltage value, the fixed amount of charge accumulated in the reset capacitor element is injected into the capacitor element of the integrator circuit.
An optical detection device characterized by that. A plurality of sets of the light receiving element, the integration circuit, the CDS circuit, the comparison circuit, the reset means, and the counting circuit, and one A / D conversion circuit for the plurality of sets,
A holding circuit that is provided in each of the plurality of sets and holds a CDS signal output from each CDS circuit and sequentially outputs the CDS signal to the A / D conversion circuit;
The photodetection device according to claim 3.

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