JP4505481B2 - Driving device for liquid crystal display device - Google Patents

Description

  The present invention relates to a driving device for a liquid crystal display device, and more particularly to a device capable of high-speed display with a smaller configuration.

  In a liquid crystal display device, gradation display is indispensable. When a pixel is displayed, a data code corresponding to the gradation is given to the driving device, and the driving device converts it to a voltage signal corresponding to this data code. The voltage signal is applied to the source line of the thin film transistor whose drain is connected to the liquid crystal cell of the pixel, and a high voltage is applied to the gate line of the thin film transistor to open the gate for a necessary period. A desired image is obtained by changing the transmittance by applying to the liquid crystal cell.

  In this case, the relationship between the data code and the drive voltage is not linear, and has a characteristic called a gamma curve. A conventional schematic configuration for obtaining a voltage corresponding to this gamma curve is shown in FIG.

  Here, the data vs. voltage is in the relationship of the curve shown in the figure, and it is assumed that a voltage of 256 gradations is obtained from this, and the data code is given from 0 to 255, that is, 8-bit data, and the desired voltage is obtained from this data. It has gained.

First, in order to obtain a voltage range, 17 types of voltages from V0 to V16 obtained by resistance division are obtained from the reference voltage generator 10 having 18 resistance dividers connected in series between the power source and the ground. to, selected by the 4-bit switch matrix 16 voltage range by using a high-order 4 bits of data, and outputs the V _n and V _{n + 1} indicating the voltage range. Any one of 16 kinds of voltages in the selected voltage range is obtained by a 4-bit linear digital-to-analog converter (DAC) 30 using lower 4 bits of data. In the example of FIG. 1, one of the voltages assigned to the data codes 223 to 239 is output as the voltage within the voltage range V14-V15.

  FIG. 2 is a block diagram showing a schematic configuration of a driving device for applying a source voltage to the source bus of the color liquid crystal display device, and the same reference numerals are given to the same portions as those in FIG. FIG. 2 representatively shows a portion for supplying a voltage to the liquid crystal cells for two rows of three colors.

Now, assuming that voltage data to be applied to the red liquid crystal cell of the pixel in the nth column is given, 17 kinds of voltage values are extracted from the reference voltage generator 10 as described in FIG. The 16 voltage ranges between them correspond to the voltage range applied to the source bus of the pixel column to be displayed by the upper 4 bits of the voltage data by the voltage selector 20 which is a 4-bit DA converter. Two voltage values V _n and V _{n + 1} are output and given to the 4-bit lower-bit DA converter 31 to obtain a voltage corresponding to the data value within this voltage range. This voltage is stabilized by the buffer 41 and applied to the source bus SB1R of the red pixel line by the 1: 3 demultiplexer 51. Each source bus is provided with a precharge circuit 60 in order to prevent the display operation from being delayed due to a large voltage fluctuation.

  With such a configuration, when a voltage is applied to a source bus of a certain column, first, precharging is performed, the first column is prepared and driven, and then the first column is prepared and driven. Then, prepare and drive the blue row in the first row.

In such a configuration, the voltage selector 20 and the linear DAC are exactly the same in each line. Therefore, by increasing the speed of the demultiplexer and increasing the selection ratio from 1: 3 in FIG. 1 to 1: 6, 1:12, the required circuit area can be reduced by half to a quarter.
US Patent Publication No. 2004-0174347

However, with such a configuration, it is still difficult to increase the speed.
That is, in the voltage selection part in the preceding stage, the speed is limited by the impedance of the resistor divider, the impedance of the transistor forming the switch matrix and the unit capacitor in the linear DAC, and in the latter part, the speed of the analog buffer itself, the impedance of the demultiplexer The speed is limited by the parasitic capacitance of the source bus.

  In order to solve this, it is conceivable to add another analog buffer between the voltage selector and the linear DAC, and to improve the performance of the analog buffer in order to increase the selection ratio of the demultiplexer.

  However, with such an approach, additional and improved analog buffers require additional footprint and increase power consumption.

  Accordingly, an object of the present invention is to provide a driving device for a liquid crystal display device that has a simpler configuration, is more efficient in area, and can reduce power consumption.

According to the present invention,
A driving device of a liquid crystal display device for driving a liquid crystal display element by a gradation voltage supplied to a source bus,
A reference voltage generator comprising a resistor divider, and generating a voltage value indicating a predetermined range including the gradation voltage value by resistance division ;
A digital-to-analog converter that extracts a value representing a voltage range from the reference voltage generator by means of an upper bit of a data code designating a gradation voltage for a display target liquid crystal cell;
A capacitor type digital-analog converter capable of selectively outputting the detailed value while selecting a detailed value within a voltage range designated by the digital-analog converter by a lower bit of the data code;
A bidirectional analog buffer connected between the digital-analog converter and the capacitor-type digital-analog converter ;
A demultiplexer for supplying an output of the capacitor type digital-analog converter to a selected line of a source bus;
Provided between the digital-analog converter and the bidirectional analog buffer, the data from the digital-analog converter to the bidirectional buffer when the bidirectional analog buffer is forward, and the capacitor-type digital analog when backward There is provided a driving device for a liquid crystal display device comprising a switch for switching a source voltage obtained by a converter to the demultiplexer.

  Since the driving circuit according to the present invention uses a bidirectional analog buffer, the signal passes through the analog buffer at the time of setup and at the time of driving, so that the signal is stabilized at an early stage and can operate at a speed twice that of the prior art. The number of source drivers themselves can be reduced by increasing the selection ratio of the demultiplexer. As a result, the area efficiency is improved with a simpler configuration, and the power consumption can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 3 is a block diagram showing a schematic configuration of the driving device of the liquid crystal display device according to the present invention, which will be described in comparison with FIG. 2 showing the conventional configuration.

  The reference voltage generator 10 for obtaining the voltage range is exactly the same as that shown in FIG. 2 and has 18 resistor dividers connected in series between the power source and ground, and is taken out by resistor division. 17 types of voltages from V0 to V16 are obtained. The 17 kinds of voltages are given to the voltage selector 110 of the source driver unit 100 through a 17-bit bus. The voltage selector 110 is a 4-bit DA converter.

  The voltage selector 110 outputs the voltage values Vn and Vn + 1 indicating the voltage range from the upper 4 bits of the given data. Here, the voltage value V is simply output for the sake of simplicity. is there.

  This voltage value V is supplied to the bidirectional analog buffer 120 via the switch SW1, and the right direction output is supplied to a 4-bit linear digital-analog converter (C-DAC) 130 having a capacitor as a basic configuration. The DAC 130 obtains one of 16 kinds of voltages within a specified voltage range from the lower 4 bits of the data.

  By the way, the bidirectional analog buffer 120 can switch the flow of signals in the opposite direction, receives the output from the near digital-analog converter (C-DAC) 130 using the output side as the input terminal, and performs buffering. Outputs the input side as an output terminal.

  When the switch SW1 is switched to the output side, the source voltage which is the buffer output is supplied to the 1:12 demultiplexer 130 and supplied to the source bus SB selected by this demultiplexer. The source bus is also provided with a precharge circuit 150 for charging to a certain level before applying a normal voltage.

  FIG. 4 is a circuit diagram showing a detailed configuration of the bidirectional analog buffer 120.

  This circuit is based on a differential amplifier, the source and gate are connected in common, the drains of p-channel transistors TP1 and TP2 are connected to the drains of n-channel transistors TN1 and TN2, respectively, and these n-channel transistors TN1. The sources of TN2 and TN2 are connected in common and connected to the drain of the n-channel transistor TN3, and the source is grounded.

  The gate of the transistor TN1 serves as an input / output terminal [A], and the gate of the transistor TN2 serves as an input / output terminal [B]. These function as complementary, ie, when one is an input terminal, the other functions as an output terminal.

  Switches SW1 and SW2 are provided between the gate common connection point of the transistors TP1 and TP2 and their respective drains. Also, the high voltage side of the current source PS is connected to the common source connection point of the p-channel transistors TP1 and TP2, and the low voltage side is grounded via an n-channel transistor TN4 that is self-biased with its drain and gate connected. Yes.

  The high voltage side of the power supply PS is grounded via a p-channel transistor TP3 and an n-channel transistor TN5 connected in series. The gate of the transistor TP3 is connected to the drain of the transistor TN1 via the switch 3, and the switch 4 And is connected to the drain of the transistor TN2.

  The connection point between the transistors TP3 and TN5 is connected to the input / output terminal [B] via the switch SW5 and to the input / output terminal [A] via the switch SW6.

  Among these switches, SW1 and SW2, SW3 and SW4, SW5 and SW6 are complementary pairs, and one of them is ON and the other is OFF.

  Next, the operation in the above configuration will be described.

  FIG. 5 is a conceptual diagram showing how the source buses are sequentially operated using the circuit shown in FIG. 3. First, each source bus is precharged using the precharge circuit 150 before the operation. It is shown that the setup and the drive are performed every time the column is sequentially changed, such that the drive is performed after the setup for the second column and then the drive is performed after the second column is set up.

  FIG. 6 is a schematic diagram showing signal flows in the setup stage (a) and the drive stage (b).

  In the setup stage of (a), the switch SW1 is switched to connect the voltage selector 110 and the bidirectional buffer 120, and the voltage selected by the voltage selector 110 is applied to the linear C-DAC 130 via the bidirectional analog buffer 120. A voltage corresponding to the code data is created.

  In the next drive stage (b), the input and output of the bidirectional buffer 120 are reversed, and the switch SW1 is switched to the demultiplexer 140 side, so that the voltage generated by the linear C-DAC 130 according to the code data is both. Is sent to the demultiplexer 140 via the direction buffer 120 and the switch SW1, and is supplied to the designated one of the 12 source buses by the demultiplexer 140.

  7 and 9 are circuit diagrams showing the operation of the bidirectional buffer 120. FIG.

  FIG. 7 corresponds to a set-up stage, in which the bidirectional buffer 120 is used as a forward buffer. The input / output terminal [A] is used as an input terminal and the input / output terminal [B] is used as an output terminal. The switches SW1, SW4 and SW6 are opened, and SW2, SW3 and SW5 are closed.

In this case, the transistor TN1 is turned on by the voltage applied to the input terminal [A], and the current flows in the range of the current flowing through the transistor TP1, so that the current flows in the transistor TP3 by the voltage on the drain side of the transistor TN1. Since the switch SW5 is turned on, a voltage is applied to the gate of the transistor TN2, which is the output terminal, and the transistor TN2 is turned on. This transistor has a pair structure with the transistor TN1, so that the transistor TN2 has a current mirror action. Therefore, the same current as TN1 is about to flow. Since the drain voltage of the transistor TN2 becomes the common gate voltage of the transistors TP1 and TP2, a balanced and stable voltage appears at the output terminal [B]. This voltage is supplied to the linear C-DAC 140 to form a voltage corresponding to the lower bit data of the data code.

  FIG. 8 is a circuit diagram showing the configuration of this linear C-DAC 140, which has five parallel capacitors whose one ends are grounded, and their capacitances are 1C, 1C, 2C, 4C, 8C, where C is a unit capacitance. It is. Each of these capacitors has switches SW11, SW12, SW13, SW14, and SW15 provided in series with the capacitors, and the opening / closing of the switches is determined by Dref, D0, D1, D2, and D3 in the data, respectively. Charging is performed for capacitor capacities from 1C to 16C.

  In the drive stage, as shown in FIG. 9, the voltage obtained by the electric charge accumulated in the linear C-DAC 140 of FIG. 8 is taken out through the bidirectional buffer 120.

  For this reason, the bidirectional buffer 120 is used as a reverse buffer. For this reason, as shown in FIG. 9, the input / output terminal [B] is used as an input terminal, and the input / output terminal [A] is used as an output terminal. Then, the switches SW1, SW4, SW6 are closed, and SW2, SW3, SW5 are opened.

  The operation in this case is the same as that in FIG. 7, and the transistor TN2 is turned on by the voltage applied to the input terminal [B], and the current flows in the range of the current flowing in the transistor TP2. The transistor TP3 conducts current by the drain-side voltage. Since the transistor SW6 is turned on, a voltage is applied to the gate of the transistor TN1, which is the output terminal, and the transistor TN1 is turned on. However, since this transistor is paired with the transistor TN2, the transistor TN1 has a current mirror action. Therefore, the same current as TN2 is about to flow. Since the drain voltage of the transistor TN1 becomes the common gate voltage of the transistors TP1 and TP2, a balanced and stable voltage appears at the output terminal [A]. This voltage is sent to the demultiplexer according to the data code by switching the switch SW1.

  The above is a simplified description. In reality, the setup in FIG. 5 is performed in two stages.

  FIG. 10 schematically represents this state, and it is clear that the setup stage consists of two stages of setup 1 and setup 2.

  This state is also apparent from FIG. 11 schematically showing the overall operation.

  Referring again to FIG. 8, in the setup 1 stage, all the switches SW11 to SW15 are closed, and the input from the analog buffer is Vn, so all the capacitors are charged to Vn.

  Next, in the setup 2 stage, SW11 is closed, but SW12 to SW15 are controlled to open and close according to the data code.

  During driving, all switches are closed and the voltage is taken out from the analog buffer.

Thus, at the time of setup, the voltage range is determined by taking out the two voltages V _n and V _{n + 1} from the voltage selector, and the voltage supplied to the source bus in the linear C-DAC 140 is accurately determined.

  The latter drive stage is the same as described in FIG.

  FIG. 12 is a waveform diagram for explaining the operation of the driving device of the liquid crystal display device according to the present invention in comparison with the conventional case.

  According to the figure, attention should be paid to the voltage change at the charging node Vch on the high voltage side and the charging node Vcl on the low voltage side of the linear C-DAC at the setup stage.

That is, when the voltages V _n and V _{n + 1} are obtained from the reference voltage generator and the DAC of the voltage selector, the node Vch is conventionally used because of the resistor string of the reference voltage generator, the impedance of the transistor, and the parasitic capacitance of the DAC. And the voltage change at Vcl is slow and requires a fairly long setup period. Also during the drive period, the substrate potential rises slowly depending on the characteristics of the buffer amplifier.

  On the other hand, in the drive device according to the present invention, the voltage change at the nodes Vch and Vcl is speeded up because the signal passes through the buffer amplifier twice at the time of setup and at the time of drive. It is faster than that. For this reason, it is possible to drive up to the conventional setup time.

  As a result, it is possible to increase the selection ratio of the demultiplexer and reduce the configuration of the buffer amplifier accordingly.

  The above embodiments are described as examples only, and are not limiting. Modifications or the like that are usually performed by those skilled in the art are included in the scope of the present invention.

It is a figure which shows the conventional typical structure for obtaining a drive voltage from a data code. It is a block diagram which shows schematic structure of the conventional drive device which applies a source voltage to the source bus | bath of a color liquid crystal display device. It is a block diagram which shows schematic structure of the drive device of the liquid crystal display device concerning this invention. 3 is a circuit diagram showing a detailed configuration of a bidirectional analog buffer 120. FIG. It is a conceptual diagram which shows a mode that a source bus | bath is operated sequentially using the circuit shown in FIG. It is a schematic diagram which shows the flow of the signal in a setup stage (a) and a drive stage (b). 3 is a circuit diagram showing a forward operation of the bidirectional buffer 120. FIG. 3 is a circuit diagram showing a configuration of a linear C-DAC 140. FIG. 3 is a circuit diagram illustrating a backward operation of the bidirectional buffer 120. FIG. This is a schematic representation of the two-stage setup. It is a figure which shows the whole operation | movement typically. It is the wave form diagram explaining the operation | movement in the drive device of the liquid crystal display device concerning this invention compared with the conventional case.

Explanation of symbols

10 reference voltage generator 110 voltage selector 120 bidirectional analog buffer 130 linear 4-bit DAC
140 Demultiplexer
SB1R, SB1G, SB1R, SB2R, SB2G, SB2B Source bus

Claims (3)

A driving device of a liquid crystal display device that drives a liquid crystal display element by a gradation voltage supplied to a source bus,
A reference voltage generator comprising a resistor divider, and generating a voltage value indicating a predetermined range including the gradation voltage value by resistance division;
A digital-to-analog converter that extracts a value representing a voltage range from the reference voltage generator by means of an upper bit of a data code designating a gradation voltage for a display target liquid crystal cell;
A capacitor type digital-analog converter capable of selectively outputting the detailed value while selecting a detailed value within a voltage range designated by the digital-analog converter by a lower bit of the data code;
A bidirectional analog buffer connected between the digital-analog converter and the capacitor-type digital-analog converter;
A demultiplexer for supplying an output of the capacitor type digital-analog converter to a selected line of a source bus;
Provided between the digital-analog converter and the bidirectional analog buffer, the data from the digital-analog converter to the bidirectional buffer when the bidirectional analog buffer is forward, and the capacitor-type digital analog when backward And a switch for switching a source voltage obtained by the converter to the demultiplexer.   2. The driving device for a liquid crystal display device according to claim 1, wherein the reference voltage generator has a plurality of resistors connected in series and extracts a voltage by resistance division from each connection point. The bidirectional analog buffer is
A first transistor (TN1) having a gate connected to the input / output terminal, a first terminal connected to the first node, and a second terminal connected to the third node;
A second transistor (TN2) having a gate connected to the other input / output terminal of the input / output terminal, a first terminal connected to a second node, and a second terminal connected to the third node When,
A third transistor (TP1) having a gate connected to the fourth node, a first terminal connected to the fifth node, and a second terminal connected to the first node;
A fourth transistor (TP2) having a gate connected to the fourth node, a first terminal connected to the fifth node, and a second terminal connected to the second node;
A fifth transistor (TP3) having a gate connected to the sixth node, a first terminal connected to the fifth node, and a second terminal connected to the seventh node;
A sixth transistor (TN3) having a first terminal connected to the third node and a second terminal grounded;
A seventh transistor (TN4) having a first terminal connected to the eighth node and the gate and a second terminal grounded;
An eighth transistor (TN5) having a gate connected to the gates of the sixth transistor and the seventh transistor, a first terminal connected to the seventh node, and a second terminal grounded;
A power supply connected between the fifth node and the eighth node;
A first switch (SW1) connected between the first node and the fourth node;
A second switch (SW2) connected between the second node and the fourth node;
A third switch (SW3) connected between the first node and the sixth node;
A fourth switch (SW4) connected between the second node and the sixth node;
A fifth switch (SW5) connected between the gate of the second transistor and the seventh node;
A sixth switch (SW6) connected between the gate of the first transistor and the seventh node;
Have
When the gate of the first transistor is an input terminal and the gate of the second transistor is an output terminal, the first switch, the fourth switch, and the sixth switch are opened, and the first switch 2 switch, the third switch, the fifth switch are closed,
When the gate of the second transistor is an input terminal and the gate of the first transistor is an output terminal, the first switch, the fourth switch, and the sixth switch are closed, and the first switch 2 switch, the third switch, the fifth switch are opened,
The driving device of the liquid crystal display device according to claim 1.

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