JP4502644B2 - Memory control device - Google Patents

Description

  The present invention relates to a memory control device that controls writing and reading of data with respect to a clock synchronous memory.

  FIG. 1 shows an embodiment of a memory control device in the prior art.

  The memory control device 1 receives the reference clock 100 as an input. The reference clock 100 is input to the multiplied clock generation unit 3, and the multiplied clock generation unit 3 generates a multiplied clock 101 that has been multiplied by a predetermined multiplication factor. The multiplied clock 101 is supplied to the system clock generation unit 4 and divided by a predetermined division ratio to become the system clock 103 of the memory control device 1. At this time, even if the multiplier circuit and the frequency divider circuit do not exist, there is no problem as long as a system clock having a desired frequency can be obtained. The system clock generation unit 4 generates a memory clock 102 that is a clock for operating the clock synchronous memory 2 and outputs the memory clock 102 to the clock synchronous memory 2. The write data / control signal / address output circuit 5 outputs the write data / control signal / address signal 107 to the clock synchronous memory 2 in synchronization with the system clock 103. Further, the memory clock 102 is wired from the outside as an input of the memory control device 1 and is used as a data fetch reference clock 109 for receiving the input data signal 108 from the clock synchronous memory 2. The input data signal 108 is input to the input data register 6 and is latched by the data fetch reference clock 109 to generate a read data signal 110.

  FIG. 2 shows a timing chart when receiving the input data signal 108 from the clock synchronous memory 2 in the data reading in the memory control device 1 shown in FIG.

  In the case of data reading, the input data signal 108 is determined with a delay of “tAC” from the rising edge of the memory clock 102 (point A in FIG. 2) and is input to the memory control device 1. Then, data is held for “tOH” from point B, which is the next rise of the memory clock. The memory control device 1 latches the input data signal 108 in the input data register 5 at the rising edge of the point C of the input data fetch reference clock 109 and generates a read data signal 110. 2 indicates an indefinite state.

  Here, when the time of one clock section of the memory clock 102 is expressed as “tCLK” as shown in FIG. 2, the input data register 6 latches the input data signal 108 at the rising edge of the point C of the reference clock 109 for data capture. In this case, the setup time is “(tCLK−tAC), and the hold time is“ tOH ”.

  With the recent trend toward higher system speeds, high-speed operation is required for clock synchronous memories, and the clock frequency of clock synchronous memories tends to increase.

  Here, FIG. 3 shows a timing chart when the frequency of the memory clock 102 with respect to the clock synchronous memory in FIG. 2 is increased.

  That the memory clock 102 has a high frequency means that “tCLK” in FIG. 3 is not small. When the same memory is used, since the value of “tAC” does not change depending on the memory, the setup time of the input data register 6 represented by “(tCLK−tAC)” decreases, and “(tCLK− If the value of tAC) "does not satisfy the setup time required for the input data register 6, the read data signal 110 cannot be generated correctly as shown in FIG.

  A clock synchronous memory having a high memory clock frequency generally has a small value of “tAC”. However, the wiring delay of the input data signal 108 on the printed circuit board and the wiring in the memory controller circuit Delays and element delays can no longer be ignored, and as a result, there are cases where the read data signal 110 cannot be correctly generated without satisfying the setup time. At this time, if the clock synchronous memory 2 having a small “tAC” value is used, the setup time can be extended. However, the clock synchronous memory 2 having a small “tAC” value is generally expensive.

  For these problems, as shown in FIG. 4, the data fetching reference clock 109 is delayed by the delay circuit 7 and the data fetching reference clock 109 is delayed to generate the data fetching delay clock 111. 6 has been devised to generate a read data signal 110. A timing chart in that case is shown in FIG.

  In FIG. 3, the input data signal 108 is latched at the point C of the data capture reference clock 109. However, in the memory control device 1 of the form shown in FIG. 4, the data capture reference clock 109 is delayed by the delay circuit 7. The input data signal 108 is latched at the point D of the delayed data capture delay clock 111. If the delay clock 7 delays the data capture reference clock 109 by “tDLY” shown in FIG. 5, the setup time at the point D of the data capture delay clock 111 becomes “(tCLK−tAC + tDLY)”. The set-up time is increased by the delay time “tDLY” added in step (b), and “tDLY” is determined so as to satisfy the set-up time of the input data register 6, whereby the read data signal 110 can be correctly generated.

  However, since the delay circuit 7 in FIG. 4 delays the data capture reference clock 109 using a semiconductor element such as an inverter or a buffer, the delay time increases or decreases due to variations in chip manufacturing, operating temperature, operating voltage, and the like. End up. Further, when the actual delay amount is smaller than the delay amount estimated at the time of design, “tDLY” becomes small, so that the increase amount of the setup time becomes insufficient and the read data signal 110 cannot be generated correctly. On the other hand, when the actual delay amount is larger than the delay amount estimated at the time of design, the hold time of the input data register 6 at the point D represented by “(tOH−tDLY)” becomes insufficient. The read data signal 110 cannot be generated correctly.

By the way, Patent Document 1 discloses a memory clock for operating a clock synchronous memory, an output clock for outputting a control signal for memory access and write data to the clock synchronous memory, and an input clock for capturing read data. , The technology to generate separately with delay to meet each setup time. However, the delay of the clock is performed by a buffer or the like which is a semiconductor element, and there is a problem that the amount of delay fluctuates due to variations in chip manufacturing and changes in characteristics due to ambient temperature and the like.
JP 2003-58415 A

  The present invention has been made in view of the above-described problems, and does not delay a data capture reference clock using a semiconductor element such as an inverter or a buffer, but has a higher frequency than the data capture reference clock. The purpose of this is to delay the reference clock for data capture using.

The present invention has been made to achieve the above object. The memory control device according to claim 1 of the present invention is provided.
This is a memory control device that controls writing and reading of data with respect to a clock synchronous memory. In the memory control device,
A multiplied clock generating means for multiplying a reference clock to generate a multiplied clock;
System clock generation means for generating a system clock of the memory control device by dividing the multiplied clock;
Sending the system clock as a memory clock to the clock synchronous memory,
Sending the control signal, address signal and write data signal to the clock synchronous memory generated in synchronization with the system clock to the clock synchronous memory,
The memory clock sent to the clock synchronous memory is taken into the memory control device and used as a reference clock for the data fetching clock at the time of data reading,
Data capture clock generation means for generating a data capture clock delayed by a predetermined amount from the data capture reference clock by latching the data capture reference clock with the multiplied clock,
Data is fetched from a clock synchronous memory using the generated data fetch clock.

A memory control device according to a second aspect of the present invention provides:
In the multiplied clock generation means, a multiplication rate from the reference clock to the multiplied clock,
2. The memory control device according to claim 1, wherein at least one of a division ratio from the multiplied clock to the system clock can be set programmably from the outside in the system clock generation means.

According to a third aspect of the present invention, there is provided a memory control device comprising:
The data capture clock generation means includes a shift register that operates with the multiplied clock.
3. The memory control device according to claim 1, wherein a data fetch clock delayed by the number of stages of the shift register is generated.

A memory control device according to a fourth aspect of the present invention provides:
The data capture clock generation means includes selection means for selecting one clock from clocks delayed by the number of stages by the shift register, and can be selected from the outside in a programmable manner. Item 4. The memory control device according to Item 3.

According to a fifth aspect of the present invention, there is provided a memory control device comprising:
5. The memory control device according to claim 1, wherein the data capture clock generation means latches using a falling edge of the multiplied clock. 6.

A memory control device according to a sixth aspect of the present invention provides:
6. The data capture clock generation means selects and latches either the rising or falling edge of the multiplied clock, and the selection can be set programmable from the outside. The memory control device described in 1.

A memory control device according to a seventh aspect of the present invention provides:
This is a memory control device that controls writing and reading of data with respect to a clock synchronous memory. In the memory control device,
Sending the system clock of the memory control device as a memory clock to the clock synchronous memory,
Sending the control signal, address signal and write data signal to the clock synchronous memory generated in synchronization with the system clock to the clock synchronous memory,
The system clock sent to the clock synchronous memory is taken into the memory control device and used as a reference clock for data fetching clock at the time of data reading,
Having a multiplied clock generating means for generating a multiplied clock using the reference clock for data capture;
Data capture clock generation means for generating a data capture clock delayed by a predetermined amount from the data capture reference clock by latching the data capture reference clock with the multiplied clock generated by the multiplied clock generation means. do it,
The data is captured from the clock synchronous memory using the generated data capturing clock ,
Furthermore,
The multiplication rate from the data fetching reference clock to the multiplication clock in the multiplication clock generation means can be set programmably from the outside.

A memory control device according to an eighth aspect of the present invention provides:
The data capture clock generation means includes a shift register that operates with the multiplied clock.
8. The memory control device according to claim 7, wherein a data fetch clock delayed by the number of stages of the shift register is generated .

According to a ninth aspect of the present invention, there is provided a memory control device comprising:
The data capture clock generation means includes selection means for selecting one clock from clocks delayed by the number of stages by the shift register, and can be selected from the outside in a programmable manner. Item 9. The memory control device according to Item 8.

According to a tenth aspect of the present invention, there is provided a memory control device.
10. The memory control device according to claim 7, wherein the data capturing clock generation unit latches using a falling edge of the multiplied clock .

A memory control device according to an eleventh aspect of the present invention provides:
11. The data capture clock generation means selects and latches either the rising or falling edge of the multiplied clock, and the selection can be set programmable from the outside. The memory control device described in 1.

  In the first aspect of the present invention, a data capture clock generation unit is included, and the data capture generation unit delays the data capture reference clock using a multiplied clock that is a source for generating the data capture reference clock. A new data capturing clock is generated. The time of one clock section of the multiplied clock is not easily affected by manufacturing variations, operating temperature, operating voltage, and the like. Therefore, by delaying the data acquisition reference clock based on the multiplied clock, the influence of manufacturing variations and increase / decrease in delay time due to operating temperature, operating voltage, etc. can be suppressed as much as possible, and the intended delay amount can be stabilized. Can be added. In addition, since the delay is added by latching the data fetch reference clock with the multiplied clock, the present invention can change the system clock frequency in contrast to a technique for adding a fixed delay amount such as an inverter or a buffer. Since a delay amount can be added in proportion to the multiplication rate, it is suitable for a memory control device in the case where the frequency is varied. Further, since the reference clock for taking in data is a clock obtained by dividing the multiplied clock, the phase adjustment is easy and it is possible to surely latch stably.

  In the invention shown in claim 2, by enabling at least one of the multiplication ratio from the reference clock to the multiplied clock and the frequency division ratio from the multiplied clock to the system clock in claim 1 to be programmable from the outside, The frequency of the multiplied clock can be changed without changing the frequency of the data acquisition reference clock. As a result, the delay amount added to the data capture reference clock by the data capture generation unit can be varied, and the delay added to the data capture reference clock according to the frequency of the memory clock for operating the clock synchronous memory It is possible to cope with a case where it is desired to vary the amount or a case where it is desired to vary the delay amount depending on the mounting condition of the chip on the printed board.

  According to a third aspect of the present invention, in the first aspect, when the data capturing clock generation unit delays the data capturing reference clock by the multiplied clock, a shift register that operates by the multiplied clock is used. A delay amount corresponding to the number of stages of the shift register can be added to the data fetch reference clock, and a delay amount larger than the time of one clock section of the multiplied clock can be added.

  According to a fourth aspect of the present invention, there is provided selection means for selecting one clock from the clocks delayed by the number of stages by the shift register according to the third aspect, so that the clock can be selected from the outside in a programmable manner. Corresponding to the case where you want to change the amount of delay added to the data capture reference clock depending on the frequency of the memory clock that operates the memory, or the case where you want to change the amount of delay depending on the mounting conditions on the printed circuit board can do.

  According to a fifth aspect of the present invention, when the data capture clock generator latches and delays the data capture reference clock with the multiplied clock in any of claims 1 to 4, the falling edge of the multiplied clock By using this, it is possible to add a smaller amount of delay than when using a rising edge, and it is possible to add a smaller amount of delay than the time of one clock section of the multiplied clock.

  According to a sixth aspect of the present invention, in the first to fourth aspects, when the data capture clock generation unit latches and delays the data capture reference clock with the multiplied clock, the rising edge of the multiplied clock If you want to change the amount of delay added to the reference clock for data capture according to the frequency of the memory clock that operates the clock synchronous memory In addition, it is possible to cope with a case where the delay amount is to be changed depending on the mounting condition of the chip on the printed circuit board.

In a seventh aspect of the present invention, a clock having an equal phase having a frequency that is an integral multiple of the data fetching reference clock is provided by having a multiplication clock generator for multiplying the data fetching reference clock and generating a multiplied clock. As a result, the data capture clock generator can always stably latch the data capture reference clock with the multiplied clock.
Furthermore, the frequency of the multiplied clock can be varied by allowing the multiplication rate from the reference clock for data capture to the multiplied clock to be set from the outside. The amount of delay added to the reference clock for capture can be varied, and the amount of delay added to the reference clock for data capture can be varied depending on the frequency of the memory clock that operates the clock synchronous memory. It is possible to cope with a case where the delay time is desired to be varied depending on the mounting conditions on the printed circuit board.

According to an eighth aspect of the present invention, when the data capture clock generation unit according to claim 7 delays the data capture reference clock by the multiplied clock, a shift register that operates with the multiplied clock is provided. A delay amount corresponding to the number of register stages can be added to the reference clock for data capture, and a delay amount larger than the time of one clock section of the multiplied clock can be added.

According to the ninth aspect of the present invention, there is provided selection means for selecting one clock from the clocks delayed by the number of stages by the shift register according to the eighth aspect, so that the clock can be selected from the outside in a programmable manner. Depending on the frequency of the memory clock that operates the equation memory, the delay amount to be added to the reference clock for data capture by the data capture clock generator may vary depending on the mounting conditions on the printed circuit board of the chip. It is possible to cope with the case where it is desired to change.

According to a tenth aspect of the present invention, in the seventh to ninth aspects, when the data capture clock generation unit latches and delays the data capture reference clock with the multiplied clock, the falling edge of the multiplied clock By using the edge, it is possible to add a smaller amount of delay than when using the rising edge, and it is possible to add a smaller amount of delay than the time of one clock section of the multiplied clock.

According to an eleventh aspect of the present invention, in the tenth aspect, when the data capture clock generator latches and delays the data capture reference clock with the multiplied clock, the rising edge of the multiplied clock is used. Whether the falling edge is used can be set from the outside in a programmable manner, so that the amount of delay added by the data capture clock generator to the data capture reference clock varies depending on the frequency of the memory clock that operates the clock synchronous memory It is possible to cope with the case where it is desired to change the delay amount depending on the mounting condition of the chip on the printed circuit board.

  Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

<< First Embodiment >>
FIG. 6 is a block diagram of the memory control device 1 according to the first embodiment of the present invention. In FIG. 6, the memory control device 1 includes a data capture clock generation unit 8, and a multiplied clock 101 generated by the multiplied clock generation unit 3 is input to the data capture clock generation unit 8.

  A block diagram of the data capture clock generator 8 is shown in FIG. In the data capture clock generator 8 shown in FIG. 7, the data capture reference clock 109 is input to the register 200, and the data capture reference clock 109 is latched and delayed using the multiplied clock 101 as the clock of the register 200. . A timing chart in this case is shown in FIG.

In the timing diagram shown in FIG. 8, as an example, a multiplied clock 101 having a frequency six times the frequency of the data capture reference clock 109 and having the same phase as the data capture reference clock 109 is supplied to the data capture clock generator 8. It shows the case of input. As shown in FIG. 8, by latching the data capture reference clock 109 at the rising edge of the multiplied clock 101, tDLY, which is the time of one clock section of the multiplied clock 101, and tREG, which is the amount of data propagation delay at the time of latching. ,
tDLY + tREG
Thus, it is possible to generate the data capture delay clock 111 in which the data capture reference clock 109 is delayed.

In the case shown in FIG. 8, when the time of one clock section of the data capture reference clock 109 is “tCLK”,
tDLY = 1/6 × tCLK
It becomes. In this way, when the multiplied clock 101 having a frequency N times (integer) of the data capture reference clock 109 is input to the data capture clock generator,
tDLY = 1 / N × tCLK
Together with the data propagation delay amount tREG of the latch,
1 / N × tCLK + tREG
Delay can be added. Here, when N is an odd number, the generated data capture delay clock 111 does not have a duty ratio (DUTY) of H section and L section of 1: 1, but the input data register 6 stores the data capture delay clock 111. This is not a problem because only the rising edge is used. What is indicated by N times is a frequency division ratio when the system clock generation unit 4 in FIG. 6 divides the multiplied clock 101 into the system clock 103.

  According to this method, the frequency of the multiplied clock 101 does not fluctuate due to variations at the time of chip manufacturing, fluctuations in operating temperature, operating voltage, etc., and tDLY, which is the time of one clock interval, is substantially constant. Therefore, in the data capture clock generation unit 8, the delay amount “(tDLY + tREG)” added to the data capture reference clock 109 is affected by variations in chip manufacturing, operating temperature, operating voltage, and the like. Is only tREG. Therefore, a delay amount in which the influence caused by variations in chip manufacturing, operating temperature, operating voltage fluctuation, etc. as much as possible can be added to the reference clock 109 for data fetching compared to the prior art, and can be read stably. A data signal 110 can be generated.

In addition, with respect to fixed delay amounts such as inverters and buffers used for delay addition in the prior art, the delay amount added to the data capture reference clock 109 in the data capture clock generation unit 8 is:
1 / N × tCLK + tREG
Therefore, even if the system clock frequency is changed, a delay amount corresponding to the time of one clock section of the system clock can be added according to the frequency division ratio N. Suitable for equipment.

  The fact that the fluctuation of the delay amount “tDLY” is smaller than that of the prior art in the embodiment of the present invention will be described using numerical values as compared with the prior art. 4 and 6, as an example, it is assumed that the frequency of the reference clock 100 is 100 MHz, and the multiplied clock generator 3 generates a multiplied clock 101 of 500 MHz at a multiplication factor of 5. Further, it is assumed that the system clock generation unit 4 divides the 500 MHz multiplied clock 101 at a 1/5 frequency division ratio to generate a 100 MHz system clock 103 and a memory clock 102. Further, in the delay circuit 7 of FIG. 4 and the data capture clock generation unit 8 of FIG. 6, when the fluctuation is maximized in consideration of variations in chip manufacturing, operating temperature, operating voltage, etc. (hereinafter referred to as MAX case). Suppose that it is necessary to add a delay amount of 3 NS to each reference clock 109 for data capture.

In order to realize this 3NS delay addition, in the prior art shown in FIG. 4, the delay circuit 7 is configured by using a buffer, an inverter or the like which is a semiconductor element. As an example, FIG. 9 shows a case where three buffers are used. Here, the buffers 300, 301, and 302 in the delay circuit 7 shown in FIG. 9 have a delay amount of 1 NS in the MAX case. Based on variations in chip manufacturing, operating temperature, operating voltage variation, and the like, If the delay amount is assumed to be minimum (hereinafter referred to as MIN case), it is assumed that the delay amount is 0.3 NS. Since the delay circuit 7 has three of these buffers, the delay amount in the MAX case is
1 x 3 = 3 (NS)
Thus, 3NS, which is a delay addition necessary amount, can be satisfied. In this case, the delay addition amount in the MIN case is
0.3 × 3 = 0.9 (NS)
It becomes.

On the other hand, in order to realize the delay addition of 3NS, in the embodiment of the present invention shown in FIG. 6, a delay is added by latching the data fetch reference clock 109 with the multiplied clock 101 as shown in FIG. Here, since the frequency of the multiplied clock 101 is 500 MHz, tDLY is 2NS. Further, assuming that the data propagation delay tREG of the register 200 in FIG. 7 is 1 NS in the MAX case and 0.3 ns in the MIN case, the delay amount added to the reference clock 109 for data capture is
2 + 1 = 3 (NS)
Thus, 3NS, which is a delay addition necessary amount, can be satisfied. Since the time of one clock section of the multiplied clock 101 is the same in both the MAX case and the MIN case, the delay amount in the MIN case is
2 + 0.3 = 2.3 (NS)
Therefore, in the embodiment of the present invention, the amount of fluctuation between the MAX case and the MIN case of the delay amount is more in the embodiment of the present invention than in the case where the delay addition amount of the MIN case is 0.9 (NS) in the prior art. Can be small.

  Further, when it is necessary to add a delay amount smaller than “(tDLY + tREG)” in FIG. 8 to the data capture reference clock 109, one of the possible ways is to further increase the frequency of the multiplied clock 101. That is, the multiplication rate of the multiplied clock generation unit 3 in FIG. However, it is often difficult to generate a high frequency clock stably. Therefore, the data capture clock generator 8 latches the data capture reference clock 109 at the falling edge of the multiplied clock 101 while keeping the frequency of the multiplied clock 101 as compared with the case where the rising edge of the multiplied clock 101 is used. Further, a small delay amount can be added.

FIG. 10 shows a timing chart when the data capture reference clock 109 is latched at the falling edge of the multiplied clock 101 in the data capture clock generation unit 8. FIG. 10 shows an example in which, as in FIG. 8, a clock having a frequency six times that of the data capture reference clock 109 and having the same phase is input as the multiplied clock 101. By latching the data capture reference clock 109 at the falling edge of the multiplied clock 101, the amount of delay added to the data capture delay clock 111 is:
1/2 x tDLY + tREG
It becomes. That is, it is possible to add a smaller amount of delay than when the rising edge of the multiplied clock 101 is used.

Further, when it is necessary to add a delay amount larger than “(tDLY + tREG)” in FIG. 8 to the data fetch reference clock 109, a shift register that operates with the multiplied clock 101 as shown in FIG. Good. FIG. 11 shows a case where a delay circuit is formed by a shift register using three registers. In the case of FIG. 11, assuming that the frequency of the multiplied clock 101 is N (integer) times the frequency of the data capture reference clock 109, the amount of delay added to the data capture reference clock by the data capture clock generator 8 is “ (3 × tDLY + tREG) ”. Here, when the number of registers forming the shift register is M, the delay amount is
M x tDLY + tREG
And in FIG.
tDLY + tREG
The amount of delay can be increased.

  On the other hand, there is a case where it is desired to vary the delay amount added by the data capture clock generation unit 8. As such a case, when it is desired to change the delay amount when the frequency of the memory clock 102 fluctuates, or when it is desired to change the delay amount because tAC which is a specific value of the clock synchronous memory 2 differs depending on the manufacturer. Or, there is a case where it is desired to vary the delay amount depending on the mounting condition of the chip on the board.

  In such a case, the multiplication rate when the multiplication clock generation unit 3 in FIG. 6 multiplies the reference clock 100 to generate the multiplication clock 101, and the system clock generation unit 4 divides the multiplication clock 101 to divide the system clock 103 and the memory. At least one of the frequency division ratio at the time of generating the clock 102 may be programmable from the outside. By making at least one of the multiplication rate in the multiplication clock generation unit 3 and the division ratio in the system clock generation unit 4 programmable from the outside, the frequency of the data capture reference clock 109 is not changed. The frequency of the multiplied clock 101 can be varied. As a result, the delay time added to the data capture reference clock 109 by the data capture clock generator 8 can be varied, and the data capture reference clock 109 can be changed depending on the frequency of the memory clock that operates the clock synchronous memory 2. This can correspond to a case where it is desired to change the delay amount to be added or a case where it is desired to change the delay amount depending on the mounting condition of the chip on the printed circuit board.

  Further, when a shift register is formed in the data capture clock generation unit 8, the data capture clock generation unit 8 has a selection means for selecting one clock from the clocks delayed by the number of stages by the shift register. You may make it selectably programmable. In FIG. 12, the data capturing clock generation unit 8 forms a shift register, and has a selection means for selecting one clock from the clocks delayed by the number of stages by the shift register, and can be selected from the outside in a programmable manner. As an example of the form, a case where three stages of shift registers are used is shown.

  The data capture clock generator 8 receives the data capture reference clock 109, the multiplied clock 101, and the delay selection signal 115. The data capture reference clock 109 is input to the register 201 and latched by the multiplied clock 101. The register 201 outputs the one-stage delay clock 112 to the register 202 and the selector 204 in the next stage. Similarly, the register 202 generates a two-stage delay clock 113 and the register 203 generates a three-stage delay clock 114, which are output to the selector 204, respectively. Based on the delay selection signal 115, the selector 204 outputs the data fetching reference clock 109, the one-stage delay clock 112, the two-stage delay clock 113, or the three-stage delay clock 114 as the data fetching delay clock 111. Select and output. According to this embodiment, the delay amount added to the data capture reference clock 109 by the data capture clock generation unit 8 can be varied programmably from the outside by the delay selection signal 115 which is an external signal.

FIG. 13 shows a timing chart when the two-stage delay clock 113 is selected as the data fetch delay clock 111 in the embodiment of FIG. Compared to the data capture reference clock 109, the one-stage delay clock 112 is
tDLY + tREG
With a delay amount of. Here, tDLY represents the time of one clock section of the multiplied clock 101, and tREG represents the data propagation delay of the register 201 in FIG. Similarly, the two-stage delay clock 113 is
2 x tDLY + tREG
The three-stage delay clock has a delay amount of
3 x tDLY + tREG
Have the amount of delay. The selector 204 selects the two-stage delay clock 113 as the data fetch delay clock 111. In this case, the data capture delay clock 111 is compared with the data capture reference clock 109.
2 x tDLY + tREG + tSEL
Have the amount of delay. Here, tSEL represents the data propagation delay of the selector 204. In this way, the delay amount added to the data capture reference clock 109 by the data capture clock generator 8 can be varied programmably from the outside.

  Further, as a method of programmably changing the delay amount added to the data capture reference clock 109 by the data capture clock generation unit 8 from the outside, the data capture clock generation unit 8 latches the data capture reference clock 109 with the multiplied clock 101. In this case, it can be assumed that either the rising edge or the falling edge of the multiplied clock 101 is selected and latched, and this selection can be set programmable from the outside.

  FIG. 14 shows an example of a configuration in which either the rising edge or falling edge of the multiplied clock 101 is selected and latched, and this selection can be set programmably from the outside. The data capture clock generator 8 receives the data capture reference clock 109, the multiplied clock 101, and the multiplied clock selection signal 118. Further, the multiplied clock 101 is input to the selector 206 and the inverter 207, and an inverted multiplied clock 116 that is an inverted signal of the multiplied clock 101 is generated by the inverter 207 and output to the selector 206. The selector 206 selects, based on the multiplied clock selection signal 118, one to be output as the selected multiplied clock 117 from the multiplied clock 101 and the inverted multiplied clock 116, and outputs the selected clock to the register 205. The register 205 latches the data capture reference clock 109 with the selective multiplication clock 117, and generates and outputs the data capture delay clock 111.

  With this configuration, the data capture clock generator 8 can select and latch either the rising or falling edge of the multiplied clock 101 when the data capture reference clock 109 is latched by the multiplied clock. Furthermore, this selection can be set in a programmable manner from the outside. As a result, the amount of delay added to the data capture reference clock 109 by the data capture clock generation unit 8 can be varied programmably from the outside.

<< Second Embodiment >>
In the first embodiment of FIG. 6, the multiplied clock 101 is input to the data capture clock generator 8 and the multiplied clock 101 is used as a clock for delaying the data capture reference clock 109 in the data capture clock generator 8. Indicates. Incidentally, a clock obtained by multiplying the data capture reference clock 109 may be used as a clock for the data capture clock generator 8 to delay the data capture reference clock 109. FIG. 15 shows an embodiment (second embodiment) in this case.

  In the second embodiment shown in FIG. 15, the memory control device 1 has a multiplied data capture clock generation unit 9, which multiplies the data capture clock reference clock 109, A multiplied data fetch clock 119 is generated and output to the data fetch clock generator 8. Then, the data capture clock generation unit 8 adds the delay amount to the data capture reference clock 109 by latching the data capture reference clock 109 with the multiplied data capture clock 119, and generates the data capture delay clock 111. In this embodiment, the multiplied data fetch clock generator 9 multiplies the data fetch reference clock 109 so that the phase is the same as that of the data fetch reference clock 109 and has a frequency that is an integral multiple of the data fetch reference clock 109. 6 can be generated more stably than the embodiment shown in FIG. 6, and the data capture reference clock 109 can be latched stably in the data capture clock generator 8.

  In the form shown in FIG. 15 as well, the multiplication rate from the data fetching reference clock 109 to the multiplied data fetching clock 119 in the multiplied data fetching clock generation unit 9 can be set programmably from the outside so that the data fetching is possible. The amount of delay added to the data fetch reference clock 109 by the clock generator 8 may be varied.

  Also in the form shown in FIG. 15, the data capture clock generator 8 has a shift register that operates with the multiplied data capture clock 119, and can generate a data capture delay clock delayed by the number of stages of the shift register. May be. Then, the data capture clock generator 8 has a selection means for selecting one clock from the clocks delayed by the number of stages by the shift register so that the data capture clock can be selected from the outside in a programmable manner. The delay amount added to the reference clock 109 for data capture by the unit 8 may be varied.

  Further, also in the form shown in FIG. 15, the data capture clock generator 8 may latch the data capture reference clock 109 at the falling edge of the multiplied data capture clock 119. The data capture clock generator 8 selects either the rising or falling edge of the multiplied data capture clock 119 and latches the data capture reference clock 109, and the selection can be set from the outside in a programmable manner. Thus, the amount of delay added by the data capture clock generator 8 to the data capture reference clock 109 may be varied.

It is a block diagram of the memory control apparatus in a prior art. FIG. 2 is a timing chart when an input data signal is received from a clock synchronous memory in data reading in the memory control device shown in FIG. 1. FIG. 3 is a timing chart when the frequency of the memory clock for the clock synchronous memory in FIG. 2 increases. It is a block diagram of the memory control apparatus of another form in a prior art. FIG. 5 is a timing chart when an input data signal is received from a clock synchronous memory in reading data in the memory control device shown in FIG. 4. 1 is a block diagram of a memory control device according to a first embodiment of the present invention. FIG. 7 is a block diagram of a data capture clock generation unit in FIG. 6. FIG. 8 is an example of a timing diagram relating to the data capture clock generation unit of FIG. 7. It is a conventional example of the configuration of a delay circuit. FIG. 10 is a timing chart when the data capture reference clock is latched at the falling edge of the multiplied clock in the data capture clock generation unit. It is one of the structural examples of a data acquisition clock generation part. It is another example of a structure of a data acquisition clock generation part. FIG. 13 is a timing chart when the two-stage delay clock is selected as the data capture delay clock in the data capture clock generation unit of the configuration example of FIG. It is another example of a structure of a data acquisition clock generation part. It is a block diagram of the memory control apparatus which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory control apparatus, 2 ... Clock synchronous memory, 3 ... Multiplication clock generation part, 4 ... System clock generation part, 5 ... Write data control signal address output circuit, 6 ... Input data register, 7... Delay circuit, 8... Data capture clock generation unit, 9.

Claims (12)

In a memory control device that controls writing and reading of data to a clock synchronous memory,
A multiplied clock generating means for multiplying a reference clock to generate a multiplied clock;
System clock generation means for generating a system clock of the memory control device by dividing the multiplied clock;
Sending the system clock as a memory clock to the clock synchronous memory,
Sending the control signal, address signal and write data signal to the clock synchronous memory generated in synchronization with the system clock to the clock synchronous memory,
The memory clock sent to the clock synchronous memory is taken into the memory control device and used as a reference clock for the data fetching clock at the time of data reading,
Data capture clock generation means for generating a data capture clock delayed by a predetermined amount from the data capture reference clock by latching the data capture reference clock with the multiplied clock,
A memory control device for fetching data from a clock synchronous memory using the generated data fetch clock. In the multiplied clock generation means, a multiplication rate from the reference clock to the multiplied clock,
2. The memory control device according to claim 1, wherein at least one of a division ratio from the multiplied clock to the system clock can be set programmably from the outside in the system clock generation means. The data capture clock generation means includes a shift register that operates with the multiplied clock.
3. The memory control device according to claim 1, wherein a data fetch clock delayed by the number of stages of the shift register is generated. The data capture clock generation means includes selection means for selecting one clock from clocks delayed by the number of stages by the shift register, and can be selected from the outside in a programmable manner. Item 4. The memory control device according to Item 3. 5. The memory control device according to claim 1, wherein the data capturing clock generation unit latches using a falling edge of the multiplied clock. 6. 6. The data capture clock generation means selects and latches either the rising or falling edge of the multiplied clock, and the selection can be set programmable from the outside. The memory control device according to 1. Writing data to the clock synchronous memory, a memory controller that controls reading,
Sending the system clock of the memory control device as a memory clock to the clock synchronous memory,
Sending the control signal, address signal and write data signal to the clock synchronous memory generated in synchronization with the system clock to the clock synchronous memory,
The system clock sent to the clock synchronous memory is taken into the memory control device and used as a reference clock for data fetching clock at the time of data reading,
Having a multiplied clock generating means for generating a multiplied clock using the reference clock for data capture;
Data capture clock generation means for generating a data capture clock delayed by a predetermined amount from the data capture reference clock by latching the data capture reference clock with the multiplied clock generated by the multiplied clock generation means. do it,
In a memory control device that captures data from a clock synchronous memory using the generated data capture clock ,
2. A memory control device according to claim 1, wherein a multiplication rate from the data fetching reference clock to the multiplication clock in the multiplication clock generation means can be set from outside . The data capture clock generation means includes a shift register that operates with the multiplied clock.
8. The memory control device according to claim 7, wherein a data fetch clock delayed by the number of stages of the shift register is generated . The data capture clock generation means includes selection means for selecting one clock from clocks delayed by the number of stages by the shift register, and can be selected from the outside in a programmable manner. Item 9. The memory control device according to Item 8. 10. The memory control device according to claim 7, wherein the data capturing clock generation unit latches using a falling edge of the multiplied clock . 11. The data capture clock generation means selects and latches either the rising or falling edge of the multiplied clock, and the selection can be set programmable from the outside. The memory control device according to 1. In a memory control method for controlling data writing and reading with respect to a clock synchronous memory,
A multiplied clock generation step of generating a multiplied clock by multiplying a reference clock;
A system clock generating step of generating a system clock by dividing the multiplied clock;
Sending the system clock as a memory clock to the clock synchronous memory,
Sending the control signal, address signal and write data signal to the clock synchronous memory generated in synchronization with the system clock to the clock synchronous memory,
The memory clock sent to the clock synchronous memory is taken as a reference clock for the data fetching clock when reading data,
A data capture clock generating step of generating a data capture clock delayed by a predetermined amount from the data capture reference clock by latching the data capture reference clock with the multiplied clock;
A memory control method for fetching data from a clock synchronous memory using the generated data fetch clock.

Images