KR100800139B1 - DLL device - Google Patents

Abstract

The DL device of the present invention includes a buffer for receiving an external clock signal, a first delay unit for receiving an output signal of the buffer, a second delay unit for receiving an output signal of the first delay unit, and an output signal for the second delay unit. And a phase comparator for detecting a phase difference between the output signal of the buffer, a first control unit receiving an output signal of a phase comparator and adjusting a delay time of the first delay unit, and using the frequency information of an external clock signal. And a second control unit for outputting a control signal for controlling the delay time of the delay unit.

Description

DL device

1 is a conventional DL device.

2 is a DL device which is an embodiment of the present invention.

3 is a DL device which is another embodiment of the present invention.

4 is an example of an MRS decoder of the DL device disclosed in FIGS. 2 and 3.

5 is an example of a delay unit controlled by the MRS decoder disclosed in FIGS. 2 and 3.

6 is another example of a delay unit controlled by the MRS decoder disclosed in FIGS. 2 and 3.

7 is another example of a delay unit controlled by the MRS decoder disclosed in FIGS. 2 and 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits and, more particularly, to DL (DLL) devices used in semiconductor devices.

As is well known, the DLL device is a circuit for controlling the output timing of a signal (for example, data, etc.) output from the inside of the semiconductor device to the outside based on the clock input from the outside of the semiconductor device. Here, the semiconductor device refers to all semiconductor devices that operate in association with an external controller such as a memory device. For convenience of description, a DLL device used for a synchronous memory device will be described as an example.

1 is an example of a general DLL device. For reference, DQ represents read data.

In FIG. 1, t1 represents a delay time of a buffer for receiving clock signals CLK and / CLK, td represents a delay time of a delay unit, and t2 represents a delay time from a DLL driver to a data output buffer. The delay time of the replica delay unit is t1 + t2.

In Fig. 1, the delay section is a circuit for delaying the phase of the external clock signal. At this time, the degree of phase delay is determined by a phase comparator, and forms a delay path that determines the phase delay under the control of the delay controller. As is well known, the delay unit is composed of a plurality of unit delay cells connected in series, and the delay time can be adjusted by the delay control unit.

As shown, the delay unit is divided into receiving a rising clock signal CLK and receiving a falling clock signal / CLK. The reason for doing this is to treat rising and falling edges in the same way to minimize the duty ratio distortion.

For the rest of the configuration and operation, since the DLL device illustrated in FIG. 1 is a general DLL device well known to those skilled in the art, specific functions and operations will be omitted.

However, in the conventional DLL device, there is a problem that the locking time is delayed by sequentially controlling the plurality of delay cell feedback operations constituting the delay unit.

The present invention has been proposed to solve the above-described problem, and to provide a DLL device that can reduce the locking time.

To this end, the present invention provides a DLL device that reduces the delay time adjustment of the delay unit by using the information of the external clock signal.

A DL device according to an embodiment of the present invention includes a buffer for receiving an external clock signal, a first delay unit for receiving an output signal of the buffer, a second delay unit for receiving an output signal of the first delay unit, and a second delay. A phase comparator for detecting a phase difference between a negative output signal and an output signal of the buffer, a first control unit receiving an output signal of a phase comparator and adjusting a delay time of the first delay unit, and frequency information of an external clock signal And a second controller for outputting a control signal for controlling the delay time of the second delay unit.

In one embodiment, the frequency information of the external clock signal applied to the second control unit is obtained from the MRS of the memory device.

In one embodiment, the second delay unit includes a plurality of delay elements, and selects only one of the plurality of delay elements according to a control signal output from the second control unit. Here, the delay amounts of each of the plurality of delay elements are determined differently and fixed.

In another embodiment of the present invention, a DL device for a memory device includes a buffer for receiving an external clock signal, a first delay unit for receiving an output signal of the buffer, a second delay unit for receiving an output signal of the first delay unit, A phase comparator for detecting a phase difference between an output signal of a second delay unit and an output signal of the buffer, a first control unit for receiving an output signal of a phase comparator and adjusting a delay time of the second delay unit, and frequency information of an external clock signal; A second control unit for outputting a control signal for controlling the delay time of the first delay unit using a.

In another embodiment of the present invention, the frequency information of the external clock signal applied to the second control unit is obtained from the MRS of the memory device. Here, the second delay unit includes a plurality of delay elements, and selects only one of the plurality of delay elements according to a control signal output from the second control unit.

(Example)

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

2 shows an embodiment of a DLL device according to the present invention.

As shown in the drawing, the DLL device includes buffers 200 and 201 for receiving external clock signals / CLK and CLK, and delay units for receiving output signals fclkt2 and rclkt2 of the buffers 200 and 201, respectively. 202 and 203, a delay control unit 204 for outputting a signal for controlling the delay times of the delay units 202 and 203, an output signal rclkt2 of the buffer 201 and an output signal of the replica delay unit 206. a phase comparator 205 for comparing the phases of (fb_clk) and providing the information to the delay control unit 204, delay units 207 and 208 for receiving the output signals of the delay units 202 and 203, respectively, and a delay; The MRS decoder 209 for controlling the delay times of the units 207 and 208, the replica delay unit 206 for receiving the output signals of the delay unit 208, and the output signals of the delay units 207 and 208, respectively, DLL drivers 210 and 211 for receiving are provided.

The respective output signals fclk_dll and rclk_dll of the DLL drivers 210 and 211 are applied to the data output buffers 212 and 213, respectively. In response, the data output buffers 212 and 213 output data DQ. .

In FIG. 2, t1 represents the delay time of the buffer for receiving the clock signals CLK and / CLK, td1 represents the delay time of the delay units 202 and 203, and td2 represents the delay of the delay units 207 and 208. Td represents td1 + td2, and t2 represents the delay from the DLL driver to the data output buffer. The delay time of the replica delay unit 206 is t1 + t2.

Unlike the related art, the DLL device of FIG. 2 is characterized by further comprising an MRS decoder and delay units 207 and 208 controlled by the DLL device.

3 shows another embodiment of a DLL device according to the present invention.

As shown in the drawing, the DLL device includes buffers 301 and 302 for receiving the external clock signals / CLK and CLK, and delay units for receiving the output signals fclkt2 and rclkt2 of the buffers 301 and 302, respectively. 303, 304, MRS decoder 305 for controlling the delay times of delay units 303, 304, delay units 306, 307 for receiving the output signals of delay units 303, 304, and delays, respectively. The phase of the delay control unit 308 for outputting a signal for controlling the delay times of the units 306 and 307 and the output signal rlktl2 of the buffer 302 and the output signal fb_clk of the replica delay unit 310 are compared. And a phase comparator 309 for providing the information to the delay control section 308, and DLL drivers 311 and 312 for receiving the output signals of the delay sections 306 and 307, respectively.

Each of the output signals fclk_dll and rclk_dll of the DLL drivers 311 and 312 is applied to the data output buffers 313 and 314, respectively. In response, the data output buffers 313 and 314 output the data DQ. .

In FIG. 3, t1 represents a delay time of a buffer for receiving the clock signals CLK and / CLK, td1 represents a delay time of the delay units 306 and 307, and td2 represents a delay of the delay units 303 and 304. Td represents td1 + td2, and t2 represents the delay from the DLL driver to the data output buffer. The delay time of the replica delay unit 310 is t1 + t2.

Unlike the related art, the DLL device of FIG. 3 further includes an MRS decoder and delay units 303 and 304 controlled by the DLL device.

Hereinafter, an embodiment of a delay unit controlled by the MRS decoder and control signals thereof disclosed in FIGS. 3 and 4 will be described with reference to FIGS. 4 to 7.

4 is an example of the MRS decoder of FIGS. 2 and 3. Here, MRS means a mode register set of the memory device.

As illustrated, the plurality of control signals tCK <0: 7> are output using the MRS code information MRS <0: 2>.

The MRS code information MRS <0: 2> contains frequency information of the external clock signal CLK.

Therefore, the MRS code information MRS <0: 2> varies according to the frequency of the external clock signal, and the control signal tCK <0: 7> that is enabled accordingly varies. For example, when the MRS code information (MRS <2>, MRS <1>, MRS <0>) is "0, 0, 0", only the control signal tCK <0> is enabled high, and the MRS code information When (MRS <2>, MRS <1>, MRS <0>) are "0, 1, 1", only the control signal tCK <3> is enabled high.

FIG. 5 is an example of the delay units 207, 208, 303, and 304 shown in FIGS. 2 and 3. For reference, "in" of FIG. 5 represents signals applied to the delay units 207, 208, 303, and 304 of FIGS. 2 and 3.

As shown in FIG. 5, the delay unit of FIG. 5 individually determines a delay time of the signal in applied to the delay elements tCK1_delay, tCK2_delay, ..., tCK7_delay according to the output signal tCK <0: 7> of the MRS decoder. It can be seen that it can be adjusted with.

That is, when the control signal tCK <0> is enabled, the input signal in is output without a delay, and when the control signal tCK <1> is enabled high, the input signal in is delayed. When the control signal tCK <2> is enabled after the device tCK1_delay is enabled, the input signal in is output after the delay device tCK2_delay, and the control signal tCK <3> is enabled. In this case, the input signal in is output after the delay element tCK3_delay, and when the control signal tCK <4> is enabled, the input signal in is output after the delay element tCK4_delay. When the signal tCK <5> is enabled, the input signal in is output beyond the delay element tCK5_delay, and when the control signal tCK <6> is enabled, the input signal in is delayed. When the control signal tCK <7> is enabled, the input signal in is output after the delayed element tCK7_delay. The delay time of each delay element is a delay element tCK1_delay <delay element tCK2_delay <delay element tCK3_delay <delay element tCK4_delay <delay element tCK5_delay <delay element tCK6_delay <delay element tCK7_delay to be.

FIG. 6 is another example of the delay units 207, 208, 303, and 304 illustrated in FIGS. 2 and 3.

As shown, it can be seen that the delay time of the signal in applied to the delay unit can be individually adjusted according to the output signal tCK <0: 7> of the MRS decoder of FIG. 4. In addition, since the basic operation is not significantly different from FIG. 5, a detailed operation description will be omitted.

FIG. 7 is another example of the delay units 207, 208, 303, and 304 illustrated in FIGS. 2 and 3.

As shown, it can be seen that the delay time of the signal in applied to the delay unit can be individually adjusted according to the output signal tCK <0: 7> of the MRS decoder of FIG. 4. In addition, since the basic operation is not significantly different from those of FIGS. 5 and 6, a detailed operation description will be omitted.

Hereinafter, an operation of a DLL device according to an embodiment of the present invention will be described with reference to FIGS. 2 to 6.

As can be seen from Figs. 2 and 3, the DLL device of the present invention includes two types of delay units.

The delay units 202, 203, 306, and 307 comprise a general delay unit using unit delay cells used in the conventional apparatus of FIG. However, the newly proposed delay units 207, 208, 303, and 304 are composed of a plurality of delay elements having different delay amounts (Figs. 5 to 7). These delay units 207, 208, 303 and 304 are one of a plurality of delay elements in accordance with the control signal tCK <0: 7> generated based on the information on the period tCK of the external clock signal through the MRS. Will be selected.

In operation, for example, when tCK is 10ns, t1 + t2 is 3ns, and the delay time td1 of the delay units 202, 203, 306, and 307 immediately after the DLL device reset is 1ns, a delay time of 6ns is obtained. If the delay elements are provided in the delay units 207, 208, 303 and 304 and the MRS is informed that tCK is 10 ns, the MRS decoder has a delay amount of 6 ns in the delay units 207, 208, 303 and 304. Select the delay element. Therefore, the value of t1 + td + t2 is set to 10 ns.

By doing this, the data DQ can be output in synchronization with the external clock signal immediately after the DLL reset. This consequently shortens the locking time.

During operation, the delay time of the delay units 202, 203, 306, and 307 is adjusted by the operation of the phase comparator to feed back the delay time change according to the change of the surrounding environment.

In addition, when the frequency of the external clock signal tCK changes during operation, tCK information is received by MRS and the delay elements used in the delay units 207, 208, 303, and 304 are reselected. Therefore, when the operating frequency changes, relocking can be performed in a short time during operation even without a DLL reset process.

In the present invention, the delay amount of the delay units 207, 208, 303, 304 is usually determined by tCK- (t1 + t2 + td), but when t1 + t2 + td is larger than tCK, (n-1) When * tCK <t1 + t2 + td <n * tCK, it is set to the size of n * tCK- (t1 + t2 + td). Therefore, the value of t1 + t2 + td becomes an integer multiple of tCK, and data can be output in synchronization with the external clock signal.

According to the present invention, the locking time can be reduced by additionally providing a delay unit capable of directly selecting a delay time of the delay unit according to the frequency of the external clock signal along with the locking operation.

Claims (16)

In the DL device for a memory device, A buffer for receiving an external clock signal, A first delay unit which receives an output signal of the buffer and outputs the first delay after the first delay; A second delay unit which receives the output signal of the first delay unit and outputs the second delay unit after outputting the second delay unit; A replica delay unit for replicating the output signal of the second delay unit; A phase comparator for detecting a phase difference between an output signal of the replica delay unit and an output signal of the buffer; A first control unit which receives the output signal of the phase comparator and controls the first delay time of the first delay unit; And a second controller configured to control the second delayed time of the second delay unit by using frequency information of the external clock signal. The method of claim 1, And the frequency information of the external clock signal applied to the second controller is obtained from the MRS of the memory device. The method of claim 2, And the second delay unit includes a plurality of delay elements, and selects only one of the plurality of delay elements according to a control signal output from the second control unit. The method of claim 3, wherein And a delay amount of each of the plurality of delay elements is determined and fixed differently. In the DL device for a memory device, A buffer for receiving an external clock signal, A first delay unit which receives an output signal of the buffer and outputs the first delay after the first delay; A second delay unit which receives the output signal of the first delay unit and outputs the second delay unit after outputting the second delay unit; A replica delay unit for replicating the output signal of the second delay unit; A phase comparator for detecting a phase difference between an output signal of the replica delay unit and an output signal of the buffer; A first controller which receives the output signal of the phase comparator and controls the second delay time of the second delay unit; And a second controller configured to control the first delayed time of the first delay unit by using frequency information of the external clock signal. The method of claim 5, wherein And the frequency information of the external clock signal applied to the second controller is obtained from the MRS of the memory device. The method of claim 6, And the first delay unit includes a plurality of delay elements, and selects only one of the plurality of delay elements according to a control signal output from the second control unit. The method of claim 7, wherein And a delay amount of each of the plurality of delay elements is determined and fixed differently. In the DL device for a memory device, A first delay circuit for receiving a first clock signal synchronized with a falling edge of an external clock signal and sequentially performing a first delay and a second delay; A second delay circuit that receives a second clock signal synchronized with the rising edge of the external clock signal and sequentially performs the first delay and the second delay; A replica delay unit for replicating the output of the second delay circuit; A phase comparator for detecting a phase difference between an output signal of the replica delay unit and the second clock signal; A first control unit which receives an output signal of the phase comparator and controls the first delayed time of the first and second delay circuits; And And a second controller configured to control the second delayed time of the first and the second delay circuits using the frequency information of the external clock signal. The method of claim 9, And the frequency information of the external clock signal applied to the second controller is obtained from the MRS of the memory device. The method of claim 10, The first and second delay circuits include a plurality of delay elements connected in parallel to perform the second delay, and one of the plurality of delay elements is output from the second control unit for the second delay. DL device, characterized in that configured to be selected by the control signal. The method of claim 11, And a delay amount of each of the plurality of delay elements is determined and fixed differently. In the DL device for a memory device, A first delay circuit for receiving a first clock signal synchronized with a falling edge of an external clock signal and sequentially performing a first delay and a second delay; A second delay circuit that receives a second clock signal synchronized with the rising edge of the external clock signal and sequentially performs the first delay and the second delay; A replica delay unit for replicating the output of the second delay circuit; A phase comparator for detecting a phase difference between an output signal of the replica delay unit and the second clock signal; A first control unit which receives the output signal of the phase comparator and controls the second delayed time of the first and second delay circuits; And And a second controller configured to control the first delayed time of the first and the second delay circuits using the frequency information of the external clock signal. The method of claim 13, And the frequency information of the external clock signal is obtained from the MRS of the memory device. The method of claim 14, The first and second delay circuits include a plurality of delay elements connected in parallel to perform the first delay, and any one of the plurality of delay elements is output from the second controller for the first delay. DL device, characterized in that configured to be selected by the control signal. The method of claim 15, And a delay amount of each of the plurality of delay elements is determined and fixed differently.

Images