JP4459258B2 - Electronic component mounting method - Google Patents

Description

The present invention relates to a printed circuit board for electronic circuits (referred to herein as a “substrate” as a representative example, but this “substrate” means an object to be mounted such as an interposer or other component on which an electronic component is mounted. If the electronic components for example, an IC chip and a surface acoustic wave (SAW) device of a single (IC chip.) is relates to the implementation how the electronic components to the circuit board mounted with bare IC) state.

  Today, electronic circuit boards are used in various products, their performance improves day by day, the frequency used on the circuit board is also increasing, and flip chip mounting where impedance is low uses high frequency It is a mounting method suitable for electronic equipment. Also, with the increase in portable devices, flip chip mounting is required for mounting an IC chip on a circuit board as it is, not as a package. For this reason, a certain number of defective products are mixed in an IC chip that is mounted on a circuit board as it is alone or mounted on an electronic device or a flat panel display. In addition to the flip chip, CSP (Chip Size Package), BGA (Ball Grid Array) and the like have been used.

  As a method for joining an IC chip to a circuit board of a conventional electronic device (conventional example 1), there is one disclosed in Japanese Patent Publication No. 06-66355. This is shown in FIG. As shown in FIG. 15, the Ag paste 74 is transferred to the IC chip 71 on which the bump 73 is formed and connected to the electrode 75 of the circuit board 76, and then the Ag paste 74 is cured, and then the sealing material 78 is attached to the IC chip 71. A method of pouring between the circuit board 76 and the circuit board 76 is generally known.

  Further, as a method of joining an IC chip to a liquid crystal display (conventional example 2), an anisotropic conductive film 80 is used as shown in Japanese Patent Publication No. 62-6652 shown in FIG. An anisotropic conductive adhesive layer 81 formed by adding conductive fine pieces 82 in a resin 83 is peeled off from the separator 85 and applied to the glass of the substrate or the liquid crystal display 84, and the IC chip 86 is thermocompression bonded, thereby making the Au A semiconductor chip connection structure in which the anisotropic conductive adhesive layer 81 is interposed between the lower surface of the IC chip 86 other than under the bumps 87 and the substrate 84 is generally known.

  In Conventional Example 3, a UV curable resin is applied to a substrate, an IC chip is mounted on the substrate, and the resin between the two is cured by applying UV while applying pressure. Methods of maintaining are known.

  Thus, in order to join the IC chips, an IC chip such as a flat package is die-bonded on the lead frame, the IC chip electrodes and the lead frame are connected by wire bonding, and resin molding is performed to form a package. Later, the bonding was performed by printing a cream solder on a circuit board, mounting a flat package IC thereon, and performing a reflow process. In these methods called SMT (Surface Mount Technology), the process of packaging the IC is long, and it takes time to produce the IC components, and it is difficult to reduce the size of the circuit board. For example, when the IC chip is sealed in a flat pack, it requires about 4 to 10 times the area of the IC chip, and this has been a factor that hinders downsizing.

  On the other hand, a flip chip method in which an IC chip is directly mounted on a substrate in a bare state for shortening the process and reducing the size and weight has recently been used. This flip chip method is used for stud bump bonding (SBB) for bump formation to IC chip, bump leveling, transfer of Ag / Pd paste, mounting, inspection, sealing with sealing resin, and inspection. Many methods have been developed, such as the formation of bumps and the application of UV curable resin to a substrate in parallel, followed by mounting, UV curing of the resin, and UV resin bonding for inspection.

  However, each method has a drawback that it takes time to cure the paste for joining the bumps of the IC chip and the electrodes of the substrate and to apply and cure the sealing resin, resulting in poor productivity. Further, it is necessary to use a ceramic or glass whose warpage is controlled as a circuit board, which has a disadvantage of being expensive.

  Further, in the method of using the conductive paste as the bonding material as in Conventional Example 1, it is necessary to use the bumps of the IC chip after leveling and flattening in order to stabilize the transfer amount.

  Moreover, in the joining structure by anisotropic conductive adhesive like the prior art example 2, what uses glass as a base material of a circuit board is developed, but the conductive particle in a conductive adhesive is disperse | distributed uniformly. In order to cause a short circuit due to abnormal dispersion of particles, an expensive conductive adhesive, or to make the bump height uniform, bumps on the electrodes of the IC chip must be formed by electroplating. I had to.

  Further, in the method of bonding using a UV curable resin as in Conventional Example 3, the bump height variation must be ± 1 (μm) or less, and a flat surface such as a resin substrate (glass epoxy substrate) or the like. There was a problem that it could not be bonded to a poor substrate. Also in the method using solder, it is necessary to pour and harden the sealing resin after bonding in order to alleviate the thermal expansion / contraction difference between the substrate and the IC chip. The curing of the resin sealing requires a time of 2 to 8 hours, and there is a problem that productivity is extremely poor.

Accordingly, an object of the present invention is to solve the above-mentioned problem, and after bonding the circuit board and the electronic component, the sealing resin process that flows between the electronic component and the substrate and the bumps that make the bump height uniform without requiring a leveling process is an electronic component that provides an implementation how the electronic components to the circuit board to be joined with high productivity and high reliability on a substrate.

  In order to achieve the above object, the present invention is configured as follows.

According to the first aspect of the present invention, the gold bump is formed on the electrode of the electronic component,
Without leveling the formed bumps, the electrode of the electronic component and the electrode of the circuit board are aligned while interposing a solid or semi-solid insulating resin layer in which an inorganic filler is mixed with an insulating resin. Mounting the electronic component on the substrate,
Thereafter, a load of 20 gf or less per bump is applied from the upper surface side of the electronic component by a tool to prepare a tip so as to prevent the neck portion of the gold bump from collapsing, and an ultrasonic wave is applied to apply the gold bump and the above Metal bonding the above electrode of the substrate,
Next, while heating from the upper surface side of the electronic component, heating from the substrate side, or heating from both the electronic component side and the substrate side, the electronic component is placed on the circuit board. Pressing with a pressure of 20 gf or more per bump, correcting the warping of the substrate and crushing the bump, curing the insulating resin interposed between the electronic component and the circuit board, and the electronic component An electronic component mounting method is provided, wherein the circuit board is joined to electrically connect the electrode of the electronic component and the electrode of the circuit board.

According to the present invention, after joining the circuit board and the electronic component, there is no need for a sealing resin process that flows between the electronic component and the board or a bump leveling process that keeps the bump height constant. implementation how the electronic components to the circuit board to be joined with high productivity and high reliability can be provided.

Embodiments according to the present invention will be described below in detail with reference to the drawings.
(First embodiment)
Hereinafter, an electronic component according to the first embodiment of the present invention, for example, an IC chip mounting method and apparatus, and an electronic component unit or module in which the IC chip is mounted on the substrate by the mounting method, for example, a circuit as an example of a semiconductor device A method of mounting an IC chip on a substrate and a mounting apparatus thereof will be described with reference to FIGS.

  First, an IC chip mounting method on a circuit board according to the first embodiment of the present invention will be described with reference to FIGS. 1 (A) to 4 (C). In the IC chip 1 which is an example of the electronic component of FIG. 1A, bumps (projection electrodes) 3 are formed on the Al pad electrode 2 of the IC chip 1 by the operation shown in FIGS. 3A to 3F by a wire bonding apparatus. Form. That is, the ball 96 is formed at the lower end of the wire 95 protruding from the capillary 93 which is the holder in FIG. 3A, the capillary 93 holding the wire 95 is lowered in FIG. 3 is joined to the electrode 2 to form the shape of the bump 3. In FIG. 3C, the wire 95 is sent downward, and the capillary 93 starts to rise, and a substantially rectangular loop as shown in FIG. The capillary 93 is moved to 99 to form the curved portion 98 on the upper portion of the bump 3 as shown in FIG. 3E, and the bump 3 as shown in FIG. 3F is formed by tearing. Alternatively, in FIG. 3B, the wire 95 is clamped by the capillary 93, and the capillary 93 is lifted and pulled upward, so that a metal wire, for example, a gold wire (gold wire) 95 (as an example of the metal wire) Is a wire of tin, aluminum, copper, or an alloy in which a trace element is contained in these metals, but in the following embodiment, it is described as a gold wire (gold wire) as a representative example. You may make it form the shape of bump 3 like FIG.3 (G). FIG. 1B shows a state in which the bump 3 is formed on each electrode 2 of the IC chip 1 as described above.

Next, as shown in FIG. 1 (D), a solid in which an inorganic filler 6f cut to a size slightly larger than the size of the IC chip 1 is blended on the electrode 5 of the circuit board 4 shown in FIG. 1 (C). Alternatively, an insulating resin sheet as an example of a semi-solid insulating resin layer, for example, a thermosetting resin sheet 6 is disposed, and for example, about 5 to 10 kgf / cm ² by a pasting tool 7 heated to 80 to 120 ° C. The thermosetting resin sheet 6 is stuck on the electrode 5 of the substrate 4 on the stage 109 with pressure. Then, the preparatory process of the board | substrate 4 is completed by peeling the separator 6a arrange | positioned so that removal to the tool 7 side of the solid or semisolid thermosetting resin sheet 6 which mix | blended the inorganic filler 6f was carried out. The separator 6a is for preventing the solid or semi-solid thermosetting resin sheet 6 in which the inorganic filler 6f is blended with the tool 7 from sticking. Here, as shown in FIG. 1 (G) by partially enlarging the G portion of FIG. 1 (F), the thermosetting resin sheet 6 is made of an inorganic filler such as ceramics such as spherical or crushed silica or alumina. 6f is dispersed in an insulating resin 6m and mixed, and this is flattened by a doctor blade method or the like, and the solvent component is vaporized and solidified, and heat resistance sufficient to withstand high temperatures in the subsequent reflow process It is preferable to have (for example, heat resistance that can withstand 240 ° C. for 10 seconds). The insulating resin is, for example, an insulating thermosetting resin (for example, epoxy resin, phenol resin, polyimide, etc.), or an insulating thermoplastic resin (for example, poniphenylene sulfide (PPS), polycarbonate, modified polyphenylene oxide (PPO). Etc.), or a mixture of an insulating thermosetting resin and an insulating thermoplastic resin can be used. Here, the description will continue as an insulating thermosetting resin as a representative example. The glass transition point of this thermosetting resin 6m is generally about 120 to 200 ° C. When using only thermoplastic resin, first heat and soften it first, then stop heating and let it cool naturally, while mixing insulating thermoplastic resin with thermoplastic resin In the case of using the above-mentioned one, the thermosetting resin functions more dominantly, so that it is cured by heating with only the thermosetting resin as in the case.

Next, as shown in FIGS. 1 (E) and 1 (F), in the electronic component mounting apparatus 600 of FIG. While the IC chip 1 formed on the electrode 2 is sucked and held from the tray 602, the IC chip 1 is fixed to the substrate 4 prepared in the previous step and placed on the stage 9. Then, the IC chip 1 is pressed against the substrate 4 by the heated bonding tool 8 after positioning so that the electrode 2 is positioned on the electrode 5 of the corresponding substrate 4. This alignment uses a known position recognition operation. For example, as shown in FIG. 21C, the position recognition mark 605 or the lead or land pattern formed on the substrate 4 is recognized by the substrate recognition camera 604 of the electronic component mounting apparatus 600, and FIG. As shown in FIG. 4, based on the image 606 obtained by the camera 604, the position of the substrate 4 is determined by recognizing the XY coordinate position of the substrate 4 in the XY direction perpendicular to the stage 9 and the rotation position of the XY coordinate with respect to the origin. recognize. On the other hand, as shown in FIG. 21A, the IC chip 1 position recognition camera 603 recognizes the position recognition mark 608 or the circuit pattern of the IC chip 1 attracted and held by the bonding tool 8, and FIG. As shown in FIG. 5, the position of the IC chip 1 is recognized by recognizing the XY coordinate position of the IC chip 1 in the XY direction and the rotation position with respect to the origin of the XY coordinate based on the image 607 obtained by the camera 603. Then, based on the result of position recognition between the substrate 4 and the IC chip 1, the bonding tool 8 or the stage 9 is moved so that the electrode 2 of the IC chip 1 is positioned on the electrode 5 of the corresponding substrate 4. After the alignment, the IC chip 1 is pressed against the substrate 4 by the heated joining tool 8.
At this time, the bump 3 is pressed while its head 3a is deformed on the electrode 5 of the substrate 4 as shown in FIGS. 4 (A) to 4 (B). At this time, as shown in FIG. 2 (A) to FIG. 2 (B), the inorganic filler 6f in the thermosetting resin 6m has sharp bumps 3 that have entered the thermosetting resin 6m at the beginning of bonding. As a result, the bump 3 is pushed outward. Further, as shown in FIG. 2 (C), the inorganic filler 6f does not enter between the bump 3 and the substrate electrode 5 due to the outward pushing action, thereby exhibiting an effect of reducing the connection resistance value. At this time, even if the inorganic filler 6f slightly enters between the bump 3 and the substrate electrode 5, there is no problem at all because the bump 3 and the substrate electrode 5 are in direct contact.
At this time, the load applied to the bump 3 side via the IC chip 1 varies depending on the outer diameter of the bump 3, but the head 3 a of the bump 3 that is bent and overlapped is surely shown in FIG. Thus, it is necessary to apply a load that deforms. This load requires a minimum of 20 (gf / per bump). That is, FIG. 17 shows that the resistance value is larger than the bump value of 100 mmΩ / bump and less than 20 mm (per gf / bump) from the graph of the relationship between the resistance value and the load in the case of the 80 μm outer diameter bump. It is shown that it is preferable to be 20 (gf / per bump) or more because it becomes too much to be practically problematic. FIG. 18 is a graph showing a highly reliable area based on the relationship between the bumps having outer diameters of 80 μm and 40 μm and the minimum load. Accordingly, the minimum load is preferably 25 (gf / per bump) for bumps with an outer diameter of 40 μm or more, and the minimum load is 20 (gf / per bump) for bumps with an outer diameter of less than 40 μm. It is estimated that the above is highly reliable. In the future, when the outer diameter of the bump is reduced to less than 40 μm as the lead pitch is reduced, it is estimated that the load tends to decrease in proportion to the square of the bump according to the projected area of the bump. Therefore, it is preferable that the minimum load applied to the bump 3 side via the IC chip 1 requires 20 (gf / per bump). The upper limit of the load applied to the bump 3 side via the IC chip 1 is set such that the IC chip 1, the bump 3, the circuit board 4 and the like are not damaged. In some cases, the maximum load may exceed 150 (gf / per bump). In the figure, reference numeral 6s is a resin in which the thermosetting resin 6m being melted by the heat of the joining tool 8 in the thermosetting resin sheet 6 is thermally cured after being melted.

  The IC chip 1 in which the bumps 3 are formed on the electrodes 2 in the previous process is applied to the substrate 4 prepared in the previous process by the bonding tool 8 heated by the built-in heater 8a such as a ceramic heater or a pulse heater. On the other hand, an alignment process for aligning the electrode 2 of the IC chip 1 so as to be positioned on the electrode 5 of the corresponding substrate 4 as shown in FIG. 1E, and after the alignment, as shown in FIG. The step of pressing and bonding in this manner may be performed by one positioning and pressing bonding apparatus, for example, the positioning and pressing bonding apparatus of FIG. However, in order to improve productivity by performing the alignment operation and the press bonding operation simultaneously in separate apparatuses, for example, when a large number of substrates are continuously produced, the alignment process is performed as shown in FIG. You may make it perform with the aligning apparatus and perform the said press joining process with the joining apparatus of FIG.5 (C). In FIG. 5C, two bonding apparatuses 8 are shown to improve productivity, and two locations of one circuit board 4 can be pressed and bonded simultaneously.

  The circuit board 4 is sold as a ceramic multilayer board, FPC, glass cloth laminated epoxy board (glass epoxy board), glass cloth laminated polyimide resin board, aramid non-woven cloth epoxy board (for example, registered trade mark “ALIVH” manufactured by Matsushita Electric Industrial Co., Ltd.) Resin multilayer substrate) or the like is used. These substrates 4 are warped and wavy due to thermal history, cutting, and processing, and are not necessarily a perfect plane. Therefore, as shown in FIGS. 5 (A) and 5 (B), for example, a stage from the joining tool 8 side by the joining tool 8 and the stage 9 in which the parallelism is respectively controlled so as to be adjusted to about 10 μm or less. By applying heat and a load locally to the circuit board 4 through the IC chip 1 toward the 9 side, the warp of the applied part of the circuit board 4 can be corrected. In addition, the IC chip 1 is warped with the center of the active surface being concave, but by pressing it with a strong load of 20 gf or more per bump at the time of bonding, warping and undulation of both the substrate 4 and the IC chip 1 are caused. It can be corrected. The warpage of the IC chip 1 is caused by internal stress generated when a thin film is formed on Si when the IC chip 1 is formed. The deformation amount of the bump is about 10 to 25 μm, and it can be allowed by adapting each bump 3 to the influence of the undulation appearing on the surface from the inner layer copper foil that the substrate of this level has from the beginning by adapting the deformation of the bump 3. become.

In a state where the warping of the circuit board 4 is corrected in this way, for example, heat of 140 to 230 ° C. is applied to the thermosetting resin sheet 6 between the IC chip 1 and the circuit board 4 for about several seconds to 20 seconds, for example. The functional resin sheet 6 is cured. At this time, first, the thermosetting resin 6m constituting the thermosetting resin sheet 6 flows and seals to the edge of the IC chip 1. In addition, since it is a resin, it is naturally softened when heated, so that fluidity flows to the edge in this way. By making the volume of the thermosetting resin 6 m larger than the volume of the space between the IC chip 1 and the circuit board 4, the thermosetting resin 6 m flows out of the space and can provide a sealing effect. Thereafter, when the heated tool 8 rises, the heating source disappears, so that the temperature of the IC chip 1 and the thermosetting resin sheet 6 rapidly decreases, and the thermosetting resin sheet 6 loses fluidity, As shown in FIGS. 1 (F) and 4 (C), the IC chip 1 is fixed on the circuit board 4 by a cured thermosetting resin 6s. Moreover, if the circuit board 4 side is heated by the heater 9a of the stage 9, etc., the temperature of the joining tool 8 can be set lower.
(Second Embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a second embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are provided. explain.

  In this 2nd Embodiment, the mixing ratio of the inorganic filler 6f mix | blended with the thermosetting resin sheet 6 in 1st Embodiment is 5-90 wt of the said insulating thermosetting resin, for example, the insulating thermosetting epoxy resin 6m. % Is more suitable. If it is less than 5 wt%, there is no point in mixing the inorganic filler 6f. On the other hand, if it exceeds 90 wt%, the adhesive strength is extremely lowered and it becomes difficult to form a sheet, which is not preferable. As an example, from the viewpoint of maintaining high reliability, 20 to 40 wt% is preferable for a resin substrate and 40 to 70 wt% for a ceramic substrate, and the linear expansion coefficient of the sheet sealant is considerably reduced even when the glass epoxy substrate is about 20 wt%. This is effective in the resin substrate. In volume%, the ratio is approximately half of wt%, or the ratio of specific gravity of about 2 silica to 1 epoxy resin. Usually, the mixing ratio of the inorganic filler 6f is determined by the manufacturing conditions when the thermosetting resin 6m is formed, the elastic modulus of the substrate 4, and finally the reliability test result.

  By blending the inorganic filler 6f in the mixing ratio as described above into the thermosetting resin sheet 6, the elastic modulus of the thermosetting resin 6m of the thermosetting resin sheet 6 can be increased, and the thermal expansion coefficient is lowered. Thus, the bonding reliability between the IC chip 1 and the substrate 4 can be improved. Further, the mixing ratio of the inorganic filler 6f can be determined so as to optimize the material constant of the thermosetting resin 6m, that is, the elastic modulus and the linear expansion coefficient, in accordance with the material of the substrate 4. Note that, as the mixing ratio of the inorganic filler 6f increases, the elastic modulus increases, but the linear expansion coefficient tends to decrease.

  In the first embodiment and the second embodiment, it is easy to handle because it uses a solid thermosetting resin sheet 6 instead of a liquid, and since it has no liquid component, it can be formed of a polymer and has a high glass transition point. There is an advantage that it is easy to form things.

In addition, in FIGS. 1 (A) to 1 (G) and FIGS. 2 (A) to 2 (C) and FIGS. 6 and 7 described later, a thermosetting resin sheet 6 as an example of an insulating resin layer. Alternatively, the thermosetting adhesive 6b is formed on the circuit board 4 side, but the present invention is not limited to this, and as shown in FIG. 14A or FIG. 14B, the IC chip 1 side is formed. After being formed, it may be bonded to the substrate 4. In this case, particularly in the case of the thermosetting resin sheet 6, the suction nozzle is attached to the elastic body 117 such as rubber on the stage 201 together with the separator 6 a detachably disposed on the circuit board side of the thermosetting resin sheet 6. Alternatively, the IC chip 1 held by the holding member 200 may be pressed so that the thermosetting resin sheet 6 is attached to the IC chip 1 along the shape of the bump 3.
(Third embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a third embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are provided. This will be described with reference to FIGS. 6A to 6C and FIGS. 7A to 7F.

  In this third embodiment, instead of attaching the thermosetting resin sheet 6 to the substrate 4 in the first embodiment, as shown in FIGS. 6 (A) and 7 (A), (D), an insulating property is provided. A liquid thermosetting adhesive 6b as an example of a resin layer is applied, printed, or transferred onto the circuit board 4 with a dispense 502 or the like, and then solidified to a semi-solid state, so-called B-stage state. Yes. Thereafter, the IC chip 1 is mounted on the substrate 4 as in the first or second embodiment.

  Specifically, as shown in FIG. 6A, the liquid thermosetting adhesive 6b is applied onto the circuit board 4, the discharge amount is controlled by air pressure as shown in FIG. Application, printing, or transfer is performed by a dispense 502 that is movable in two orthogonal directions. Next, as shown in FIG. 6 (B), a tool 78 incorporating a heater 78a is applied to heat and pressure to make it uniform and solidify to a semi-solid state, so-called B stage state, as shown in FIG. 6 (C).

  Alternatively, when the viscosity of the liquid thermosetting adhesive 6b is low, the liquid thermosetting adhesive 6b is applied to a predetermined position on the substrate 4 with a dispenser 502 as shown in FIG. After that, since the thermosetting adhesive 6b has a low viscosity, it naturally spreads on the substrate, resulting in a state as shown in FIG. Thereafter, as shown in FIG. 7C, the substrate 4 is placed in a furnace 503 by a transfer device 505 such as a conveyor, and the liquid thermosetting of the insulating resin applied by the heater 504 of the furnace 503 is performed. By curing the adhesive 6b, it is solidified to a semi-solid state, that is, a so-called B-stage state.

  On the other hand, when the viscosity of the liquid thermosetting adhesive 6b is high, the liquid thermosetting adhesive 6b is applied to a predetermined position on the substrate 4 with the dispenser 502 as shown in FIG. After that, since the thermosetting adhesive 6b has a high viscosity and does not naturally spread on the substrate, it is flattened with a squeegee 506 as shown in FIGS. Thereafter, as shown in FIG. 7C, the substrate 4 is placed in a furnace 503 by a transfer device 505 such as a conveyor, and the liquid thermosetting of the insulating resin applied by the heater 504 of the furnace 503 is performed. By curing the adhesive 6b, it is solidified to a semi-solid state, that is, a so-called B-stage state.

  Thus, when making thermosetting adhesive 6b semi-solid, although there is a difference depending on the characteristics of the thermosetting resin in thermosetting adhesive 6b, 30 to 80% of the glass transition point of the thermosetting resin. It presses at 80-130 degreeC which is the temperature of this. Usually, it is performed at a temperature of about 30% of the glass transition point of the thermosetting resin. As described above, the reason why the glass transition point of the thermosetting resin is 30 to 80% is that if it is within the range of 80 to 130 ° C. from the graph of the heating temperature and the reaction rate of the resin sheet in FIG. A sufficient range for further reaction can be left in the process. In other words, if the temperature is in the range of 80 to 130 ° C., depending on the time, the reaction rate of the insulating resin such as epoxy resin can be suppressed to about 10 to 50%. There is no problem. That is, a predetermined pressing amount can be ensured when pressing at the time of IC chip press-bonding, and it is difficult to cause a problem that the pressing cannot be performed. In addition, semi-solid may be obtained by suppressing the reaction and vaporizing only the solvent.

In the case where a plurality of IC chips 1 are mounted on the substrate 4 after the thermosetting adhesive 6b is semi-solidified as described above, the plurality of IC chips 1 on the substrate 4 are mounted at a plurality of locations. The semi-solidification step of the thermosetting adhesive 6b is performed in advance as a pre-setup step, and the plurality of IC chips 1 are placed on the substrate 4 supplied by supplying the substrate 4 thus pre-set. Productivity becomes higher by joining to the place. In the subsequent steps, even when the thermosetting adhesive 6b is used, the same steps as those using the thermosetting resin sheet 6 of the first or second embodiment described above are basically performed. By adding the semi-fixing step, the liquid thermosetting adhesive 6b can be used in the same manner as the thermosetting resin sheet 6, and since it is solid, it is easy to handle and has no liquid component, so it is formed of a polymer. And has an advantage of easily forming a glass transition point. When the fluid thermosetting adhesive 6b is used as described above, it is applied to an arbitrary position on the substrate 4 in an arbitrary size as compared with the case where the solid thermosetting resin sheet 6 is used. It also has the advantage that it can be printed or transferred.
(Fourth embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a fourth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are provided. This will be described with reference to FIG. The fourth embodiment differs from the first embodiment in that when the IC chip 1 is bonded to the substrate 4, an ultrasonic wave is also applied in addition to the load, and the bump 3 is not leveled and is 20 gf or less as required. The bump tip is adjusted so as to prevent a short-circuit with an adjacent bump or electrode due to a fall of the neck (whisker) portion of the tip of the bump 3 caused by the shredding at the time of bump formation. The IC chip 1 is mounted on the substrate 4 in alignment with the chip 1, and the metal bump 3 is thermocompression-bonded with the metal on the electrode surface on the substrate side and ultrasonic waves. The state in which the IC chip 1 is bonded to the substrate 4 is the same as in FIGS. 2 and 6 in the previous embodiment.
When applying the ultrasonic wave to metal-bond the gold bump and the electrode of the substrate, heating from the upper surface side of the electronic component, heating from the substrate side, or the electronic component Heating may be performed from both the substrate side and the substrate side.

  In the fourth embodiment, a solid thermosetting resin sheet 6 in which an insulating filler 6f is blended with an insulating thermosetting resin 6m or a liquid thermosetting adhesive 6b semi-solidified as described above is used. After bonding to the substrate 4 or applying a thermosetting adhesive 6b containing a thermosetting resin to the substrate 4 to make it semi-solid, the electrode 5 of the circuit substrate 4 and the electrode 2 of the electronic component 1 are similar to the wire bonding. 3A to 3F, a ball 96 is formed by electric spark at the tip of the gold wire 95, and this ball 96 is formed on the substrate electrode 5 by ultrasonic thermocompression bonding using a capillary 93. The bump 3 is aligned with the IC chip 1 without being leveled, and the IC chip 1 is mounted on the substrate 4. Here, “the liquid thermosetting adhesive 6b semi-solidified as described above” means that the liquid thermosetting adhesive 6b as described in the third embodiment is semi-solidified. It is almost the same as the B stage. By using this, a material cheaper than the sheet sealing material or ACF (anisotropic conductive film) can be used. At this time, in the ultrasonic wave application device 620 shown in FIG. 22, the load by the air cylinder 625 from the upper surface of the IC chip 1 attracted to the bonding tool 628 by the bonding tool 628 preliminarily heated by the built-in heater 622, and the piezoelectric element The gold bump 3 while adjusting the tip so as to prevent the neck portion of the gold bump 3 from collapsing by applying the ultrasonic wave generated by the ultrasonic generator 623 and applied via the ultrasonic horn 624. And the gold plating on the substrate side are metal-bonded. Next, while heating from the upper surface of the IC chip 1 or the substrate side, the IC chip 1 is pressed against the circuit board 4 with a pressing force of 20 gf or more per bump to correct the warp of the board 4 and the bump 3. The thermosetting resin sheet 6 or the thermosetting adhesive 6b interposed between the IC chip 1 and the circuit board 4 is cured by the heat to crush the IC chip 1 and the circuit board 4. It joins and both the electrodes 2 and 5 are electrically connected. In addition, at the time of the metal joining by the ultrasonic wave application device 620, heating may be performed from the upper surface side of the IC chip 1, from the substrate side, or from both the IC chip 1 side and the substrate side. Good. Specifically, the built-in heater 622 heats the IC chip 1 from the upper surface side, the circuit board 4 side from the substrate side is heated by the heater 9a of the stage 9, or the built-in heater 622. The heater 9a of the stage 9 may be heated from both the IC chip 1 side and the substrate side.

  The reason why a pressing force of 20 gf or more per bump is required is that the frictional heat is hardly generated even in the joining using ultrasonic waves as described above, so that the joining cannot be performed. Even in the case of bonding gold and gold, the bumps are pressed with a certain load, and ultrasonic waves are applied thereto to generate frictional heat, thereby bonding the metals together. Therefore, in this case as well, a constant load enough to press the bumps, that is, a pressing force of 20 gf or more per bump is required. As an example of the applied pressure, it is set to 50 gf or more per bump.

According to the fourth embodiment, since the metal plating of the metal bump 3 and the substrate 4 is metal diffusion bonded, when it is desired to increase the strength at the bump portion or when it is desired to further reduce the connection resistance value. It is suitable for.
(Fifth embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a fifth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are provided. This will be described with reference to FIGS. 8A to 8C and FIGS. 9A to 9C. The fifth embodiment is different from the first embodiment in that the sealing step can be omitted.

As described above, the protruding electrodes (bumps) 3 are formed on the electrodes 2 on the IC chip 1, and the circuit board 4 is formed on the circuit board 4 as shown in FIGS. 8B, 8 C, 9 A, and 23. As shown in the figure, a rectangular sheet-like thermosetting resin sheet 6 or a thermosetting adhesive 6b having a shape dimension smaller than a substantially rectangular outer dimension OL connecting the inner edges of the plurality of electrodes 2 of the IC chip 1 is provided. Affixed or applied to the central portion of the circuit board 4 where the electrodes 5 are connected. At this time, the thickness of the sheet-like thermosetting resin sheet 6 or the thermosetting adhesive 6 b is set so that the volume thereof is larger than the gap between the IC chip 1 and the substrate 4. Further, a rectangular sheet-like thermosetting resin sheet 656 that is unwound from the rewinding roll 644 and wound around the winding roll 643 by the affixing device 640 in FIG. The upper and lower cutters 641 are cut into shapes smaller than the generally rectangular outer dimensions OL connecting the inner edges of the plurality of electrodes 2 of the IC chip 1. The cut rectangular sheet-like thermosetting resin sheet 6 is sucked and held by a pasting head 642 preheated by a built-in heater 646 and pasted to the central portion of the circuit board 4 connecting the electrodes 5. The Next, the bump 3 and the electrode 5 of the circuit board 4 are aligned, and as shown in FIGS. 8A and 9B, the IC chip 1 is attached to the circuit board 4 by the bonding tool 8 heated by the heater 8a. The thermosetting resin sheet 6 or the thermosetting adhesive 6b interposed between the IC chip 1 and the circuit board 4 is cured while simultaneously correcting the warp of the board 4 by pressing and pressing. At this time, the thermosetting resin sheet 6 or the thermosetting adhesive 6b is softened as described above by the heat applied from the joining tool 8 through the IC chip 1, and is attached as shown in FIG. 9C. Pressurized from the position where it is applied or applied and flows outward. The flowing thermosetting resin sheet 6 or thermosetting adhesive 6b becomes a sealing material (underfill), and the bonding reliability between the bumps 3 and the electrodes 5 is remarkably improved. Further, after a certain period of time, the thermosetting resin sheet 6 or the thermosetting adhesive 6b gradually cures, and finally the IC chip 1 and the circuit board 4 are joined by the cured resin 6s. It will be. By raising the joining tool 8 pressing the IC chip 1, the joining of the IC chip 1 and the electrode 5 of the circuit board 4 is completed. Strictly speaking, in the case of thermosetting, the reaction of the thermosetting resin proceeds while heating, and the joining tool 8 rises and the fluidity is almost lost. According to the method as described above, since the thermosetting resin sheet 6 or the thermosetting adhesive 6b does not cover the electrode 5 before joining, the bump 3 directly contacts the electrode 5 when joining, and the electrode 5 The thermosetting resin sheet 6 or the thermosetting adhesive 6b does not enter below, and the connection resistance value between the bump 3 and the electrode 5 can be lowered. Further, if the circuit board side is heated, the temperature of the bonding head 8 can be further lowered. When this method is applied to the third embodiment, it is possible to more easily join the gold bump and the gold electrode of the circuit board (for example, nickel or gold plated copper or tungsten).
(Sixth embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a sixth embodiment, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are shown in FIGS. This will be described with reference to FIG. The sixth embodiment is different from the first embodiment in that highly reliable bonding can be achieved even when the bump 103 is mounted on the electrode 5 of the circuit board 4 in a shifted manner.

In the sixth embodiment, as shown in FIG. 10A, when the bump 3 is formed on the IC chip 1, a gold ball 96 is formed by electric sparking with a gold wire 95 similarly to wire bonding. Next, while adjusting the size of the ball according to the time when electric sparking is performed, a ball 96a having a diameter Φd-Bump indicated by 95a is formed,
The ball 96a having the diameter Φd-Bump thus formed is controlled by the time or voltage parameter for generating an electric spark, and the Chamfer diameter indicated by 93a of the capillary 193 having a Chamfer angle θc of 100 ° or less. The ball 96a is formed so that φD is 1/2 to 3/4 of the gold ball diameter d-Bump.
As shown in FIG. 10C, the flat portion 93b is not provided in the portion of the capillary 93 that contacts the gold ball to form the bump 3 as shown in FIG. As shown in FIG. 10B, the capillary 193 has a tip-shaped capillary 193 having a tip portion 193a that does not provide a flat portion at the portion in contact with the gold ball 96a. A bump 103 as shown in FIG. By using the tip-shaped capillary 193, the bump 103 having a generally conical tip as shown in FIG. 10B can be formed on the electrode 2 of the IC chip 1. Even when the bump 103 having a generally conical tip formed by the above method is mounted on the electrode 5 of the circuit board 4 as shown in FIG. 11C, the bump 103 has a generally conical tip. If the deviation is up to half of the outer diameter of the bump 103, a part of the bump 103 can always be in contact with the electrode 5 of the substrate 4.

On the other hand, in the bump 3 as shown in FIG. 11D, when the bump 3 is mounted on the electrode 5 of the circuit board 4 by being shifted by the dimension Z as shown in FIG. As shown in E), a part of the so-called pedestal 3g having the width dimension d is in contact with the electrode 5, but it is only in partial contact, resulting in an unstable contact state. In such an unstable bonding state, when the substrate 4 is subjected to a thermal shock test or reflow, the bonding in the unstable bonding state may be open, that is, a bonding failure. It was. On the other hand, in the sixth embodiment, even when the bump 103 having a substantially conical tip at the tip is displaced by the dimension Z with respect to the electrode 5 of the circuit board 4 as shown in FIG. Since 103 is a conical shape, when the deviation is up to half of the outer diameter of the bump 103, a part of the bump 103 can always come into contact with the electrode 5 of the substrate 4 and is subjected to a thermal shock test or reflow However, it is possible to prevent poor bonding.
(Seventh embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a seventh embodiment, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are shown in FIGS. This will be described with reference to FIG. In the seventh embodiment, in the first embodiment, the stress of the IC chip 1 and the circuit board 4 can be relieved when the thermosetting resin is cured after the IC chip 1 is bonded to the circuit board 4. It is a thing.

In the seventh embodiment, the electrode 2 of the IC chip 1 is interposed with a solid or semi-solid thermosetting resin sheet 6 or a thermosetting adhesive 6b in which an insulating filler 6m is mixed with an inorganic filler 6f. The bumps 3 formed by the wire bonding are aligned with the electrodes 5 of the circuit board 4 without leveling. For example, while heating the IC chip 1 from the back surface thereof with the tool 8 heated to a constant temperature of about 230 ° C., the pressure of P1 = 80 gf or more in the case where the IC chip 1 is a ceramic substrate per bump on the circuit board 4. The thermosetting resin sheet 6 or the thermosetting adhesive 6b interposed between the IC chip 1 and the circuit board 4 is cured by the heat while pressing with pressure to correct the warp of the board 4. To do. Next, after a certain time t ₁ , that is, if the total time is 20 seconds, for example, it changes depending on the reaction rate of the material, but after 1/4 or 1/2 of 5 seconds to 10 seconds, in other words, Before the reaction rate reaches 90%, the pressure is lowered to a pressure P2 lower than the pressure P1 to relieve the stress at the time of curing the thermosetting adhesive 6b, and the IC chip 1 and the circuit board 4 are joined to both electrodes. 2 and 5 are electrically connected. Preferably, a minimum of about 20 gf is necessary for the deformation of the bump, that is, a pressure necessary for the deformation and adaptation of the bump is obtained, and excess resin is used between the IC chip 1 and the substrate 4. Since the pressure P1 is 20 gf / bump or more because it is pushed out from the space, the pressure P2 is less than 20 gf / bump in order to remove the hardened strain that is unevenly distributed inside the resin before the deformation of the bump. Will improve. The reason is as follows in detail. That is, as shown in FIG. 12C, the stress distribution of the thermosetting resin in the thermosetting resin sheet 6 or the thermosetting adhesive 6b is large between the IC chip 1 and the substrate 4 side at the time of pressure bonding. .
In this state, when fatigue is repeatedly given in a reliability test or normal long-term use, the thermosetting resin in the thermosetting resin sheet 6 or the thermosetting adhesive 6b on the IC chip 1 or the substrate 4 side can withstand stress. May peel without being broken. In such a state, the adhesive force between the IC chip 1 and the circuit board 4 becomes insufficient, and the joint is opened. Therefore, as shown in FIG. 13, by using a two-stage pressure profile of a higher pressure P1 and a lower pressure P2, the pressure can be lowered to a pressure P2 lower than the pressure P1 when the thermosetting adhesive 6b is cured. Thus, as shown in FIG. 12D, the stress of the IC chip 1 and the circuit board 4 can be relieved (in other words, the degree of concentration of stress is reduced) by removing the curing strain unevenly distributed inside the resin at the pressure P2. Then, by raising the pressure to the pressure P1, the pressure required for the deformation and adaptation of the bumps can be obtained, and excess resin can be pushed out from between the IC chip 1 and the substrate 4 to improve the reliability. .

The “adhesive force between the IC chip 1 and the circuit board 4” means a force that holds the IC chip 1 and the board 4 together. This is because the adhesive force by the adhesive, the curing shrinkage force when the adhesive is cured, and the shrinkage force in the Z direction (for example, the shrinkage force when the adhesive heated to 180 ° C. shrinks to normal temperature) The IC 1 and the substrate 4 are bonded by these three forces.
(Eighth embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to the eighth embodiment, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are shown in FIGS. This will be described with reference to FIG. In the eighth embodiment, in each of the above embodiments, the average particle diameter of the inorganic filler 6f blended in the insulating resin 6m is 3 μm or more. However, the maximum average particle diameter of the inorganic filler 6f is set to a size that does not exceed the gap size after the IC chip 1 and the substrate 4 are joined.

  If the inorganic filler 6f is blended with the insulating resin 6m and fine particles having an average particle size of less than 3 μm are used as the inorganic filler 6f, the surface area of the particles itself increases as a whole, and the average particle size becomes smaller. Moisture absorption may occur around the inorganic filler 6f which is fine particles of less than 3 μm, which is not preferable in joining the IC chip 1 and the substrate 4.

Therefore, when blending the inorganic filler 6f having the same weight, the moisture absorption amount around the inorganic filler 6f can be reduced by using a large inorganic filler 6f having an average particle diameter of 3 μm or more, and the moisture resistance is improved. It becomes possible to make it. In general, an inorganic filler having a larger average particle size (in other words, average particle size) is less expensive and therefore preferable in terms of cost. In addition, as shown in FIG. 24A, in the method of using an ACF (Anisotropic Conductive Film) 598 for bonding the IC chip 1 and the substrate 4, the conductive particles 599 in the ACF 598 are bumps 3. However, since there is no conductive particle in the above-described embodiment of the present invention, there is no such need, and the bump 3 is formed by the substrate electrode 5 as shown in FIG. Since the pressure is applied while being squeezed, the inorganic filler 6f also escapes from between the bump 3 and the substrate electrode 4 together with the insulating resin layers 6 and 6b between the bump 3 and the substrate electrode 4 at the time of this pressure bonding. And an unnecessary inorganic filler 6f sandwiched between the bumps 3 so that the conductivity is hardly hindered. An inorganic filler 6f having an average particle diameter can be used.
(Ninth embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a ninth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method are provided. This will be described with reference to FIGS. 25 and 26 are schematic cross-sectional views of a joined state manufactured by a method and apparatus for mounting an electronic component such as an IC chip on the circuit board according to the ninth embodiment, and a resin sheet 6 used at that time, respectively. It is a partial expanded schematic cross section. In the ninth embodiment, in each of the above embodiments, the inorganic filler 6f to be blended in the insulating resin 6m of the insulating resin layers 6 and 6b is an inorganic filler 6f-1 having a plurality of different average particle diameters. 6f-2. As a specific example, an inorganic filler having an average particle diameter of 0.5 μm and an inorganic filler having an average particle diameter of 2 to 4 μm are used.

According to the ninth embodiment, by mixing the inorganic fillers 6f-1 and 6f-2 having a plurality of different average particle diameters with the insulating resin 6m, the amount of the inorganic filler 6f mixed with the insulating resin 6m is reduced. The amount of moisture absorption around the inorganic filler can be reduced, the moisture resistance can be improved, and film formation (solidification) is facilitated. That is, when considered in terms of% by weight, it is possible to increase the amount of inorganic filler per unit volume when mixed with inorganic fillers having different particle diameters, rather than one kind of inorganic filler. Thereby, the compounding quantity of the inorganic filler 6f to the resin sheet 6 or the adhesive 6b as the sealing sheet can be increased, the linear expansion coefficient of the resin sheet 6 or the adhesive 6b can be reduced, and the life can be extended. And reliability can be improved.
(10th Embodiment)
Next, in a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a tenth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method. In order to make the effect in the ninth embodiment more reliable, the average of one inorganic filler 6f-1 among the plurality of inorganic fillers 6f-1 and 6f-2 having a plurality of different average particle diameters is further provided. The particle diameter is different from the average particle diameter of the other inorganic filler 6f-2 by at least twice. As a specific example, an inorganic filler having an average particle diameter of 0.5 μm and an inorganic filler having an average particle diameter of 2 to 4 μm are used.

By doing in this way, the effect in the said 9th Embodiment can be improved further. That is, the average particle diameter of one inorganic filler 6f-1 is different from the average particle diameter of the other inorganic filler 6f-2 by more than twice, and the inorganic fillers 6f-1 and 6f-2 have a plurality of different average particle diameters. Is mixed with the insulating resin 6m, the amount of the inorganic filler 6f mixed with the insulating resin 6m can be increased more reliably, and it becomes easier to form a film (solidify), and the resin sheet. 6 or the amount of the inorganic filler 6f in the adhesive 6b can be increased, the linear expansion coefficient of the resin sheet 6 or the adhesive 6b can be further reduced, the life can be extended, and the reliability can be further improved. Can be improved.
(Eleventh embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to an eleventh embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method. In order to make the effect in the ninth embodiment more reliable, the inorganic filler 6f to be blended in the insulating resin 6m further includes at least two kinds of inorganic fillers 6f- having a plurality of different average particle diameters. 1 and 6f-2, and one inorganic filler 6f-1 of the at least two types of inorganic fillers has an average particle diameter exceeding 3 μm, and the other inorganic filler of the at least two types of inorganic fillers 6f-2 preferably has an average particle size of 3 μm or less. As a specific example, an inorganic filler having an average particle diameter of 0.5 μm and an inorganic filler having an average particle diameter of 2 to 4 μm are used.
(Twelfth embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a twelfth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method. In each of the above embodiments, the inorganic filler 6f blended in the insulating resin 6m is at least two types of inorganic fillers 6f-1 and 6f-2 having a plurality of different average particle diameters, Of the at least two types of inorganic fillers, one of the inorganic fillers 6f-1 having a large average particle diameter can be made of the same material as the insulating resin 6m, thereby exerting a stress relaxation action. As a specific example, an inorganic filler having an average particle diameter of 0.5 μm and an inorganic filler having an average particle diameter of 2 to 4 μm are used.

According to the twelfth embodiment, in addition to the function and effect of the ninth embodiment, one of the inorganic fillers 6f-1 having a large average particle diameter is made of the same material as the insulating resin 6m. When stress acts on the resin 6m, one of the inorganic fillers 6f-1 having a large average particle diameter is integrated with the insulating resin 6m, so that a stress relaxation action can be achieved.
(13th Embodiment)
Next, a mounting method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a thirteenth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method. In each of the above embodiments, the inorganic filler 6f blended in the insulating resin 6m is at least two types of inorganic fillers 6f-1 and 6f-2 having a plurality of different average particle diameters, One inorganic filler 6f-1 having a large average particle size among at least two kinds of inorganic fillers is softer than the epoxy resin that is the insulating resin 6m, and the one inorganic filler 6f-1 is compressed. It is also possible to exert a stress relaxation action.

According to the thirteenth embodiment, in addition to the function and effect of the ninth embodiment, one of the inorganic fillers 6f-1 having a large average particle diameter is made of the same material as the insulating resin 6m. When stress is applied to the resin 6m, the one inorganic filler 6f-1 having a large average particle diameter is softer than the epoxy resin that is the insulating resin 6m. As shown in 27, by compressing and dispersing a tensile force which is a reaction force against the compression around it, a stress relaxation action can be achieved.
(14th Embodiment)
Next, a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a fourteenth embodiment of the present invention, and an electronic component unit or module such as a semiconductor device in which the IC chip is mounted on the substrate by the mounting method. In each of the above embodiments, as shown in FIGS. 28 (A), (B), FIGS. 29 (A), (B), FIG. 30 and FIG. The portion 700 or the layer 6x in contact with the IC chip 1 or the substrate 4 has a smaller amount of the inorganic filler than the other portion 701 or the layer 6y, or may not contain the inorganic filler 6f. . In this case, as shown in FIGS. 28A and 28B, the amount of inorganic filler is gradually increased without clearly distinguishing between the portion 700 that contacts the IC chip 1 or the substrate 4 and the other portion 701. May be changed, or may be clearly distinguished as shown in FIGS. 29A and 29B and FIGS. That is, in FIGS. 29A, 29B, 30 and 31, the insulating resin layers 6 and 6b are located at a portion in contact with the IC chip 1 or the substrate 4 and the insulating resin 6m. The first resin layer 6x in which the inorganic filler 6f is blended with the same insulating resin and the first resin layer 6x is in contact with the first resin layer 6x, and the amount of the inorganic filler is less than the first resin layer 6x, or A multilayer structure can also be provided by including the second resin layer 6y made of the insulating resin not containing the inorganic filler 6f.

  In this way, the following effects can be achieved. That is, if the inorganic filler 6f is added to the entire insulating resin layer at the same weight percent (wt%), the inorganic filler 6f may increase in the vicinity of the IC chip side or the substrate side or both opposing surfaces. On the other hand, there is a decrease in the intermediate portion between the IC chip 1 and the substrate 4. As a result, since there are many inorganic fillers 6f in the vicinity of the opposing surface on the IC chip side or the substrate side or both, the adhesive force between the insulating resin layers 6 and 6b and the IC chip 1 or the substrate 4 or both is high. May decrease. According to the fourteenth embodiment, the portion 700 or the layer 6x in contact with either the IC chip 1 or the substrate 4 has a smaller amount of the inorganic filler than the other portion 701 or the layer 6y, or the above By not blending the inorganic filler 6f, it is possible to prevent the adhesive force from being lowered due to the large amount of the inorganic filler.

  Hereinafter, various modifications of the fourteenth embodiment will be described.

  First, as a first modification, as shown in FIGS. 28C, 29C, and 32A, the insulating resin layers 6 and 6b are formed of the IC chip 1 and the substrate 4 as described above. It is also possible that the portion 700 that contacts both of the above portions has a smaller amount of the inorganic filler than the other portion 701 or does not contain the inorganic filler 6f. Also in this case, as shown in FIG. 28C, the amount of the inorganic filler is gradually increased without clearly distinguishing between the portion 700 that contacts both the IC chip 1 and the substrate 4 and the other portion 701. It may be changed or may be clearly distinguished as shown in FIGS. 29C and 32A. That is, in FIGS. 29C and 32A, the insulating resin layers 6 and 6b are disposed on the opposite side of the first resin layer 6x to the second resin layer 6y, and the first resin layer 6x. The first resin layer 6x and the third resin are further provided with a third resin layer 6z made of the insulating resin having a smaller amount of the inorganic filler than the inorganic filler 6f or not containing the inorganic filler 6f. The layers 6z may be in contact with the IC chip 1 and the substrate 4, respectively.

  Furthermore, as another modified example, the portion 700 that is in contact with the IC chip 1 or the substrate 4 or both, respectively, has an amount of the inorganic filler of less than 20 wt%, or does not contain the inorganic filler 6f. The other portion 701 may have the inorganic filler content of 20 wt% or more. In this case, as shown in FIGS. 28A, 28 </ b> B, and 28 </ b> C, the portion 700 that contacts the IC chip 1 or the substrate 4 or both and the other portion 701 are not clearly distinguished, The amount of the inorganic filler may be gradually changed, and is clearly distinguished as shown in FIGS. 29 (A), (B), FIG. 29 (C), FIG. 30, FIG. 31, and FIG. You may do it. That is, the first resin layer 6x or the first resin layer 6x and the third resin layer 6z have an amount of the inorganic filler of less than 20 wt% or do not contain the inorganic filler 6f, while the second The resin layer 6y may have an inorganic filler content of 20 wt% or more.

  As a specific example, when the second resin layer 6y is a thermosetting epoxy resin as the insulating resin 6m, it is 50 wt% in the case of a ceramic substrate and 20 wt% in the case of a glass epoxy substrate. As an example, the thickness of the first resin layer 6x or the third resin layer 6z or both is 15 μm, and the thickness of the second resin layer 6y is 40 to 60 μm. Further, the thickness of the insulating resin layers 6 and 6b is larger than the gap size after bonding the IC chip 1 and the substrate 4, and the IC chip 1 and the substrate 4 are bonded when the IC chip 1 and the substrate 4 are bonded. To ensure complete joining between the two.

  As another modification, the blending amount of the inorganic filler and the modification shown in FIGS. 28C, 29C, and 32A may be reversed. That is, as shown in FIG. 28 (D), the insulating resin layers 6 and 6b are formed such that the intermediate portion 702 of the portion 703 that contacts both the IC chip 1 and the substrate 4 is the IC chip 1 and The amount of the inorganic filler may be less than the portion 703 that contacts both of the substrates 4, or the inorganic filler 6f may not be blended. Also in this case, the amount of the inorganic filler may be gradually changed without clearly distinguishing between the portion 703 that contacts the IC chip 1 or the substrate 4 or both, and the intermediate portion 702. FIG. As shown in FIG. 32D and FIG. 32B, it may be clearly distinguished. That is, as shown in FIGS. 29 (D) and 32 (B), the insulating resin layers 6 and 6b are located at the portions in contact with the IC chip 1 and the substrate 4, and the inorganic filler 6f is removed. 4th resin layer 6v comprised by the mix | blended insulating resin 6m, and it is located in the intermediate part of the said IC chip 1 and the said board | substrate 4, and the said inorganic filler amount is less than or contains the said 4th resin layer 6v It is also possible to provide a fifth resin layer 6w composed of an insulating resin 6m that is not provided.

  In this way, in the intermediate portion 702 or the fifth resin layer 6w between the IC chip 1 and the substrate 4, the portion 703 or the fourth resin layer that contacts the IC chip 1 and the substrate 4 respectively. Since the amount of the inorganic filler is less than or not contained in 6v, the elastic modulus is lowered and a stress relaxation effect can be achieved. Further, if a part 703 that contacts the IC chip 1 and the substrate 4 or an insulating resin of the fourth resin layer 6v is selected and used, a resin having high adhesion to the IC chip 1 and the substrate 4 is used. In the portion 703 that contacts the IC chip 1 or the fourth resin layer 6v in the vicinity of the IC chip 1, the amount or material of the inorganic filler 6f is selected so as to be as close as possible to the linear expansion coefficient of the IC chip 1. In the fourth resin layer 6v in the portion 703 in contact with the substrate 4 or in the vicinity of the substrate 4, the blending amount or material of the inorganic filler 6f can be selected so as to be as close as possible to the linear expansion coefficient of the substrate 4. . As a result, the linear expansion coefficient between the IC chip 1 and the fourth resin layer 6v in the vicinity of the portion 703 that contacts the IC chip 1 or in the vicinity of the IC chip 1 approaches, so that separation between the two is less likely to occur. At the same time, the linear expansion coefficient between the fourth resin layer 6v and the substrate 4 in the portion 703 in contact with the substrate 4 or in the vicinity of the substrate 4 approaches, so that the separation between the two hardly occurs.

  Further, as shown by solid lines in FIGS. 33A and 33B, the insulating resin layers 6 and 6b are changed from the portion P1 in contact with either the IC chip 1 or the substrate 4 to the other portion P2. The amount of the inorganic filler can be decreased gradually or stepwise.

  Further, as shown by solid lines in FIGS. 33C and 33D, the insulating resin layers 6 and 6b are separated from the portions P3 and P4 that are in contact with the IC chip 1 and the substrate 4 respectively, that is, ICs. The amount of the inorganic filler can be increased gradually or stepwise toward the intermediate portion P5 between the chip 1 and the substrate 4.

  In addition, as shown by a solid line in FIG. 33 (E), the insulating resin layers 6 and 6b are in contact with the IC chip 1 and the substrate 4, respectively (contact portions 703 in the modification of FIG. 28D). From the portion corresponding to the IC chip 1 and the substrate 4 (portion corresponding to the intermediate portion 702 in the modified example of FIG. 28D) gradually decreases in amount of the inorganic filler. It can also be done.

  Further, as indicated by a solid line in FIG. 33 (F), the insulating resin layers 6 and 6b are formed in the vicinity of the IC chip 1, the vicinity of the substrate 4, and then the vicinity of the IC chip 1. The amount of the inorganic filler can be reduced in the order of the intermediate portion between the substrate 4 and the vicinity of the substrate 4. In FIG. 33 (F), the inorganic filler amount is exemplified to change gradually in the above order, but the present invention is not limited to this, and it may be changed stepwise.

  33E and 33F, the intermediate portion between the IC chip 1 and the substrate 4 is more inorganic than the portion in contact with the IC chip 1 and the substrate 4 respectively. Since the amount of filler is small or not contained, the elastic modulus is lowered and a stress relaxation effect can be achieved. In addition, if a part having high adhesion to the IC chip 1 and the substrate 4 is selected and used as the insulating resin for the part that contacts the IC chip 1 and the substrate 4 respectively, While the blending amount or material of the inorganic filler 6f is selected so as to be as close as possible to the linear expansion coefficient of the IC chip 1, the portion of the inorganic filler 6f that is in contact with the substrate 4 is as close as possible to the linear expansion coefficient of the substrate 4. The amount or material can be selected. When the blending amount of the inorganic filler 6f is determined from this viewpoint, normally, as shown by a solid line in FIG. 33 (F), the vicinity of the IC chip 1, then the vicinity of the substrate 4, and then the IC chip The amount of the inorganic filler becomes smaller in the order of the intermediate portion between the vicinity portion of 1 and the vicinity portion of the substrate 4. By adopting such a configuration, the linear expansion coefficient between the IC chip 1 and the portion that contacts the IC chip 1 approaches, so that separation between the two is less likely to occur, and the portion that contacts the substrate 4 and the substrate Since the linear expansion coefficient with 4 approaches, peeling between them becomes difficult to occur.

  In any case of FIGS. 33A to 33F, the amount of the inorganic filler is preferably in the range of 5 to 90 wt% for practical use. If it is less than 5 wt%, there is no point in mixing the inorganic filler 6f. On the other hand, if it exceeds 90 wt%, the adhesive strength is extremely lowered and it is difficult to form a sheet, which is not preferable.

  In the case where the IC chip 1 is thermocompression bonded to the substrate 4 using a multilayered film composed of a plurality of resin layers 6x, 6y or 6x, 6y, 6z as described above as an insulating resin layer, bonding is performed. Since the insulating resin 6m is softened and melted by the heat of time and the resin layers are mixed, finally, there is no clear boundary between the resin layers, and an inclined inorganic filler distribution is obtained as shown in FIG.

  Furthermore, in the fourteenth embodiment or each modification, in the insulating resin layer having a portion or layer containing the inorganic filler 6f or the insulating resin layer having an inclined inorganic filler distribution, depending on the portion or the resin layer. It is also possible to use different insulating resins. For example, an insulating resin that improves adhesion to a film material used on the surface of the IC chip is used in the portion or resin layer that contacts the IC chip 1, while the substrate surface is used in the portion or resin layer that contacts the substrate 4. It is also possible to use an insulating resin that improves adhesion to the material.

  According to the fourteenth embodiment and the various modifications thereof, the inorganic filler 6f does not exist or is small in the bonding interface between the IC chip 1 or the substrate 4 and the insulating resin layers 6 and 6b. The inherent adhesiveness of the conductive resin is exhibited, the insulating resin having high adhesiveness at the bonding interface is increased, and the adhesion strength between the IC chip 1 or the substrate 4 and the insulating resin 6m can be improved. Adhesiveness with the IC chip 1 or the substrate 4 is improved. Thereby, the life in various reliability tests is improved, and the peel strength against bending is improved.

  If the inorganic filler 6f, which does not contribute to the bonding itself but has the effect of reducing the linear expansion coefficient, is uniformly dispersed in the insulating resin 6m, the inorganic filler 6f comes into contact with the substrate 4 or the IC chip surface and adheres. As a result, the amount of the adhesive that contributes to the decrease is reduced, resulting in a decrease in adhesiveness. As a result, if peeling occurs between the IC chip 1 or the substrate 4 and the adhesive, moisture enters from there and causes corrosion of the electrodes of the IC chip 1. Moreover, when peeling progresses from the peeled portion, the bonding itself between the IC chip 1 and the substrate 4 becomes defective, resulting in poor electrical connection.

  On the other hand, according to the fourteenth embodiment and the various modifications thereof, as described above, it is possible to improve the adhesive force while having the effect of reducing the linear expansion coefficient by the inorganic filler 6f. . Thereby, the adhesion strength between the IC chip 1 and the substrate 4 is improved, and the reliability is improved.

  Further, when the portion 700 or the resin layer 6x with a small amount of the inorganic filler 6f is arranged on the IC chip side, or when the inorganic filler distribution is reduced on the IC chip side, the portion 700 or the resin layer 6x is formed on the surface of the IC chip. It is possible to improve the adhesion to a passivation film made of silicon nitride or silicon oxide. It is also possible to appropriately select and use an insulating resin that improves adhesion to the film material used on the surface of the IC chip. Moreover, the stress concentration in the sealing sheet material which is an example of an insulating resin layer is relieved by reducing the elastic modulus in the vicinity of the IC chip. When the material used for the substrate 4 is hard like ceramic (high modulus of elasticity), such a structure matches the modulus of elasticity and the linear expansion coefficient with the sealing sheet material in the vicinity of the substrate. In addition, it is preferable.

  On the other hand, when the portion 700 having a small amount of the inorganic filler 6f or the resin layer 6x is arranged on the substrate side, or when the inorganic filler distribution is reduced on the substrate side, such as a resin substrate or a flexible substrate (FPC). In the case where bending is applied to the substrate 4, when bending stress is applied when the substrate 4 is incorporated into the housing of the electronic device, the adhesion strength between the substrate 4 and the sealing sheet which is an example of the insulating resin layer is increased. It can be used for the purpose of improving. When the surface layer on the IC chip side is made of a protective film formed of a polyimide film, in general, when the insulating resin adheres well and there is no problem, the elastic modulus and linear expansion from the IC chip 1 to the substrate 4 By changing the coefficient continuously or stepwise, the sealing sheet can be made hard on the IC chip side and soft on the substrate side. Thereby, since generation | occurrence | production of the stress inside a sealing sheet becomes small, reliability improves.

Furthermore, when the portion 700 or the resin layer 6x, 6z with a small amount of the inorganic filler 6f is disposed on both sides of the IC chip side and the substrate side, or when the inorganic filler distribution is reduced on both sides of the IC chip side and the substrate side, The above-mentioned two cases of the IC chip side and the substrate side are made compatible, and the adhesion on both the IC chip side and the substrate side can be improved, and the linear expansion coefficient is lowered to reduce the IC chip 1 and the substrate. 4 can be connected with high reliability. In addition, an insulating resin having better adhesion and better resin coating can be selected and used according to the material of the IC chip side surface and the substrate material. In addition, since the inclination with a large amount of these inorganic fillers 6f can be freely changed, matching with the substrate material is possible by making the portion or layer with a small amount of the inorganic fillers 6f extremely thin.
(Fifteenth embodiment)
Next, in the fifteenth embodiment of the present invention, the IC chip is mounted by a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to the eighth to fourteenth embodiments and modifications thereof, and the mounting method. A manufacturing process of an insulating resin layer used by an electronic component unit or module mounted on the substrate, for example, a semiconductor device will be described with reference to FIGS.

  First, when forming an insulating resin layer directly on the circuit board 4, a 1st resin sheet is affixed on the circuit board 4, and a 2nd resin sheet is affixed on it. At this time, when the first resin sheet contains a large amount of the inorganic filler 6f, the result is as shown in FIG. 28 (A) or FIG. 30, and in the opposite case, the result is as shown in FIG. 28 (B) or FIG. That is, in the former case, the first resin sheet is a portion 701 with a large amount of the inorganic filler 6f or a resin sheet corresponding to the second resin layer 6y, and in the latter case, the portion 700 with a small amount of the inorganic filler 6f or A resin sheet corresponding to the first resin layer 6x is obtained.

  Further, when a third resin sheet is further formed on the second resin sheet, and the first resin sheet and the third resin sheet correspond to the portion 700 or the first resin layer 6x with a small amount of the inorganic filler 6f, As shown in FIG. 28C or FIG.

  Further, as shown in FIGS. 34 and 35, the first resin sheet 673 and the second resin sheet 674 are placed in this order on a base film 672 called a separator in advance (in this case in FIGS. 34 and 35). Only the third resin sheet may be formed by attaching the third resin sheet. In this case, as shown in FIGS. 34 and 35, a plurality of resin sheets 673 and 674 are attached while being heated as necessary with a pair of upper and lower heatable rollers 670 and 270. Then, if the formed resin sheet body 671 is cut into predetermined dimensions, the above-mentioned as shown in any of FIGS. 28 (A) to (C), FIGS. 29 (A) to (C), and FIGS. The insulating resin sheet 6 is obtained.

  As another modification, when producing an insulating resin sheet body in which the insulating resin sheet 6 is continuous, an epoxy and an inorganic filler dissolved in a solvent are applied onto a base film called a separator by a doctor blade method or the like. To do. This solvent is dried to produce an insulating resin sheet body.

  At this time, once the concentration of the inorganic filler 6f is low, or a liquid insulating resin not containing the inorganic filler 6f is applied as a first layer on the base film. Dry one layer. When the inorganic filler 6f is not dried, the inorganic filler 6f of the second layer is slightly mixed with the first layer, and the inorganic filler distribution is inclined as shown in FIG.

  A liquid insulating resin in which more inorganic filler 6f is mixed than the first layer is applied on the first layer formed by coating to form a second layer. By drying the second layer, an insulating resin sheet having a two-layer structure in which the first layer and the second layer are formed on the base film can be formed. If the insulating resin sheet body is cut into predetermined dimensions, the insulating resin sheet 6 as shown in FIGS. 28 (A), 29 (A), and 30 is obtained.

  In addition, when arrange | positioning the layer with few inorganic fillers 6f on the board | substrate side, after forming a 2nd layer on a base film and a 2nd layer on a base film, a 1st layer is formed on a 2nd layer. An insulating resin sheet having a two-layer structure can be formed. If the insulating resin sheet body is cut into predetermined dimensions, the insulating resin sheet 6 as shown in FIGS. 28 (B), 29 (B), and 31 is obtained.

  In addition, once the concentration of the inorganic filler 6f is low or the insulating resin 6m not containing the inorganic filler 6f is applied and dried (may be omitted) as a first layer, the inorganic layer is inorganic on the first layer. An insulating resin mixed with more filler 3f than the first layer is applied, applied and dried as the second layer (may be omitted), and the amount of the inorganic filler is smaller or absent than the second layer. Apply a third layer. By drying this, an insulating resin sheet having a three-layer structure in which the first layer, the second layer, and the third layer are formed on the base film can be formed. If the insulating resin sheet body is cut into predetermined dimensions, the insulating resin sheet 6 as shown in FIGS. 28 (C), 29 (C), and 32 (A) is obtained.

  According to the method of directly forming the insulating resin layer on the circuit board 4, the electronic component unit is manufactured on the side of manufacturing the electronic component unit by selecting a resin of the material most suitable for the electronic component in the electronic component unit. On the other hand, it is possible to select the resin of the optimum material for the substrate and arrange it on the substrate side while arranging on the component side, so that the degree of freedom in selecting the resin can be increased.

  On the other hand, in the method of manufacturing the insulating resin sheet body, there is no degree of freedom of selection as described above, but a large number of the insulating resin sheets 6 can be manufactured at once, and the manufacturing efficiency is good. At the same time, it becomes inexpensive, and a single attaching device is sufficient.

  As described above, according to the above embodiments of the present invention, it is possible to eliminate many of the processes conventionally required for bonding an electronic component such as an IC chip and a circuit board, thereby greatly improving productivity. it can. That is, for example, in the case of bonding by stud bump bonding or solder bump described as a conventional example, it is necessary to inject a sealing material after flip-chip bonding and put it in a batch furnace to be cured. The injection of the sealing material takes several minutes per one piece, and it takes 2 to 5 hours to cure the sealing material. In the stud bump bonding mounting, as a previous process, a process of transferring the Ag paste to the bump, mounting it on the substrate, and then curing the Ag paste is required. This process takes 2 hours. On the other hand, in the method of the above embodiment, the sealing step can be eliminated, and the productivity can be greatly improved. Furthermore, in the above embodiment, by using a sealing sheet of a solid or semi-solid insulating resin, for example, an epoxy resin having a large molecular weight can be used, and can be joined in a short time of about 10 to 20 seconds. Thus, the joining time can be shortened, and the productivity can be further improved. Further, when the thermosetting resin sheet 6 or the thermosetting adhesive 6b without conductive particles is used as the bonding material, conductive fine pieces are added to the insulating resin as compared with the method shown in the conventional example 2. Since it is not necessary, an inexpensive IC chip mounting method and apparatus can be provided.

  Furthermore, the following effects can also be achieved.

(1) Bump formation In the method of forming bumps by plating (conventional example 3), it is necessary to carry out a dedicated bump formation process by a semiconductor manufacturer, and bumps can be formed only by a limited manufacturer. However, according to the embodiment of the present invention, a general-purpose wire bonding IC chip can be used by the wire bonding apparatus, and the acquisition of the IC chip is facilitated. In other words, the reason why a general-purpose wire bonding IC chip can be used is that, when wire bonding is used, bumps are formed on a normal IC pad on which an Al pad is formed using a wire bonding apparatus or a bump bonding apparatus. It is possible. On the other hand, in order to form plated bumps by a method of forming bumps by plating (conventional example 3), a barrier metal such as Ti, Cu, Cr or the like is formed on an Al pad, and then a resist is applied by spin coating. Expose only the bump forming part. It is formed by energizing this and plating the hole with Au or the like. Accordingly, in order to form the plating bump, a large-scale plating apparatus and a waste liquid processing apparatus for hazardous materials such as cyanide are required.

  Further, compared to the method of the conventional example 1, bump leveling for stabilizing the transfer amount of the adhesive in the unstable transfer process such as transfer of the conductive adhesive becomes unnecessary, and the leveling device for such leveling process Is no longer necessary. This is because the bumps are crushed on the electrodes of the substrate while pressing the bumps, so that it is not necessary to level the bumps in advance.

  Further, in the embodiment described above, even when the bump 103 is mounted on the electrode 5 of the circuit board 4 in a shifted manner, highly reliable bonding can be achieved. That is, when the bump 3 is formed on the IC chip 1, a gold ball 96a is formed by electric sparking of a gold wire in the same manner as wire bonding. Next, a ball 96a having a diameter Φd-Bump indicated by 95a is formed, and a Chamfer diameter φD indicated by 93a of the capillary 193 having a Chamfer angle θc of 100 ° or less is set to 1 of the diameter d-Bump of the gold ball 96a. The bumps 103 are formed on the electrodes 2 of the IC chip 1 by ultrasonic waves and thermocompression bonding with the capillaries 193 having a tip shape that does not provide a flat portion at the portion that contacts the gold ball 96a of the capillaries 193. By using the capillary 193 having the above-described shape, the bump 103 having a substantially conical tip as shown in FIG. 10B can be formed on the electrode 2 of the IC chip 1. Even when the bump 103 formed by the above method is mounted on the electrode 5 of the circuit board 4 so as to be displaced by the dimension Z as shown in FIG. 11C, the bump 103 has a substantially conical tip. When the deviation is up to half of the diameter, a part of the bump 103 can always be in contact with the electrode 5 of the substrate 4. In FIG. 11D of the conventional bump 3, a part of the width dimension d of the so-called pedestal 3 g of the bump 3 is in contact, but it is only in partial contact, resulting in unstable bonding. When this is subjected to a thermal shock test or reflow, the joint portion becomes open. In the present invention, such unstable bonding is eliminated, and a bonding with high production yield and reliability can be provided.

(2) Bonding of IC chip and circuit board According to the method of Conventional Example 2, the connection resistance depends on the number of conductive particles existing between the bump and the electrode of the circuit board. In the embodiment, the bump 3 is not leveled in the leveling process as an independent process, and is pressed against the electrode 5 of the circuit board 4 with a load stronger than the conventional examples 1 and 2 (for example, a pressing force of 20 gf or more per bump 3). Since the bump 3 and the electrode 5 can be directly joined, the connection resistance value does not depend on the number of intervening particles, and the connection resistance value can be obtained stably.

  In the conventional leveling process, the bump height at the time of bonding to the substrate electrode is made constant. In the above embodiments of the present invention, the crushing of the bump 3 is performed simultaneously with the bonding to the electrode 2 or 5. In addition to eliminating the need for an independent leveling process, it is possible to perform bonding while deforming and correcting the warping and undulation of the circuit board 4 at the time of bonding, or to adhere to the bumps 3 and 103. Since the conductive paste is cured and the conductive paste is deformed at the time of bonding, the leveling of the bumps 3 and 103 is not required at all, and the warping and undulation of the circuit board 4 is deformed and bonded at the time of bonding. Strong against warping and swell.

  By the way, the conventional example 1 has a 10 μm / IC chip (meaning that 10 μm thickness warpage dimension accuracy is required per IC chip), the conventional example 2 has a 2 μm / IC, and the conventional example 3 has a 1 μm / IC chip. It is necessary to make the substrate 4 and the bumps 3 and 103 with high accuracy such as (bump height variation ± 1 μm or less) uniform, and in practice, a glass substrate typified by LCD is used. On the other hand, according to the above-described embodiment of the present invention, since the warp and undulation of the circuit board 4 are deformed and bonded at the time of bonding, the substrate is warped and undulated and has poor flatness, for example, a resin substrate. In addition, a flexible substrate, a multilayer ceramic substrate, or the like can be used, and a more inexpensive and versatile IC chip bonding method can be provided.

  Further, if the volume of the thermosetting resin 6m between the IC chip 1 and the circuit board 4 is made larger than the volume of the space between the IC chip 1 and the circuit board 4, it will flow out of this space. Thus, a sealing effect can be achieved. Therefore, it is not necessary to perform sealing resin (underfill coating) under the IC chip after bonding the IC chip and the circuit board with the conductive adhesive required in Conventional Example 1, and the process can be shortened.

  In addition, the elastic modulus and thermal expansion coefficient of the thermosetting resin can be controlled to be optimal for the substrate 4 by blending about 5 to 90 wt% of the inorganic filler 6f with the thermosetting resin 6m. In addition to this, when this is used in a normal plating bump, an inorganic filler enters between the bump and the circuit board, and the bonding reliability is lowered. However, if stud bumps (formation method applying wire bonding) are used as in the above-described embodiment of the present invention, the sharp bumps 3, 103 that have entered the thermosetting resin 6m at the beginning of bonding. By pushing the inorganic filler 6f and thus the thermosetting resin 6m outward of the bumps 3 and 103, the inorganic filler 6f and the thermosetting resin 6m are transformed in the process of the bumps 3 and 103 being deformed. It is possible to extrude from between the bumps 3 and 103 and the electrodes 5 and 2 so that unnecessary inclusions do not exist, and the reliability can be further improved.

  As described above, according to the present invention, it is possible to provide a method and an apparatus for joining an electronic component such as an IC chip and a circuit board, which are more productive than the conventional joining method and are inexpensive.

(A), (B), (C), (D), (E), (F), and (G) are each a method of mounting an electronic component, for example, an IC chip, on the circuit board according to the first embodiment of the present invention. It is explanatory drawing which shows. (A) and (B) are the methods of mounting an electronic component such as an IC chip on the circuit board according to the first embodiment, respectively, and the inorganic filler in the thermosetting resin enters the thermosetting resin at the beginning of bonding. FIG. 5 is an explanatory view showing a state where the bump is sharply pushed out toward the outer side of the bump, and (C) is an explanatory view showing a state where an inorganic filler does not enter between the bump and the substrate electrode. (A), (B), (C), (D), (E), (F), (G) are bumps using a wire bonder of an IC chip in the mounting method according to the first embodiment of the present invention. It is explanatory drawing which shows a formation process. (A), (B), (C) is explanatory drawing which shows the joining process of a circuit board and an IC chip, respectively, in the mounting method concerning 1st Embodiment of this invention. (A), (B), (C) is explanatory drawing which shows the joining process of a circuit board and an IC chip in the mounting method which is 1st Embodiment of this invention, respectively. (A), (B), and (C) explain that a thermosetting adhesive is disposed on a circuit board in place of the thermosetting resin sheet in the mounting method according to the third embodiment of the present invention. It is explanatory drawing for doing. (A), (B), (C), (D), (E), and (F) are thermosetting resins as a modification of FIG. 6 in the mounting method of the third embodiment of the present invention. It is explanatory drawing for demonstrating replacing with a sheet | seat and arrange | positioning a thermosetting adhesive agent on a circuit board. (A), (B), (C) is explanatory drawing which shows the joining process of a circuit board and an IC chip in the mounting method concerning 5th Embodiment of this invention, respectively. (A), (B), (C) is explanatory drawing which shows the joining process of a circuit board and an IC chip in the mounting method which is 5th Embodiment of this invention, respectively. (A), (B), (C), (D) is explanatory drawing which shows the joining process of a circuit board and an IC chip in the mounting method which is 6th Embodiment of this invention, respectively. (A), (B), (C), (D), and (E) are explanatory views showing a bonding step of a circuit board and an IC chip in the mounting method according to the sixth embodiment of the present invention. (A), (B), (C), (D) is explanatory drawing which shows the joining process of a circuit board and an IC chip, respectively, in the mounting method which is 7th Embodiment of this invention. These are explanatory drawings which show the joining process of a circuit board and IC chip in the mounting method which is 7th Embodiment of this invention. (A), (B) is explanatory drawing which shows the modification of 1st Embodiment which formed the thermosetting resin sheet in the IC chip 1 side, respectively, and the 1st which formed the thermosetting adhesive in the IC chip 1 side It is explanatory drawing which shows the modification of 1 embodiment. It is sectional drawing which shows the joining method of the IC chip with the conventional circuit board. (A), (B) is explanatory drawing which shows the joining method of IC chip with the conventional circuit board, respectively. In the said 1st Embodiment, it is a figure of the graph of the relationship between resistance value and a load in the case of a bump of an outer diameter of 80 micrometers. In the said 1st Embodiment, it is a figure of the graph which showed the area | region with high reliability based on the relationship between the bump | vamp of each outer diameter of 80 micrometers and 40 micrometers, and the minimum load. In the said 3rd Embodiment, it is a figure of the graph of the heating temperature and reaction rate of a resin sheet. It is a perspective view of the electronic component mounting apparatus used by the said 1st Embodiment. (A), (B), (C), and (D) are perspective views showing the position recognition operation on the component side in the electronic component mounting apparatus of FIG. It is a perspective view showing position recognition operation, and a figure of a position recognition image of a substrate. It is the schematic of the ultrasonic application apparatus used in the said 4th Embodiment. It is the schematic of the sticking apparatus used by the said 5th Embodiment. (A), (B) is an expanded sectional view of the vicinity of a bump for comparison explanation of the ACF method and the method of the above embodiment, respectively. It is a schematic cross section of the joining state joined by the mounting method and apparatus of the electronic component, for example, IC chip, to the circuit board concerning 9th Embodiment of this invention. It is a partial expanded schematic cross section of the resin sheet used with the mounting method and apparatus of an electronic component, for example, IC chip, on the circuit board according to the ninth embodiment. It is a schematic cross section of an insulating resin and an inorganic filler in a joined state joined by a mounting method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a thirteenth embodiment of the present invention. (A), (B), (C), (D) are various types of insulating resin layers used by a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to the fourteenth embodiment of the present invention. It is a schematic cross section of the electronic component unit which shows the example. (A), (B), (C), and (D) are insulating resins used by a method and apparatus for mounting an electronic component such as an IC chip on a circuit board according to a modification of the fourteenth embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of various examples of layers. 29A is a schematic cross-section of a joined state joined using an insulating resin layer used by a method and apparatus for mounting an electronic component such as an IC chip on the circuit board according to the fourteenth embodiment shown in FIG. FIG. A schematic cross-section of a joined state joined using an insulating resin layer used by a method and apparatus for mounting an electronic component such as an IC chip on the circuit board according to the fourteenth embodiment shown in FIG. FIG. (A) and (B) are insulating resins used by a method and apparatus for mounting an electronic component such as an IC chip on the circuit board according to the fourteenth embodiment shown in FIGS. 29 (C) and (D), respectively. It is a schematic cross section of the joining state joined using the layer. (A), (B), (C), (D), (E), and (F) are respectively used by the mounting method and apparatus of an electronic component such as an IC chip on the circuit board according to the fourteenth embodiment. It is a figure which shows the graph of the various relationship between the quantity of the inorganic filler of an insulating resin layer, and the position of the thickness direction of an insulating resin layer. It is explanatory drawing of the manufacturing process of the insulating resin layer used with the mounting method and apparatus of an electronic component, for example, IC chip, on the circuit board concerning 15th Embodiment of this invention. It is the elements on larger scale of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... IC chip, 2,5 ... Electrode, 3,103 ... Bump, 3g ... Base, 4 ... Circuit board, 6 ... Thermosetting resin sheet, 6a ... Separator, 6b ... Thermosetting adhesive, 6f ... Inorganic filler , 6f-1 ... inorganic filler with a large average particle diameter, 6f-2 ... inorganic filler with a small average particle diameter, 6m ... an insulating resin layer (for example, thermosetting resin), 6s ... a thermoset resin, 6v 4th resin layer, 6w ... 5th resin layer, 6x ... 1st resin layer, 6y ... 2nd resin layer, 6z ... 3rd resin layer, 7 ... Pasting tool, 8 ... Joining tool, 8a ... Heater, 9, 109, 201 ... stage, 93,193 ... capillary, 193a ... tip portion, 93b ... flat portion, 95 ... wire, 96,96a ... ball, 98 ... curved portion, 99 ... loop, 200 ... holding member, 670 ... roller 671: Insulating resin sheath Body, 672 ... base film, 673 ... first resin sheet, 674 ... second resin sheet, 700 ... part in contact with IC chip and / or substrate (the part where the amount of inorganic filler is small or the above inorganic filler is not blended) 701: Other portion (a portion with a large amount of inorganic filler), 702 ... A portion with a small amount of inorganic filler, or a portion not containing the above inorganic filler, 703 ... A portion with a large amount of inorganic filler.

Claims (1)

Gold bumps (3, 103) are formed on the electrodes (2) of the electronic component (1),
Without leveling the formed bumps, the above-described electronic component is in contact with a solid or semi-solid insulating resin layer (6, 6b) in which an inorganic filler (6f) is blended with an insulating resin (6m). The electrode and the electrode (5) of the circuit board (4) are aligned and the electronic component is mounted on the board,
Thereafter, a tool (8) applies a load of 20 gf or less per bump from the upper surface side of the electronic component to adjust the tip so as to prevent the neck portion of the gold bump from collapsing and to apply ultrasonic waves to the gold component. Metal bonding the bump and the electrode of the substrate,
Next, while heating from the upper surface side of the electronic component, heating from the substrate side, or heating from both the electronic component side and the substrate side, the electronic component is placed on the circuit board. Pressing with a pressure of 20 gf or more per bump, correcting the warpage of the substrate and crushing the bump, curing the insulating resin interposed between the electronic component and the circuit board, A mounting method of an electronic component, wherein the circuit board is joined to electrically connect the electrode of the electronic component and the electrode of the circuit board.

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