JP3454977B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a flip chip structure in which a resin is sealed around a gap between a semiconductor chip and a circuit wiring board on which the semiconductor chip is mounted and around the semiconductor chip, and a method for manufacturing the same in order to improve the connection reliability of the bump electrode portion.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been highly integrated, and packaging technology is required to have high density. Wire bonding technology and TAB are used for high-density mounting technology of semiconductor devices.
As a typical example, a flip-chip mounting technique has been widely used in recent years as a technique for high-density mounting semiconductor devices such as computer equipment as the highest-density mounting technique. This flip chip mounting technology is disclosed in US Pat. No. 3,401,126 and US Pat. No. 34290.
It has become a widely known technique since the publication of Japanese Patent No. 40.

FIG. 16 is a schematic diagram showing the basic structure of a conventional flip chip mounting.

In the flip-chip mounting, as shown in FIG. 16, bump electrodes 3 having a protrusion shape are formed on the bonding pads 24 of the semiconductor chip 1, and the bonding pads 24 of the semiconductor chip 1 are interposed via the bump electrodes 3. And the electrode pad 21 of the circuit wiring board 2 are electrically and mechanically interconnected.

In the flip-chip mounting technique, the coefficient of thermal expansion of the semiconductor chip and the coefficient of thermal expansion of the circuit wiring board are generally different from each other, so that heat generated during the operation of the semiconductor chip is transferred to the circuit wiring board through the bump electrodes. Displacement due to the difference in thermal expansion coefficient occurs in the semiconductor chip and the circuit wiring board. The generated displacement causes stress strain in the bump electrode connecting the semiconductor chip and the circuit wiring board. The stress strain due to the displacement due to the difference in the thermal expansion coefficient also occurs when the semiconductor device that has generated heat is cooled.

Further, even when a temperature difference occurs in the external temperature atmosphere, the same stress strain as described above occurs in the bump electrode portion. The stress strain of the bump electrode portion destroys the bump electrode mounted on the flip chip, which shortens the reliability life.

Reliability life is measured by IBM J. Res. De
velop. , 13; 251 (1969), Nf = Cf ^1/3 γ _max ^-2 · exp (1428 /
Tmax) cycle life formula (C; constant,
It is known that the reliability life is improved by reducing the maximum shear strain γmax generated in the bump portion from the frequency (f: frequency, Tmax: maximum temperature). Further, the maximum shear strain generated in the bump electrode shown in the reliability life formula is represented by the following formula.

Γ _max = {1 / (Dmin / 2) ^{2 / β} }
(V / πh ^{1 + β} ) ^{1 / β} · d · ΔT · Δα (Dmin; minimum bump diameter, β; material constant, V; solder volume, h; solder height, Δα; thermal expansion coefficient difference, ΔT;
Temperature difference, d; distance from the center of the chip to the center of the bump) From the above, in order to improve the reliability of the flip chip mounting, (1) the distance from the center point of the semiconductor chip to the center point of the bump electrode is set. (2) reduce the difference between the coefficient of thermal expansion of the semiconductor chip and the coefficient of thermal expansion of the circuit wiring board; (3) improve heat dissipation so that the temperature difference does not increase; and (4) bump electrode structure. Means have been used such as making the material a strong structure against stress strain.

Further, when the thermal expansion coefficients are remarkably different from each other, as in the case of flip-chip mounting on an organic resin substrate which has been frequently performed in recent years, resin is injected into a gap between a semiconductor chip and a circuit wiring board. The flip-chip mounting structure has been strengthened to improve reliability.

In order to improve the reliability of the flip-chip mounting structure, it has been practiced to coat the semiconductor chip with a resin. In particular, for the purpose of improving the moisture resistance, the semiconductor chip is sealed with silicon gen or the like. Was being done.
Even in this resin encapsulation for the purpose of moisture resistance, the flip chip structure has a structure in which the stress applied to the bump electrode portion is reduced and the cycle life is not shortened.

FIG. 17 is a schematic diagram showing an example of a conventional flip chip mounting structure. JP-A-57-20814
9, JP-A-58-18348, JP-A-58-103.
Japanese Patent Publication No. 143 discloses a mounting method of a structure in which a gap between the semiconductor chip 1 and the circuit wiring board 2 is filled with a resin 6 as a conventional technique as shown in FIG. However, since the physical properties of the resin 6 used for sealing have not been specified, the destruction of the connection bump 3 portion may be accelerated.

FIG. 18 is a diagram showing another example of a conventional flip chip mounting structure. As a structure for improving the reliability of the bump connecting portion 3 of the flip chip mounting structure as shown in FIG. 17, as shown in FIG.
46, JP-A-58-134449, JP-A-61.
No. 177738 discloses a structure in which the resin 6 is not filled in the gap between the semiconductor chip 1 and the circuit wiring board 2 and the resin is provided around the gap.

However, in the structure as shown in FIG. 18, although the thermal cycle reliability of the bump connecting portion is improved, moisture is accumulated and retained in the gap portion and the bump electrode portion is corroded, so that the consumer equipment etc. There is a problem in that it is not sufficient when an electronic circuit device that does not perform hermetic sealing or when an organic polymer material having an extremely large difference in thermal expansion coefficient is used as a circuit wiring board.

In view of this, Japanese Patent Laid-Open No. 58-10841 discloses the physical properties of the resin to be sealed, and discloses a structure in which a soft resin such as silicone is filled in the gap between the semiconductor chip and the circuit wiring board. Since the thermal expansion coefficient of the soft resin is generally very large, there has been a problem that the thermal cycle life of the bump connection portion cannot be improved as in the conventional case.

Japanese Examined Patent Publication No. 4-51057 was devised to solve these problems, and is a hard organic material in which the shear elastic modulus of the resin to be sealed is larger than the shear elastic modulus of the solder at the bump connecting portion. Polymer material (up to 300 kg /
mm ² ), while making the coefficient of thermal expansion equal to the coefficient of thermal expansion of the solder and making it smaller than the coefficient of thermal expansion of the solder (20 × 10 ^{−6 to} 28 × 10 ⁻⁶ / ° C.),
This is a proposal to reduce the amount of shear deformation of the solder, prevent breakage due to shear fatigue at the bump connection portion, and improve the reliability life.

Furthermore, in Japanese Patent Laid-Open No. 63-316447, the shear modulus of the resin to be sealed is (10 to 900 kg / mm) when a low melting point metal is used as a bump bonding metal.
^{In addition to 2} ), we also propose to make the coefficient of thermal expansion smaller than that of solder.

Further, in Japanese Patent Laid-Open No. 4-219944, flip-chip mounting on an organic material substrate is possible by using a curable resin composed of a thermosetting binder and a filler as a sealing material. Is disclosed. At this time, in the resin used, the binder has a viscosity of 1000 centipoise or less at room temperature, and the maximum particle size of the filler is 50.
μm. The weight of the binder is 60% to 25% by weight based on the total weight of the binder and the filler.
It is disclosed that the reliability is improved when the content is 0% by weight to 75% by weight.

On the other hand, a method of resin-sealing a gap between a semiconductor chip and a circuit wiring board is disclosed in JP-A-4-7447, JP-A-2-234447 and JP-A-62-123333.
A typical method is, as in Japanese Patent Laid-Open No. 1-1990, in which resin is applied in advance on the surface of the semiconductor chip or on the place where the semiconductor chip is mounted on the circuit wiring board, and then the semiconductor chip is bonded to the circuit wiring board. However, in such a method, the resin may be interposed between the bump electrode of the semiconductor chip and the connection electrode of the circuit wiring board to cause connection failure.

Therefore, as disclosed in JP-A-60-147140 and JP-A-3-18435, after the semiconductor chip is flip-chip mounted on the circuit wiring board, the semiconductor chip and the circuit wiring board are utilized by utilizing the capillary phenomenon. There is also a method of sealing resin in the gap and the peripheral portion of the semiconductor chip.

In this case, since the gap between the semiconductor chip 1 and the circuit wiring board 2 is usually about 20 μm to 50 μm, it is difficult to seal the resin having high viscosity. Therefore, the resin to be sealed in the gap formed by the semiconductor chip and the circuit wiring board is heated below the curing temperature to reduce the viscosity of the resin and enable the sealing.

However, in the method utilizing the capillary phenomenon, if the resin viscosity to be sealed is extremely high or low and the resin viscosity is not an appropriate value for the gap size, the resin to be sealed is a semiconductor chip. There is a problem that it is not formed uniformly over the entire gap with the circuit wiring board, which causes a decrease in reliability when a temperature cycle is applied. In particular, when the bump electrode pitch on the semiconductor chip is narrow, resin encapsulation is completely performed, so that it is necessary to use a resin having an extremely low viscosity, which is an important problem. That is, when resin encapsulation is performed using a low-viscosity resin, an encapsulation resin end is formed over a wide area around the semiconductor chip, and an MCM (Mul (Mul) that mounts a plurality of semiconductor chips on the circuit wiring board is formed.
In the case of the "Tichip Module", there has been a limit to increase the density.

Further, as in recent years, when the size of the semiconductor chip becomes large, there is a problem that the reliability cannot be secured unless the adhesion between the sealing resin and the semiconductor chip is improved more than ever before. . Therefore, JP-A-64-
In Japanese Patent Publication No. 59827, a proposal has been made to improve the adhesion strength between the circuit wiring board and the semiconductor chip by disposing an insulating film that chemically bonds with the sealing resin on the surface of the semiconductor chip to be flip-chip mounted and the surface of the circuit wiring board. .

However, if the bump electrode pitch is narrow, it becomes difficult to align the semiconductor chip with the circuit wiring board and the gap for resin sealing becomes narrow. Therefore, the gap between the semiconductor chip and the circuit wiring substrate should be resin sealed. At the same time, the problem that it becomes difficult.

In addition, as the size of the semiconductor chip increases in recent years, the amount of heat generated also increases, which has been a cause of increasing stress strain when heat dissipation is insufficient.

In any case, in the conventional flip-chip structure, reliability has been improved by optimizing only the resin properties and the sealing structure in the gap portion formed by the semiconductor chip to be flip-chip mounted and the circuit wiring board. However, a method of uniformly forming a resin in the gap between the semiconductor chip and the circuit wiring board, the resin size around the semiconductor chip,
Since the adhesive strength between the semiconductor chip and the sealing resin has not been sufficiently taken into consideration, the conventional sealing structure and its method have been problems in reliability.

[0026]

As described above, high density,
In the flip-chip mounting method that enables high-speed mounting, stress strain caused by the difference in thermal expansion coefficient between the semiconductor chip and the circuit wiring board is generated in the bump electrode portion, and the bump electrode is destroyed. There has been a serious problem that the flip chip mounting structure does not have sufficient reliability.

Therefore, as a method of reducing stress strain,
(1) Shorten the distance from the center point of the semiconductor chip to the center point of the bump electrode, (2) reduce the difference between the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the circuit wiring board, (3)
Improves heat dissipation so that the temperature difference does not increase,
(4) A method of making the bump electrode structure strong against stress strain has been proposed, and its effect has been exhibited to some extent.

Further, it has been proposed to enclose a resin in the gap between the semiconductor chip and the circuit wiring board to improve the mechanical strength of the bump connection portion, and the thermal expansion coefficient is significantly different from that of the semiconductor chip on the organic resin substrate. The effect was exhibited when the semiconductor chip was flip-chip mounted. However, in this resin-encapsulated flip-chip structure, it is difficult to secure a sufficient reliability life unless the physical properties of the resin encapsulating the gap between the semiconductor chip and the circuit wiring board are specified.

Therefore, the physical properties of the sealing resin are specified, for example, by making the shear elastic modulus of the resin to be sealed larger than the solder elastic coefficient of the bump connecting portion or making the thermal expansion coefficient of the resin smaller than the thermal expansion coefficient of the solder. In order to reduce the amount of shear deformation of the solder, it is possible to prevent damage due to shear fatigue of the bump connection portion and improve reliability. Further, the reliability has also been improved by specifying the content of the filler, the maximum particle size of the filler, and the average particle size of the filler together with the viscosity of the sealing resin.

On the other hand, in the method of sealing the resin in the gap between the semiconductor chip and the circuit wiring board, the resin is applied in advance on the surface of the semiconductor chip or the portion of the circuit wiring board where the semiconductor chip is mounted, and then the semiconductor chip is pressed. There has been a method of connecting the resin to the circuit wiring board and encapsulating the resin, but there was a problem that a connection failure occurred when a very small amount of resin remained between the bump electrode and the electrode pad of the circuit wiring board. .

Therefore, it has been proposed that the semiconductor chip and the circuit wiring board are flip-chip connected and then the resin is injected into the gap. However, in this method, the viscosity is lowered by heating at a temperature not higher than the curing temperature of the resin, so there is a problem that the resin is not uniformly formed in the gap between the semiconductor chip and the circuit wiring board. Furthermore, since the stress strain generated with the increase in size of the semiconductor chip also increases, there is a problem that sufficient reliability cannot be secured unless the adhesion between the sealing resin and the semiconductor chip is improved more than in the past.

Therefore, a method of arranging an insulating film which is chemically bonded to the sealing resin on the semiconductor chip and the circuit wiring board has been proposed. However, relaxation of stress strain which increases with the increase in size of the semiconductor chip and bump pitch This has been a problem because sufficient solutions have not been studied for uniform sealing of resin sealing, which becomes difficult with miniaturization.

Further, there have been problems with a heat dissipation method associated with an increase in size of a semiconductor chip and an alignment method associated with miniaturization of a bump pitch.

The present invention has been made in view of the above problems, and in a semiconductor device having a structure in which a semiconductor chip is flip-chip mounted on a circuit wiring board, a gap between the semiconductor chip and the circuit wiring board and the semiconductor chip. An object of the present invention is to provide a semiconductor device that has a long reliability life and is easily resin-sealed by optimally specifying the structure and physical properties of the sealing resin formed in the periphery.

[0035]

According to the present invention, firstly, a circuit board, a semiconductor chip connected to the circuit board through a plurality of bump electrodes, and at least a portion between the circuit board and the semiconductor chip are provided. A semiconductor device having a sealing resin layer provided in the circuit, the circuit facing the semiconductor chip.
15 from the surface of the connecting side of the substrate to the size of the semiconductor chip
Provided is a semiconductor device, wherein a polymer film having good wettability with the sealing resin is formed in a region having an enlarged dimension of 25% to 25%.

Secondly, the present invention relates to a circuit board, a semiconductor chip connected to the circuit board via a plurality of bump electrodes, and a sealing provided at least between the circuit board and the semiconductor chip. In a semiconductor device including a resin layer,
The sealing resin layer is a sealing resin formed on the semiconductor chip and containing dispersed fused silica filler in a first content rate.
An oil layer and the fused silica filler formed on the sealing resin.
Resin containing a second content different from the first content
Provided is a semiconductor device, which is a laminated body including layers.

Thirdly, the present invention is, in a method of manufacturing a semiconductor device in which a sealing resin layer is provided between a circuit board and a semiconductor chip connected via a plurality of bump electrodes, the semiconductor device facing the semiconductor chip. From the surface of the circuit board on the connection side to a region having an enlarged dimension of 15 to 25% of the dimension of the semiconductor chip, except for the connection portion or the bump end portion, wettability with the sealing resin. A step of forming a good polymer film, aligning the connection portion of the circuit board and the bump electrode of the semiconductor chip, and connecting, between the circuit board and the semiconductor chip, the sealing resin Provided is a method for manufacturing a semiconductor device, which includes a step of implanting and solidifying.

A fourth aspect of the present invention is a method of manufacturing a semiconductor device, wherein a sealing resin layer containing a filler is provided between a semiconductor substrate and a circuit board connected via bump electrodes. A step of forming a sealing resin layer containing a filler at a first content rate on the surface of the substrate or the connection side of the semiconductor chip, except for the connection portion or the bump end portion, and the connection portion of the circuit board; Aligning and connecting bump electrodes of the semiconductor chip,
A sealing resin layer containing a filler at the first content rate,
Provided is a method for manufacturing a semiconductor device, which comprises a step of injecting a sealing resin containing a filler at a second content rate different from a first content rate into a gap between the circuit board and the semiconductor chip and solidifying the resin.

Fifth, the present invention provides a method of manufacturing a semiconductor device, wherein a sealing resin layer containing a filler is provided between a semiconductor chip and a circuit board connected via bump electrodes. And on the surface of the semiconductor chip on the connection side, except for the connection portion or the bump end portion.
Forming a sealing resin layer containing a filler at a second content different from the content and the first content, and aligning the connection portion of the circuit board and the bump electrode of the semiconductor chip, The step of connecting, between the sealing resin layer containing the filler at the first content rate and the sealing resin layer containing the filler at the second content rate, different from the first and second content rates. Provided is a method for manufacturing a semiconductor device, which comprises a step of injecting a sealing resin containing a filler at a content rate of 3 and solidifying the resin.

In the third to fifth inventions, in particular, the dimension of the sealing resin to be laminated is preferably a step shape having a large dimension on the circuit wiring board side and a small dimension on the semiconductor chip side.

In the first to fifth inventions, preferably, the contact surface between the semiconductor chip and the sealing resin layer is within ± 5% of the semiconductor chip size, and the circuit wiring board and the sealing resin layer are in contact with each other. Contact surface is 15% of the semiconductor chip size
It has an enlarged dimension of ~ 25%.

In the first to fifth inventions, an annular protrusion having a height larger than the height of the bump electrode formed on the semiconductor chip is provided on at least the contact surface of the circuit wiring board with the sealing resin layer. Can be placed.

In the first to fifth inventions, the heat conductivity of the sealing resin is 5 (Wm ^-1 ° C) in order to improve the heat dissipation from the flip-chip mounted semiconductor chip.
It is preferably a resin having a value of ^-1 ) to 2.0 (Wm ^-1 ° C ^-1 ).

The above-mentioned third invention shows one production example of the first invention, and the fourth and fifth inventions are respectively the second invention.
2 shows a production example of the invention. The operation of the present invention will be described below.

Conventionally, it has been difficult to uniformly form the resin by the method of injecting the resin into the gap between the semiconductor chip and the circuit wiring board. On the other hand, according to the present invention, the sealing resin is uniformly arranged on the four sides of the semiconductor chip. This allows
The stress is uniformly distributed around the four sides of the semiconductor chip. Therefore, unlike the conventional case, the stress and strain are not concentrated due to the resin being concentrated on one side of the semiconductor chip, so that the semiconductor chip is not separated and broken from the circuit wiring board.

According to the first and third aspects of the invention, since the polymer film having good wettability with the sealing resin is applied to at least one of the semiconductor chip and the circuit wiring board,
By adjusting the coating size, it is possible to form a uniform resin around the semiconductor chip. In particular, when the bump pitch formed on the semiconductor chip is fine and a low-viscosity sealing resin is used to facilitate sealing, the conventional method forms the sealing resin over a wide range around the semiconductor chip. However, according to the first and third inventions, the polymer film having good wettability limits the area where the applied sealing resin spreads, which facilitates uniform resin sealing. Will be feasible.

Further, according to the second, fourth, and fifth inventions, since the gaps formed by the semiconductor chip and the circuit wiring board and the resin contents around the semiconductor chip are different from each other, the resin is laminated. By comparison, a large stress strain can be gradually relaxed, and the reliability life can be easily improved.

In the present invention, preferably, the size of the sealing resin is gradually reduced from the circuit wiring board side to the semiconductor chip side. This makes it possible to gradually relax the stress at the end portion of the sealing resin, and prevent the stress from being concentrated at the end portion of the sealing resin and destroying the sealing resin itself.

The encapsulating resin is preferably arranged on the surface of the circuit wiring board with an enlarged dimension of 15% to 25% with respect to the semiconductor chip. As a result, the stress is evenly distributed around the four sides of the semiconductor chip. Therefore, unlike the conventional case, the stress and strain are not concentrated due to the resin being concentrated on one side of the semiconductor chip, so that the semiconductor chip is not separated and broken from the circuit wiring board.

The method of limiting the spreading area of the sealing resin is also effective in the method of limiting by the polymer film as in the first and third inventions, but in the first to fifth inventions, It is also effective to further form an annular protrusion around the portion on the circuit board to which the semiconductor chip is connected as a resin spread preventing frame. This resin spread prevention frame can be used also as a position guide for the semiconductor chip and the circuit wiring board if the frame size is made substantially the same as that of the semiconductor chip. At this time, if the self-alignment of the solder is used, the semiconductor chip can be easily flip-chip mounted on the circuit wiring board without the need for a high-precision mounter as in the past.

Furthermore, according to the first and third aspects of the invention, since the polymer film having good wettability with the sealing resin is formed on at least one of the semiconductor chip and the circuit wiring board, reliability is improved. Even if sealing is performed using a high-viscosity resin having a high filler content for the purpose of improvement, the sealing time does not become long, and resin sealing can be realized at high speed in a short time.

Further, as shown in the second, fourth and fifth inventions, among the resins constituting the laminated sealing resin, the resin body which is the lowermost layer is previously formed on the connection surface of the semiconductor chip or the circuit wiring board. Even if the method of applying to at least one of the above is used, the resin sealing is similarly speeded up. Further, the sealing resin does not spread around the semiconductor chip, and uniform resin sealing is possible. As a result, the reliability life can be significantly improved.

In the present invention, the thermal conductivity is 0.5.
When using a resin having a value of ^{Wm -1 ℃ -1 ~2.0 Wm -1 ℃} -1, is improved thermal conductivity, it is possible to simplify the heat dissipation means such as heat radiating fins in the semiconductor device. This makes it possible to make the semiconductor device thinner and more compact.

[0054]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

1 to 5 are views showing a manufacturing process according to the first embodiment of the present invention.

In the figure, 1 is a semiconductor chip, 2 is a circuit wiring board on which the semiconductor chip is mounted, 3 is a bump electrode, 4 is a first sealing resin which constitutes a sealing resin laminate, and 5 is a sealing resin laminate. , A third sealing resin that constitutes a sealing resin laminated body, 7 is a polymer coating formed on a semiconductor chip, 8 is a polymer coating formed on a circuit wiring board, 9
Is an annular protrusion formed on the semiconductor chip.

First, as shown in FIG. 1, a silicon substrate 6
1, the aluminum bonding pad 24 provided on the silicon substrate 61, the barrier metal layer 25 provided thereon, the bump electrode 3 provided thereon, and the PSG (phosphorus) on the other substrate surface.・ Silica / glass)
A semiconductor chip 1 having a passivation film 23 formed of SiN (silicon nitride) is prepared.

The bump electrode 3 is formed, for example, in US Pat. No. 345.
It is formed using a known technique such as the vapor deposition method or the electroplating method as disclosed in Japanese Patent Application Laid-Open No. 8925, Japanese Patent Application Laid-Open No. 47-24765, and Japanese Patent Application Laid-Open No. 2-232928. This bump electrode is generally composed of solder, but in the case of the present invention, it does not necessarily have to be solder.
It may be a metal having rigidity as compared with solder such as u or Cu.

The formed bump electrode has a diameter of 100 μm, and 256 bumps are arranged along the periphery of the semiconductor chip. The size of the semiconductor chip is 10mm x 10m
The one having a size of m was used. Bump electrode is Cu / T
An i-barrier metal was formed and a Pb / Sn = 40/60 alloy was formed with an accuracy of 75 μm ± 5 μm in height.

Next, a plurality of bump electrodes 3 are formed from the center of the semiconductor chip 1 on the passivation film 23 of the semiconductor chip.
A polymer material having a good wettability with the sealing resin, such as a hydrocarbon wax, a fatty acid wax, a fatty acid amide wax, and an ester wax, is applied to the outer region to obtain a high wettability with the sealing resin. The molecular film 7 is formed.
Specifically, from the viewpoint of moisture resistance, ester waxes such as carnauba wax and montan wax are preferable, and in addition, long-chain carboxylic acids such as stearic acid, palmitic acid, zinc stearate and calcium stearate, and metal salts thereof. , Low molecular weight polyethylene wax and the like. These polymeric materials may be used alone,
Moreover, you may use it in combination. Further, for example, various amines, imidazoles, diazabicycloalkenes,
It is desirable to apply organic phosphines, zirconium alcoholates, zirconium chelates and the like. Examples of amines include N, N-dimethylcyclohexylamine, N-methyldicyclohexylamine, triethylenediamine, diaminodiphenylsulfone, dimethylaminomethylphenol, benzyldimethylamine, and trisdimethylaminomethylphenol. Examples of imidazoles are 2 -Methylimidazole, 2-phenylimidazole, heptadecylimidazole, 2-
Heptadecyl imidazole, 2-ethyl imidazole,
And 2-ethyl-4-methylimidazole, and the like. The diazacycloalkenes are 1,8-
Diazabicyclo (5,4,0) undensen-7 (DB
U) and (DUB) phenolic salts (eg U-CA)
TSA No. 1) and the like, and examples of the organic phosphines include triphenylphosphine (TPP), tributylphosphine, tricyclohexylphosphine, and dimethyldiphenylphosphine.

On the other hand, the circuit wiring board 2 on which the semiconductor chip is mounted is formed by using a known method such as US Pat. No. 4,811,082 or an ordinary laminated glass epoxy substrate.

Therefore, the material and structure of the substrate are not particularly limited in the case of the present invention, but here, for the sake of explanation, for example, a printed circuit board SLC of a system in which an insulating layer and a conductor layer are built up on a glass epoxy substrate is used. Surface L
Aminar Circuit) substrate will be used. The circuit wiring board is provided with an opening having a diameter of 110 μm in the connection terminal portion corresponding to the bump electrode of the semiconductor chip, and the connection terminal Cu21 is exposed. The solder resist layer 22 is coated on the portion other than the terminal 21 portion of the substrate. On the solder resist layer of the circuit wiring board 2, if necessary, a polymer film similar to a polymer material having good wettability with the sealing resin applied and formed on the semiconductor chip 1 is formed.

Next, as shown in FIG. 2, the semiconductor chip 1 and the circuit wiring board 2 are aligned using a flip chip bonder having a half mirror, which is a known technique, for alignment, and bump electrodes are formed. 3 and circuit wiring board 2
The connection terminal 21 of is brought into electrical and mechanical contact. At this time, the circuit wiring board 2 is held on a stage having a heating mechanism and is higher than the melting point of Pb / Sn = 40/60.
It is preheated to 0 ° C. in a nitrogen atmosphere.

Further, the semiconductor chip 1 and the circuit wiring board 2
Contacting the collet 31 holding the semiconductor chip 1 at the same temperature as the stage 32 mounting the substrate.
The semiconductor chip 1 and the electrode 21 of the circuit wiring board 2 are temporarily electrically and mechanically connected to each other by heating at 0 ° C. in a nitrogen atmosphere to melt the solder formed on the bump. Finally, by passing the circuit wiring board on which the semiconductor chip is mounted in a reflow furnace heated to 250 ° C. having a nitrogen atmosphere, electrical and mechanical connection is realized,
A semiconductor device as shown in FIG. 3 is obtained.

At this time, in the semiconductor chip 1, the self-alignment effect is generated due to the surface tension of the solder, a slight positional deviation generated at the time of mounting is corrected, and bonding is performed at an accurate position.

As described above, in the semiconductor device in which the semiconductor chip 1 is flip-chip mounted, the gap between the semiconductor chip 1 and the circuit wiring board 2 is formed on the semiconductor chip 1 before flip-chip mounting. 50 μm, which is 25 μm smaller than the height of the bump electrode 3
Had a value of.

Next, the semiconductor chip 1 and the circuit wiring board 2
About 10 ml of the resin 6 to be sealed is potted in the gap formed by and using the dispenser 33, and the region surrounded by the bump electrodes 3 is resin-sealed by the capillary phenomenon. This resin potting method is disclosed in Japanese Patent Laid-Open No.
No. 0-147140, a method of uniformly forming a resin in the gap between the semiconductor chip 1 and the circuit wiring board 2 as necessary, such as one-pot potting or L-shaped potting by a known technique. It is not particularly limited.

The sealing resin contains, for example, bisphenol epoxy, an imidazole curing catalyst, an acid anhydride curing agent and spherical quartz filler in a weight ratio of 45% by weight, and has a maximum particle size of 35 μm and an average particle size of 35 μm. Particle size is 10μ
A resin having m and a viscosity of 50 cps (25 ° C.) was used.

As a sealing resin, a novolac epoxy resin, an alicyclic epoxy resin, or a glycidyl ester resin is used as a main material, and an acid anhydride, an amine acid, a fatty acid, an alkyd resin, or the like is used as a curing agent to form spherical quartz. 40 to 50% by weight of filler is contained, the maximum particle size is 35 μm, the average particle size is 9 μm, and the viscosity is 50 to 1
A resin or the like having a temperature of 00 cps (25 ° C.) can be used.

To further cure the encapsulated resin, store it in a clean oven at 80 ° C. for 4 hours.
By carrying out the steps described above, a semiconductor device having the cross-sectional structure shown in FIG. 5 can be realized. Also,
FIG. 6 is a perspective view of the semiconductor device having the cross-sectional structure shown in FIG. 5 as seen from above.

7 to 11 are views showing the manufacturing process according to the second embodiment of the present invention.

First, the semiconductor chip 1 on which the bump electrodes 3 are formed and the glass epoxy substrate (SLC substrate) 2 are prepared using the same method as described above.

Next, on the passivation film 23 of the semiconductor chip 1 on which the bump electrodes 3 are formed, a cresol novolac type epoxy resin (ECON-195X).
L: manufactured by Sumitomo Chemical Co., Ltd.), 54 parts by weight of a phenol resin as a curing agent, 100 parts by weight of fused silica as a filler, 0.5 parts by weight of benzyldimethylamine as a catalyst, and carbon as other additives. 3 parts by weight of black,
The first epoxy sealing resin obtained by crushing, mixing, and melting 3 parts by weight of the silane coupling agent is applied to a thickness of 10 μm to form the first sealing resin layer 4. The coating method of the sealing resin is not particularly limited, but any method such as a screen printing method or a dipping method can be used, and the epoxy resin melt is rolled to form a sheet. It is also possible to use a method in which only the bump-corresponding portion is bored and the resultant is arranged on the semiconductor chip.

The coefficient of thermal expansion of this sealing resin was 40 × 10 ^-6 (° C. ^-1 ) as a result of a separate test. Further, on the circuit wiring board 2 covered with the solder resist 22, a cresol novolac type epoxy resin (ECON) having a filler content different from that of the sealing resin formed on the surface of the semiconductor chip 1 is used. -195XL; Sumitomo Chemical Co., Ltd.) 350 parts by weight, curing agent 54 parts by weight phenol resin, filler 100 parts by weight fused silica, catalyst benzyl dimethylamine 0.5 parts by weight, other additives car A second epoxy resin in which 3 parts by weight of Bonblack and 3 parts by weight of a silane coupling agent are crushed, mixed, and melted is applied to a thickness of about 10 μm to form a second sealing resin layer 5. The method of applying this resin is not particularly limited as in the case of the semiconductor chip.

The coefficient of thermal expansion of this sealing resin was 20 × 10 ^-6 (° C. ^-1 ) as a result of the test.

Then, as shown in FIG. 8, the semiconductor chip 1 and the circuit wiring board 2 are aligned with each other by using a flip chip bonder which has a publicly-known technique such as a half mirror and performs alignment. , Bump electrode 3 and circuit wiring board 2
The connection terminal 21 of is brought into electrical and mechanical contact. With the semiconductor chip 1 and the circuit wiring board 2 in contact with each other, the collet 31 holding the semiconductor chip 1 is heated to the same temperature 200 ° C. as the stage 32 on which the board 2 is mounted in a nitrogen atmosphere, and bumps are applied. The semiconductor chip 1 and the electrodes 21 of the circuit wiring board 2 are melted by melting the solder formed on the
And are temporarily connected electrically and mechanically. Finally, the circuit wiring board 2 having the semiconductor chip 1 mounted thereon is passed through a reflow furnace heated to 250 ° C. having a nitrogen atmosphere to realize electrical and mechanical connection, and as shown in FIG. A semiconductor device is obtained.

Further, as shown in FIG. 10, about 10 ml of the sealing resin 6 is potted in the vicinity of the gap formed by the semiconductor chip 1 and the circuit wiring board 2 and surrounded by the bump electrode 3 by the capillary phenomenon. The area that is formed is sealed with resin. This resin 6 contains bisphenol-based epoxy, an imidazole curing catalyst, an acid anhydride curing agent and spherical silica filler in a weight ratio of 45% by weight, and has a maximum particle size of 35 μm.
A resin having an average particle diameter of 10 μm, a viscosity of 50 cps (25 ° C.) and a thermal expansion coefficient of 30 × 10 ⁻⁶ (° C. ⁻¹ ) may be used. Further, a cresol novolac type epoxy (ECON-195XL; manufactured by Sumitomo Chemical Co., Ltd.) having a filler content different from that of the first and second epoxy encapsulating resins is provided.
Parts by weight, 54 parts by weight of phenolic resin as a curing agent, 200 parts by weight of fused silica as a filler, 0.5 parts by weight of benzyldimethylamine as a catalyst, 3 parts by weight of carbon black as other additives, silane coupling 3 parts by weight of the agent was crushed, mixed, and melted to have a thermal expansion coefficient of 35 × 10 ^-6
A third epoxy resin of (° C. ^-1 ) may be used as long as it finally realizes a resin laminate having different filler contents in the gap between the semiconductor chip and the circuit wiring board. It is not particularly limited.

Further, in order to cure the encapsulated resin, it is stored in a clean oven at 80 ° C. for 4 hours.
By carrying out the steps described above, the semiconductor device having the structure shown in FIG. 11 can be realized.

FIG. 12 is a sectional view showing a third embodiment of the present invention. As shown in FIG. 12, the semiconductor chip 1
It is also possible to manufacture the semiconductor device according to the present invention by forming the ring-shaped projection 9 on the circuit wiring board 2 around the periphery of the semiconductor chip 1 with a size larger by 15% to 25% and resin sealing. is there. This example is also applicable to the first and second embodiments of the present invention.

In this embodiment, for the sake of explanation, the inner dimensions are 120 mm × 120 mm and the outer dimensions are 122 mm × 122 m.
m, frame thickness 2 mm, frame height 75 mm made of epoxy resin, the ring-shaped projection 9 was arranged on the circuit wiring board 2 with a silane coupling agent as a polymer material. It is not particularly limited. The ring-shaped projections 9 were 200 parts by weight of a cresol novolac type epoxy resin (ECON-195XL; manufactured by Sumitomo Chemical Co., Ltd.), 54 parts by weight of a phenol resin as a curing agent, 100 parts by weight of fused silica as a filler, and a catalyst. 0.5 parts by weight of benzyl dimethylamine as an additive, and other additives as a car
The epoxy resin obtained by crushing, mixing and melting 3 parts by weight of Bonblack and 3 parts by weight of a silane coupling agent and rolling it into a sheet was used as a frame.

At this time, the alignment of the semiconductor chip 1 is
Accurate alignment was not performed by a flip chip bonder using a half mirror, and reflow connection was performed by using an annular projection as an alignment guide.

As a result, all the bump electrodes were accurately connected by the self-alignment of the solder, and no connection failure occurred between the bump electrodes and the connection terminals on the circuit wiring board.

Further, since the sealing resin 6 on the circuit wiring board 2 is the annular projection 9 made of epoxy resin, it does not spread over a wide area around the semiconductor chip 1 and the epoxy resin frame 9 is used as a stopper. As a frame, it is possible to form a uniform sealing resin around the four sides of the semiconductor chip 1.

Here, of the embodiments shown above, the reliability of the semiconductor device shown in FIG. 11 according to the second embodiment of the present invention was evaluated, and the following results were obtained.

FIG. 13 shows a semiconductor chip of 10 mm × 10 mm used for explaining the method of manufacturing a semiconductor device.
256 bump electrodes with Pb / Sn = 40/60, diameter 1
It represents the result of a reliability test of a sample formed by 00 μmφ and flip-chip mounted on an SLC substrate.
It is a graph which shows the relationship between the number of cycles and a cumulative failure rate. In the figure, a solid line 701 indicates a semiconductor device without resin sealing, a solid line 702 indicates a resin containing no filler, and a solid line 703 indicates 40% by weight of a filler.
When the sealing resin contained is used, the solid line 704 is shown in FIG.
Results of the semiconductor device according to the second embodiment of the present invention shown in FIG. Temperature cycle condition is (-55 ℃
(30 minutes) -25 ° C (5 minutes) -125 ° C (30 minutes) -2
It carried out at 5 degreeC (5 minutes)), and implemented it with 1000 samples. The cumulative failure rate is shown on the vertical axis and the temperature cycle is shown on the horizontal axis.

The sample which was not resin-sealed had a defect after 500 cycles, and after 2000 cycles, the defect was 100%.
% Was bad. Moreover, the reliability of the resin-sealed sample was higher than that of the non-resin-sealed sample, but the reliability was further improved when the resin containing the filler was used.

Further, as indicated by the solid line 704, when the resin whose thermal expansion coefficient is changed by the filler is used as in the present invention, no defect occurs up to 3000 cycles,
It was found that the reliability was significantly improved.

FIG. 14 is a result showing the relationship between the dimension of the resin disposed in the gap between the semiconductor chip and the circuit wiring board with respect to the peripheral portion of the semiconductor chip and the reliability life. FIG. 5 is a graph showing the relationship between the ratio of the size of the resin protruding and the number of fatigue life cycles. The sample shape, number, and reliability test environment were the same as in the case of FIG. 13, and only the type of circuit board was changed. Solid line 8
Reference numeral 01 indicates the result when an AlN substrate is used, solid line 802 indicates the result when a glass epoxy substrate is used, and solid line 803 indicates the result when the epoxy substrate is used. As for reliability, the cumulative defect of the sample is 5
It was evaluated by Nf ₅₀ showing 0%.

When the resin size in the peripheral portion of the semiconductor chip is less than 15%, the semiconductor chip may be peeled off from the circuit wiring board, and when the resin size in the peripheral portion of the semiconductor chip is larger than 25%, the entire resin to be sealed is large. It has been found that when the peeling failure occurs and the resin dimension in the peripheral portion of the semiconductor chip is 15% to 25% of the vertical dimension of the semiconductor chip, the reliability life is high. It was also found that the reliability life of the semiconductor device is high when the difference in the coefficient of thermal expansion from the semiconductor chip is small, and low when the difference in the coefficient of thermal expansion is large.

Further, according to the first embodiment of the present invention, since the polymer film having good wettability with the sealing resin is formed on at least one of the semiconductor chip and the circuit wiring board, The conventional sealing speed, which was 0.1 mm / min, became 1.0 mm / min, which enabled sealing at about 10 times higher speed. Further, conventionally, about 10 voids of about 2 mm × 2 mm have been generated with a probability of about 50%, but by using the present invention, it becomes possible to prevent the generation of voids.

The pressure distribution of the resin in the gap formed by the semiconductor chip and the circuit board from the flow of the viscous fluid between the parallel plates is expressed by the following equation.

L = {(R ² h ⁴ +48 μNht) ^1/2 −
Rh ² } / 12μ where N is the wetting force, R is the flow path resistance of the bump portion, L is the injection distance, μ is the viscosity, and t is the time h and the gap size.

As is clear from the above equation, the injection rate is
It can be seen that it depends on the flow path resistance, the resin viscosity, and the wetting force.

The relationship between the injection distance and the sealing time was measured based on this equation. A graph showing the result is shown in FIG. In the figure, a solid line 151 indicates that when a polymer film is formed on the surface of the circuit board and the semiconductor chip, and a sealing resin having a low viscosity is injected into the gap for sealing, the solid line 152 similarly indicates the polymer film. Is formed and sealing is performed by injecting a sealing resin having a normal viscosity, a solid line 153 is a graph when the sealing resin is injected and sealing is performed without forming a polymer film. Shown respectively.

From this graph, as indicated by the solid line 153, it can be seen that the injection rate is extremely slow when the polymer film is not formed. In some cases, the sealing could not be performed during the filling. On the other hand, when the polymer film having good wettability with the sealing resin is formed, as shown by the solid line 152, the injection speed is increased and the sealing is sufficiently possible without any problem. Further, as shown by the solid line 151, when the viscosity of the sealing resin is lowered and sealing is performed by a method such as heating, the sealing speed can be extremely increased.

Regarding the heat dissipation property, the heat conductivity of the sealing resin can be improved by adjusting the filler content, and the heat dissipation property can be improved up to 20 ° C./W. Therefore, when the heat dissipation of the semiconductor device, which conventionally requires the provision of five heat dissipation fins, is made to be the same as that of the conventional device, the thickness of the semiconductor device can be reduced to 1/10.

From the results shown above, it is understood that the reliability of the semiconductor device using the present invention is sufficient as compared with the conventional method.

The present invention is not limited to the above embodiments, but can be variously modified without departing from the spirit thereof. For example, the material configuration of the circuit wiring board is not limited, and naturally the thickness of the sealing resin corresponding to the solder bump size is not particularly limited. Further, in the present invention, the material configuration is not particularly limited as long as the thermal expansion coefficients are mutually changed. Therefore, the stepwise change of the thermal expansion coefficient may be any stepwise change from the semiconductor chip side to the circuit wiring board side or from the circuit wiring board side to the semiconductor chip side.

[0099]

According to the first and third aspects of the present invention, the polymer film having good wettability with the sealing resin is formed by coating on either the surface of the semiconductor chip or the circuit wiring board. By appropriately adjusting the coating size, uniform resin sealing can be performed around the semiconductor chip. Therefore, even when the bump pitch formed on the semiconductor chip is fine and a low-viscosity encapsulating resin is required, it is possible to prevent the resin from spreading over a wide range around the semiconductor chip and to increase the density of the plurality of semiconductor chips. Will be possible.

According to the second invention, the fourth invention and the fifth invention, the resin having different filler contents is laminated and arranged around the gap formed by the semiconductor chip and the circuit wiring board and around the semiconductor chip. The stress strain can be gradually relaxed, and the reliability can be easily improved as compared with the conventional case.

Furthermore, in the present invention, when the size of the sealing resin is reduced stepwise from the circuit wiring board side to the semiconductor chip side, stress concentrates on the end portions of the sealing resin and the sealing resin itself is destroyed. This prevents the semiconductor device from being destroyed.

Therefore, according to the present invention, it is possible to realize a semiconductor device which has higher reliability than the case of using the conventional technique and which can be easily sealed with resin.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a manufacturing process according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention.

6 is a top view of a semiconductor device having the cross-sectional structure shown in FIG.

FIG. 7 is a sectional view showing a manufacturing process according to a second embodiment of the present invention.

FIG. 8 is a sectional view showing a manufacturing process according to a second embodiment of the present invention.

FIG. 9 is a sectional view showing a manufacturing process according to a second embodiment of the present invention.

FIG. 10 is a sectional view showing a manufacturing process according to a second embodiment of the present invention.

FIG. 11 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 12 is a sectional view showing a third embodiment of the present invention.

FIG. 13 is a graph showing the result of a reliability test of the semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a graph showing the relationship between the protruding resin size and the reliability life of the semiconductor device according to the second embodiment of the present invention.

FIG. 15 is a graph showing the relationship between the injection distance and the sealing time.

FIG. 16 is a schematic diagram for explaining a basic mounting structure of a conventional semiconductor device.

FIG. 17 is a schematic diagram showing an example of a conventional semiconductor device.

FIG. 18 is a schematic diagram showing another example of a conventional semiconductor device.

[Explanation of symbols]

1 semiconductor chip 2 circuit wiring board 3 bump electrodes 4 First sealing resin 5 Second sealing resin 6 Third sealing resin 7 Polymer coating formed on semiconductor chips 8 Polymer film formed on circuit wiring board 9 Annular protrusions formed around semiconductor chips 21 Connection terminal 22 Solder resist 23 Passivation film 24 Al bonding pad 25 barrier metal 31 Collet 32 Substrate heating heater 33 dispensers

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-310567 (JP, A) JP-A-5-13119 (JP, A) JP-A-5-166976 (JP, A) JP-A-6- 314715 (JP, A) JP-A-63-124425 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/60

Claims (7)

(57) [Claims] 1. A circuit board, a semiconductor chip connected to the circuit board via a plurality of bump electrodes, and a sealing resin layer provided at least between the circuit board and the semiconductor chip. In a semiconductor device, a connection-side surface of the circuit board facing the semiconductor chip
In the semiconductor device, a polymer film having good wettability with the sealing resin is formed in a region having an enlarged size of 15 to 25% of the size of the semiconductor chip. To 2. A region according to the outside from the plurality of bump electrodes from the connection side surface center of the semiconductor chip, wherein wherein said polymer film is further formed
Item 2. The semiconductor device according to item 1 . 3. A circuit board, a semiconductor chip connected to the circuit board via a plurality of bump electrodes, and a sealing resin layer provided at least between the circuit board and the semiconductor chip. In a semiconductor device, the encapsulating resin layer is formed on the semiconductor chip and contains a dispersed fused silica filler at a first content rate, and the encapsulating resin layer is formed on the encapsulating resin and melts. A semiconductor device comprising: a laminate including a sealing resin layer containing a silica filler in a second content different from the first content. 4. A method of manufacturing a semiconductor device, wherein a sealing resin layer is provided between a semiconductor chip and a circuit board connected via a plurality of bump electrodes, and connecting the circuit board facing the semiconductor chip. A step of forming a polymer film having good wettability with the encapsulating resin in a region having an enlarged dimension of 15 to 25% with respect to the dimension of the semiconductor chip from the side surface , excluding the connection portion or the bump end portion. A semiconductor including a step of aligning and connecting a connection portion of the circuit board and a bump electrode of the semiconductor chip, and a step of injecting the sealing resin between the circuit board and the semiconductor chip to solidify Device manufacturing method. 5. A step of forming the polymer film
The plurality of semiconductor chips from the center of the connection side surface of the semiconductor chip.
Apply the polymer coating to the area outside the bump electrode.
5. The semiconductor according to claim 4, characterized in that
Device manufacturing method. 6. A circuit board connected via bump electrodes.
Resin layer containing a filler between the semiconductor chip and the semiconductor chip
In the method for manufacturing a semiconductor device provided with
Also, the surface of the connection side of the circuit board or the semiconductor chip
On top of the first, except for its connections or bump ends
Process to form a sealing resin layer containing filler at the content rate
The connection part of the circuit board and the bump of the semiconductor chip
Step of aligning and connecting electrodes, the first containing
A sealing resin layer containing a filler at a ratio of a circuit board or
In the gap between the semiconductor chip and the first content ratio different from the first
Inject the sealing resin containing the filler at the content ratio of 2 and
A method of manufacturing a semiconductor device, comprising the step of: 7. A circuit board connected via bump electrodes.
Resin layer containing a filler between the semiconductor chip and the semiconductor chip
In a method of manufacturing a semiconductor device provided with
On the surface of the connection side of the substrate and the semiconductor chip, the contact
Except for the continuation part or the bump end part, the first content ratio and the first content ratio
A seal containing a filler in a second content different from the content of
Steps of forming respective resin layers, connecting portions of the circuit board
Align and connect with bump electrodes of the semiconductor chip
Step of sealing, containing the filler in the first content rate
Sealing tree containing resin layer and filler in the second content ratio
Between the fat layer, a third content different from the first and second content rates
The process of injecting the encapsulating resin containing the filler at a rate to solidify
And a method for manufacturing a semiconductor device .