JP4445338B2 - Spread spectrum signal receiver - Google Patents

Description

  The present invention relates to a spread spectrum signal receiving apparatus that demodulates a spread spectrum received signal using a pseudo noise signal (hereinafter referred to as a PN code).

  In the current GPS (Global Positioning System), an artificial satellite as a transmitting device superimposes a carrier wave having a frequency of 1575.42 MHz on a navigation message, and a C / A code is applied to the navigation message on which the carrier wave is superimposed. Spread spectrum is performed using a PN code referred to as “P”, and the spread spectrum navigation message is transmitted as an L1 signal to a spread spectrum signal receiving apparatus.

  Here, the C / A code is a code sequence obtained by adding modulo 2 to two types of code sequences generated by two 10-bit code generators (G1 generator and G2 generator) arranged in the transmitter. The rate is 1.023 MHz, the number of chips is 1023 chips, and the repetition period is 1 ms. Also, by changing the output tap of the G2 generator, a unique code string can be obtained for each artificial satellite.

  By the way, GPS is scheduled to be updated around 2008 (see Non-Patent Document 1). Along with this, transmission of a spectrum-spread signal using an L2C code as a new PN code is scheduled to start on the L2 signal (carrier frequency: 1227.6 MHz).

  In this case, the L2C code is time-divided into two types of PN codes (L2CM code and L2CL code), the chip rate of the L2CM code is 511.5 kHz, the number of chips is 10230 chips, and the repetition period is 20 ms. It is. On the other hand, the chip rate of the L2CL code is 511.5 kHz, the number of chips is 767250 chips, and the repetition period is 1.5 s.

The L2CM code and the L2CL code are code strings specific to each satellite constituting the GPS, and are generated by a 27-bit code generator disposed in a transmission device (here, each artificial satellite) ( It is obtained by dividing 2 ²⁷ -1) code strings into a start interval and an end interval by each artificial satellite.

  Based on the existing technology and the contents disclosed in Non-Patent Document 1, a spread spectrum signal receiving apparatus that demodulates a signal spread by an L2C code can be considered as follows.

  This spread spectrum signal receiving apparatus receives a signal from a GPS artificial satellite, performs frequency conversion and amplification processing on the received signal, removes a carrier wave component contained in the received signal, and generates a baseband signal Is generated. The code generation unit of the spread spectrum signal receiving apparatus generates an L2CM code and outputs the L2CM code to the L2CM correlation unit. The L2CM correlation unit correlates the L2CM code with the baseband signal, and the result is L2CM correlation. The value is output to the L2CM integrating unit. The L2CM integration unit performs an integration process of the L2CM correlation value, and outputs the result as an L2CM integration correlation value to the control unit. The control unit sets the frequency and phase of the L2CM code generated by the code generation unit so that initial acquisition and stable tracking of the received signal can be performed.

  The code generator generates an L2CL code and outputs the L2CL code to the L2CL correlator. The L2CL correlator correlates the L2CL code and the baseband signal, and the result is used as an L2CL correlation value as an L2CL integration value. To the output. The L2CL integration unit performs an integration process of the L2CL correlation value, and outputs the result as an L2CL integration correlation value to the control unit. The control unit sets the frequency and phase of the L2CL code generated by the code generation unit so that initial acquisition and stable tracking of the received signal can be performed.

  Here, the code generation unit includes a code clock generation unit, an L2CM code generation unit, and an L2CL code generation unit. The code clock generation unit generates a code clock, which is an operation clock of the L2C code, based on a frequency and a phase indicating the L2C code clock setting content from the control unit. The L2CM code generation unit generates the L2CM code based on the code clock, designation of an artificial satellite from the control unit, and setting contents indicating the state (initial state or end state) of the L2CM code. The L2CL code generation unit generates the L2CL code based on the code clock, the designation of the artificial satellite, and the setting content indicating the state (initial state or end state) of the L2CL code.

The L2CM code generation unit and the L2CL code generation unit each include a code generation unit including a 27-bit shift register sequence and a logical combination thereof, and a phase state setting unit. by dividing the state of tHAT represented (2 ²⁷ -1) in the initial state and the end state, so as to obtain the L2CM code and L2CL code as a unique code sequence in the satellite.

  In this case, the phase state setting unit monitors the output of the state value from each shift register of the code generation unit, and the output state value corresponds to the artificial satellite number designated by the control unit. When the state is reached, each shift register is set to an initial state.

  In addition, since the spread spectrum signal receiving apparatus may receive an L2C code from an artificial satellite with an arbitrary number of chips, the L2CM code generation unit and the L2CL code generation unit may receive the L2CM code and L2CL from the control unit. Based on the code state setting, an L2CM code and an L2CL code of an arbitrary number of chips are generated so that the spread spectrum signal receiving apparatus can reliably capture and track the L2C code.

ARINC RESEARCH CORPORATION, ICD-GPS-200C-005R1 Navstar GPS Space Segment / Navigation User Interfaces, 14 January, 2003, p.5-32b

  In the spread spectrum signal receiving apparatus according to the prior art, it is only necessary to hold one type of G1 generator and G2 generator state value common to each artificial satellite for the C / A code. The memory capacity necessary to hold the data is 1023 chips × 10 bits × 2 types.

  On the other hand, in the spread spectrum signal receiving apparatus for L2C code assumed based on the existing technology and Non-Patent Document 1, the L2C code is compared with the number of bits (10 bits) of the C / A code. Since the number of bits (27 bits) is long and the phase state of the L2C code varies from satellite to satellite, the memory capacity required to hold the state value of the L2C code is (767250 chips + 10230 chips) × 27 bits × 32 satellites. Therefore, the spread spectrum signal receiving apparatus for the L2C code requires a memory capacity of 30,000 times or more as compared with the spread spectrum signal receiving apparatus according to the prior art.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a spread spectrum signal receiving apparatus capable of reducing the memory capacity necessary for holding the L2C code.

A spread spectrum signal receiving apparatus according to the present invention includes a code generation unit having a code state generation unit, a correlation unit connected to the code generation unit, an integration unit connected to the code generation unit and the correlation unit, A control unit connected to the integration unit and the code generation unit, wherein the code generation unit generates a state value in a desired number of chips of the PN code by the code state generation unit, and the generated Based on the state value, a PN code for performing demodulation processing by despreading on the spread spectrum received signal input to the correlation unit is output to the correlation unit, and the correlation unit receives the input The received signal and the PN code are correlated, and the processing result is output as a correlation value to the integrating unit. The integrating unit performs an integration process on the input correlation value, and the processing Result was output to the controller as the integrated correlation value, the control unit, based on the input the integrated correlation value, to control the frequency and phase of the PN code generated by the code generator Features.

In this case, the code state generating unit on the basis of the frequency and phase of the PN code from the control unit to generate the state value at a desired number of chips of the PN code, the code generation unit, the Based on the state value, a PN code for demodulating the received signal is generated and output to the correlator, so that the spread spectrum signal receiving apparatus can detect the phase related to the PN code of each artificial satellite. It becomes unnecessary to store the state. Thereby, the memory capacity in the spread spectrum signal receiving apparatus can be reduced.

Here, the code state generating unit comprises a shift register unit, wherein the code state generating unit, based on the number of chips before Symbol PN code are entered from the control unit, the state value from the shift register unit Is preferably output.

To the code state generating unit from the control unit, simply outputs the switch number of taps of the PN code, the code state generating unit, based on these instruction content, the state value from the shift register unit , The memory capacity can be further reduced.

  The code generation unit includes a clock pulse multiplication unit connected to the code state generation unit, and the clock pulse multiplication unit outputs a clock pulse having a desired frequency to the shift register unit. Is preferred.

  As a result, the state value can be generated and output in a short time in the shift register unit.

The code state generation unit further includes a state holding unit, and the state holding unit stores a state value regarding each chip constituting the PN code in a state holding table, and the code state generation unit and Ji number of taps of the PN code inputted from the control unit compares said each chip of the state holding unit, select the status value of the chip closer to the number of chips, said the state value as an initial value Preferably, the shift register unit outputs the state value of the number of chips input from the control unit based on the input initial value.

  When information on an arbitrary number of chips is input from the control unit to the code state generation unit, the shift register unit is a period corresponding to the difference between each chip in the state holding unit and the number of chips, Generation processing may be performed. As a result, the state value can be output in a shorter time.

  Further, the spread spectrum signal receiving apparatus includes a plurality of the correlation units and the integration units, and the code generation unit generates PN codes corresponding to the PN codes of the plurality of spread spectrum received signals, respectively. preferable.

  As a result, the PN code of each received signal can be generated by one code generation unit.

  Furthermore, it is preferable that the PN code is at least one of an L2CM code and an L2CL code.

According to the spread spectrum signal receiving apparatus according to the present invention, the code state generating unit on the basis of the frequency and phase of the PN code from the control unit, generates a status value of a desired number of chips of the PN code, the code Since the generation unit generates a PN code for demodulating the received signal based on the state value and outputs the generated PN code to the correlation unit, the spread spectrum signal receiving apparatus can receive the PN code of each artificial satellite. It is not necessary to store the phase state for the code. Thereby, the memory capacity in the spread spectrum signal receiving apparatus can be reduced.

  A preferred embodiment of a spread spectrum signal receiving apparatus according to the present invention will be given and described in detail below with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a spread spectrum signal receiving apparatus 10 according to the present embodiment.

  As shown in FIG. 1, the spread spectrum signal receiving apparatus 10 is connected to a code generation unit 12, two correlation units 14 and 16 connected to the code generation unit 12, and the code generation unit 12 and the correlation unit 14. L2CM integration unit 18, L2CL integration unit 20 connected to code generation unit 12 and correlation unit 16, and control unit 22 connected to L2CM integration unit 18, L2CL integration unit 20 and code generation unit 12. is doing.

  When receiving the L2 signal from the artificial satellite, the spread spectrum signal receiving apparatus 10 uses a frequency converter and an amplifier (not shown) to remove the carrier from the L2 signal that is a received signal, and the received signal from which the carrier has been removed. Are output to the L2CM correlation unit 14 and the L2CL correlation unit 16 as baseband signals. The L2CM correlation unit 14 receives a signal (hereinafter, referred to as a first baseband signal) of the baseband signal that is spectrum-spread with the L2CM code, and the L2CL correlation unit 16 receives the signal of the baseband signal. A signal (hereinafter, referred to as a second baseband signal) subjected to spectrum spreading with the L2CL code is input.

  The code generation unit 12 outputs the L2CM code to the L2CM correlation unit 14. Further, the code generation unit 12 outputs the L2CL code to the L2CL correlation unit 16.

  The L2CM correlation unit 14 correlates the first baseband signal and the L2CM code input from the code generation unit 12, and outputs the processing result to the L2CM integration unit 18 as a first correlation value (L2CM correlation value). Output. The L2CL correlator 16 correlates the second baseband signal with the L2CM code input from the code generator 12, and outputs the processing result to the L2CM accumulator 18 as a second correlation value (L2CL correlation value). Output.

  The L2CM integration unit 18 performs integration processing on the input first correlation value, and outputs the processing result to the control unit 22 as a first integration correlation value (L2CM integration correlation value). On the other hand, the L2CL integration unit 20 performs integration processing on the input second correlation value, and outputs the processing result to the control unit 22 as a second integration correlation value (L2CL integration correlation value).

  The control unit 22 outputs control content related to the L2CM code and the L2CL code to the code generation unit 12 based on the input first integrated correlation value and the second integrated correlation value.

  This control content is for the spread spectrum signal receiving apparatus 10 to perform reliable initial acquisition and stable tracking of the L2 signal, the content indicating the number of the satellite that is the transmission source of the L2 signal, the L2CM code, The content indicating the number of chips of the L2CL code and the code clock information indicating the phase and frequency of the L2CM code and the L2CL code are included.

  FIG. 2 is a block diagram illustrating an internal configuration of the code generation unit 12.

  The code generation unit 12 includes a clock generation unit 40, a multiplication circuit unit 38 connected to the clock generation unit 40, a code state generation unit 36 connected to the multiplication circuit unit 38, and a code connected to the clock generation unit 40. The clock generator 30 includes an L2CM code generator 32 and an L2CL code generator 34 connected to the code clock generator 30 and the code state generator 36.

  The clock generator 40 simultaneously outputs a clock (hereinafter referred to as a first clock) to the code clock generator 30 and the multiplier circuit unit 38.

  The multiplier circuit unit 38 outputs a clock generated by multiplying the frequency of the input first clock to a desired frequency (hereinafter referred to as a second clock) to the code state generator 36. The multiplication number is an arbitrary value including 1 time.

  Based on the input second clock, the satellite number, and the number of chips of the L2CM code and L2CL code, the code state generation unit 36 determines the state values of the L2CM code and L2CL code in the number of chips. Information indicating the phase of the L2CM code and the L2CL code is output to the L2CM code generator 32 and the L2CL code generator 34.

  Based on the code clock information and the first clock from the clock generator 40, the code clock generator 30 generates a code clock signal having a repetition rate of the chip rate (511.5 kHz) of the L2CM code and the L2CL code. The code clock signal is output to the L2CM code generator 32 and the L2CL code generator 34, and generally includes a numerically controlled oscillator (NCO) or the like.

  The L2CM code generator 32 and the L2CL code generator 34 are composed of shift registers (not shown). In this case, the code clock signal is input to the shift register as a control clock in the L2CM code generation unit 32, and the state input from the code state generation unit 36 is set, so that the state of the shift register is the code code. Transition is made according to the clock signal. Simultaneously with this state transition, the value of the shift register is also monitored. Here, when the end state of the designated satellite number is detected, the L2CM code generator 32 sets the shift register to the designated initial state, thereby repeating the code generation of 10230 chips. Is output to the correlation unit 14 as an L2CM code.

On the other hand, the L2CL code generation unit 34 is composed of a shift register (not shown), like the L2CM code generation unit 32. In this case, in the L2CL code generation unit 34, the code clock signal is input to the shift register as a control clock, and the state input from the code state generation unit 36 is set. Transition is made according to the clock signal. Simultaneously with this state transition, the value of the shift register is also monitored. Here, when the end state of the designated satellite number is detected, the L2C L code generation unit 34 sets the shift register to the designated initial state, thereby repeatedly generating the code of 767250 chips. The state of the last bit of the register is output to the correlation unit 16 as an L2CL code.

  FIG. 3 is a block diagram showing an internal configuration of the code state generation unit 36.

  The code state generation unit 36 includes a shift register unit 50 and a phase state generation unit 52.

  In the phase state generation unit 52, a table storing the numbers of the artificial satellites shown in FIG. 4 from the control unit 22 and the state values of the L2CM code and the L2CL code corresponding to the numbers is arranged. In this case, the table stores state values indicating the initial state among the initial states and end states of the L2CM code and the L2CL code.

  In addition, when the instruction content indicating the number of the artificial satellite and the number of chips of the L2CM code and the L2CL code is input from the control unit 22, the phase state generation unit 52 transmits the instruction to the shift register unit 50 based on the instruction content. The instruction content indicating the initial state is output. Then, when the second clock is input from the multiplier circuit unit 38, the phase state generation unit 52 outputs a control clock to the shift register unit 50 every repetition cycle of the second clock. The total number of the control clocks input to the shift register unit 50 corresponds to the number of chips.

  The shift register unit 50 includes a total of 27 shift registers representing 27 bits and a plurality of coupling units that logically couple these registers. The shift register unit 50 performs a write process based on the control clock and the instruction content from the phase state generation unit 52, and the shift register unit 50 when the number of input control clocks reaches the number of chips. The state is output to the phase state generator 52 as a state value corresponding to the number of chips of the L2CM code (L2CL code).

  The phase state generation unit 52 outputs the input state value as a state value necessary for synchronizing the L2CM code (L2CL code) to the L2CM code generation unit 32 and the L2CL code generation unit 34, and further, a shift register unit 50, the instruction contents indicating the initial state are output and all shift registers are reset.

  The spread spectrum signal receiving apparatus 10 according to the present embodiment is basically configured as described above. Next, regarding the operation when receiving an L2 signal from an unillustrated artificial satellite, FIG. This will be described with reference to FIG. Here, the spread spectrum signal receiving apparatus 10 receives an L2 signal from the same artificial satellite, and the code generation unit 12 generates an L2CM code and an L2CM epoch signal based on the control content from the control unit 22. To do.

  When receiving the L2 signal from the artificial satellite, the spread spectrum signal receiving device 10 generates a baseband signal by removing a carrier wave component from the received L2 signal using a frequency converter and an amplifier not shown. Among the band signals, the first baseband signal is input to the correlator 14 while the second baseband signal is input to the correlator 16.

  The control unit 22 outputs code clock information indicating the frequency and phase of the L2CM code to the code generating unit 30 to the code clock generating unit 30, and the instruction content indicating the number of the artificial satellite and the number of chips of the L2C code Is output to the code state generation unit 36.

  On the other hand, the clock generator 40 outputs a first clock having a predetermined frequency to the code clock generator 30 and the multiplier circuit unit 38, respectively. The multiplier circuit unit 38 multiplies the frequency of the input first clock to generate a second clock, and outputs the second clock to the code state generator 36.

  The phase state generation unit 52 of the code state generation unit 36 calls the state value (see FIG. 4) of the initial state corresponding to the inputted satellite number from the table, and stores this state value in the shift register unit 50. Output. Thereby, each register of the shift register unit 50 is set to an initial state by inputting the state value.

  Next, the phase state generation unit 52 outputs a control clock to the shift register unit 50 at every repetition period of the input second clock. In this case, the phase state generation unit 52 outputs the control clock to the shift register unit 50 until the number of chips is reached.

  When the number of control clocks reaches the number of chips, the shift register unit 50 outputs the state of each register to the phase state generation unit 52 as a state value. The phase state generation unit 52 outputs the input state value to the L2CM code generation unit 32 as information indicating the phase state in the number of chips.

  On the other hand, based on the code clock information from the control unit 22 and the first clock from the clock generation unit 40, the code clock generation unit 30 uses the code clock having the L2CM code chip rate (511.5 kHz) as a repetition frequency. The signal is output to the L2CM code generator 32.

  Next, the L2CM code generator 32 outputs the input code clock signal to a shift register (not shown), and sets the state input from the code state generator 36. As a result, the state of the shift register transitions according to the code clock signal. Simultaneously with this state transition, the value of the shift register is also monitored. Here, when the end state of the designated satellite number is detected, the L2CM code generator 32 sets the shift register to the designated initial state, thereby repeating the code generation of 10230 chips. Is output to the correlation unit 14 as an L2CM code, while a control signal for controlling the integration process is output to the L2CM integration unit 18.

  The correlation unit 14 correlates the input first baseband signal and the L2CM code, and outputs the processing result to the L2CM integration unit 18 as a first correlation value. The L2CM integration unit 18 performs integration processing on the input first correlation value, and outputs the processing result to the control unit 22 as the first integration correlation value.

  The control unit 22 outputs again the control content indicating the phase and frequency of the L2CM code to the code generation unit 12 based on the input result of the first integration correlation unit.

  Although the above description has been for the case where the code generation unit 12 generates the L2CM code based on the control content from the control unit 22, the L2CL code can be generated in the same manner.

  In this case, an instruction content indicating the number of chips of the L2CL code is given from the control unit 22 to the code state generation unit 36 instead of the L2CM code. The control unit 22 gives the code state generation unit 36 with an instruction content indicating the number of chips of the L2CL code, while the control unit 22 sets the phase and frequency of the L2CL code to the code clock generation unit 30. Code clock information is provided.

  As a result, the state value is output from the code state generator 36 to the L2CL code generator 34, and the code clock signal is output from the code clock generator 30 to the L2CL code generator 34. The L2CL code generation unit 34 generates an L2CL code based on the code clock signal and the state value.

  Note that the L2CM code and the L2CL code described above are synchronized when a signal is transmitted from the artificial satellite, so that the code clock generator 30 can be shared.

  As described above, in the spread spectrum signal receiving apparatus 10 according to the present embodiment, the code state generation unit 36 is based on the artificial satellite number and the number of chips of the L2C code (L2CM code and L2CL code) from the control unit 22. Since the state value corresponding to the number of chips of the L2CM code and the L2CL code is output to the L2CM code generation unit 32 and the L2CL code generation unit 34, it is unnecessary to store the phase state of each artificial satellite regarding the L2C code as a table. Become. As a result, the memory capacity of the entire spread spectrum signal receiving apparatus 10 can be reduced.

  Further, the code state generation unit 36 sends a control clock to the shift register unit 50 based on the second clock from the multiplication circuit unit 38. In this case, the state value is output from the shift register unit 50 to the phase state generation unit 52 in a short time by setting the frequency of the second clock to a desired frequency, and the state value is output to the L2CM code generation unit 32 and the L2CL. It is possible to output to the code generator 34.

  Further, when each of the L2 signals is received from a plurality of artificial satellites, the spread spectrum signal receiving apparatus 10 includes a code generation unit 12, correlation units 14 and 16, integration units 18 and 20, and a despreading unit 22. A plurality of units may be arranged so that each despreading unit receives each L2 signal.

  In addition, a plurality of correlation units 14 and 16, integration units 18 and 20, and control unit 22 are arranged for one common code generation unit 12, and the L2C code included in each L2 signal is transmitted from this code generation unit 12 Each may be output.

  Further, in the spread spectrum signal receiving apparatus 10 according to the present embodiment, a code state generation unit 60 of a modification shown in FIG. 5 may be arranged instead of the code state generation unit 36 shown in FIG.

  In this case, a state holding unit 62 is arranged in the code state generation unit 60. In the state holding unit 62, a state holding table 70 is disposed as shown in FIG.

  The state holding table 70 is classified by a satellite number address 72 indicating each artificial satellite (for example, 37 artificial satellites) and 20 types of state addresses 74 indicating predetermined chips (chips for each 1023 chip) of the L2CM code. One 27-bit state value is stored for one address selected by each satellite number address 72 and each state address 74. In FIG. 6, the state values stored in the state holding table 70 are expressed as L2CM (i, j) (i = 1 to 37, j = 0 to 9718).

  In this case, the state holding table 70 extracts, for example, 20 state values from the state values 76 of the 10230 chips constituting the L2CM code at approximately equal chip intervals, and these state values are extracted as the state value L2CM ( i, j). In the state holding table 70, since the state value L2CM (i, j) is stored for every 1023 chips, the memory capacity is increased to 1/1023 times as compared with the case where the state value is stored for each chip. It is possible to reduce up to.

  Here, for example, when the control content in which the satellite number is 2 and the number of chips of the L2CM code is 1040 is input from the control unit 22 to the code state generation unit 60, the phase of the code state generation unit 60 The state generation unit 52 outputs these control contents to the state holding unit 62.

  The state holding unit 62 divides the input chip number (1040) by the chip resolution 1023 of the state holding table 70, and searches the state holding table 70 for a state address 74 that matches the number (1) indicating the quotient. At the same time, the satellite number address 72 corresponding to the input artificial satellite number (2) is searched. Thereby, the state holding unit 62 selects the state value L2CM (2, 1023) close to the input number of chips (1040) and the satellite number from the state holding table 70.

  In this case, since the selected state value L2CM (2, 1023) is a state value at the number of chips 1023, the state holding unit 62 receives the input number of chips (1040) and the selected state value L2CM (2 1023) and the number of chips (1023) (17 chips) are calculated, and information indicating the 17 chips and the state value L2CM (2, 1023) are output to the phase state generator 52.

  The phase state generation unit 52 outputs the input state value L2CM (2, 1023) as an initial state to the shift register unit 50, sets each register of the shift register unit 50 to an initial state, and corresponds to 17 chips. The 17 control clocks are sequentially output to the shift register unit 50 every cycle of the second clock.

  The shift register unit 50 outputs the generated state value to the phase state generation unit 52 after the 17th control clock is input. The phase state generation unit 52 determines that the input state value is the state value L2CM (2, 1040) in the number of chips 1040, and uses this state value L2CM (2, 1040) as the phase state of the L2CM code. Information to be output is output to the L2CM code generation unit 32.

  When storing the state value of the L2CL code in the state holding table 70, if the state value is stored for every 1023 chips, the memory capacity becomes 75 times that of the L2CM code. The memory capacity of the state holding table 70 can be reduced to 1/1023 times as compared with the case where the state value of each chip is stored.

  As described above, even when information regarding an arbitrary number of chips is input from the control unit 22 to the code state generation unit 36, the shift register unit 50 corresponds to the difference between the chip in the state holding unit 62 and the number of chips. By processing only the minutes, the state value is output to the phase state generation unit 52 in a shorter time, and the phase state generation unit 52 quickly outputs the state value to the L2CM code generation unit 32 and the L2CL code generation unit 34. It becomes possible to do.

  Further, in the multiplier circuit unit 38, the frequency of the second clock is set to, for example, five times the frequency of the first clock, and the state value L2CM (i, j) stored in the state holding table 70 is set every 5115 chips. If the state value is set, the memory capacity of the state holding table 70 is reduced by 1/5115 times compared with the case where the state value is stored for each chip without changing the calculation speed of the shift register unit 50. Is possible.

  Of course, the spread spectrum signal receiving apparatus according to the present invention is not limited to the above-described embodiment, and various configurations can be adopted without departing from the gist of the present invention.

It is a block diagram which shows the internal structure of the principal part of the spread spectrum signal receiver which concerns on this Embodiment. It is a block diagram which shows the internal structure of the code generation part of FIG. It is a block diagram which shows the internal structure of the code state production | generation part of FIG. It is explanatory drawing of a L2CM code and a L2CL code. It is a block diagram which shows the modification of the code state production | generation part of FIG. It is explanatory drawing of the state holding table arrange | positioned in the state holding part of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Spread spectrum signal receiver 12 ... Code generation part 14, 16 ... Correlation part 18 ... L2CM integration part 20 ... L2CL integration part 22 ... Control part 30 ... Code clock generation part 32 ... L2CM code generation part 34 ... L2CL code generation part 36, 60 ... code state generation unit 38 ... multiplication circuit unit 40 ... clock generation unit 50 ... shift register unit 52 ... phase state generation unit 62 ... state holding unit 70 ... state holding table 72 ... satellite number address 74 ... state address

Claims (5)

A code generator, a correlator connected to the code generator, and the integration section being connected to the code generator and the correlator unit, the integration unit and a control unit connected to the code generator With
The code generation unit has a code state generating unit that generates a status value of a desired number of chips P N code,
The code state generation unit includes a state holding unit including a state holding table that stores a state value related to each chip constituting the PN code,
The code generation unit generates a PN code for performing demodulation processing by despreading on the spread spectrum received signal input to the correlation unit based on the state value generated by the code state generation unit. Output to the correlator,
The correlation unit correlates the input received signal and the PN code, and outputs the processing result to the integration unit as a correlation value.
The integration unit performs integration processing of the input correlation value, and outputs the processing result to the control unit as an integration correlation value.
Wherein, based on the input the integrated correlation value, and controls the frequency and phase of the PN code generated by the code generator,
The code state generation unit compares the number of PN code chips input from the control unit with each of the chips in the state holding table, and selects a state value of a chip close to the number of chips, and this state Using the value as an initial value, the state value of the number of chips input from the control unit is generated based on the initial value,
The spread spectrum signal receiving apparatus according to claim 1, wherein the PN code is at least one of an L2CM code and an L2CL code . The spread spectrum signal receiving apparatus according to claim 1, wherein
The code state generation unit includes a shift register unit,
Wherein the code state generating unit, based on the number of chips before Symbol PN code are entered from the control unit, the spread spectrum signal receiving apparatus and outputs the state value from the shift register unit. The spread spectrum signal receiving apparatus according to claim 2,
The code generator has a clock pulse multiplier connected to the code state generator,
The spread spectrum signal receiving apparatus, wherein the clock pulse multiplication unit outputs a clock pulse having a desired frequency to the shift register unit. In the spread spectrum signal receiving apparatus according to claim 2 or 3 ,
Before Symbol Code state generation unit includes a switch number of taps of the PN code inputted from the control unit, by comparing the respective chips of the state holding table, select the status value of the chip closer to the number of chips The state value is output to the shift register unit as an initial value,
The shift register unit outputs a state value of the number of chips input from the control unit based on the input initial value. In the spread spectrum signal receiving apparatus according to any one of claims 1 to 4,
The spread spectrum signal receiving device includes a plurality of the correlation unit and the integration unit,
The code generation unit generates a PN code corresponding to a PN code of a plurality of reception signals subjected to spectrum spreading.

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