JP4243473B2 - FIR digital filter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an FIR digital filter, and more particularly to a reduction in the circuit scale of an FIR (Finite Impulse Response) digital filter.
[0002]
[Prior art]
Conventionally, in the FIR digital filter, as shown in FIG. 4, delay elements 200 to 20 m (m is a positive integer), multipliers 210 to 21 n (n is a positive integer, n = m + 1), and an adder 220. It is comprised from -220m.
[0003]
In the above FIR digital filter, a plurality of delay elements 200 to 20m are connected in series between a data signal input terminal and a data signal output terminal, and a tap is formed for each connection.
[0004]
Each tap is connected to a plurality of multipliers 210 to 21n for multiplying tap coefficients H0 to Hn, and output terminals of the multipliers 210 to 21n are connected to a plurality of adders 220 to 220m, and the sum of the multiplication results. Is calculated and output (for example, see Patent Document 1).
[0005]
[Patent Document 1]
JP 2001-177378 A (2nd and 3rd pages, FIG. 5)
[0006]
[Problems to be solved by the invention]
In the conventional FIR digital filter described above, when the number of taps of the FIR digital filter is increased in order to obtain good characteristics, the number of multipliers equal to the number of taps and the number of adders one less than the number of taps are obtained. Is required.
[0007]
For example, in the case of a 1000 tap digital filter, 1000 multipliers and 999 adders are required. When a multi-tap filter is configured, a large number of multipliers and adders are required as described above, so that the circuit scale becomes enormous and it is very difficult to make an integrated circuit.
[0008]
Accordingly, an object of the present invention is to provide an FIR digital filter that can solve the above-described problems and reduce the circuit scale.
[0009]
[Means for Solving the Problems]
The FIR digital filter according to the present invention includes a first clock that is m times (m is a positive integer) an input clock signal obtained by sampling an input data signal, and a second clock that is phase-controlled with respect to the input clock signal. A clock generator that generates a tap output signal by performing calculation processing of a predetermined filter coefficient on the input data signal based on the first clock, and the product-sum calculator And a first latch that samples the tap output signal from the second clock ,
The product-sum calculator includes a delay element that delays an input signal by (m−1) stages, a first selector that switches between an output signal of the delay element and the input data signal, and a memory that stores a tap coefficient signal in advance. A multiplier that multiplies the tap coefficient signal output from the memory and the output signal from the delay element, an accumulator that sequentially accumulates and outputs the multiplication result of the multiplier, and the delay element. And a second latch that samples the output signal of the second clock with the second clock,
While outputting the output of the accumulator as the tap output signal,
The accumulator includes an adder that adds an output signal from the multiplier and the tap output signal, a second selector that switches an output signal from the multiplier and an addition result from the adder, And a latch for holding the output signal of the second selector at the first clock .
[0010]
That is, the FIR (Finite Impulse Response) digital filter of the present invention performs phase control on the first clock and the input clock signal that are m times (m is a positive integer) from the input clock signal obtained by sampling the input data signal. A clock generator for generating a second clock, a sum-of-products calculator for calculating a predetermined filter coefficient on the input data signal based on the first clock, and an output signal of the sum-of-products calculator And a latch for sampling with the second clock.
[0011]
The product-sum operation unit includes a delay element that delays an input signal by (m−1) stages, a selector that switches an output signal and an input data signal of the delay element, a switching control unit that switches the selector, a tap coefficient A memory for storing the signal, a memory control unit for controlling the output of the memory, a multiplier for multiplying the tap coefficient signal output from the memory by the output signal from the delay element, a tap coefficient signal, One accumulator that sequentially accumulates and outputs the result of multiplying the delayed output signal and a latch for sampling the output signal from the delay element at the input clock frequency are provided.
[0012]
The accumulator includes one adder for adding the output signal from the multiplier and the tap output signal output from the latch, a selector for switching between the output signal from the multiplier and the addition result from the adder, A switching control unit for switching the selector and a latch for holding an output signal of the selector.
[0013]
With the configuration as described above, the FIR digital filter of the present invention can be greatly reduced in circuit scale. Therefore, the FIR digital filter can be realized by an integrated circuit having a smaller scale than the conventional one, and the FIR digital filter has good characteristics. It is also possible to maintain proper characteristics.
[0014]
The FIR digital filter according to the present invention can be realized by multiplying the clock by m times when an m-tap filter is configured. That is, the FIR digital filter of the present invention can realize a multi-tap filter by increasing the multiple m of the input clock in the clock generator when increasing the tap number. In this case, m is the number of taps. For example, if m = 2000, a filter having 2000 taps can be realized.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an FIR (Finite Impulse Response) digital filter according to an embodiment of the present invention. In FIG. 1, the FIR digital filter according to the embodiment of the present invention samples an input data signal d1 inputted from the data signal input terminal 12 and m times the input clock signal a1 inputted from the clock signal input terminal 11. b1 and a clock generator 21 that generates clocks c1 and h1 whose phases are controlled by the input clock signal a1, a sum-of-products calculator 31 that performs filter calculation processing, and a tap output signal that is output from within the sum-of-products calculator 31 and a latch 42 for sampling g1 at an input clock frequency (clock c1).
[0016]
The product-sum calculator 31 delays the input signal by (m−1) stages, a selector 51 that switches between the output signal e1 and the input data signal d1 of the delay element 61, and switching that switches the selector 51. The control unit 101, the memory 112 that stores the tap coefficient signal f1, the memory control unit 111 that controls the output of the memory 112, the tap coefficient signal f1 output from the memory 112 and the output signal e1 from the delay element 61 1 multiplier 71, one accumulator 91 that sequentially accumulates and outputs the result of multiplying the tap coefficient signal f1 and the delayed output signal e1, and the delay element 61 And a latch 41 for sampling the output signal e1 at the input clock frequency (clock h1).
[0017]
The accumulator 91 includes one adder 81 that adds the output signal m1 from the multiplier 71 and the tap output signal g1 output from the latch 43, and the output signal m1 from the multiplier 71 and the adder 81. It comprises a selector 52 for switching the addition result n1, a switching control unit 102 for switching the selector 52, and a latch 43 for holding the output signal q1 of the selector 52.
[0018]
FIG. 2 is a timing chart showing the operation of the FIR digital filter according to the embodiment of the present invention. FIG. 2 shows the timing in the case of m = 4 as an example. The operation of the FIR digital filter according to the embodiment of the present invention will be described with reference to FIG. 1 and FIG.
[0019]
An input clock signal a1 is input from the clock signal input terminal 11, and this input clock signal a1 is a clock for sampling the input data signal d1 from the data signal input terminal 12. Therefore, the data signal d1 input from the data signal input terminal 12 is sampled by the input clock signal a1. The timing relationship between the input clock signal a1 and the input data signal d1 is as shown in FIG.
[0020]
The clock generator 21 outputs the input clock signal a1 as m times the clock b1, and the product-sum operation unit 31 performs the filter processing based on the m times clock b1. For example, the timing relationship between the quadruple clock b1 output from the clock generator 21 and the input clock signal a1 when m = 4 is as shown in FIG.
[0021]
The clock generator 21 supplies the clock h1 to the latch 41 and supplies the clock c1 to the latch 42. The clocks c1 and h1 are clocks having the same sampling frequency as that of the input clock signal a1, but the phase of the input clock signal a1 is adjusted in order to synchronize the timing with the data signals input to the latches 41 and 42. It is generated under control and output to the respective latches 41 and 42.
[0022]
The selector 51 selectively outputs the input data signal d 1 and the data signal e 1 output from the delay element 61 delayed by (m−1) stages, and supplies it to the delay element 61. In the switching control unit 101, the switching control signal r <b> 1 that outputs a high pulse is supplied to the selector 51 once in m times, and the selector 51 is switched. For example, the timing relationship among the delay element 61, the switching control unit 101, and the selector 51 when m = 4 is as shown in FIG.
[0023]
In FIG. 2, the switching control signal r1 that is the output of the switching control unit 101 is output as a high pulse once every four times. The selector 51 selects the input data signal (A, B, C, D) when the switching control signal r1 is a high pulse, and the output data [(X, Y) of the delay element 61 when the switching control signal r1 is a low pulse. , Z), (Y, Z, A), (Z, A, B), (A, B, C)] are selected and output.
[0024]
The output data k1 of the selector 51 is input to the delay element 61, delayed by three stages, and then input to the selector 51 again. Thus, the data processing between the selector 51 and the delay element 61 is repeated cyclically, and the data signal e1 output from the delay element 61 is supplied to the latch 41.
[0025]
As shown in FIG. 2, the clock h1 used for the latch 41 is phase-controlled by the clock generator 21 in order to synchronize the timing with the data signal e1 output from the delay element 61. Is output. Therefore, the data signal e1 is output to the data signal output terminal 14 through the latch 41 as the data signal s1 (W, X, Y, Z in this case) sampled at the same frequency as the input clock signal a1.
[0026]
The memory control unit 111 controls the output timing from the memory 112 and outputs the tap coefficient signal f1. The tap coefficient signal f1 corresponds to the tap coefficients H0 to Hn of the conventional example shown in FIG. All the tap coefficients are stored in the memory 112, output with a clock b 1 multiplied by m under the control of the memory control unit 111, and supplied to the multiplier 71.
[0027]
Further, since the data signal e1 output from the delay element 61 is also supplied to the multiplier 71, the multiplier 71 is output in synchronization with the output from the delay element 61. The tap coefficient signal f1 is multiplied. For example, when m = 4, the input timing to the multiplier 71 is as shown in FIG.
[0028]
In FIG. 2, the tap coefficient signal f1 is the same as the timing of the four data signals e1 output from the delay element 61 [here, (X, Y, Z, A)], and is equivalent to four taps ( Here, H3 to H0) are output and are multiplied in order by X * H3, Y * H2, Z * H1, and A * H0. The result m1 by the multiplier 71 is output as Mb0 to Mb3 as shown in FIG.
[0029]
One of the outputs from the multiplier 71 is directly supplied to the selector 52. The other output from the multiplier 71 is supplied to the adder 81. The adder 81 adds the output m1 from the multiplier 71 and the tap output signal g1 output from the latch 43, and supplies the addition result to the selector 52.
[0030]
The switching control unit 102 switches the selector 52 once every m times as a switching control signal p1 that outputs a high pulse. For example, when m = 4, the timing relationship among the latch 43, the adder 81, the switching control unit 102, and the selector 52 is as shown in FIG.
[0031]
In FIG. 2, the switching control signal p <b> 1 that is the output of the switching control unit 102 outputs a high pulse once every four times. The selector 52 selects the output data m1 (Mb0, Mc0, Md0, Me0) of the multiplier 71 when the switching control signal p1 is a high pulse, and the output data n1 of the adder 81 when the switching control signal p1 is a low pulse. (Ab1 to Ab3, Ac1 to Ac3, Ad1 to Ad3) are selected and output.
[0032]
The output data q1 of the selector 52 is delayed by one stage by the latch 43 and then input to the adder 81 again. As described above, the switching control unit 102, the adder 81, the selector 52, and the latch 43 constitute an accumulator 91. The accumulator 91 sequentially accumulates and outputs the multiplied results. ing.
[0033]
The accumulator 91 selects the output data of the multiplier 71 by the selector 52, thereby clearing the accumulated result so far and starting the successive accumulation again as the initial value of accumulation. The arithmetic processing or data processing up to this point is configured as a product-sum arithmetic unit 31 by the selector 51 to accumulator 91.
[0034]
As shown in FIG. 2, the clock c1 used for the latch 42 is input by the clock generator 21 in order to synchronize the timing with the tap output signal g1 output from the accumulator 91 of the product-sum calculator 31. The clock signal a1 is phase-controlled and output. Therefore, the tap output signal g1 is output to the filter signal output terminal 13 through the latch 42 as the tap output signal t1 (here, Az3, Aa3, Ab3, Ac3) sampled at the same frequency as the input clock signal a1. .
[0035]
As described above, the FIR digital filter according to the embodiment of the present invention can greatly reduce the circuit scale. For example, in the case of a conventional FIR digital filter having 1000 taps, 1000 multipliers and 999 adders are required, whereas in the FIR digital filter according to the embodiment of the present invention, the clock multiplied by m is used. Is set to 1000 times, one multiplier 71 and one accumulator 91 are sufficient. Therefore, the circuit scale can be greatly reduced, and good characteristics of the FIR digital filter can be maintained.
[0036]
Furthermore, in the FIR digital filter according to the embodiment of the present invention, when the number of taps is increased, the multi-tap filter can be realized by increasing the multiple m of the input clock signal a1 in the clock generator 21. . That is, m is the number of taps. For example, if m = 2000, a filter having 2000 taps can be realized.
[0037]
FIG. 3 is a block diagram showing the configuration of the FIR digital filter according to one embodiment of the present invention. In FIG. 3, the FIR digital filter according to one embodiment of the present invention adds product-sum arithmetic units 31 to 35 connected in series in five stages and tap output signals g1 to g5 from the product-sum arithmetic units 31 to 35. The adder 121, the clock generator 21, and a latch 42 are included. Since the operation of the clock generator 21 is the same as that of the above-described embodiment of the present invention, description of the operation is omitted.
[0038]
The input data signal d1 input from the data signal input terminal 12 is supplied to the first-stage product-sum operation unit 31, and a data signal s1 is output from the product-sum operation unit 31 by the operation of the product-sum operation unit 31 described above. Then, it is supplied to the product-sum calculator 32 at the second stage. Thereafter, similarly to this operation, the operation is performed by the third-stage product-sum operation unit 33, the fourth-stage product-sum operation unit 34, and the fifth-stage product-sum operation unit 35.
[0039]
The tap output signals g1 to g5 output from the product-sum calculators 31 to 35 are supplied to the adder 121 in order to calculate a final accumulation result. As described above, the addition result u1 output from the adder 121 is output to the filter signal output terminal 13 through the latch 42 as the tap output signal t1 sampled at the same frequency as the input clock signal a1.
[0040]
In this embodiment, even when the frequency of the clock signal multiplied by m is limited in the digital filter, the circuit scale can be greatly reduced by connecting the product-sum calculators 31 to 35 in series, in comparison with the conventional digital filter. This is an example showing that it is possible. For example, in the case of 1000 taps in the conventional FIR digital filter, 1000 multipliers and 999 adders are required, whereas in this embodiment, the maximum clock in the product-sum calculators 31 to 35 is required. Even if the frequency is limited to 200 times the input clock, only five multipliers and five accumulators and one adder 121 in the product-sum calculators 31 to 35 are required. Therefore, the circuit scale can be reduced, and good characteristics of the FIR digital filter can be maintained.
[0041]
Further, when increasing the number of taps, a multi-tap filter can be achieved by connecting n stages of product-sum calculators. That is, when the maximum clock frequency is limited in the digital filter as described above, m × n is the number of taps. For example, if m = 200 and n = 10, a filter with 2000 taps can be realized. .
[0042]
As described above, in the FIR digital filter according to the present embodiment, the circuit scale can be greatly reduced, and good characteristics of the FIR digital filter can be maintained.
[0043]
Further, in the FIR digital filter according to the present embodiment, when the number of taps is increased, a multiple tap filter can be realized by increasing the multiple m of the input clock signal a1 in the clock generator 21. In this case, since m is the number of taps, for example, if m = 2000, a filter with 2000 taps can be realized.
[0044]
【The invention's effect】
As described above, according to the present invention, the first clock obtained by multiplying the input clock signal obtained by sampling the input data signal (m is a positive integer) and the second clock in which the phase control is performed on the input clock signal, A clock generator that generates a tap, a product-sum calculator that performs a predetermined filter coefficient calculation process on the input data signal based on the first clock and outputs a tap output signal, and a tap from the product-sum calculator By providing the latch that samples the output signal with the first clock, an effect that the circuit scale can be reduced is obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an FIR digital filter according to an embodiment of the present invention.
FIG. 2 is a timing chart showing the operation of the FIR digital filter according to the embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of an FIR digital filter according to an embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of a conventional FIR digital filter.
[Explanation of symbols]
11 Clock signal input terminal 12 Data signal input terminal 13 Filter signal output terminal 14 Data signal output terminal 21 Clock generators 31 to 35 Multiply-add calculators 41 to 43 Latches 51 and 52 Selector 61 Delay element 71 Multiplier 81 Adder 91 Cumulative Calculators 101 and 102 Switching control unit 111 Memory control unit 112 Memory 121 Adder

Claims (6)

A clock generator that generates a first clock that is m times (m is a positive integer) an input clock signal obtained by sampling the input data signal and a second clock that is phase-controlled with respect to the input clock signal; A product-sum calculator that performs a calculation process of a predetermined filter coefficient on the input data signal based on the first clock and outputs a tap output signal; and a tap output signal from the product-sum calculator have a first latch for sampling by 2 clocks,
The product-sum calculator includes a delay element that delays an input signal by (m−1) stages, a first selector that switches between an output signal of the delay element and the input data signal, and a memory that stores a tap coefficient signal in advance. A multiplier that multiplies the tap coefficient signal output from the memory and the output signal from the delay element, an accumulator that sequentially accumulates and outputs the multiplication result of the multiplier, and the delay element. And a second latch that samples the output signal of the second clock with the second clock,
While outputting the output of the accumulator as the tap output signal,
The accumulator includes an adder that adds an output signal from the multiplier and the tap output signal, a second selector that switches an output signal from the multiplier and an addition result from the adder, And a latch for holding the output signal of the second selector at the first clock . 2. The FIR digital filter according to claim 1, further comprising first switching control means for switching the first selector based on the first clock. 3. The FIR digital filter according to claim 1, further comprising memory control means for controlling output of the tap coefficient signal from the memory based on the first clock. 4. The FIR digital filter according to claim 1, further comprising second switching control means for switching the second selector based on the first clock. 5. The FIR digital filter according to claim 1, wherein a plurality of stages of the product-sum calculators are connected in series. 6. The FIR digital filter according to claim 1, wherein when the number of taps is increased, a multiple m of the input clock signal in the clock generator is increased.

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