JP4197587B2 - Data processing apparatus and data reading method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data processing apparatus and a data reading method including a storage device in which data is recorded in a manner in which a logical address arrangement used for a read request and a physical address arrangement for storing data are different.
[0002]
[Prior art]
In a data processing system equipped with a disk drive, as a method for speeding up sequential reads to a disk, a pre-read processing technique in which data in an area following an address for which a read request has been made is previously read onto a cache memory. Are known. This prefetching process is disclosed in, for example, Japanese Patent Publication No. 7-76941.
[0003]
At this time, in the conventional read-ahead technique described above, in the magnetic disk device or the like, even if the logical address at the time of the read request is continuous, the actual data is not arranged in the order indicated by the address. There is a problem that the above-described prefetching process does not function sufficiently.
[0004]
In other words, in a system that requires conversion to the physical location (physical address) where the data actually exists, the read-requested area (logical address) is logically continuous. However, there are cases where they are physically discontinuously arranged, and it is impossible to prefetch the entire area requested to be read. For this reason, since the access to the disk is random access, there is a problem that the prefetching effect cannot be obtained even if the prefetching is simply performed according to the physical arrangement, and thus the prefetching process described above does not function sufficiently. .
[0005]
[Problems to be solved by the invention]
As described above, in the conventional read-ahead technology, even if the logical address at the time of the read request is continuous, the actual data is not arranged in the order indicated by the address. There was a problem that the function of could not be fully demonstrated.
[0006]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data processing apparatus and a data prefetching method capable of efficiently performing a prefetching process by reducing the total number of read instructions for prefetching.
[0007]
Another object of the present invention is to provide a data processing apparatus and a data prefetching method that can efficiently perform disk access processing by reducing the total number of read instructions for the disk.
[0008]
[Means for Solving the Problems]
The present invention calculates a physical address for all areas requested to be read, and reads data that is physically adjacent addresses or data that is physically located in an address area and reads them collectively It is characterized by having a function.
[0009]
Furthermore, in the present invention, when prefetching processing is performed, physical addresses are calculated in advance for all areas where prefetching processing is to be performed. It is characterized by a processing function for reading data in the address area collectively.
[0010]
That is, according to the present invention, a data processing apparatus comprising a disk drive for controlling access to at least one disk and a cache memory for temporarily storing data read from the disk drive is designated by a read / write request. An address conversion map indicating the correspondence between the logical address to be read and the physical arrangement on the disk, and whether the request is accepted and prefetching is performed based on the continuity of a plurality of logical addresses requested to be read A prefetch determination unit that determines whether or not, and when performing prefetching according to the determination of the prefetch determination unit, the address conversion map is referred to for n consecutive logical addresses including the plurality of logical addresses, Check the physical layout of all the address areas to be, and when the layout interval is within the set range Pre-read area determination means for determining all physical address areas existing in the set range as pre-read areas, and read access to the disk drive according to the pre-read area determined by the pre-read area determination means, from the disk drive Access control means for reading data in each area according to the pre-read area all at once .
[0011]
According to another aspect of the present invention, there is provided a data prefetching method for a data processing apparatus having a cache for temporarily storing data read from a disk drive, wherein the continuity of a plurality of logical addresses requested to be read is maintained when a read request is made to the disk drive. Whether or not prefetching is performed, and when it is determined to perform prefetching, the physical arrangement of the n consecutive logical addresses including the plurality of logical addresses is examined, and the arrangement interval examined is When it is within the set range, all physical address areas existing within the set range are determined as pre-read areas, and read access is made to the disk drive according to the determined pre-read areas, and the pre-read areas from the disk drive The data of each area according to the above is read at once .
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
First, a first embodiment of the present invention will be described with reference to FIGS.
[0015]
In the first embodiment, when a read request is issued from the host device, it is determined whether or not prefetching is to be performed. When prefetching is performed, an address to be prefetched is referred to by referring to the address conversion map. Realizes batch read-ahead processing of multiple areas by examining the physical layout of all areas and reading multiple physical address areas collectively so that the number of read requests to the disk is minimized is doing.
[0016]
FIG. 1 is a block diagram showing the main components of the data processing apparatus according to the first embodiment of the present invention, which includes a host device 10, a disk controller 20, a disk drive 30, and the like.
[0017]
The disk controller 20 includes a disk access control unit 21, an address conversion map 22, a cache (cache memory) 23, a prefetch processing unit 24, and the like.
[0018]
The disk access control unit 21 receives a read request, a write request, and the like from the host device 10 and performs control such as disk access control and cache 23 allocation. When a read request is received, a physical address (location where data is actually placed) corresponding to the requested logical address is calculated with reference to the address conversion map 22. If the data of the requested area is on the cache 23, the hit data is returned to the host device 10, otherwise (if not hit) the data of the physical address obtained on the address translation map 22 is stored in the disk. An operation of reading from the drive 30 onto the cache 23 is performed. Further, when a read request is received, the prefetch processing unit 24 is activated to determine whether or not to prefetch.
[0019]
The address conversion map 22 is composed of an address conversion table that takes a correspondence between a logical address and a physical address, and is referred to by the disk access control unit 21 at the time of read / write access, and physically (disk The above address arrangement is recognized. A specific configuration example of the address conversion map 22 will be described later with reference to FIG.
[0020]
The prefetch processing unit 24 is activated by the disk access control unit 21 at the time of a read request from the host device 10, and determines whether to perform prefetching and performs actual prefetching processing. There are various methods for determining whether to perform prefetching. Here, when there is a read request (recognized as sequential read) in a continuous area (logical address) two or more times, prefetching is performed. If it is not, look ahead is not performed.
[0021]
If it is determined that prefetching should be performed, an operation is performed to read the corresponding data from the disk drive 30 and place it on the cache 23 for consecutive n logical addresses. In the operation example in this embodiment, the corresponding data is read from the disk drive 30 for eight consecutive logical addresses (see LA “2” to “9” in FIG. 3) where n is “8”. Is stored in the cache 23. At this time, with respect to all eight logical addresses to be prefetched, the physical arrangement on the disk where the data is placed is checked with reference to the address conversion map 22 (see hatching in FIG. 4), and the state of the arrangement Thus, a plurality of physical address areas are read together (collectively) so as to minimize the number of read requests to the disk drive 30 (see the → marks in FIG. 5).
[0022]
FIG. 2 is a flowchart showing the procedure of the prefetch process in the embodiment.
[0023]
FIG. 3 is a diagram showing a correspondence example of logical-physical addresses for explaining the configuration of the address conversion map 22, where LA is a logical address included in a read command from the host device 10, and PA is a physical address on the disk. It is. In this example, when a read command for two logical addresses “0” and “1” having consecutive logical addresses is received from the host device 10, the subsequent logical addresses “2” to “9” are used as prefetch targets, and address conversion is performed. The map 22 is used to calculate addresses on each physical, and whether there are physically adjacent addresses from these address arrays, or whether they are physically close (for example, within two addresses). The conditions for enabling batch reading such as the above are checked, and data is read collectively for all areas included in the conditions.
[0024]
FIG. 4 is a diagram showing a state of physical arrangement on the pre-read target disk in the logical-physical address correspondence shown in FIG. 3, and here, the logical address (LA) shown in FIG. ) About "2" to "9", the data positions (physical arrangement states) are indicated by hatching.
[0025]
FIG. 5 is a diagram showing a prefetch instruction issue location (illustration → mark) for the address arrangement of FIGS. 3 and 4 described above. In this example, the physical addresses “8” to “11” corresponding to the logical addresses “5”, “7”, “2”, and “8” and the logical addresses “3”, “4”, “9” The data of the physical addresses “20” to “23” corresponding to “” is read together (collectively).
[0026]
Here, the operation in the first embodiment of the present invention will be described with reference to the respective drawings.
[0027]
In the first embodiment, the physical address allocation state of a plurality of physical address areas corresponding to the logical address area to be prefetched is checked, and a read request to the disk drive is issued. A plurality of physical address areas are collectively read so as to minimize the number of times.
[0028]
The prefetch processing unit 24 is activated by the disk access control unit 21 at the time of a read request from the host device 10, and determines whether to perform prefetching and performs actual prefetching processing. Here, when there is a read request (recognized as sequential read) in a continuous area (logical address) two or more times, it is determined that prefetching should be performed. Otherwise, prefetching is not performed. (FIG. 2, step A11).
[0029]
As a specific example, here, when there is a read request for sequential logical addresses “0” and “1” in the order of the addresses, the prefetch processing unit 24 recognizes that the read is sequential and prefetches. Processing is started, and prefetch processing is performed on the data of logical addresses “2” to “9” following logical addresses “0” and “1” subjected to the prefetch determination.
[0030]
First, the prefetch processing unit 24 physically assigns the addresses (logical addresses “2” to “9”) to all locations on the disk (on the physical addresses) for all areas to be prefetched. Whether it is arranged or not is checked in advance with reference to the address conversion map 22 (step A12 in FIG. 2).
[0031]
FIG. 3 shows an example of the correspondence between the areas (logical addresses “2” to “9”) to be prefetched in the address conversion map 22 at this time and the physical addresses, and the correspondence between the logical and physical addresses. In FIG. 4, the physical arrangement on the pre-read target disk is shown by hatching in FIG.
[0032]
From this physical address arrangement, it is determined how to read the area distributed by one read instruction (steps A13 to A17 in FIG. 2). Here, it is determined that prefetching should be performed on data in a continuous area and nearby data whose physical addresses are not separated by 2 (i = 2) or more. It is assumed that it is performed in batch with instructions.
[0033]
In the case of the example shown in FIG. 4, the read command is as shown by the → mark in FIG. That is, since the data at the logical address “6” is arranged at the physical address “5” and there is no data to be prefetched in the vicinity (a range that is not two or more physical addresses away), the size from the physical address “5” 1 (1 block data) prefetch instruction is issued (steps A13, A14, A16 in FIG. 2).
[0034]
The data of logical addresses “5”, “7”, “2”, “8” are arranged at physical addresses “8”, “9”, “10”, “11”, respectively, and these data are physical Therefore, a prefetch command of size 4 (4 block data) is issued from the physical address “8” (steps A13 to A16 in FIG. 2).
[0035]
Further, the data of the logical addresses “3”, “4”, and “9” are arranged at the physical addresses “20”, “22”, and “23”, respectively. Here, the data of the physical address “20” is close to the physical addresses “22” and “23” (a range not separated by 2 or more in the physical address), and therefore the size is 4 (4 block data) from the physical address “20”. Is issued (steps A13 to A16 in FIG. 2). In this case, the processing related to the data corresponding to the physical address “21” is useless, but it is more efficient to execute the nearby data in one instruction than to issue the prefetch instruction twice.
[0036]
In this way, by batching instructions for prefetching for consecutive areas, the total number of read instructions for prefetching can be reduced, and prefetching processing can be performed efficiently.
[0037]
In the above-described embodiment, by limiting the number of read requests to the disk drive and dynamically adjusting the amount of data prefetched from the disk drive, the number of prefetch requests increases, A state where an excessive load is applied can be avoided. In addition, by issuing read instructions to the disk drive in the order of physical arrangement on the disk, the amount of head movement on the disk drive can be reduced and the seek operation can be performed quickly and smoothly.
[0038]
Next, a second embodiment of the present invention will be described with reference to FIGS.
[0039]
In the second embodiment, in a system having a disk drive and a cache, a plurality of read requests issued from the host side until one read request processing to the disk is completed. On the other hand, the physical data arrangement (physical address arrangement) of each of the plurality of logical addresses requested to be read is checked, and the read request to the disk is determined from the arrangement state within a preset allowable range. In order to minimize the number of times, a function of reading a plurality of physical areas together is realized.
[0040]
FIG. 6 is a block diagram showing the main components of the data processing apparatus according to the second embodiment of the present invention, and includes a host device 1, a disk controller 2, a disk drive 3, and the like.
[0041]
The disk controller 2 includes an access control unit 2a, an address conversion map 2b, a buffer memory 2c, a disk access processing unit 2d, and the like.
[0042]
The access control unit 2a receives a read request, a write request, etc. from the host device 1 and controls disk access. With respect to the read request at this time, the address conversion map 2b is referred to for all the read requests issued from the host apparatus 1 until one read request processing to the disk drive 3 is completed. When the address (logical address) of each read request is converted into a physical address indicating the location where the data is actually placed, and the physical address (on the medium) is checked for address allocation, and the addresses are physically adjacent Or, when the physical arrangement is close (for example, within two addresses), the data in all these address areas are read together (collectively).
[0043]
Similar to the first embodiment, the address conversion map 2b constitutes a table indicating the correspondence between logical addresses and physical addresses, and is referred to by the access control unit 2a at the time of read / write access. The physical (medium) address arrangement is recognized.
[0044]
FIG. 7 is a flowchart showing a procedure of batch read processing in the second embodiment of the present invention.
[0045]
Here, the operation in the second embodiment of the present invention will be described with reference to FIG. 6 and FIG.
[0046]
The access control unit 2a of the disk controller 2 stacks the read requests issued from the host device 1 until one read request processing to the disk provided in the disk drive 3 is completed, and For all, referring to the address conversion map 2b, the address (logical address) of each read request is converted into a physical address indicating the location where the data is actually placed, and the physical (on the medium) is converted. The address arrangement is examined (steps B11 and B12 in FIG. 7). Here, when the arrangement is physically adjacent or physically adjacent (for example, within two addresses), the data in all these address areas are read together (collectively). (Steps B13, B14, B15 in FIG. 7). The batch read process at this time is substantially the same as the operation described with reference to FIGS. 3 to 5 in the first embodiment, and can be easily understood from the operation description of the first embodiment. Therefore, detailed description of the operation is omitted here.
[0047]
In this way, the batch of read instructions for the continuous areas can be reduced, so that the total number of read instructions for the disk can be reduced, whereby the disk access processing can be performed efficiently.
[0048]
【The invention's effect】
As described above in detail, according to the present invention, the number of read instructions for prefetching can be reduced by batching instructions for prefetching for continuous areas, thereby enabling efficient prefetching processing. it can.
[0049]
Also, by batching the read commands for the continuous areas, the total number of read commands for the disk can be reduced, and the disk access process can be performed efficiently.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a data processing device according to a first embodiment of the present invention.
FIG. 2 is a flowchart showing a procedure of prefetch processing in the first embodiment.
FIG. 3 is a view showing an address correspondence example of an address conversion map in the first embodiment.
FIG. 4 is a diagram showing a physical arrangement state to be prefetched in the first embodiment.
FIG. 5 is a diagram showing a prefetch instruction issue location in the first embodiment.
FIG. 6 is a block diagram showing a configuration of a data processing device in a second embodiment of the present invention.
FIG. 7 is a flowchart showing a procedure of batch read processing according to the second embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Host apparatus 2 ... Disk controller 2a ... Access control part 2b ... Address conversion map 2c ... Cache (cache memory)
2d ... Address conversion map 3 ... Disk drive 10 ... Host device 20 ... Disk controller 21 ... Access control unit 22 ... Address conversion map 23 ... Cache (cache memory)
24 ... Prefetch processing unit 30 ... Disk drive

Claims (2)

In a data processing apparatus comprising: a disk drive for controlling access to at least one disk; and a cache memory for temporarily storing data read from the disk drive.
An address conversion map indicating a correspondence between a logical address designated by a read / write request and a physical arrangement on the disk;
Prefetch determination means for accepting the request and determining whether to perform prefetch based on continuity of a plurality of logical addresses requested to be read at the time of a read request;
When performing prefetching according to the determination of the pre-read determination means, for n consecutive logical address including a plurality of logical addresses, referring to the address translation map, subject to address space all physical addresses of the look-ahead Check the continuity of the arrangement, determine whether or not the arrangement interval is within the set allowable range for the non-contiguous address arrangement portion, and assign all the physical address areas within the allowable range to the continuous address arrangement. As a series of read-ahead areas to read together with the partial address area,
Prefetching area judging means for judging a prefetching area;
According to the prefetch area determined by the prefetch area determination means, the disk drive is read-accessed, and access control means for reading all data of the prefetch area from the disk drive at once,
A data processing apparatus comprising: In a data prefetching method of a data processing apparatus having a cache for temporarily storing data read from a disk drive,
The data processing device includes:
An address conversion map indicating a correspondence between a logical address designated by a read / write request and a physical arrangement of the disk drive on the disk;
Determining whether to perform prefetching based on the continuity of a plurality of logical addresses requested to be read at the time of a read request to the disk drive;
When you make a decision to prefetch,
For n consecutive logical addresses including the plurality of logical addresses, referring to the address conversion map, the continuity of the physical address arrangement of all address areas to be prefetched is examined,
For non-contiguous address arrangement parts, determine whether the arrangement interval is within the set allowable range,
Decide the prefetch area as a series of prefetch areas to read all physical address areas within the allowable range together with the address area of the continuous address arrangement part ,
According determined lookahead region, the perform read access to the disk drives, data prefetching wherein the reading from the disk drive together all the data of the read-ahead region at a time.

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