JP4162666B2 - Synchronization signal detection circuit and disk reproducing apparatus - Google Patents

Description

  The present invention relates to a synchronization signal detection circuit and a disk reproducing device, and is particularly suitable for use when intersymbol interference occurs in a signal waveform.

A disk reproduction device such as a CD drive or a DVD drive is provided with a synchronization signal detection circuit for detecting a synchronization signal from a reproduction signal. Here, the synchronization signal often has a longer signal period than a normal signal. In this case, the synchronization signal detection circuit slices the reproduction signal at zero level to detect the signal width, The longest signal width period is detected as the synchronization signal period. Note that the inventions described in Patent Documents 1 and 2 below are known as synchronization signal detection circuits.
JP 7-326139 A JP-A-8-138328

  However, when the synchronization signal is detected by slicing at zero level as described above, the synchronization signal period cannot be correctly detected when intersymbol interference occurs in the reproduced signal waveform, particularly when a high-density disk is handled. Problem arises. In other words, when intersymbol interference occurs in the reproduced signal, a signal width longer than the signal width that should appear originally is detected by the slice at zero level, and therefore a period that is not a synchronization signal period is erroneously detected as a synchronization signal period Can happen.

  On the other hand, a method of slicing the playback signal at a level different from the zero level and detecting the synchronization signal is conceivable. However, in this case, if an offset or asymmetry occurs in the playback signal waveform, the slice is sliced at the plus slice level. Therefore, the synchronization signal width when sliced on the minus side is different. For this reason, when synchronization signals are generated on both the positive side and the negative side of the reproduction signal, if the longest signal period is detected as the synchronization signal period, either the positive side or the negative side synchronization signal period May not be detected properly.

  Accordingly, the present invention provides a synchronization signal detection circuit and a disk reproducing apparatus that can solve such a problem and can detect the synchronization signal period on the plus side and the minus side smoothly and appropriately even if intersymbol interference occurs in the reproduction signal waveform. The task is to do.

  In view of the above problems, the present invention has the following features.

  According to the first aspect of the present invention, there is provided a signal width detection unit for detecting a signal width L when a signal waveform is sliced at positive and negative signal levels different from zero level, and a signal detected by the signal width detection unit. Among the widths L, the maximum signal width L on the positive side and the negative side within the period T1 in which at least both the positive side and negative side synchronization signals are expected to appear at the time of the sync signal detection process is set to the positive side reference synchronization. The signal width W_Th1 and the synchronization signal width setting unit set as the negative reference synchronization signal W_Th2, the positive and negative signal widths L detected by the signal width detection unit, and the synchronization signal width setting unit The positive-side reference synchronization signal width W_Th1 and the negative-side reference synchronization signal W_Th2 are respectively compared in magnitude, and the period of the signal width L that matches the reference synchronization signal width W_Th1 or W_Th2 is determined as the synchronization signal. In the motivation signal detection circuit including a synchronization signal detection unit that detects between, the synchronization signal detection unit is the shortest expected during the synchronization signal detection process among the signal widths L detected by the signal width detection unit The maximum signal width L on the positive side and the negative side in the period T2 smaller than the synchronization signal generation interval is detected as the maximum signal width MAX_L1 and MAX_L2 in the period T2, respectively, and this maximum signal width MAX_L1 is the reference synchronization signal width. When matching with W_Th1 or when MAX_L2 matches with W_Th2, a period corresponding to the maximum signal width MAX_L1 or MAX_L2 at that time is detected as a synchronization signal period.

  According to a second aspect of the present invention, in the synchronization signal detection circuit according to the first aspect, the synchronization signal width setting unit sets a period T1 in parallel with the synchronization detection in the synchronization signal detection unit, and the maximum in the period T1 The signal width L to be updated is set as the reference synchronization signal width W.

  According to a third aspect of the present invention, there is provided a signal width detection unit for detecting a signal width L when a signal waveform is sliced at positive and negative signal levels different from zero level, and a signal detected by the signal width detection unit. Among the widths L, the maximum signal width L on the positive side and the negative side within the period T1 in which at least both the positive side and negative side synchronization signals are expected to appear at the time of the sync signal detection process is set to the positive side reference synchronization. The signal width W_Th1 and the synchronization signal width setting unit set as the negative reference synchronization signal W_Th2, the positive and negative signal widths L detected by the signal width detection unit, and the synchronization signal width setting unit The positive-side reference synchronization signal width W_Th1 and the negative-side reference synchronization signal W_Th2 are respectively compared in magnitude, and the period of the signal width L that matches the reference synchronization signal width W_Th1 or W_Th2 is determined as the synchronization signal. In a disc reproducing apparatus for detecting a synchronization signal inserted in a recording signal by a synchronization detection circuit having a synchronization signal detection unit for detecting the synchronization signal, the synchronization signal detection unit is detected by the signal width detection unit Among the signal widths L, the maximum signal width MAX_L1 in the period T2 is set as the maximum signal width L on the positive side and the negative side in the period T2 smaller than the shortest synchronization signal generation interval assumed at the time of the synchronization signal detection process. MAX_L2 is detected, and when this maximum signal width MAX_L1 matches the reference synchronization signal width W_Th1, or when MAX_L2 matches W_Th2, the period corresponding to the maximum signal width MAX_L1 or MAX_L2 at that time is detected as the synchronization signal period. It is characterized by that.

  According to a fourth aspect of the present invention, in the disc reproducing apparatus according to the third aspect, the synchronization signal width setting unit sets a period T1 in parallel with the synchronization detection in the synchronization signal detection unit, and becomes maximum within the period T1. The signal width L is updated and set as the reference synchronization signal width W.

  The “period T1” in the present invention is indicated as a “reference synchronization signal width detection period” in the following embodiment. In addition, the “period T2” in the above-described invention is indicated as a “maximum width detection period” in the following embodiment. Further, the “variable allowable value α” and the “variable allowable value β” in the above invention are indicated as “margin α” and “margin β” in the following embodiment.

  According to the present invention, since the synchronization signal is detected based on the signal width L when the signal waveform is sliced at a signal level different from the zero level in the synchronization signal detection circuit, intersymbol interference occurs in the signal waveform. Even if it occurs, the synchronization signal period can be properly detected. At this time, since the reference synchronization signal widths W_Th1 and W_Th2 are appropriately set according to the offset of the reproduction signal waveform and the state of asymmetry, the synchronization signal period can be detected smoothly even if an offset or asymmetry occurs in the reproduction signal waveform. Can do.

  According to the invention of claim 2 or 9, since the reference synchronization signal widths W_Th1 and W_Th2 are updated, the synchronization signal period can be detected smoothly even when the synchronization signal period fluctuates, such as during synchronization pull-in. be able to.

  Further, according to the third, fourth, tenth, and eleventh aspects, the synchronization signal detection process can be facilitated.

  Further, according to the invention of claim 5 or 12, since the variation allowable values α and β are set according to the size of the reference synchronization signal widths W_Th1 and W_Th2 or the disk rotation speed, Even when the synchronization signal period varies, the synchronization signal period can be detected smoothly.

  According to the invention of claim 6 or 13, since the positive and negative synchronization signals are always included in the period T1, the reference synchronization signal widths W_Th1 and W_Th2 can be set appropriately.

  According to the invention of claim 7 or 14, since it is possible to avoid two synchronization signals being included in the period T2, it is possible to suppress the detection omission of the synchronization signal.

The effects and significance of the present invention will become more apparent from the following description of embodiments. However, the embodiment described below is merely an example of the present invention, and the meaning of the present invention or each constituent element is not limited to that described in the following embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, the present invention is applied to an optical disc apparatus that performs recording / reproduction on a high density optical disc such as a next generation DVD (Digital Versatile Disc).

  FIG. 1 shows a format of data recorded on a disc. Such a disk is assigned a synchronization signal period (Sync) for each frame. Further, the synchronization signal appears on the reproduction signal from the zero level to the plus side and the minus side, respectively. Whether it appears on the plus side or the minus side may have regularity such as, for example, inverting the polarity of the synchronization signal every other frame. Make it not exist.

  FIG. 2 shows a configuration of the optical disc apparatus according to the embodiment. In FIG. 2, only the reproduction system is shown, and the recording system is not shown. Also, a focus servo circuit, a tracking servo circuit, etc. are not shown.

  As shown in FIG. 2, the optical disc apparatus according to the present embodiment includes an optical pickup 101, an amplifier circuit 102, an ADC (Analog-Digital Converter) 103, a data interpolation circuit 104, an equalizer 105, a Viterbi decoder 106, A phase comparator 107, an LPF (loop filter) 108, an adder 109, a digital VCO (Voltage Controlled Oscillator) 110, a synchronization signal detection circuit 111, a frequency error detection circuit 112, and an LPF (loop filter) 113. A spindle motor servo circuit 114 and a spindle motor 115.

  The optical pickup 101 irradiates a disk with laser light to write data and receives reflected light from the disk to read data. The amplification circuit 102 amplifies the reproduction RF signal supplied from the optical pickup 101 and outputs it to the ADC 103. The ADC 103 samples the reproduced RF signal at a sampling timing corresponding to an asynchronous clock (hereinafter referred to as a system clock) having a frequency higher than that of the resample clock generated by the digital VCO 110, converts the sample value into digital data, and converts the data into digital data. Output to the interpolation circuit 104.

  The data interpolation circuit 104 uses the digital data input from the ADC 103 and the resample clock and resample phase information input from the digital VCO 110 to use the data value (resample timing) at the data interpolation timing (hereinafter referred to as “resample timing”). Data) and the calculated resample data is output to the equalizer 105 and the phase comparator 107. That is, as shown in FIG. 3, the interpolated value at the resample timing (timing indicated by ● in the figure) shifted by the phase corresponding to the resample phase information from the rise timing of the resample clock is the AD before and after the resample timing. Calculation is performed based on the data (digital data input from the ADC 103), and this is output to the equalizer 105 and the phase comparator 107 as resample data at the resample timing.

  The equalizer 105 performs waveform equalization processing on the resampled data supplied from the data interpolation circuit 104 and outputs the result to the Viterbi decoder 106. The Viterbi decoder 106 performs Viterbi decoding processing on the digital data supplied from the equalizer 105 to generate and output binary data of 1 and 0.

  The phase comparator 107 discriminates the edge of the reproduced RF signal waveform based on the resampled data supplied from the data interpolation circuit 104, that is, the intersection position of the reproduced RF signal waveform and the slice level shown in FIG. The phase difference between the normal resample timing set based on the above and the resample timing generated by the digital VCO 110 is detected. Then, digital data (phase difference data ΔP) corresponding to the phase difference is output to the LPF 108.

  The LPF 108 cuts off the high-frequency component of the phase difference data and turns it into a direct current, and outputs this to the adder 109. The adder 109 adds the phase difference data ΔP supplied from the LPF 108 and the frequency shift data ΔF (described later) supplied from the LPF 113 and outputs the result to the digital VCO 110.

  The digital VCO 110 adjusts the period of the resample clock so as to compensate for the phase difference and the frequency shift in accordance with the data (phase difference data + frequency shift data) supplied from the adder 109, The resample phase information is output to the data interpolation circuit 104. The adjusted resample clock is output to the spindle motor servo circuit 114.

  The synchronization signal detection circuit 111 detects the synchronization signal period from the digital data input from the ADC 103 and outputs the detection result to the frequency error detection circuit 112. Details of the synchronization signal detection circuit 111 will be described later.

  The frequency error detection circuit 112 detects the frequency of the synchronization signal from the synchronization signal period detection signal supplied from the synchronization signal detection circuit 111, and outputs the difference ΔF between this frequency and the reference frequency to the LPF 113 as frequency shift data. . The LPF 113 cuts off the high frequency component of the frequency shift data and turns it into a direct current, and outputs this to the adder 109.

  The spindle motor servo circuit 114 calculates the difference between the frequency of the resample timing supplied from the digital VCO 110 and the target frequency, and uses this as frequency shift data to rotate the disk to approximate the frequency of the resample timing to an appropriate value. Generate a servo signal. For example, if the difference is a positive value, the rotation of the disk is slower than the appropriate value, so that the rotation needs to be accelerated. Conversely, if the difference is a negative value, the rotation of the disk needs to be delayed. The spindle motor servo circuit 114 adjusts the rotation roughly at a rotational speed corresponding to the disk radial position, and then controls the rotational speed to an appropriate rotational speed with reference to the difference. However, it is also possible to rotate at CAV (constant angular velocity) regardless of the radial position from the beginning, and adjust the value to an appropriate value by referring to the difference.

  The spindle motor 115 rotationally drives the disk according to the servo signal supplied from the spindle motor servo circuit 114.

  Next, a synchronization detection method in the synchronization signal detection circuit 111 will be described with reference to FIG.

  In such synchronization detection, first, the reproduction signal waveform is sliced at two threshold levels Th1 and Th2, and a signal period (signal width L) at each slice is detected. That is, when sliced at the positive threshold level Th1, the period from when the amplitude value of the reproduction signal becomes equal to or greater than Th1 to less than Th1 is detected as the signal width L, and sliced at the negative threshold level Th2 In this case, a period from when the amplitude value of the reproduction signal becomes equal to or less than Th2 to exceed Th2 is detected as the signal width L. Specifically, the number of system clocks included in the period is counted, and the counted number is set as the signal width L. Then, the lengths of a plurality of signal widths L acquired in a preset period (maximum width detection period) are compared, and the longest signal width L on the plus side is the plus side in the maximum width detection period. Obtained as the maximum signal width MAX_L1. Similarly, the longest signal width L on the minus side is acquired as the maximum signal width MAX_L2 on the minus side in the maximum width detection period.

  The maximum signal widths MAX_L1 and MAX_L2 acquired in this way are compared with the signal widths W_Th1 ± α and W_Th2 ± β obtained by adjusting the reference synchronization signal widths W_Th1 and W_Th2 by the margins α and β. Here, the reference synchronization signal widths W_Th1 and W_Th2 are appropriately set during the synchronization signal detection process (this will be described later).

  Then, it is determined whether the maximum signal width MAX_L1 is in the range of W_Th1-α to W_Th1 + α, and it is determined whether the maximum signal width MAX_L1 is the synchronization signal period according to the determination result. Specifically, the difference between the maximum signal width MAX_L1 and the reference synchronization signal width W_Th1 is obtained, and when the difference is within a range of ± α, the maximum signal width MAX_L1 is set as the synchronization signal period. When this difference is not within the range of ± α, the maximum signal width MAX_L1 is not set as the synchronization signal period.

  Similarly, it is determined whether the maximum signal width MAX_L2 is in the range of W_Th2-β to W_Th2 + β, and it is determined whether the maximum signal width MAX_L2 is the synchronization signal period according to the determination result. Specifically, a difference between the maximum signal width MAX_L2 and the reference synchronization signal width W_Th2 is obtained, and when the difference is within a range of ± β, the maximum signal width MAX_L2 is set as the synchronization signal period. When this difference is not within the range of ± β, the maximum signal width MAX_L2 is not set as the synchronization signal period.

  In the example shown in FIG. 4, a total of three signal widths L, two on the plus side and one on the minus side, are detected. Of these, the 12T signal width L detected on the plus side is the plus maximum signal width MAX_L1, and the 13T signal width L detected on the minus side is the minus maximum signal width MAX_L2. Then, when the maximum signal widths MAX_L1 and MAX_L2 are compared with the reference synchronization signal widths W_Th1 and W_Th2, and the difference is within the range of ± α and ± β, the maximum signal widths MAX_L1 and MAX_L2 are used as the synchronization signal periods. Detected. In the case of the figure, the negative maximum signal width MAX_L2 matches W_Th2, and this signal width period is detected as the synchronization signal period.

  As described in the prior art, when the reproduction signal waveform is sliced at zero level, as shown in the figure, the period other than the true synchronization signal period is the longest period. It is erroneously detected as the synchronization signal period. On the other hand, when synchronization detection is performed as in the present embodiment, the possibility that the true synchronization signal detection period is properly detected as the synchronization signal period is raised.

  FIG. 5 shows a method for setting the reference synchronization signal widths W_Th1 and W_Th2. This figure shows an example in the case where a plus-direction offset occurs in the reproduction signal waveform.

  The reference synchronization signal widths W_Th1 and W_Th2 are obtained by comparing the signal width L obtained by slicing the reproduction signal waveform at two threshold levels Th1 and Th2 in the positive and negative threshold levels in a preset reference synchronization signal width detection period. The maximum signal width L on the negative side and the negative side is set to be reference synchronization signal widths W_Th1 and W_Th2, respectively.

  As shown in FIG. 4, when there is no offset or asymmetry in the reproduced signal waveform, the reference synchronization signal widths W_Th1 and W_Th2 have substantially the same signal width. In this case, the maximum signal width L in the reference synchronization signal width detection period regardless of the plus side and the minus side is set as the signal widths of the reference synchronization signal widths W_Th1 and W_Th2 as shown in FIG. The synchronization signal period can be properly detected by the method.

  On the other hand, when the reproduction signal waveform has an offset as shown in FIG. 5, the reference synchronization signal widths W_Th1 and W_Th2 change according to the state of the offset or asymmetry. In the case of FIG. 5, since a positive offset occurs in the reproduction signal waveform, there is a relationship of W_Th1> W_Th2 between the reference synchronization signal widths W_Th1 and W_Th2. In this case, if the maximum signal width L in the reference synchronization signal width detection period is set as the signal width of the reference synchronization signal widths W_Th1 and W_Th2 regardless of the plus side and the minus side, either the plus side or the minus side is set. The synchronization signal period cannot be properly detected.

  For example, in the case of FIG. 5, the signal width L corresponding to the plus side 13T becomes the maximum in the reference synchronization signal width detection period. If this signal width L is set as the signal width of the reference synchronization signal widths W_Th1 and W_Th2, the positive synchronization signal period (13T) is properly detected, but the negative synchronization signal period (13T) is set. Since the signal width becomes smaller than the signal width W_Th2 beyond the margin β, it is not detected as the synchronization signal period.

  Therefore, in the present embodiment, as described above, the maximum signal widths L on the positive side and the negative side in the reference synchronization signal width detection period are set as the reference synchronization signal widths W_Th1 and W_Th2. As a result, even if an offset or asymmetry occurs in the reproduced signal waveform, the reference synchronization signal widths W_Th1 and W_Th2 corresponding to the state are set. Therefore, the synchronization signal period can be properly detected on both the plus side and the minus side.

  FIG. 6 shows a configuration example of the synchronization signal detection circuit 111.

  In such a configuration example, the synchronization signal detection circuit 111 includes a data slice unit 11, a signal width detection unit 12, a + side maximum width detection unit 13, a + side synchronization signal width setting unit 14, an α setting unit 15, The negative side maximum width detection unit 16, the negative side synchronization signal width setting unit 17, the β setting unit 18, and the synchronization signal detection unit 19 are configured.

  The data slicing unit 11 compares the AD data input from the ADC 103 with the threshold levels Th <b> 1 and Th <b> 2 and supplies the comparison result to the signal width detection unit 12. The signal width detection unit 12 detects the signal width L (the number of system clocks) as described above based on the data supplied from the data slice unit 11, and the plus side signal width L and the minus side signal width. L is output to the + side maximum width detecting unit 13 and the −side maximum width detecting unit 16, respectively.

  The + side maximum width detection unit 13 compares the length of the signal width L supplied from the signal width detection unit 12 for each maximum width detection period, and detects the longest signal width L as the maximum signal width MAX_L1. Similarly, the-side maximum width detection unit 16 compares the length of the signal width L supplied from the signal width detection unit 12 for each maximum width detection period, and sets the longest signal width L as the maximum signal width MAX_L2. To detect.

  The + side synchronization signal width setting unit 14 compares the maximum signal width MAX_L1 supplied from the + side maximum width detection unit 13 during the synchronization signal width setting period, and the maximum signal width MAX_L1 that is the maximum is compared with the reference synchronization on the plus side. Set as signal width W_Th1. Similarly, the − side synchronization signal width setting unit 17 compares the maximum signal width MAX_L2 supplied from the − side maximum width detection unit 16 during the synchronization signal width setting period, and the maximum signal width MAX_L2 that is the maximum is negative. Is set as the reference synchronization signal width W_Th2.

  The α setting unit 15 sets a margin α for the reference synchronization signal width W_Th1. Similarly, the β setting unit 18 sets a margin β for the reference synchronization signal width W_Th2. Here, the margins α and β may be fixed, but more preferably adjusted according to the rotational speed of the disc. That is, it may be adjusted so that it decreases as the rotational speed of the disk increases. For example, the reference synchronization signal widths W_Th1 and W_Th2 set by the + side synchronization signal width setting unit 14 and the −side synchronization signal width setting unit 17 are appropriately monitored, and the margin is set so that the reference synchronization signal width increases as the reference synchronization signal width increases. Adjust α and β.

  The synchronization signal detection unit 19 detects the synchronization signal period by comparing the maximum signal width MAX_L1 supplied from the + side maximum width detection unit 13 with the reference synchronization signal width W_Th1 and the margin α. Further, the maximum signal width MAX_L2 supplied from the negative side maximum width detection unit 17 is compared with the reference synchronization signal width W_Th2 and the margin β to detect the synchronization signal period.

  That is, the synchronization signal detection unit 19 obtains a difference between the maximum signal width MAX_L1 and the reference synchronization signal width W_Th1, and only supplies the supplied maximum signal width MAX_L1 to the synchronization signal when the obtained difference is within a range of ± α. Detect as period. Further, the difference between the maximum signal width MAX_L2 and the reference synchronization signal width W_Th2 is obtained, and the supplied maximum signal width MAX_L2 is detected as the synchronization signal period only when the obtained difference is within the range of ± β.

  FIG. 7 shows a timing chart when synchronization is detected. In the example shown in the figure, the period during which the system clock is continuously counted for 1000 clocks is the maximum width detection period, and the period during which the system clock is continuously counted for 10000 clocks at the start of synchronization detection is the synchronization signal width setting period. (Initialization period).

  Note that the length of the maximum width detection period is set such that two synchronization signals are not included in the period. For example, as shown in FIG. 2, when referring to the synchronization signal when pulling in the PLL using the digital VCO 110, one frame period (1 shown in FIG. 1) at the disk rotation speed set as the earliest at the time of PLL pull-in. Frame period).

  The synchronization signal width setting period (initialization period) is set to a length that can include at least one plus side synchronization signal and minus side synchronization signal in the period. For example, when it is assumed that at least one plus-side sync signal and at least one minus-side sync signal are usually included in 10 frames, the sync signal width setting period is set to be the slowest at the time of PLL pull-in. It is set to a period longer than 10 frame periods at the rotation speed. If there is regularity in the appearance of the plus-side synchronization signal and the minus-side synchronization signal, the synchronization signal has a length that can include at least one plus-side synchronization signal and minus-side synchronization signal in consideration of the regularity. The width setting period may be set.

  Referring to FIG. 7, when synchronization detection is started, first, the maximum signal width MAX_L is detected in each maximum width detection period (for 1000 clocks) within the initialization period (for 10,000 clocks). On the minus side, the longest maximum signal widths MAX_L1 and MAX_L2 are set as reference synchronization signal widths W_Th1 and W_Th2, respectively. Thereafter, detection of a synchronization signal is started using these reference synchronization signal widths W_Th1, W_Th2 and margins α, β. When such a synchronization signal is detected, the number of clocks from the start position of each maximum width detection period to the positions of the maximum signal widths MAX_L1 and MAX_L2 are sequentially stored. If either of the maximum signal widths MAX_L1 and MAX_L2 is detected as the synchronization signal, the number of clocks from the start position of the next maximum width detection period to the maximum width detected as the synchronization signal is stored in the memory. A synchronization detection signal is output at the timing when the number of clocks has elapsed. That is, the synchronization detection signal is output after being delayed by the maximum width detection period.

  FIG. 8 shows a flowchart for detecting the maximum signal width.

  When the maximum signal width is detected, the reproduction signal waveform is sliced at the threshold levels Th1 and Th2, and the signal width L is sequentially acquired (S10), and is distributed to the positive signal width L and the negative signal width L (S11). ). Next, the signal width L on the plus side and the signal width L on the minus side are respectively compared with the signal widths MAX_L1 and MAX_L2 that are the longest so far (S12, S14), and if larger than this (S12: YES, (S14: YES), the maximum values MAX_L1 and MAX_L2 of the signal width L on the plus side and the minus side are replaced (S13, S15). This replacement is repeated from the start to the end of the maximum width detection period (S16). That is, in the example of FIG. 7, the system clock count (ClkCNT) from the start of detection of the maximum signal width is repeated until it reaches 1000 clocks (MAXCNT). When the maximum width detection period ends, the maximum signal width values MAX_L1 and MAX_L2 remaining at that time are output as the maximum signal widths MAX_L1 and MAX_L2 on the plus side and the minus side as they are.

  FIG. 9 shows a flowchart when the reference sync signal width is detected.

  When the reference sync signal width is detected, the reproduction signal waveform is sliced at the threshold levels Th1 and Th2, and the signal width L is sequentially acquired (S20). The signal is divided into a positive signal width L and a negative signal width L (S21). Next, the plus-side signal width L and the minus-side signal width L are respectively compared with the longest W_Th1 and W_Th2 (S22, S24), and if larger than this (S22: YES, S24: YES)), the maximum values W_Th1 and W_Th2 of the signal width L on the plus side and the minus side are replaced (S23, S25). This replacement is repeated from the start to the end of the reference synchronization signal width detection period (S26). That is, in the example of FIG. 9, the system clock count (ClkCNT) from the start of detection of the maximum signal width is repeated until it reaches 10,000 clocks (INICNT). When the reference synchronization signal width detection period ends, the maximum signal width values W_Th1 and W_Th2 remaining at that time are output as positive and negative reference synchronization signal widths W_Th1 and W_Th2 as they are.

  FIG. 10 shows a flowchart when the synchronization signal is detected.

  When the synchronization signal detection is started, first, the reference synchronization signal width setting process shown in FIG. 9 is executed to set the reference synchronization signal widths W_Th1 and W_Th2 (S101). Then, margins α and β are set based on the set reference synchronization signal width W (S102). Thus, the initial period ends, and the synchronization signal detection period starts. If the margins α and β are fixed, S102 is omitted.

  Therefore, when the synchronization signal detection period is started, the maximum signal width detection process of FIG. 8 is executed, and the maximum signal widths MAX_L1 and MAX_L2 are acquired (S103). The acquired maximum signal widths MAX_L1 and MAX_L2 are respectively compared with the reference synchronization signal widths W_Th1 and W_Th2 set in S101 (S104 and S108).

  Here, if the maximum signal width MAX_L1 is “W_Th1-α <MAX_L1 <W_Th1 + α” (S104: YES), the period of the maximum signal width MAX_L1 is detected as a synchronization signal period (S105). If the maximum signal width MAX_L1 is not “W_Th1−α <MAX_L <W_Th1 + α”, the period of the maximum signal width MAX_L1 is not detected as the synchronization signal period (S106). If the maximum signal width MAX_L2 is “W_Th2−β <MAX_L2 <W_Th2 + β” (S108: YES), the period of the maximum signal width MAX_L2 is detected as the synchronization signal period (S109). If the maximum signal width MAX_L2 is not “W_Th2−β <MAX_L2 <W_Th2 + β”, the period of the maximum signal width MAX_L2 is not detected as the synchronization signal period (S110).

  When the period of the maximum signal width MAX_L1 or MAX_L2 is detected as the synchronization signal period in S105 or S109, the position POS (number of clocks from the start position) from the start position of the maximum width detection period to the maximum signal width MAX_L1 or MAX_L2 ) Is stored as the synchronization signal output timing (S107, S111). Then, the synchronization detection signal is output at the timing when the position reaches the position POS from the start position of the next maximum width detection period (S112).

  Thereafter, the process returns to S103, and the same process is executed for the next maximum width detection period. Such processing is repeated until the synchronization detection operation is completed.

  According to the present embodiment, since the maximum signal width when the reproduced signal waveform is sliced at the threshold levels Th1 and Th2 is detected as the synchronization signal period, when the intersymbol interference occurs in the reproduced signal waveform as shown in FIG. In addition, the synchronization signal period can be accurately detected. In addition, since the reference synchronization signal widths W_Th1 and W_Th2 are appropriately set according to the offset of the reproduction signal waveform and the state of asymmetry, the synchronization signal period can be detected smoothly even if the reproduction signal waveform has an offset or asymmetry. it can.

  In the present embodiment, the threshold levels Th1 and Th2 affect the synchronization signal detection accuracy. These threshold levels Th1 and Th2 may be set within a range in which the synchronization detection accuracy can be increased while repeating the experiment and verification on the sample disk. FIG. 11 shows the verification results for the HDDVD-ROM. This is an experiment of the detection error rate of the synchronization signal when the positive slice level (Th1) and the negative slice level (Th2) are similarly separated from the zero level by the level shown on the horizontal axis. The horizontal axis represents the signal level when normalized with 8 bits.

  In the case of the figure, if the signal level of the slice level (Th1) (Th2) with respect to the zero level is set to about 140 to 165, errors at the time of synchronization detection can be suppressed. The same experiment is performed on other sample disks, and the size of the slice level may be set to an appropriate value based on these experiments. In addition, after the offset of the reproduction signal is reduced by the offset canceller, for example, a calculation such as Th1 = (peak level−0 level) / 2, Th2 = (0 level−bottom level) / 2 is performed to set the threshold value. The levels Th1 and Th2 may be automatically set.

  In the above embodiment, the reference synchronization signal widths W_Th1 and W_Th2 are set in the initialization period and used in the synchronization signal detection period after the initialization period. However, the reference synchronization signal widths W_Th1 and W_Th2 are used after the initialization period. It is also possible to update appropriately during the synchronization signal detection period, and to perform synchronization signal detection using the reference synchronization signal widths W_Th1 and W_Th2 after the update. Such updating can be performed every fixed period, or when synchronization detection fails or when synchronization detection cannot be performed continuously for a certain period or longer.

  FIG. 12 shows a timing chart when the reference synchronization signal widths W_Th1 and W_Th2 are updated every predetermined period.

  Here, during the synchronization signal detection period after the initialization period, the reference synchronization signal widths W_Th1 and W_Th2 are updated every 10000 clock periods (reference synchronization signal width detection periods). That is, in parallel with the synchronization detection, the maximum signal widths MAX_L1 and MAX_L2 acquired during the 10000 clock period are compared, and the longest maximum signal widths MAX_L1 and MAX_L2 are compared in the next 10000 clock period following the 10000 clock period. The reference synchronization signal widths W_Th1 and W_Th2 to be used are set.

  FIG. 13 shows a flowchart when the synchronization signal is detected in such a case. In the flowchart, in S201, the reference synchronization signal widths W_Th1 and W_Th2 are updated every reference synchronization signal width detection period (10000 clock periods in the example of FIG. 12). Further, the margins α and β are reset based on the updated reference synchronization signal widths W_Th1 and W_Th2. In the reference synchronization signal width detection period, the synchronization signal period is detected using the updated reference synchronization signal widths W_Th1 and W_Th2 and the margins α and β (S103 to S107).

  As mentioned above, although embodiment which concerns on this invention was described, this invention is not limited to the said embodiment.

For example, in the above embodiment, the number of system clocks counted from the time when the amplitude value of the reproduction signal is equal to or higher than the positive threshold level Th1 to the time when it is lower than Th1 and the negative threshold level Th2 or lower. The system clock count counted until Th2 is exceeded is acquired as the signal width L. As shown in FIG. 14, the widths EDGE_LENGTH1 and EDGE_LENGTH2 from this signal width L to the front and rear edge positions are set to the signal width L. By adding, a more precise signal width L_DETAIL is obtained, and based on this, the maximum signal width MAX_L1, MAX_L2 and the reference synchronization signal width W_Th1, W_Th2 may be set, and the synchronization signal period may be detected. . In this case, when the signal width L_DETAIL is acquired by the number of clocks as in the above embodiment, EDGE_LENGTH1 and EDGE_LENGTH2 are:
EDGE_LENGTH1 = B1 / (A1 + B1)
EDGE_LENGTH2 = B2 / (A2 + B2)
As required. A1 and B1, A2 and B2 are differences (absolute values) of reproduced signals with respect to Th1 and Th2 at the system clock timing before and after the edge position, respectively. In this case, EDGE_LENGTH1 and EDGE_LENGTH2 represent the width from the signal width L (system clock unit) shown in the figure to the front and rear edge positions as the number of system clocks below the decimal point.

  As described above, if the setting of the maximum signal widths MAX_L1, MAX_L2 and the reference synchronization signal widths W_Th1, W_Th2 and the detection of the synchronization signal period are performed based on the signal width L_DETAIL, the reference synchronization signal widths W_Th1, W_Th2 And maximum signal widths MAX_L1 and MAX_L2 can be compared more precisely, and the detection accuracy of the synchronization signal can be further increased.

  In the above embodiment, an example in which the present invention is applied to an optical disk apparatus that performs recording / reproduction on a high-density optical disk such as a next-generation DVD (Digital Versatile Disc) has been described. The present invention can also be applied to a drive device that performs reproduction or other drive devices such as a magneto-optical disk device and a magnetic disk device. However, the present invention is effective when applied to a drive device that handles a disk in which intersymbol interference occurs.

  Furthermore, in the above embodiment, the configuration example (FIG. 2) in which the synchronization signal is referred to when pulling in the PLL using the digital VCO 110 has been shown, but the present invention may be applied to other configuration examples using the synchronization signal. Of course it is possible.

The embodiments of the present invention can be appropriately modified in various ways within the scope of the technical idea shown in the claims.

The figure which shows the format of the recording data which concerns on embodiment The figure which shows the structural example of the optical disk apparatus which concerns on embodiment The figure which shows the figure explaining the production | generation method of the resample data which concerns on embodiment The figure which shows notionally the synchronous detection method which concerns on embodiment The figure explaining the setting method of the reference | standard synchronizing signal width which concerns on embodiment The figure which shows the structural example of the synchronizing signal detection circuit which concerns on embodiment Timing chart at the time of synchronization detection according to the embodiment Flowchart when detecting maximum signal width according to the embodiment Flowchart when detecting reference sync signal width according to the embodiment Flowchart at the time of synchronization detection according to the embodiment The figure explaining the setting method of the threshold level which concerns on embodiment Timing chart when detecting synchronization according to another embodiment Flowchart at the time of synchronization detection according to another embodiment The figure explaining the signal width detection method which concerns on other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 111 Synchronization signal detection circuit 11 Data slice part 12 Signal width detection part 13 Maximum width detection part 14 Synchronization signal width setting part 15 (alpha) setting part 16 Synchronization signal detection part

Claims (4)

A signal width detection unit for detecting a signal width L when the signal waveform is sliced at positive and negative signal levels different from the zero level, and a synchronization signal detection among the signal widths L detected by the signal width detection unit The signal width L that is maximum on the positive side and the negative side in the period T1 in which at least both the positive side and negative side synchronization signals are expected to appear at the time of processing is set to the positive reference sync signal width W_Th1 and the negative side, respectively. A synchronization signal width setting unit set as a reference synchronization signal W_Th2, a positive and negative signal width L detected by the signal width detection unit, and a positive reference synchronization set by the synchronization signal width setting unit The signal width W_Th1 and the negative reference synchronization signal W_Th2 are respectively compared in magnitude, and the period of the signal width L that matches the reference synchronization signal width W_Th1 or W_Th2 is detected as the synchronization signal period. In Motivation signal detection circuit that includes a period signal detection unit,
The synchronization signal detection unit is on the positive side and the negative side within a period T2 that is smaller than the shortest synchronization signal generation interval assumed during the synchronization signal detection processing of the signal width L detected by the signal width detection unit. The maximum signal width L is detected as the maximum signal width MAX_L1 and MAX_L2 in the period T2, respectively. When this maximum signal width MAX_L1 matches the reference synchronization signal width W_Th1, or when MAX_L2 matches W_Th2, A synchronization signal detection circuit that detects a period corresponding to a maximum signal width MAX_L1 or MAX_L2 as a synchronization signal period.   2. The synchronization signal width setting unit according to claim 1, wherein the synchronization signal width setting unit sets a period T1 in parallel with the synchronization detection in the synchronization signal detection unit, and updates the maximum signal width L as the reference synchronization signal width W within the period T1. A synchronization signal detection circuit, wherein the synchronization signal detection circuit is set. A signal width detection unit for detecting a signal width L when the signal waveform is sliced at positive and negative signal levels different from the zero level, and a synchronization signal detection among the signal widths L detected by the signal width detection unit The signal width L that is maximum on the positive side and the negative side in the period T1 in which at least both the positive side and negative side synchronization signals are expected to appear at the time of processing is set to the positive reference sync signal width W_Th1 and the negative side, respectively. A synchronization signal width setting unit set as a reference synchronization signal W_Th2, a positive and negative signal width L detected by the signal width detection unit, and a positive reference synchronization set by the synchronization signal width setting unit The signal width W_Th1 and the negative reference synchronization signal W_Th2 are respectively compared in magnitude, and the period of the signal width L that matches the reference synchronization signal width W_Th1 or W_Th2 is detected as the synchronization signal period. In the disc reproducing apparatus for detecting a synchronizing signal inserted into the recording signal by the synchronous detection circuit and a period signal detection unit,
The synchronization signal detection unit is on the positive side and the negative side within a period T2 that is smaller than the shortest synchronization signal generation interval assumed during the synchronization signal detection processing of the signal width L detected by the signal width detection unit. When the maximum signal width L is detected as the maximum signal width MAX_L1 and MAX_L2 in the period T2, respectively, and the maximum signal width MAX_L1 matches the reference synchronization signal width W_Th1, or when MAX_L2 matches W_Th2, A disc reproducing apparatus for detecting a period corresponding to a maximum signal width MAX_L1 or MAX_L2 as a synchronization signal period.   4. The synchronization signal width setting unit according to claim 3, wherein the synchronization signal width setting unit sets a period T1 in parallel with the synchronization detection in the synchronization signal detection unit, and updates a signal width L that is maximum within the period T1 as a reference synchronization signal width W. A disc playback apparatus characterized by setting.

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