JP2004234808A - Optical disk device and open loop gain control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a decoding error of a reproduced signal caused by scratch, dirt, or the like of an optical disk in an optical disk device. <P>SOLUTION: In an optical disk device 1, an abnormal pattern detecting circuit 10 detects abnormality of pattern length of a reproduced signal S1 read from an optical disk 20, and outputs a detected signal S2 indicating this detection quantity. A gain control circuit 11 generates a control signal S3 in accordance with the detected signal S2, when detection quantity indicated by the detected signal S2 is increased, the circuit 11 decreases open loop gain of a PLL circuit 12. By such operation, when reliability of the reproduced signal S1 is low, the PLL circuit 12 becomes hard to follow the reproduced signal S1, an increase in jitter of a generated clock CLK is suppressed, a stable clock CLK is supplied. Thereby, a decoding error of the reproduced signal S1 is reduced. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an optical disc device, and particularly to a technique for improving reliability related to reproduction of recorded information from an optical disc.
[0002]
[Prior art]
Optical disc devices such as CD players, CD-ROM drives, DVD players, DVD-ROM drives, and MD players generally include a PLL (Phase Locked Loop) that extracts a clock synchronized with the reproduction signal from a reproduction signal read from the optical disc. A phase locked loop (Phase Locked Loop) circuit is provided. Then, using the clock extracted by the PLL circuit, signal processing such as decoding and correction processing of a reproduction signal is performed, and finally, information recorded on the optical disk is reproduced (for example, see Non-Patent Document 1).
[0003]
[Non-patent document 1]
Heitaro Nakajima and Hiroshi Ogawa, co-authored, "Illustrated Compact Disc Reader", 2nd revised edition, Ohmsha, December 1993, p. 149-150
[0004]
[Problems to be solved by the invention]
If the signal recording surface of the optical disc has scratches or dirt, the reproduced signal is affected by this and causes abnormalities. However, in the conventional optical disk device, the PLL circuit attempts to extract the clock with the same open loop gain as in the normal state, even for an abnormal, that is, a low-reliability reproduction signal. As a result, the jitter of the extracted clock increases, and as a result, decoding errors of the reproduction signal frequently occur, and the recorded information cannot be normally reproduced.
[0005]
In view of the above problems, it is an object of the present invention to reduce a decoding error of a reproduction signal due to a scratch or dirt on an optical disc and improve the reliability of reproducing recorded information on the optical disc in an optical disc device.
[0006]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the present invention provides an optical disk device for reproducing information recorded on an optical disk, a PLL circuit for extracting a clock from a first signal read from the optical disk, A detection circuit that detects an abnormality in the pattern length of the first signal and outputs a second signal indicating the detected amount, and generates a third signal in accordance with the detected amount indicated by the second signal; A gain control circuit for controlling the open loop gain of the PLL circuit based on the third signal is provided. Here, the gain control circuit, when the detection amount indicated by the second signal increases, decreases the open loop gain of the PLL circuit while decreasing the detection amount indicated by the second signal. Then, the open loop gain of the PLL circuit is increased.
[0007]
According to the present invention, an abnormality in the pattern length of the first signal read from the optical disk is detected by the detection circuit, and the second signal indicating the detected amount is output. Then, a third signal is generated by the gain control circuit in accordance with the detection amount indicated by the second signal, and the open-loop gain of the PLL circuit is controlled by the third signal. Here, the open loop gain of the PLL circuit is controlled so as to decrease when the detection amount indicated by the second signal increases, and is controlled to increase when the detection amount decreases. Accordingly, when the first signal becomes abnormal due to the influence of scratches or dirt on the optical disk, the open loop gain of the PLL circuit decreases, and it becomes difficult to follow the first signal having reduced reliability. In addition, it is possible to suppress an increase in jitter of the extracted clock. As a result, the clock supplied from the PLL circuit is stabilized, the decoding error when reproducing the signal recorded on the optical disk is reduced, and the reliability of reproducing the recorded information on the optical disk is improved.
[0008]
Preferably, the detection circuit weights the second signal according to a pattern length of the first signal. More preferably, the detection circuit changes a coefficient related to the weighting of the second signal according to a reproduction speed of the optical disc.
[0009]
Preferably, the detection circuit in the optical disc device calculates an average value per a predetermined period for the detected pattern length abnormality of the first signal, and outputs the average value as the second signal. Shall be. More preferably, the detection circuit changes the predetermined period according to a reproduction speed of the optical disc.
[0010]
Further, in order to solve the above-mentioned problem, a means taken by the present invention is, as an optical disk device for reproducing information recorded on an optical disk, a PLL circuit for extracting a clock from a first signal read from the optical disk; A detection circuit for detecting jitter of the clock extracted by the PLL circuit and outputting a second signal indicating the detected amount, and generating a third signal in accordance with the detected amount indicated by the second signal A gain control circuit for controlling an open loop gain of the PLL circuit based on the third signal is provided. Here, the gain control circuit, when the detection amount indicated by the second signal increases, decreases the open loop gain of the PLL circuit while decreasing the detection amount indicated by the second signal. Then, the open loop gain of the PLL circuit is increased.
[0011]
According to the present invention, the jitter of the clock extracted by the PLL circuit is detected by the detection circuit, and the second signal indicating the detected amount is output. Then, a third signal is generated by the gain control circuit in accordance with the detection amount indicated by the second signal, and the open-loop gain of the PLL circuit is controlled by the third signal. Here, the open loop gain of the PLL circuit is controlled so as to decrease when the detection amount indicated by the second signal increases, and is controlled to increase when the detection amount decreases. As a result, if the first signal becomes abnormal due to the influence of scratches or dirt on the optical disc and the jitter of the clock extracted by the PLL circuit increases, the open loop gain of the PLL circuit decreases and the reliability increases. It becomes difficult to follow the reduced first signal, and an increase in clock jitter can be suppressed. As a result, the clock supplied from the PLL circuit is stabilized, the decoding error when reproducing the signal recorded on the optical disk is reduced, and the reliability of reproducing the recorded information on the optical disk is improved.
[0012]
Preferably, the detection circuit calculates an average value per a predetermined period for the detected jitter of the clock, and outputs the average value as the second signal. More preferably, the detection circuit changes the predetermined period according to a reproduction speed of the optical disc.
[0013]
On the other hand, it is preferable that the gain control circuit in the optical disc device according to the present invention has a hysteresis characteristic in the relationship between the second signal and the control of the open loop gain of the PLL circuit. Thus, when the detection amount indicated by the second signal increases, the open-loop gain of the PLL circuit is reduced early to stabilize the extracted clock, while when the detection amount decreases, the extraction amount becomes early. Control such as increasing the open loop gain to return to the steady state is possible.
[0014]
Preferably, the optical disk device according to the present invention further includes a loss detection circuit that detects a loss of a signal read from the optical disk. Then, the gain control circuit in the optical disk device sets the third signal to a predetermined value when a loss is detected by the loss detection circuit.
[0015]
Further, it is preferable that the gain control circuit in the optical disk device according to the present invention changes the third signal in accordance with a reproduction speed of the optical disk.
[0016]
Further, it is preferable that the gain control circuit in the optical disc device according to the present invention holds the value indicated by the third signal for a predetermined period after changing the third signal. More preferably, the gain control circuit changes the predetermined period according to a reproduction speed of the optical disc. More preferably, the gain control circuit changes the predetermined period according to a detection amount indicated by the second signal.
[0017]
On the other hand, the PLL circuit in the optical disk device according to the present invention determines the frequency of the phase comparison between the first signal and the clock extracted by the PLL circuit in accordance with the third signal generated by the gain control circuit. It is preferable to have a varying phase comparator.
[0018]
Further, it is preferable that the PLL circuit in the optical disc device according to the present invention has a charge pump circuit that changes the amount of current to be output and sucked in accordance with the third signal generated by the gain control circuit.
[0019]
Further, it is preferable that the PLL circuit in the optical disc device according to the present invention includes a loop filter circuit that changes a time constant according to the third signal generated by the gain control circuit.
[0020]
Further, it is preferable that the PLL circuit in the optical disk device according to the present invention has a frequency divider that changes a frequency division ratio in accordance with the third signal generated by the gain control circuit.
[0021]
As described above, the characteristic of any one of the phase comparator, the charge pump circuit, the loop filter circuit, and the frequency divider constituting the PLL circuit is changed according to the third signal generated by the gain control circuit. By doing so, the open loop gain of the PLL circuit can be adjusted.
[0022]
Also, the PLL circuit in the optical disc device according to the present invention compares the phase of the first signal with the clock extracted by the PLL circuit, and outputs a digital signal indicating the result of the phase comparison. A digital operation circuit that performs an operation on a digital signal output from the comparator with an operation coefficient corresponding to a third signal generated by the gain control circuit; and a clock based on an operation result of the digital operation circuit. And a clock generation circuit for generating the clock signal.
[0023]
On the other hand, in order to solve the above-mentioned problems, a means taken by the present invention is a method of controlling an open loop gain of a PLL circuit in an optical disk device for reproducing information recorded on an optical disk, by controlling a pattern of a signal read from the optical disk. An abnormal pattern detecting step of detecting an abnormal length, and when the amount of the abnormal pattern length detected by the abnormal pattern detecting step increases, while reducing the open loop gain of the PLL circuit, the abnormal pattern detecting step A gain control step of increasing an open loop gain of the PLL circuit when the detected amount of the pattern length abnormality is reduced.
[0024]
Further, in order to solve the above problem, a means taken by the present invention is a method of controlling an open loop gain of a PLL circuit in an optical disk device for reproducing information recorded on an optical disk, the method of controlling a clock extracted by the PLL circuit. A jitter detecting step for detecting jitter; and, when an amount of jitter of the clock detected by the jitter detecting step increases, the clock detected by the jitter detecting step while reducing an open loop gain of the PLL circuit. And the gain control step of increasing the open loop gain of the PLL circuit when the amount of jitter of the PLL circuit decreases.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0026]
(1st Embodiment)
FIG. 1 shows a configuration of an optical disc device according to a first embodiment of the present invention. The optical disc device 1 of the present embodiment includes an abnormal pattern detection circuit (corresponding to the detection circuit of the present invention) 10, a gain control circuit 11, a PLL circuit 12, a missing detection circuit 13, a spindle motor 14, an optical pickup 15, an RF amplifier 16, A data slicer 17, a servo controller 18, and a driver 19 are provided.
[0027]
An optical disc 20 such as a CD or DVD is driven to rotate by a spindle motor 14. The spindle motor 14 is controlled by a servo controller 18 via a driver 19. The rotation speed is controlled by a reproduction speed control signal S5 for controlling the reproduction speed of the optical disc 20. The optical pickup 15 irradiates the optical disc 20 with a laser beam, detects the return light from the optical disc 20, and converts it into a voltage value.
[0028]
The output from the optical pickup 15 is amplified by the RF amplifier 16 (RF signal) and binarized by the data slicer 17. Thus, the information recorded on the optical disc 20 is restored as the reproduction signal S1 (corresponding to the first signal of the present invention). Then, decoding / correction processing and the like are performed on the reproduction signal S1 by a reproduction signal processing unit (not shown) provided at a subsequent stage. To perform these processes, a clock synchronized with the reproduction signal S1 is required. This clock is generated by the PLL circuit 12 (clock CLK).
[0029]
Next, the abnormal pattern detection circuit 10 will be described in detail. FIG. 2 shows the internal configuration of the abnormal pattern detection circuit 10. The abnormal pattern detecting circuit 10 includes a pattern detecting circuit 101, a multiplier 102-i (1 ≦ i ≦ n), an adder 103, an integrating circuit 104, and a timer circuit 105, and detects an abnormal pattern length of the reproduction signal S1. A detection signal S2 (corresponding to the second signal of the present invention) indicating the detected amount is output. For example, in the case of a CD, a pattern having a length of 3 to 11 times the basic unit appears in the reproduction signal S1, but a different pattern appears when the optical disc 20 has a scratch or dirt. The abnormal pattern detection circuit 10 detects such an abnormal pattern length of the reproduced signal S1. Since the normal pattern length differs depending on the type of the optical disc 20 to be reproduced, the abnormal pattern detection circuit 10 switches the pattern length to be detected according to the type of the optical disc 20.
[0030]
The pattern detection circuit 101 receives the reproduction signal S1, detects an abnormal pattern, and outputs a signal SP corresponding to the pattern length. The signal SP is weighted by the multipliers 102-1 to 102-n with the coefficients α1 to αn, and is added by the adder 103. The signal SP 'thus output from the adder 103 indicates the amount of the detected pattern length abnormality.
[0031]
In general, if the reproduction signal S1 is greatly affected by scratches or dirt on the optical disc, the detected abnormal pattern length largely deviates from the regular pattern length. Therefore, the coefficient αi is set to increase as the pattern length increases.
[0032]
The value of the coefficient αi can be changed according to the reproduction speed control signal S5. This allows the open loop gain of the PLL circuit 12 to follow the change in the reproduction speed of the optical disk 20, and suppresses an increase in the jitter of the clock CLK. The coefficient αi may be fixed regardless of the reproduction speed control signal S5.
[0033]
The integration circuit 104 receives the signal SP ', integrates the signal SP' for a predetermined period designated by the timer circuit 105, divides the integration value by a value corresponding to the integration period, and outputs the result. That is, the integrating circuit 104 calculates an average value of the signal SP 'per predetermined period, and outputs the average value as the detection signal S2. Here, if the integration period is shortened, a detection signal S2 that immediately responds to a change in the detection amount of the pattern length abnormality is output. Conversely, when the integration period is lengthened, the detection signal S2 shows an almost average value during the integration period and is smoothed. As described above, it is possible to set the integration period suitable for the characteristics of the optical disk device 1 by changing the predetermined period specified by the timer circuit 105 in various ways.
[0034]
The timer circuit 105 can change a predetermined period designated for the integrating circuit 104 according to the reproduction speed control signal S5. This allows the open loop gain of the PLL circuit 12 to follow the change in the reproduction speed of the optical disk 20, and suppresses an increase in the jitter of the clock CLK. Note that the predetermined period of the timer circuit 105 may be fixed regardless of the reproduction speed control signal S5.
[0035]
Next, the gain control circuit 11 will be described in detail. FIG. 3 shows an internal configuration of the gain control circuit 11. The gain control circuit 11 includes a gain calculation circuit 111, a control signal generation circuit 112, and a timer circuit 113, and controls the control signal S3 (the third signal of the present invention) according to the detection signal S2 output from the abnormal pattern detection circuit 10. Equivalent). This control signal S3 is used for controlling the open loop gain of the PLL circuit 12.
[0036]
The gain calculation circuit 111 calculates a gain coefficient GS according to the detection signal S2. Here, the gain calculation circuit 111 is provided with a hysteresis characteristic in the relationship between the detection signal S2 and the gain coefficient GS so that the gain coefficient GS calculated when the detection signal S2 increases and decreases when the detection signal S2 decreases. . Hereinafter, the hysteresis will be described with reference to the graph of FIG.
[0037]
When the detection signal S2 increases, the gain coefficient GS maintains Vb until the value of the detection signal S2 reaches Eub, and gradually decreases from Vb until the value of the detection signal S2 reaches Eu1 and then reaches Eu1. I do. When the value of the detection signal S2 reaches Eu1, the gain coefficient GS becomes V1 (<Vb). Further, the gain coefficient GS gradually decreases from V1 until the value of the detection signal S2 reaches Eu1 and reaches Eua, and becomes Va (<V1) when the value of the detection signal S2 reaches Eua. Keep this value.
[0038]
When the detection signal S2 starts to decrease, the gain coefficient GS maintains Va until the value of the detection signal S2 reaches Eda (> Eua), and after the value of the detection signal S2 reaches Eda, Ed1 (> Eu1). , And gradually increases from Va. When the value of the detection signal S2 reaches Ed1, the gain coefficient GS becomes V1 (> Va). Further, the gain coefficient GS gradually increases from V1 until the value of the detection signal S2 reaches Ed1 until it reaches Edb (> Eub), and when the value of the detection signal S2 reaches Edb, Vb (> V1) ), And this value is maintained thereafter. That is, when the detection signal S2 decreases, the gain coefficient GS increases earlier than when it increases. In other words, when the detection signal S2 increases, the gain coefficient GS decreases earlier than when it decreases.
[0039]
As described above, by providing the gain calculation circuit 111 with the hysteresis characteristic, when a scratched or dirty portion of the optical disc 20 is reproduced, the open loop gain of the PLL circuit 12 is decreased early while In the case where a normal part is reproduced by removing a dirty part, the open loop gain of the PLL circuit 12 can be increased earlier to return to a normal state earlier.
[0040]
The control signal generation circuit 112 generates a control signal S3 according to the gain coefficient GS output from the gain calculation circuit 111. Further, when the missing signal S4 output from the missing detecting circuit 13 is input, the control signal generating circuit 112 sets the control signal S3 to a predetermined value regardless of the gain coefficient GS. Here, the missing detection circuit 13 monitors the RF signal output from the RF amplifier 16 and outputs a missing signal S4 when a missing (dropout) is detected. Note that the missing detection circuit 13 can be omitted.
[0041]
In the present embodiment, the control signal S3 is composed of the signals S11, S12 and S13, the signals S21, S22 and S23, the signals S31, S32 and S33, and the signals S41, S42 and S43. A specific example of the relationship between the gain coefficient GS and the control signal S3 will be described later.
[0042]
In addition, the control signal generation circuit 112 can change the control signal S3 according to the reproduction speed control signal S5. Specifically, the control signal S3 is changed so that the gain of the PLL circuit 12 is increased as the reproduction speed of the optical disk 20 increases. Thereby, the responsiveness of the PLL circuit 12 to the reproduction signal S1 having a high reproduction speed is improved, and the information recorded on the optical disc 20 can be read more accurately.
[0043]
Further, the control signal generation circuit 112 maintains the value for a predetermined period specified by the timer circuit 113 after the control signal S3 changes. Thus, for example, when an abnormality occurs in the reproduction signal S1 such as a continuous scratch or dirt on the optical disk 20, the open loop gain of the PLL circuit 12 is reduced for a predetermined period in advance, and the clock CLK is reduced. An increase in jitter can be suppressed.
[0044]
Whether or not the influence of the scratches, dirt, and the like on the optical disc 20 is continuous can be predicted from the detection signal S2. That is, when the detection signal S2 continues to increase, it is considered that the influence of the scratches, dirt, and the like is continuous. The timer circuit 113 receives the detection signal S2, and if it can be predicted that the influence of the scratches and dirt is continuous, the timer circuit 113 extends the predetermined period specified for the control signal generation circuit 112. This makes it possible to reduce the open loop gain of the PLL circuit 12 for a longer period of time, for example, when the influence of scratches and dirt on the optical disc 20 continues.
[0045]
In addition, the time during which the influence of the scratches or dirt on the optical disc 20 continues due to the difference in the reproduction speed naturally differs, so the timer circuit 113 sends the control signal generation circuit 112 to the control signal generation circuit 112 in response to the reproduction speed control signal S5. The specified predetermined period can be changed. Specifically, the reciprocal of the reproduction speed of the optical disc 20 is given as the predetermined period specified by the timer circuit 113. As described above, by changing the predetermined period designated by the timer circuit 113 in accordance with the reproduction speed of the optical disk 20, an increase in jitter of the clock CLK due to scratches, dirt, and the like on the optical disk 20 can be suppressed. .
[0046]
Next, the PLL circuit 12 will be described in detail. FIG. 5 shows an internal configuration of the PLL circuit 12. The PLL circuit 12 includes a phase comparator 121, a charge pump circuit 122, a loop filter circuit 123, a voltage controlled oscillator (VCO) 124, and a frequency divider 125, and extracts a clock CLK from the reproduction signal S1.
[0047]
The phase comparator 121 compares the phase of the reproduction signal S1 with the clock CLK, and outputs signals UP and DN according to the phase difference. In the present embodiment, the signal UP is in an activated state during a period from the rising or falling edge of the reproduction signal S1 to the rising edge of the clock CLK generated next to the edge. In addition, the signal DN is assumed to be in an activated state during a period in which the clock CLK is inactivated after the signal UP is inactivated. Of course, various other ways of defining the signals UP and DN are possible.
[0048]
Further, the phase comparator 121 changes the frequency of the phase comparison according to the control signal S3 (more specifically, the signals S11 to S13) output from the gain control circuit 11. This will be described with reference to the timing chart of FIG.
[0049]
First, when (S11, S12, S13) = (1, 1, 1) for the control signal S3, the phase comparator 121 outputs the signals UP and DN for each rising and falling edge of the reproduction signal S1. Next, when (S11, S12, S13) = (1, 1, 0), the phase comparator 121 outputs the signals UP and DN every other edge of the reproduction signal S1, ie, every rising edge or every falling edge. Is output. Then, when (S11, S12, S13) = (1, 0, 0), the phase comparator 121 outputs the signals UP and DN at every second edge of the reproduction signal S1.
[0050]
The charge pump circuit 122 includes current sources 201 (current amount I1), 202 (current amount I2) and 203 (current amount I3) for current output, and current sources 204 (current amount I1) and 205 (current amount) for current inhalation. I2) and 206 (current I3), and the difference between the activated signal UP and the signal DN according to each of the signals UP and DN output from the phase comparator 121, that is, the reproduction signal S1 and the clock CLK. A current corresponding to the phase difference with the current is output and sucked.
[0051]
The current sources 201 to 203 are selectively and independently circuit-connected by switches 207, 208, and 209 controlled by a control signal S3 (more specifically, signals S31 to S33). Similarly, the current sources 204 to 206 are independently and selectively connected to circuits by switches 211, 212, and 213 controlled by signals S31 to S33. Specifically, when (S31, S32, S33) = (1, 1, 1) for the control signal S3, the current amount is I1 + I2 + I3, and when (S31, S32, S33) = (1, 1, 0) , The current amount becomes I1 + I2, and when (S31, S32, S33) = (1, 0, 0), the current amount becomes I1. When (S31, S32, S33) = (0, 0, 0), the charge pump circuit 122 enters an open state in which current is not output or drawn.
[0052]
The total current determined as described above is circuit-connected by the switch 210 controlled by the signal UP and the switch 214 controlled by the signal DN, and is output and sucked from the charge pump circuit 122. Thus, the charge pump circuit 122 can change the output and the amount of current to be sucked by appropriately controlling the signals S31 to S33.
[0053]
The configuration of the charge pump circuit 122 described above is merely an example, and other various configurations such as, for example, changing the insertion location of each switch are possible. Even if there is a difference in the configuration, if the charge pump circuit changes the amount of current in accordance with the signals S31 to S33, the effects of the present invention can be obtained.
[0054]
The loop filter circuit 123 includes resistors 301 (resistance R1), 302 (resistance R2) and 303 (resistance R3) arranged in parallel, and a capacitor 304 connected in series to the resistors 301 to 303. Integrates (smooths) the current output and drawn in from the charge pump circuit 122 with a time constant determined by the capacitor 303 and the capacitor 304, and outputs a control voltage Vct.
[0055]
The resistors 301 to 303 are independently and selectively connected to circuits by switches 305, 306, and 307 controlled by a control signal S3 (more specifically, signals S41 to S43). The time constant of the loop filter circuit 123 is determined by the combined resistance value of the resistors 301 to 303 connected by the switches 305 to 307. Specifically, when (S41, S42, S43) = (1, 1, 1) for the control signal S3, the combined resistance value is R1 // R2 // R3 (parallel connection of R1, R2 and R3), When (S41, S42, S43) = (1, 1, 0), the combined resistance value is R1 // R2 (parallel connection of R1 and R2), and (S41, S42, S43) = (1, 0, 0). ), The combined resistance value is R1. When (S41, S42, S43) = (0, 0, 0), the filtering by the loop filter circuit 123 is not performed. Thus, the time constant of the loop filter circuit 123 can be changed by appropriately controlling the signals S41 to S43.
[0056]
The configuration of the loop filter circuit 123 is merely an example, and other various configurations such as, for example, selectively connecting a plurality of capacitors arranged in parallel to a circuit are possible. Even if there is a difference in the configuration, the effects of the present invention can be obtained as long as the loop filter circuit changes the time constant by the signals S41 to S43.
[0057]
The VCO 124 generates a clock CLK0 having a frequency according to the control voltage Vct output from the loop filter circuit 123.
[0058]
The frequency divider 125 changes the frequency division ratio according to the control signal S3 (more specifically, the signals S21 to S23), divides the frequency of the clock CLK0 output from the VCO 124, and outputs the clock CLK. Specifically, when (S21, S22, S23) = (1, 1, 1) for the control signal S3, the frequency division ratio becomes 1 (a state equivalent to no frequency division), and (S21, S22, S23) = When (1, 1, 0), the division ratio is 2 (divide by 2), and when (S21, S22, S23) = (1, 0, 0), the division ratio is 3 (divide by 3). It becomes.
[0059]
Next, adjustment of the open loop gain of the PLL circuit 12 will be described in detail.
[0060]
In general, the open loop gain of the PLL circuit 12 is proportional to the phase comparison frequency of the phase comparator 121, the amount of current of the charge pump circuit 122, and the combined resistance value (that is, the time constant) of the loop filter circuit 123. It increases in inverse proportion to the frequency division ratio of the frequency divider 125. In consideration of this relationship, the control signal S3 is associated with the control level of the open loop gain of the PLL circuit 12.
[0061]
FIG. 7 shows a correspondence table between the control signal S3 and the control level of the open loop gain of the PLL circuit 12. As can be seen from the table, the control level is increased as the phase comparison frequency, the current amount, and the combined resistance value are reduced, and as the division ratio is increased. Then, as the control level increases, the open loop gain of the PLL circuit 12 decreases (see the graph showing the characteristics of the open loop gain of the PLL circuit 12 for each control level shown in FIG. 8).
[0062]
The gain control circuit 13 sets all the signals S31 to S33 to zero when the missing signal S4 is input from the missing detection circuit 13 or when the value of the detection signal S2 is extremely large and exceeds the threshold value Th (control Level I). As a result, the output of the loop filter circuit 123 is fixed, and the frequency of the clock CLK is fixed. As a result, a stable clock CLK is output without being affected by the low-reliability reproduction signal S1. At this time, the signals S11 to S13, the signals S31 to S33, and the signals S41 to S43 may have any values, for example, holding the values up to that time. In the same table, this is indicated as "K".
[0063]
By the way, when a portion such as a scratch or dirt on the optical disc 20 is reproduced, the RF signal is disturbed and the detection signal S2 increases. Then, when the spot of the scratch or dirt comes off, the detection signal S2 decreases and returns to the original level. FIG. 9 is a graph showing how the detection signal S2 changes. The change of the gain coefficient GS inside the gain control circuit 11 with respect to the change of the detection signal S2 is as already described with reference to FIG. Here, the relationship between the gain coefficient GS and the control signal S3 will be described.
[0064]
First, in FIG. 9, until time t1, the value of the detection signal S2 is equal to or less than Eub, and the detection amount of the abnormal pattern is within the normal range. At this time, the gain coefficient GS is Vb (GS = Vb), and the control level of the open loop gain of the PLL circuit 12 is “1” as can be seen from the correspondence table. Note that the control level 1 corresponds to a steady state of the PLL circuit 12.
[0065]
Next, from time t1 to time t2, the value of the detection signal S2 exceeds Eub and is equal to or less than Eu1. At this time, the gain coefficient GS is in the range from Vb to V1 (V1 ≦ GS <Vb), and the control level of the open loop gain of the PLL circuit 12 is “2” as can be seen from the correspondence table.
[0066]
Then, after time t2, at time t3, the detection signal S2 becomes maximum. After the time t3, the detection signal S2 starts to decrease and becomes Ed1 at the time t4. From time t2 to time t4, the gain coefficient GS is in the range of V1 to Va (Va ≦ GS <V1), and the control level of the open loop gain of the PLL circuit 12 is “3” as can be seen from the correspondence table. ".
[0067]
Subsequently, from time t4 to time t5, the value of the detection signal S2 is lower than Ed1 and is higher than Edb. At this time, the gain coefficient GS is in the range from Vb to V1 (V1 ≦ GS <Vb), and the control level of the open loop gain of the PLL circuit 12 is “2” as can be seen from the correspondence table.
[0068]
Then, after the time t5, the value of the detection signal S2 becomes equal to or less than Edb. At this time, the gain coefficient GS is Vb (GS = Vb), and the control level of the open loop gain of the PLL circuit 12 becomes "1" as seen from the correspondence table, and returns to the steady state.
[0069]
As described above, according to the present embodiment, when an abnormality occurs in the reproduction signal S1 due to the influence of a scratch or dirt on the optical disc 20, the open-loop gain of the PLL circuit 12 is adjusted in accordance with the detection amount of the pattern length abnormality of the reproduction signal S1. Can be adjusted. This makes it difficult for the PLL circuit 12 to follow the low-reliability reproduction signal S1, suppresses an increase in jitter of the clock CLK generated by the PLL circuit 12, and supplies a stable clock CLK. Can be. As a result, the decoding error of the reproduction signal S1 is reduced, and the reliability of the recording information reproduction of the optical disc 20 can be improved.
[0070]
In the PLL circuit 12, it is not necessary that all of the phase comparator 121, the charge pump circuit 122, the loop filter circuit 123, and the frequency divider 125 can be controlled by the control signal S3. By controlling at least one of them by the control signal S3, the open loop gain of the PLL circuit 12 can be adjusted.
[0071]
Further, in the above description, the control level of the open loop gain of the PLL circuit 12 is three levels (excluding the control level ∞), but it can be set more finely. For example, as shown in FIG. 10, for the gain coefficient GS, seven intermediate values from V1 to V7 are provided between Va and Vb. Then, using these intermediate values, as shown in FIG. 11, the control levels 1 to 9 are set by appropriately combining the phase comparison frequency, the frequency division ratio, the current amount, and the combined resistance value. Thereby, the open loop gain of the PLL circuit 12 can be adjusted more finely.
[0072]
(Second embodiment)
FIG. 12 is a configuration diagram of an optical disk device according to the second embodiment of the present invention. The optical disc device 1 'of the present embodiment includes a jitter detection circuit 10' (corresponding to a detection circuit of the present invention) instead of the abnormal pattern detection circuit 10 in the optical disc device 1 according to the first embodiment, and a PLL in the optical disc device 1. A PLL circuit 12 'having a different configuration from the circuit 12 is provided. The same components as those in the optical disc device 1 are referred to by the reference numerals shown in FIG. 1 and their detailed description is omitted, and only the jitter detection circuit 10 'and the PLL circuit 12' will be described below.
[0073]
The jitter detection circuit 10 'detects the jitter of the clock CLK and outputs a detection signal S2 indicating the detection amount to the gain control circuit 11. The correlation between the jitter of the clock CLK and the disturbance of the RF signal is substantially equal to the correlation between the detection signal S2 and the disturbance of the RF signal shown in FIG. That is, if the RF signal is disturbed when a portion of the optical disc 20 such as a scratch or dirt is reproduced, the jitter of the clock CLK increases, and when the scratch or dirt is removed, the jitter decreases and returns to the original level. . Therefore, the jitter of the clock CLK can be detected, and the open loop gain of the PLL circuit 12 'can be adjusted according to the amount of the detected jitter in the same manner as described above.
[0074]
Next, the PLL circuit 12 'will be described in detail. FIG. 13 shows the internal configuration of the PLL circuit 12 '. The PLL circuit 12 'includes a phase comparator 121', a digital operation circuit 126, a clock generation circuit 127, and a frequency divider 125, and extracts a clock CLK from the reproduction signal S1. The charge pump circuit 122, the loop filter circuit 123, and the VCO 124 in the PLL circuit 12 according to the first embodiment are all realized by analog circuits that process analog signals, whereas the PLL circuit 12 'according to the present embodiment. Has a digital circuit configuration that receives the result of the phase comparison between the reproduction signal S1 and the clock CLK and performs digital signal processing until the clock CLK is generated.
[0075]
The phase comparator 121 'compares the phase of the reproduction signal S1 with the clock CLK, and outputs a digital signal S6 indicating the result. At this time, the frequency of the phase comparison is switched according to the control signal S3 (more specifically, the signals S11 to S13) output from the gain control circuit 11.
[0076]
The digital operation circuit 126 receives the digital signal S6 output from the phase comparator 121 ', and outputs a signal S7. At this time, according to the control signal S3 (more specifically, the signals S31 to S33), an internal operation coefficient and the like are changed, and a digital operation is performed on the digital signal S6 to generate a signal S7.
[0077]
The clock generation circuit 127 generates a clock CLK0 based on the signal S7 output from the digital operation circuit 126. Then, the clock CLK0 is frequency-divided by the frequency divider 125 to generate the clock CLK. The operation of the frequency divider 125 is as described above.
[0078]
As described above, according to the present embodiment, the open loop gain of the PLL circuit 12 'can be adjusted based on the jitter of the clock CLK generated by the PLL circuit 12'.
[0079]
In the optical disk device 1 'of the present embodiment, the PLL circuit 12 according to the first embodiment may be provided instead of the PLL circuit 12'. Conversely, in the optical disc device 1 of the first embodiment, the PLL circuit 12 'according to the present embodiment may be provided instead of the PLL circuit 12.
[0080]
Further, in the PLL circuit 12 ', it is not necessary that all of the phase comparator 121', the digital operation circuit 126, and the frequency divider 125 can be controlled by the control signal S3. By controlling at least one of these by the control signal S3, the open loop gain of the PLL circuit 12 'can be adjusted.
[0081]
【The invention's effect】
As described above, according to the present invention, in the optical disk device, when a reproduced signal read from the optical disk is disturbed due to a scratch or dirt on the optical disk, the open loop gain of the PLL circuit in the optical disk device is changed. It is possible to suppress the increase of the jitter of the clock extracted from the reproduction signal by the PLL circuit, and to supply a stable clock. As a result, decoding errors of the reproduction signal can be reduced, and the reliability of reproducing the recorded information on the optical disk can be improved.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an optical disk device according to a first embodiment of the present invention.
FIG. 2 is a configuration diagram of an abnormal pattern detection circuit in the optical disk device of FIG.
FIG. 3 is a configuration diagram of a gain control circuit in the optical disk device of FIG. 1;
4 is a graph showing an input / output relationship of a gain operation circuit in the gain control circuit of FIG. 3;
FIG. 5 is a configuration diagram of a PLL circuit in the optical disc device of FIG. 1;
6 is a timing chart showing an operation of the phase comparator in the PLL circuit of FIG.
7 is a correspondence table between control signals output from the gain control circuit of FIG. 3 and control levels of the open loop gain of the PLL circuit of FIG. 5;
8 is a graph showing characteristics of the open-loop gain of the PLL circuit of FIG. 5 for each control level.
FIG. 9 is a graph showing changes in an RF signal and a detection signal when reproducing a scratched or dirty portion of an optical disc.
FIG. 10 is a graph showing the relationship between the input and output of a gain operation circuit set more finely.
FIG. 11 is a correspondence table between control signals output from the gain control circuit and control levels of the open loop gain of the PLL circuit set more finely.
FIG. 12 is a configuration diagram of an optical disc device according to a second embodiment of the present invention.
13 is a configuration diagram of a PLL circuit in the optical disc device of FIG.
[Explanation of symbols]
1,1 'optical disk device
20 optical disk
12,12 'PLL circuit
10 Abnormal pattern detection circuit (detection circuit)
10 'Jitter detection circuit (detection circuit)
11 Gain control circuit
13 Missing detection circuit
121, 121 'phase comparator
122 charge pump circuit
123 Loop filter circuit
125 divider
126 Digital Operation Circuit
127 clock generation circuit
CLK clock (clock extracted by PLL circuit)
S1 playback signal (first signal)
S2 detection signal (second signal)
S3 control signal (third signal)
S6 Digital signal

Claims (20)

An optical disc device for reproducing information recorded on an optical disc, comprising:
A PLL circuit for extracting a clock from a first signal read from the optical disc;
A detection circuit that detects an abnormality in the pattern length of the first signal and outputs a second signal indicating the detected amount;
A gain control circuit that generates a third signal in accordance with the detection amount indicated by the second signal, and controls an open loop gain of the PLL circuit by the third signal;
The gain control circuit decreases the open loop gain of the PLL circuit when the detection amount indicated by the second signal increases, and decreases the detection amount indicated by the second signal when the detection amount indicated by the second signal decreases. An optical disk device characterized by increasing an open loop gain of the PLL circuit. The optical disk device according to claim 1,
An optical disc device, wherein the detection circuit weights the second signal according to a pattern length of the first signal. The optical disc device according to claim 2,
An optical disc device, wherein the detection circuit changes a coefficient related to weighting of the second signal according to a reproduction speed of the optical disc. The optical disk device according to claim 1,
The optical disk device, wherein the detection circuit calculates an average value per a predetermined period for the detected pattern length abnormality of the first signal, and outputs the average value as the second signal. An optical disc device for reproducing information recorded on an optical disc, comprising:
A PLL circuit for extracting a clock from a first signal read from the optical disc;
A detection circuit that detects jitter of a clock extracted by the PLL circuit and outputs a second signal indicating the detected amount;
A gain control circuit that generates a third signal in accordance with the detection amount indicated by the second signal, and controls an open loop gain of the PLL circuit by the third signal;
The gain control circuit decreases the open loop gain of the PLL circuit when the detection amount indicated by the second signal increases, and decreases the detection amount indicated by the second signal when the detection amount indicated by the second signal decreases. An optical disk device characterized by increasing an open loop gain of the PLL circuit. The optical disc device according to claim 5,
The optical disc apparatus according to claim 1, wherein the detection circuit calculates an average value per predetermined period for the detected jitter of the clock, and outputs the average value as the second signal. The optical disc device according to claim 4, wherein
The optical disc apparatus according to claim 1, wherein the detection circuit changes the predetermined period according to a reproduction speed of the optical disc. The optical disc device according to claim 1, wherein
An optical disc device, wherein the gain control circuit has a hysteresis characteristic in a relationship between the second signal and control of an open loop gain of the PLL circuit. The optical disc device according to claim 1, wherein
A loss detection circuit that detects loss of a signal read from the optical disc,
The optical disc device, wherein the gain control circuit sets the third signal to a predetermined value when a loss is detected by the loss detection circuit. The optical disc device according to claim 1, wherein
The optical disc device according to claim 1, wherein the gain control circuit changes the third signal according to a reproduction speed of the optical disc. The optical disc device according to claim 1, wherein
An optical disc device, wherein the gain control circuit holds a value indicated by the third signal for a predetermined period after changing the third signal. The optical disc device according to claim 11,
An optical disc device, wherein the gain control circuit changes the predetermined period according to a reproduction speed of the optical disc. The optical disc device according to claim 11,
The optical disk device, wherein the gain control circuit changes the predetermined period according to a detection amount indicated by the second signal. The optical disc device according to claim 1, wherein
The PLL circuit includes a phase comparator that changes a frequency of a phase comparison between the first signal and a clock extracted by the PLL circuit according to a third signal generated by the gain control circuit. An optical disc device characterized by the above-mentioned. The optical disc device according to claim 1, wherein
The optical disc device according to claim 1, wherein the PLL circuit includes a charge pump circuit that changes an amount of current to be output and sucked according to a third signal generated by the gain control circuit. The optical disc device according to claim 1, wherein
The optical disk device, wherein the PLL circuit includes a loop filter circuit that changes a time constant according to a third signal generated by the gain control circuit. The optical disc device according to claim 1, wherein
An optical disc device, wherein the PLL circuit includes a frequency divider that changes a frequency division ratio in accordance with a third signal generated by the gain control circuit. The optical disc device according to claim 1, wherein
The PLL circuit comprises:
A phase comparator that performs a phase comparison between the first signal and a clock extracted by the PLL circuit, and outputs a digital signal indicating the result;
A digital operation circuit that performs an operation on a digital signal output from the phase comparator with an operation coefficient corresponding to a third signal generated by the gain control circuit;
An optical disk device, comprising: a clock generation circuit that generates a clock based on a calculation result of the digital calculation circuit. A method for controlling an open loop gain of a PLL circuit in an optical disk device for reproducing information recorded on an optical disk, comprising:
An abnormal pattern detecting step of detecting an abnormal pattern length of a signal read from the optical disc;
When the amount of abnormalities in the pattern length detected in the abnormal pattern detecting step increases, the open loop gain of the PLL circuit decreases, while the amount of abnormalities in the pattern length detected in the abnormal pattern detecting step decreases. A gain control step of increasing the open loop gain of the PLL circuit. A method for controlling an open loop gain of a PLL circuit in an optical disk device for reproducing information recorded on an optical disk, comprising:
A jitter detection step of detecting jitter of a clock extracted by the PLL circuit;
When the amount of jitter of the clock detected by the jitter detecting step increases, the open loop gain of the PLL circuit decreases, while when the amount of jitter of the clock detected by the jitter detecting step decreases, A gain control step of increasing an open loop gain of the PLL circuit.

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