JP4137450B2 - Data processing device that can continue processing with backup data - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data processing device, a data storage method, and a data reading method that can continue processing without stopping even if a failure occurs in the storage device.
[0002]
[Prior art]
In a processing device in which a program stored in a memory, for example, a flash memory is executed by the CPU, the processing device may hang up (runaway) due to an error in data (program command or the like) due to a failure in the flash memory. Therefore, in order to prevent such a hang-up, when a failure of the flash memory is detected, processing such as stopping the CPU is performed.
[0003]
For example, a subscriber line terminal (SLT) that communicates in an asynchronous transfer mode (ATM) is used to back up operational information related to monitoring and control of the device, and an application program for a CPU (for example, from a remote device). The application program for receiving the control is stored in the flash memory.
[0004]
When a failure occurs in the flash memory, the CPU executing the SLT process stops the process. Then, after the flash memory is replaced and the failure is recovered, the processing is resumed.
[0005]
[Problems to be solved by the invention]
However, if the CPU, that is, the SLT stops processing until the failure is recovered, the monitoring function stops, and in some cases, the user data (main signal) cannot be switched between operational and non-operational. It may cause a fatal failure such as interruption.
[0006]
Further, the SLT cannot be controlled from the remote device, and a failure occurs that makes the SLT state invisible to the operator.
[0007]
The present invention has been made in view of such a situation, and an object of the present invention is when a failure occurs in the storage device in a processing device that executes processing based on data stored in the storage device (memory). Even so, an object of the present invention is to provide a processing apparatus that can continue the processing without stopping.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a data processing apparatus according to a first aspect of the present invention is a data processing apparatus that is connected to an external data storage device via a communication line and performs predetermined processing on data. , Storage means for storing data, writing means for writing the data to the storage means, and data writing to the storage means before or after the writing to the storage means by the writing means via the communication line Transmitting means for transmitting to the data storage device.
[0009]
The data storage method according to the first aspect of the present invention transmits the data to an external data storage device connected via a communication line before or after the data is written to the storage means for storing the data. When a failure is detected in the storage means, data is received from the external data storage device via the communication line.
[0010]
Furthermore, a program according to the first aspect of the present invention causes a computer to execute the data storage method.
[0011]
According to the first aspect of the present invention, the data is transmitted to the external data storage device via the communication line before or after the data is written to the storage means. The transmitted data is stored in an external data storage device. Therefore, even if a failure occurs in the storage means and the data stored in the storage means cannot be read correctly or data cannot be correctly written in the storage means, the data processing device receives the data from the external storage device. And processing can be executed according to the received data. Thereby, even if a failure occurs in the storage means, the processing can be continued without stopping.
[0012]
A data processing device according to a second aspect of the present invention is a data processing device that is connected to an external data storage device in which backup data is stored in advance via a communication line and performs predetermined processing on the data. The storage means for storing data, the inspection means for inspecting the presence or absence of a failure in the storage means when reading the data stored in the storage means, and when the failure is detected by the inspection means, Receiving means for receiving data for backup of the read data from the external data storage device via the communication line.
[0013]
In addition, the data reading method according to the second aspect of the present invention is a data processing for connecting to an external data storage device in which backup data is stored in advance via a communication line and performing predetermined processing on the data. A data reading method for an apparatus, wherein when reading data stored in a storage means for storing data, the storage means is inspected for a fault, and if a fault is detected by the inspection, a backup of the read data is performed. Data is received from the external data storage device via the communication line.
[0014]
According to the second aspect of the present invention, when the data stored in the storage means is read out, the storage means is inspected for a failure, and if a failure is detected, the data for backup of the read data is transferred to the communication line. Via an external data storage device. Therefore, a device that has received this data can execute processing using the received data. Therefore, even if a failure occurs in the storage means, the processing can be continued without stopping.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a configuration of a communication system according to an embodiment of the present invention. This communication system includes an element manager 1, a subscriber line terminal (SLT) 2 ₁ And 2 ₂ , Optical Line Termination (OLT) 3 ₁ ~ 3 _Four , And user terminal 4 ₁ ~ 4 ₈ Have
[0016]
This communication system includes a user terminal 4 ₁ ~ 4 ₈ Is a data exchange network that switches (exchanges) end user data (user voice, text data, image data, etc., hereinafter referred to as “user data”).
[0017]
Here, as an example, two SLT2 ₁ And 2 ₂ However, there may be one SLT or three or more SLTs. Further, although two OLTs are shown for each SLT, other numbers may be used. Furthermore, user terminals other than the number shown in the figure may be provided. In the following, SLT2 ₁ And 2 ₂ Are collectively referred to as “SLT2” unless it is particularly necessary to distinguish them. Similarly, OLT3 ₁ ~ 3 _Four Are collectively referred to as OLT3 and user terminal 4 ₁ ~ 4 ₈ Are collectively referred to as user terminal 4.
[0018]
The element manager 1 and the SLT 2 are connected by a communication network (for example, a LAN such as Ethernet) 5. The element manager 1 and the SLT 2 have identification information (for example, IP address) in the communication network 5 and communicate with each other based on this identification information.
[0019]
Between the SLTs 2 and between the SLT 2 and the OLT 3 are connected by an optical fiber cable, and data is communicated between them by an asynchronous transfer mode (ATM). The OLT 3 and the user terminal 4 are connected by an optical fiber cable or an electric line according to the user terminal 4, and data is communicated between them by ATM, IP packet, or the like according to the user terminal.
[0020]
The element manager 1 includes a computer, a workstation, and the like. The element manager 1 transmits a program (for example, firmware) necessary for the SLT 2 to the SLT 2 via the communication network 5 and, as will be described later, data such as a program and monitoring information transmitted from the SLT 2 via the communication network 5 Is stored in a storage device (hard disk, optical disk, semiconductor memory, etc.) 11 for backup. Then, when a failure occurs in the internal memory of the SLT 2 and the data stored in the memory cannot be used, the element manager 1 transmits the data stored in the storage device 11 for backup to the SLT 2 To do.
[0021]
The user terminal 4 is a terminal used by an end user, such as a telephone or a personal computer. The user terminal 4 transmits user data to the OLT 3. The OLT 3 switches (exchanges) user data from the user terminal 4 or SLT 2 connected to the OLT 3 to another user terminal 4 or SLT 2. The SLT 2 exchanges user data transmitted from the user terminal 4 via the OLT 3 with another OLT 3 or another SLT 2.
[0022]
FIG. 2 is a block diagram showing a detailed configuration of the SLT 2. The SLT 2 includes a monitoring device 21, a switch 22, and interface devices 23 to 25.
[0023]
The interface device 23 is connected to the other SLT 2, and the interface devices 24 and 25 are connected to the OLT 3. The interface devices 23 to 25 perform mutual conversion between an electric signal and an optical signal, processing of a layer 1 (and 2) communication protocol, and the like. Two interface devices 23 to 25 are provided. When a failure occurs in one of the interface devices 23 to 25, the interface device 23 to 25 is switched by the monitoring device 21 and the other is used.
[0024]
The switch 22 performs switching of user data from the OLT 3 input via the interface device 24 or 25 and user data from the other SLT 2 input via the interface device 23, and these user data are transferred to other interfaces. Output to the device.
[0025]
The monitoring device 21 monitors the state of the switch 22 and the interface devices 23 to 24, switches the interface devices 23 to 25, and the like. FIG. 3 is a block diagram illustrating a detailed configuration of the monitoring device 21. FIG. 4 is a block diagram showing a detailed configuration of the flash memory unit 36 of the monitoring device 21.
[0026]
The monitoring device 21 includes a LAN (Local Area Network) port 31, a CPU 32, a boot ROM 33, a management information storage EEPROM 34, a work SDRAM 35, and a flash memory unit 36. The flash memory unit 36 includes four flash memories 41a to 41d, four parity check circuits 42a to 42d, and registers 43 and 44.
[0027]
The CPU 32, the LAN port 31, the boot ROM 33, the management information storage EEPROM 34, the work SDRAM 35, and the flash memory unit 36 are interconnected by a bus (including an address bus and a data bus).
[0028]
The LAN port 31 is an interface device for communicating with the element manager 1 via the Internet 5 and mainly executes processing of communication protocols of layers 1 and 2.
[0029]
The boot ROM 33 stores a boot program that is activated when the SLT 2 (monitoring device 21) is started up. In the management information storing EEPROM 34, management information such as identification information (IP address, MAC address) of the SLT 2 is stored. The work SDRAM 35 is a memory used for a work area of the CPU 32, and temporarily stores a program stored in the flash memory unit 36, data generated by processing of the CPU 32, and the like.
[0030]
The flash memory unit 36 stores operation information for SLT2 backup, application programs (firmware), and the like. A plurality of types of application programs may be provided. In this case, flash memory units 36 corresponding to the number of types of application programs may be provided.
[0031]
The flash memories 41a to 41d of the flash memory unit 36 are flash memories having the same configuration. As an example, each memory cell of the flash memories 41a to 41d has 9 bits. Data (application program instructions, operation information, etc.) is stored in 8 bits out of 9 bits, and a parity check bit for 8 bits of data is stored in the remaining 1 bit.
[0032]
At the time of data writing to the flash memories 41a to 41d, the CPU 32 outputs to the flash memories 41a to 41d an address for designating a memory cell to which data is written and data for writing (and a write signal by a signal line (not shown)). The address is given simultaneously to the flash memories 41a to 41d. The data to be written is 32 bits, and this 32-bit data is divided into four 8-bit data from the first bit to the 32nd bit, and each 8-bit data is given to the flash memories 41a to 41d, respectively. , Stored in the memory cell indicated by the address.
[0033]
At the time of data writing, each 8-bit data is also supplied to the parity check circuits 42a to 42d. The parity check circuits 42a to 42d generate parity bits for each 8-bit data, and write the parity bits to the ninth bits of the memory cells of the flash memories 41a to 41d indicated by the addresses. The parity bit may be odd parity or even parity.
[0034]
On the other hand, when data is read from the flash memories 41a to 41d, the CPU 32 outputs addresses (and read signals by signal lines (not shown)) specifying memory cells to which data is read to the flash memories 41a to 41d. Each of the flash memories 41a to 41d outputs 8-bit data from the memory cell specified by the address. As a result, a total of 32-bit data is read out and applied to the CPU 32.
[0035]
At the time of this data reading, in addition to the 8-bit data from the flash memories 41a to 41d, parity check bits corresponding to the 8-bit data are given from the flash memories 41a to 41d to the parity check circuits 42a to 42d, respectively.
[0036]
The parity check circuits 42 a to 42 d perform a parity check by collating the 8-bit data and the parity check bit given from the flash memories 41 a to 41 d, respectively, and output the check result to the register 43. The check result is, for example, “1” of 1-bit data when a parity error has occurred, and “0” of 1-bit data when normal (when no parity error has occurred).
[0037]
The register 43 has 4 bits, for example. Each bit corresponds to each of the parity check circuits 42a to 42d, and stores the check results of the parity check circuits 42a to 42d. Therefore, it is possible to determine which of the flash memories 41a to 41d has caused a parity error depending on which of the 4 bits is “1”.
[0038]
The check result stored in the register 43 is read by the CPU 32, and the CPU 32 determines whether or not there is a parity error.
[0039]
The register 44 has, for example, 4 bits, and each bit stores the presence / absence of the output of the respective busy signals of the flash memories 41a to 41d. This busy signal is a signal output from the flash memories 41a to 41d for a predetermined time after writing data to the flash memories 41a to 41d or after erasing data stored in the flash memories 41a to 41d. It is. While this busy signal is being output, data cannot be written or erased, and even when data is read, the data value is in a toggle state (described later) and remains constant while the busy signal is being output. Because there is no, accurate data cannot be read.
[0040]
The predetermined time during which the busy signal is output is determined in advance according to the type of memory circuit (for example, a semiconductor chip) used in the flash memories 41a to 41d. Further, the time when the busy signal is output after data writing and the time when the busy signal is output after data erasure may be the same or different. In the following, the time when the busy signal is output after data erasure is T1, and the time when the busy signal is output after data writing is T2.
[0041]
When data is written to the flash memory 41, the data is written after the data in the memory cell at the data write address is once erased.
[0042]
While the busy signal is output, the corresponding bit of the register 44 is set to “1”, and when the output of the busy signal is stopped, the bit is set to “0”.
[0043]
The 4-bit data stored in the register 44 is read by the CPU 32. After writing the data, the CPU 32 measures the time T2 with, for example, a watchdog timer, and if the bit value of the register 44 is “1” even after the time T2 has elapsed, the flash memory corresponding to the bit has failed. It can be determined that it has occurred.
[0044]
Similarly, the CPU 32 measures the time T1 after erasing data, and if the value of the bit of the register 44 is “1” even after the time T1 has elapsed, a failure occurs in the flash memory corresponding to the bit. Can be determined.
[0045]
Some flash memories do not have a busy signal output terminal. In this case, the presence of a failure is checked by polling. That is, the CPU 32 reads the written data at a predetermined time interval after the data is written. During time T2 after data writing, at least one bit of the read data is in a toggle state in which “0” and “1” are alternately repeated. On the other hand, after the time T2, when the flash memory is normal, the toggle state is canceled and the written data can be read accurately. When a failure occurs in the flash memory, the toggle state is not resolved and the written data cannot be read accurately.
[0046]
Therefore, even after the elapse of time T2, the CPU 32 can determine whether the flash memory is normal or has a failure by determining whether the flash memory is in a toggle state by polling. .
[0047]
Similarly, the presence or absence of a failure in the flash memory can be determined by detecting the presence or absence of the toggle state after the time T1 has elapsed by polling after the data is erased.
[0048]
In the communication system having such a configuration, the CPU 32 is stopped when a failure occurs in the flash memories 41a to 41d of the SLT 2 (hereinafter collectively referred to as “flash memory 41” unless otherwise required). The processing of the CPU 32 (SLT2) for continuing the processing without any problem will be described below. There are several methods for this processing, and will be described separately below.
[0049]
(1) First method
The first method is to receive the data portion where the parity error has occurred from the element manager 1. FIG. 5 is a flowchart showing the flow of processing according to the first method.
[0050]
Step S2 is a process executed when the CPU 32 writes data to the flash memory 41 during execution of a boot program stored in the boot ROM 33 or an application program stored in the flash memory 41 or the work SDRAM 35, for example. is there.
[0051]
When data (for example, monitoring information) is written to the flash memory 41 during execution of the boot program or application program (S1), the CPU 32 writes the same data into the LAN by packet after the data is written to the flash memory 41. It transmits to the element manager 1 through the port 31 (S2).
[0052]
FIG. 6 shows a data structure of a packet (payload portion) transmitted from the SLT 2 to the element manager 1. This packet is, for example, an IP packet. In FIG. 6, illustration of the header portion of the packet is omitted, and only the payload portion is illustrated. The payload portion of the packet includes SLT identification information, flash memory identification information, address, and data.
[0053]
“SLT identification information” is identification information (for example, an IP address) of SLT 2 that transmits data.
[0054]
“Flash memory identification information” is information for identifying a flash memory in units of memory circuits (semiconductor chips). For example, in the configuration shown in FIG. 4, the information for identifying each of the flash memories 41a to 41d is the flash memory identification information. As described above, when a plurality of flash memory units 36 are provided according to the type of application program, the identification information of each flash memory unit 36 and the identification information of each memory circuit in the flash memory unit 36 are used. is there.
[0055]
“Address” is the address of the flash memory 41 to which data is written, and “Data” is data written to the flash memory 41.
[0056]
When the packet transmitted from the SLT 2 is an IP packet, the IP address of the source SLT 2 is included in the header portion of the IP packet. In this case, the “SLT identification information” can be omitted.
[0057]
The element manager 1 stores the packet transmitted from the SLT 2 in its own storage device 11. The data structure stored in the storage device 11 of the element manager 1 is also the same as the data structure of the payload portion of the packet shown in FIG.
[0058]
In this way, the same data as the data written to the flash memory 41 by the CPU 32 is stored in the element manager 1 for backup, and the element manager 1 has the same data as the data stored in the flash memory 41. Note that step S2 may be executed before step S1.
[0059]
On the other hand, steps S4 to S7 are processes executed when the CPU 32 writes data into the flash memory 41 during execution of a boot program or an application program, for example.
[0060]
If data is read from the flash memory 41 during execution of the boot program or application program (S3), the CPU 32 reads the data from the flash memory 41 and then reads the contents of the register 43 (S4). In this register 43, the parity check results of the data read by the CPU 32 are stored by the parity check circuits 42a to 42d.
[0061]
Subsequently, the CPU 32 determines whether a parity error has occurred based on the value of the register 43 (S5). When a parity error has occurred (for example, when at least one of the 4 bits is “1”) (YES in S5), the CPU 32 sends a data transmission request of the address where the parity error has occurred by a packet. It transmits to the element manager 1 (S6).
[0062]
The packet of this data transmission request includes “SLT identification information”, “flash memory identification information”, and “address” in the payload portion in substantially the same manner as the packet shown in FIG. Information indicating a data transmission request is included.
[0063]
When the element manager 1 receives the data transmission request from the SLT 2, the element manager 1 reads the data corresponding to the SLT identification information, the flash memory identification information, and the address included in the data transmission request from the storage device 11, and transmits the read data to the data transmission It returns to SLT2 which transmitted the request. As a result, the same data as the data in which the parity error is detected is returned from the element manager 1 to the SLT 2.
[0064]
Upon receiving the returned data, the CPU 32 of the SLT 2 stores this data in, for example, the work SDRAM 35, and thereafter continues the program processing based on the returned data.
[0065]
On the other hand, if no parity error has occurred in step S5 (NO in S5), the CPU 32 continues the processing of the program based on the read data.
[0066]
As described above, according to the first method, even when a failure occurs in the flash memory 41 and accurate data cannot be read, the CPU 32 uses the data stored in the element manager 1 for backup. Thus, program execution can be continued without stopping the operation.
[0067]
Note that the data received from the element manager 1 in step S7 may be 32-bit data that is simultaneously read from the four flash memories 41a to 41d. Of the 32-bit data, 8-bit data in which a parity error is detected. (Or 16-bit, 24-bit data) portion.
[0068]
The processes in steps S2 and S4 to S7 may be described as program instructions in the boot program or application program, or an interrupt is generated in the CPU 32 when data is written to or read from the flash memory 41. In such a configuration, it may be described as a program for this interrupt processing.
[0069]
Further, when the data (for example, application program) stored in the flash memory 41 is downloaded from the element manager 1, the data is stored in advance in the storage device 11 of the element manager 1, so that the flash The process of step S2 executed when data is written to the memory 41 can be omitted.
[0070]
(2) Second method
In the second method, transmission of an alarm is added to the first method.
[0071]
In step S5 (see FIG. 5) of the first method, the CPU 32 transmits an alarm to the element manager 1 when a parity error occurs. This alarm can be transmitted together with the data transmission request in step S6, or can be transmitted before or after the data transmission request separately from the data transmission request. When the alarm is transmitted together with the data transmission request, information indicating the alarm is added to the rear part of the data shown in FIG.
[0072]
The element manager 1 that has received the alarm displays the alarm on a display device (CRT display, liquid crystal display, etc.) or stores it in a storage device. Thereby, it is possible to notify the operator, administrator, etc. of the element manager 1 that the flash memory 41 needs to be replaced.
[0073]
Further, the alarm to be displayed or stored can include the flash memory identification information in which a parity error is detected and the address of the flash memory (for example, address 0x100). As a result, the flash memory where the failure is detected can be easily identified, and the time required for repair and maintenance can be shortened.
[0074]
When the element manager 1 receives a data transmission request from the SLT 2 without the SLT 2 transmitting such an alarm, the alarm may be automatically displayed / output / stored upon reception of the data transmission request. it can.
[0075]
(3) Third method
In the third method, when a parity error occurs, the SLT 2 receives data from the element manager 1 in units of segments of the flash memory 41 or in units of memory circuits (semiconductor chips) and stores them in the work SDRAM 35.
[0076]
A segment is a unit in which a plurality of continuous memory cells of one memory circuit (semiconductor chip) of the flash memory 41 are grouped. For example, segments are set in various units such as 1 Kbyte unit and 16 Kbyte unit.
[0077]
This third method is almost the same as the reading process (S3 to S7) of FIG. 5, but when a data transmission request is transmitted to the element manager 1 in step S6, the element manager 1 is included in this data transmission request. All data of the segment or memory circuit including the address is transmitted to SLT2.
[0078]
When receiving the data transmitted from the element manager 1, the CPU 32 of the SLT 2 stores this data in the work SDRAM 35, and then continues the processing of the program.
[0079]
Data read / write from the address corresponding to the flash memory 2 thereafter is data read / write of the work SDRAM 35.
[0080]
Thus, even if a failure (parity error) is detected at a different address of the same flash memory 41 by receiving data from the element manager 1 in segment units or memory circuit units, the data transmission request and the request The transmission of data corresponding to 1 from the element manager 1 is omitted. Thereby, immediately after the parity error is detected, the traffic amount of the communication network 5 temporarily increases, but the number of data transmission / reception between the SLT 2 and the element manager 1 decreases. As a result, the communication quality of the communication network 5 except immediately after the parity error detection can be improved.
[0081]
(4) Fourth method
When data (application programs, etc.) is stored in advance in the flash memory 41 at the time of factory shipment, etc., and this data is used when SLT2 is started up (when power is turned on, reset, power is restored after a momentary power interruption, etc.) (Including the process of copying (developing) data (application program or the like) stored in the flash memory 41 to the work SDRAM 35), when a failure is detected in the flash memory 41, it is stored in the flash memory 41. It is also possible to download all of the data from the element manager 1 to the work SDRAM 35 of the SLT 2 and to start up the SLT 2 using the downloaded data.
[0082]
In this case, the same data as the data stored in the flash memory 41 is stored in advance in the storage device 11 of the element manager 1. In addition, a process of downloading all data stored in the flash memory 41 from the element manager 1 is incorporated into the boot program at the time of starting up the SLT 2.
[0083]
In this download process, the transmission request in step S6 in the read process of FIG. 5 described above becomes a transmission request for all data in the flash memory 41, and reception of data in step S7 becomes reception of all data in the flash memory 41.
[0084]
As a result, even if a failure occurs in the flash memory 41 after power-on, recovery from an instantaneous power interruption, reset, or the like, the SLT 2 can be started up without stopping the CPU 32. Can also be used.
[0085]
(5) Fifth method
The fifth method is a method of detecting a failure in writing data to the flash memory 41 and a countermeasure when a failure is detected.
[0086]
FIG. 7 is a flowchart showing a flow of processing at the time of data writing to the flash memory 41. When data is written to the flash memory 41, the data at the writing location is erased before writing. Therefore, first, the CPU 32 erases the data of the memory cells (each memory cell of the four flash memories 41a to 41d) to which the data (32-bit data) of the flash memory 41 is written (S11).
[0087]
Subsequently, the CPU 32 reads the value of the register 43 after a predetermined time T1 after erasure (S12). When at least one 4-bit value of the register 43 is “1”, the CPU 32 determines that a failure has occurred in the flash memory 41 (YES in S13) and stops writing data in the flash memory 41. Then, the data (32-bit data) is transmitted to the element manager 1 (S18). Transmission is performed by the packet shown in FIG.
[0088]
The element manager 1 stores the received packet in the storage device 11. Thereafter, when the CPU 32 uses this data, the data is received from the element manager 1 and used (S19).
[0089]
On the other hand, when the value of the register 43 is 0 (NO in S13), the CPU 32 writes data (32-bit data) to the flash memory 41 (S14).
[0090]
Subsequently, the CPU 32 reads the value of the register 43 after a predetermined time T2 after writing (S12). If at least one of the four bits of the register 43 is “1”, the CPU 32 determines that a failure has occurred in the flash memory 41 (YES in S13) and is the same as the data written in step S14. Is transmitted to the element manager 1 by the packet shown in FIG. 6 (S18). Thereafter, the process of step S19 described above is executed.
On the other hand, when the value of the register 43 is 0 in step S16 (NO in S16), the CPU 32 has not failed in the flash memory 41. Therefore, the data written in the flash memory 41 is not stored in the flash memory 41. And then the written data is read out from the flash memory 41 (S17).
[0091]
As a result, even when a failure is detected when erasing / writing data in the flash memory 41, the failure can be dealt with without stopping the processing of the SLT2.
[0092]
As in the second method described above, when a failure is detected during erasure and / or writing, the CPU 32 notifies the element manager 1 that a failure has been detected in the flash memory 41. Can also be sent.
[0093]
(6) Other embodiments
A spare flash memory unit having the same configuration as that of the flash memory unit 36 can be provided in the monitoring device 21.
[0094]
In this case, the data can be written into the flash memory of the spare flash memory unit instead of the process of step S2 (see FIG. 5) of the first method described above or together with the process of step S2. Then, instead of the processing in steps S6 and S7, data may be read from the flash memory of the spare flash memory unit.
[0095]
Similarly, in the third method, data can be stored in a spare flash memory unit, and data can be read from the spare flash memory unit in segments or memory circuits.
[0096]
Also in the fourth method, data such as an application program is stored in the flash memory of the spare flash memory unit, and if a failure is detected in the flash memory 41, the data is transferred from the spare flash memory unit. Can also be read. In the fourth method, when data is downloaded from the element manager 1 when a failure of the flash memory 41 is detected, the downloaded data is stored in the flash memory of the spare flash memory unit, not in the work SDRAM. You can also
[0097]
Further, also in the fifth method, when a failure is detected in the flash memory 41 after erasing or writing, the data is stored not in the element manager 1 but in the flash memory of the spare flash memory unit. Data can be read from the flash memory for use.
[0098]
When a plurality of flash memory units 36 are provided according to the type of application program, a spare flash memory unit (the same capacity of the flash memory) is provided for each of the plurality of flash memory units 36. It is also possible to provide one common spare flash memory unit for the plurality of flash memory units 36. When a failure is detected in any of the plurality of flash memory units 36, data can be stored in the spare flash memory unit.
[0099]
Further, by providing a plurality of spare flash memory units, when a fault is detected in one spare flash memory unit, data can be stored in another spare flash memory.
[0100]
(Supplementary note 1) A data processing device connected to an external data storage device via a communication line and performing predetermined processing on data,
Storage means for storing data;
Writing means for writing the data into the storage means;
Transmitting means for transmitting the data to the external data storage device via the communication line before or after the data is written to the storage means by the writing means;
A data processing apparatus comprising:
[0101]
(Appendix 2) In Appendix 1,
After writing data to the storage means by the writing means, further comprising a first inspection means for inspecting the storage means for failure,
The transmission means transmits the data to the external data storage device when a failure is detected by the first inspection means.
Data processing device.
[0102]
(Supplementary Note 3) A data processing apparatus that performs predetermined processing on data,
Storage means for storing data;
Auxiliary storage means for storing the data;
Writing means for writing the data into the storage means;
Auxiliary writing means for writing the data to the auxiliary storage means before or after writing the data to the storage means by the writing means;
A data processing apparatus comprising:
[0103]
(Appendix 4) In Appendix 3,
After writing data to the storage means by the writing means, further comprising a first inspection means for inspecting the storage means for failure,
The auxiliary writing means writes the data into the auxiliary storage means when a failure is detected by the first checking means;
Data processing device.
[0104]
(Appendix 5) In Appendix 2 or 4,
The storage means is a flash memory;
When the busy signal output from the flash memory for a predetermined time after the data is written to the flash memory is output beyond the predetermined time after the data is written to the flash memory, Judge that there is a problem with
Data processing device.
[0105]
(Appendix 6) In Appendix 2 or 4,
The storage means is a flash memory;
The first checking means reads the data from the flash memory at a predetermined time interval after writing the data to the flash memory, and changes every time the read data is read beyond a predetermined time. If it is determined that the flash memory is faulty,
Data processing device.
[0106]
(Appendix 7) In Appendix 1 or 2,
An erasing unit for erasing at least the data stored in the storage unit for storing the data before writing the data in the storage unit;
A second inspection means for inspecting the storage means for failure after erasing data by the erasure means;
Further comprising
The transmission means transmits the data to the external data storage device when a failure is detected by the second inspection means.
Data processing device.
[0107]
(Appendix 8) In Appendix 3 or 4,
An erasing unit for erasing at least a storage location of the storage unit for storing the data before writing the data to the storage unit;
A second inspection means for inspecting the storage means for failure after erasing the data by the erasure means;
Further comprising
The auxiliary writing means writes the data into the auxiliary storage means when a failure is detected by the second checking means;
Data processing device.
[0108]
(Appendix 9) In Appendix 7 or 8,
The storage means is a flash memory;
When the busy signal output from the flash memory for a predetermined time after the data in the flash memory is erased by the erasing means is output beyond the predetermined time, the second checking means Determining that the flash memory is faulty,
Data processing device.
[0109]
(Appendix 10) In Appendix 7 or 8,
The storage means is a flash memory;
The second checking means reads the data from the flash memory at a predetermined time interval after erasing the data in the flash memory by the erasing means, and reads the read data beyond a predetermined time each time. If it has changed, it is determined that the flash memory has a failure.
Data processing device.
[0110]
(Appendix 11) In Appendix 1, 2, or 7,
The external data storage device stores in advance the same data as the data stored in the storage means,
A third inspection means for inspecting whether or not there is a failure in the storage means when data is read from the storage means;
Receiving means for receiving the same data as the read data from the external data storage device via the communication line when a failure is detected by the third checking means;
A data processing apparatus further comprising:
[0111]
(Appendix 12) In Appendix 11,
The storage means is a flash memory;
The third checking means performs a parity check of the data read from the flash memory, and determines that the flash memory is faulty in the case of a parity check error;
Data processing device.
[0112]
(Supplementary note 13) In Supplementary note 11 or 12,
A data processing apparatus further comprising auxiliary storage means for storing data received by the data receiving means.
[0113]
(Supplementary note 14) In Supplementary note 2, 7, 11, 12, or 13,
A data processing apparatus, further comprising a failure notification means for notifying the data storage device that a failure has been detected in the storage means before or after transmission of the data by the transmission means.
[0114]
(Supplementary note 15) A data processing device connected via a communication line to an external data storage device in which backup data is stored in advance, and performing predetermined processing on the data,
Storage means for storing data;
An inspection means for inspecting whether or not there is a failure in the storage means when reading the data stored in the storage means;
Receiving means for receiving backup data of the read data from the external data storage device via the communication line when a failure is detected by the checking means;
A data processing apparatus comprising:
[0115]
(Supplementary Note 16) Before or after writing data in the storage means for storing data, the data is transmitted to an external data storage device connected via a communication line,
When a failure is detected in the storage means, data is received from the external data storage device via the communication line.
Data storage method.
[0116]
(Supplementary note 17)
A procedure for transmitting the data to an external data storage device connected via a communication line before or after writing the data in the storage means for storing data, and when a failure is detected in the storage means, Receiving data from the external data storage device via the communication line;
A program for running
[0117]
(Supplementary note 18) A data reading method for a data processing apparatus connected to an external data storage device in which backup data is stored in advance via a communication line and performing predetermined processing on the data,
When reading the data stored in the storage means for storing data, the storage means is inspected for failure,
When a failure is detected by the inspection, backup data for the read data is received from the external data storage device via the communication line.
Data reading method.
[0118]
(Supplementary Note 19) A computer connected to an external data storage device in which backup data is stored in advance via a communication line and performing predetermined processing on the data,
A procedure for inspecting whether there is a failure in the storage means when reading data stored in the storage means for storing data;
When a failure is detected by the inspection, a procedure for receiving backup data of the read data from the external data storage device via the communication line;
A program for running
[0119]
【The invention's effect】
According to the present invention, even if a storage means (for example, flash memory) fails, the data processing apparatus (for example, SLT monitoring apparatus) can continue the processing without stopping the processing.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a communication system according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a detailed internal configuration of an SLT.
FIG. 3 is a block diagram showing a detailed configuration of a monitoring device.
FIG. 4 is a block diagram showing a detailed configuration of a flash memory unit of the monitoring device.
FIG. 5 is a flowchart showing a flow of processing by the first method of SLT when a failure is detected in the flash memory.
FIG. 6 shows a data structure of a packet transmitted from the SLT to the element manager.
FIG. 7 is a flowchart showing a flow of processing when data is written to the flash memory.
[Explanation of symbols]
1 Element manager
2 ₁ , 2 ₂ Subscriber line terminal (SLT)
21 Monitoring device
32 CPU
36 Flash memory unit
41a to 41d flash memory
42a to 42d Parity check circuit
43,44 registers

Claims (3)

A data processing device that is connected to an external data storage device via a communication line and performs predetermined processing on data,
Storage means for storing data;
Writing means for writing the data into the storage means;
Transmitting means for transmitting the data to the external data storage device via the communication line before or after the data is written to the storage means by the writing means;
Before the data is written to the storage means, the data is erased from the storage means, and after the first time has elapsed after the data is erased, the storage means is checked for failure and the writing means Inspection means for inspecting the storage means for failure after a second time has elapsed after data is written to the storage means;
The data processing apparatus, wherein the transmission means transmits the data to the external data storage device when the failure is detected by the inspection means. Before or after writing data to the storage means for storing data, the data is transmitted to an external data storage device connected via a communication line;
Before the data is written to the storage means, the data is erased from the storage means, and after the first time after the data is erased, the storage means is checked for failure;
After the second time elapses after the data is written to the storage means, the storage means is checked for failure,
When a failure is detected in the storage means by the inspection, data is received from the external data storage device via the communication line.
Data storage method. Computer
A procedure for transmitting the data to or from an external data storage device connected via a communication line before or after the data is written to the storage means for storing the data;
Before the data is written to the storage means, the data is erased from the storage means, and after the first time after the data is erased, the storage means is checked for failure;
A procedure for inspecting the storage means for failure after a second time has elapsed after the data has been written to the storage means;
A procedure for receiving data from the external data storage device via the communication line when a failure is detected in the storage means by the inspection;
A program for running

Images