JP2008217811A - Disk controller using nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve performance, maintainability and reliability of a disk controller itself by implementing making the most of its characteristic by using a semiconductor nonvolatile memory as an exchange medium of a semiconductor memory device and a disk device used for the disk controller. <P>SOLUTION: A nonvolatile memory part is composed of three kinds of memory modules including an actual data storage device, a spare storage device and a parity redundant data device, and is constituted by implementing in parallel. Data are held in the respective devices for each smallest block unit, and update information and a protective code are arranged as spare information for each block, to monitor the obstacle and failure of a nonvolatile memory device. The nonvolatile memory part is provided with the diagnostic rewrite function of finding out a failure block by enabling read protection and write protection for each divided block of the memory device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a disk controller using a non-volatile memory, and in particular, makes use of the characteristics of the non-volatile memory so that it can be easily mounted and replaced in parallel, and functions as an alternative to other memories and disks. The present invention relates to a disk control device using a disk.

  In general, a storage device of an information processing system such as a computer has a pyramid structure in which an access speed and a cost per capacity are in inverse proportion. Typical examples include a semiconductor memory having a high access speed from a CPU used for a main storage device but having a disadvantageous capacity / cost ratio, and an HDD (magnetic disk device) having the opposite characteristics used as an auxiliary storage device. MT (magnetic tape device).

  As a semiconductor memory device used for the main memory device, a volatile memory is usually used because of its simple structure and large capacity. A semiconductor nonvolatile memory typified by a flash EEPROM is mainly used for a memory card or the like by utilizing the characteristic of being nonvolatile.

  Compared with magnetic disk devices, semiconductor nonvolatile memories such as flash EEPROMs have the characteristics of small size, low power consumption, and high reliability. As mentioned above, they are used as memory cards for portable information terminals and notebook computers. It is popular. On the other hand, magnetic disk devices are widely used from small personal computers to large storage devices such as mainframes and large storage devices, and have a large capacity although reliability is a problem. It is characterized by being overwhelmingly advantageous compared to. For these reasons, the current situation is that the magnetic disk device and the semiconductor nonvolatile memory such as the flash EEPROM are clearly divided as media.

  In this way, magnetic disk devices have become the mainstream of auxiliary storage devices for information processing systems because of their advantageous capacity-price ratio, and technical innovations have been made in an effort to dramatically improve storage capacity per unit area. As a result, the capacity of individual HDD media has increased, and the capacity of a single magnetic disk drive has increased from several GB to several hundred GB even over the past few years. On the other hand, in order to cover the reliability of magnetic disk devices, which is a weak point, disk array control using RAID technology improves the reliability of the entire device, and a product with a capacity of several TB as a large storage subsystem is on the market. Is coming out.

  In recent information processing systems, I / O performance to disk storage devices has become a bottleneck, and the demand for improving I / O performance to disk storage devices is particularly high. Efforts have been made to improve O performance.

  As one of the methods, as shown in the configuration of the disk device device according to the prior art in FIG. 10, the disk control device 1 is accompanied by an increase in device access speed of the host computer 50 on the upper side (front end side). A buffer memory buffer (cache memory) is provided.

  However, when this method is adopted, there has been a tendency that a difference in access speed with respect to the cache back processing for the HDD medium on the back end side is increasing.

  Along with this, efforts have been made to improve the performance of I / F such as optical fiber interfaces in order to increase the access speed on the back end side, but there are also many technical problems such as mounting due to physical disturbances, etc. .

  The cache memory is usually composed of a volatile memory such as an SDRAM, and has a tendency to have a backup power supply function for retaining data in the event of a power failure by providing redundancy for improving reliability. ). At the same time, the capacity of the device itself is increased to increase the mounting density, resulting in a problem that the consumption current of the subsystem increases and an excessive equipment cost is required.

  In the disk control device according to the prior art shown in FIG. 10, the non-volatile memory is partly used for storing an actual program of an operation system that operates on a data processing MPU (microprocessor unit) under the restriction of a small capacity. It is currently used (microprocessor 6 in FIG. 10).

  Recently, however, the capacity of flash EEPROMs and the like has increased and the cost per bit has decreased, and some of them have been used as replacements for HDDs as partial storage devices for notebook personal computers. Compared with HDDs, it has a higher resistance to shocks and is more reliable due to the features of no physical wear. In addition, other semiconductor nonvolatile memory devices are also being actively developed, and it can be expected that devices that surpass HDD in the future in terms of space saving, large capacity, and reliability will be expected. However, when it is actually used for a current disk storage device or the like, there are disadvantages of non-volatile memory such as a flash EEPROM, the write time has an overhead such as erase, the number of write operations is limited, It is possible to point out problems such as the need for data guarantee by maintenance.

  As described above, as shown in flash EEPROMs and the like, nonvolatile memory media have been developed year by year and the cost per capacity has been reduced, and the boundary between the conventional space and the magnetic disk device has disappeared. It has become to. However, the nonvolatile memory has a problem that the number of rewrites is limited as described above. Therefore, when used in a disk storage control system that requires high reliability, a mechanism for replacing a memory device is required for maintenance, and a function for determining the replacement time is essential, and a flash EEPROM is also required. And the like have the feature of writing after erasing the area in units of blocks, so it is necessary to consider the negative performance aspect that the write access time becomes longer than the read access time.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to make it possible to use a semiconductor non-volatile memory as a semiconductor storage device used in a disk control device and a replacement medium of the disk device, and to improve the characteristics of the semiconductor non-volatile memory. An object of the present invention is to provide a semiconductor memory device in which the performance, maintainability, and reliability of the disk control device itself are improved by making full use of the mounting.

  In the disk controller using the non-volatile memory of the present invention, the non-volatile memory unit includes three types of non-volatile memories: an actual data storage device, a spare storage device, and a parity redundant data device in which the actual data parity redundant data is stored. Including a memory module composed of devices, these nonvolatile memory devices are configured by being mounted in parallel. Each nonvolatile memory device holds data for each minimum block unit, and is provided with update information and a protection code as spare information for each block to monitor failures and defects of the nonvolatile memory device.

  Nonvolatile memory devices can be easily replaced because they are implemented in parallel. The faulty nonvolatile memory device can be restored from the parity redundant data and the protection code.

  The nonvolatile memory unit enables read protection and write protection for each divided block of the memory device, and has a diagnostic rewrite function for finding a defective block.

  Non-volatile memory is used as a substitute for a quiche memory that holds data exchanged between a host and a disk device, a shared memory that holds control information, and a spare disk device.

  Furthermore, a program executed by the microprocessor may be stored, and disk access log information and failure log information may be stored.

  According to the present invention, a semiconductor non-volatile memory can be used as a semiconductor storage device used in a disk control device and a replacement medium for the disk device, and the performance and maintainability of the device itself can be obtained by making use of its characteristics. A semiconductor memory device with improved reliability can be provided.

  Hereinafter, an embodiment according to the present invention will be described with reference to FIGS. 1 to 9.

[Configuration of disk controller]
First, the configuration of the disk controller according to the present invention will be described with reference to FIG.
FIG. 1 is a configuration diagram of a disk control apparatus according to the present invention.

  The disk controller 1 has a host adapter unit 11, a disk adapter unit 12, and a cache memory unit 14, and has a cache memory path 16 for connecting them. In addition, it has a shared memory unit 15 and a shared memory path 17 that connects the host adapter unit 11 and the disk adapter unit 12.

  The host adapter unit 11 is a part that interfaces with the host, and includes a plurality of processors 6 that control input and output to the host computer 50. The host adapter unit 11 executes data transfer of the cache memory unit 14 via the host computer 50 and the cache memory path 16 under the control of the processor 6. Also, data is transferred to the shared memory unit 15 using the shared memory path 17 under the control of the processor 6.

  The disk adapter unit 12 is a part that interfaces with the disk device 20, and has a processor 6 that controls input / output to the disk device 20. Data transfer between the disk device 20 and the cache memory unit 14 is controlled by the processor 6. Execute. The disk adapter unit 12 also executes arithmetic functions such as RAID control for the disk.

  Also, data is transferred to the shared memory unit 15 using the shared memory path 17 connected to the shared memory unit 15 under the control of the microprocessor 6.

  Both the host adapter unit 11 and the disk adapter unit 12 are duplexed in order to improve reliability.

  The cache memory unit 14 has a memory module 9 therein, and is a part that temporarily holds data exchanged between the host computer 50 and the disk device 20. .

  The shared memory unit 15 has a memory module 9 therein, and stores cache data management information. That is, table information and the like necessary for exclusive control of data update and the like are stored for access to the cache memory of the plurality of host adapter units 11 or the plurality of drive adapter units 12. Unlike the cache memory data, the shared memory data has a small capacity, a large number of transactional accesses and a short response time, which are indispensable for improving the performance. Therefore, it is necessary to reduce the protocol overhead time. The reason for having a path in which the cache memory unit and the shared memory unit are separated is because the nature of the data access is considered in this way, and the cache memory unit 14 and the shared memory unit 15 have fault tolerance. In consideration of this, it is common to use a duplex system. In addition, as in the conventional apparatus (see FIG. 10), the battery is normally backed up to hold data when the apparatus power is cut off.

  The disk controller of the present invention uses a nonvolatile memory in three different forms.

  The nonvolatile memory unit 8 a is a connection form subordinate to the cache memory unit 14 or the shared memory unit 15.

  The nonvolatile memory unit 8b is directly connected to the shared memory path.

  The nonvolatile memory unit 8c is connected as part of the HDD disk array.

  The non-volatile memory unit 8a has a subordinate connection with the cache memory unit 14 or the shared memory unit 15, and enables cache memory data or shared memory data to be transferred respectively. Therefore, if the data is saved immediately before the power interruption occurs, the data can be preserved without the power backup by the battery.

  In addition, when energized, a part of data can be written as a temporary area before writing to the disk when cashing back. This has the advantage that the next read is faster than putting the data on the disk.

  The nonvolatile memory unit 8 b is connected to the host adapter unit 11 and the disk adapter unit 12 via the shared memory path 17.

  The nonvolatile memory unit 8b functions as an independent storage area unlike the nonvolatile memory unit 8a, and is a memory that is accessed from a plurality of processors 6. Possible uses include storing system configuration / management information, storing a program for executing a microprocessor, and writing and saving disk access information, failure log information, and the like.

  The nonvolatile memory unit 8c is used as a part of the media device of the HDD disk array, and can be used as a spare device for replacement when a failure occurs in the disk.

  A configuration in which all of the disk devices 20 are arranged by the nonvolatile memory unit 8c is also conceivable.

  These nonvolatile memory units 8a, 8b, 8c and the like are mounted so that the capacity can be expanded and replaced.

  In addition, in consideration of the characteristics of the nonvolatile memory, the limitation on the number of writings is managed so that a device failure can be detected. Then, the memory module is composed of a plurality of memory devices so that defective memory devices can be replaced.

  Furthermore, these nonvolatile memory units are provided with a function of intentionally reading and rewriting for memory failure detection and data integrity.

  That is, information on the area management table and update history mapping information and the like is provided in an internal register (block management register), and a rewrite check is periodically performed when there is no access to the designated area. Then, at the time of writing, the corresponding area is locked, and updates from the upper level are suppressed. Alternatively, when there is an update request from a host, this rewrite process may be interrupted, the lock may be released, and after the request is completed, the rewrite process may be performed again.

[Details of non-volatile memory]
Next, details of the nonvolatile memory unit in the disk controller will be described with reference to FIGS.
FIG. 2 is a block diagram of the nonvolatile memory unit.
FIG. 3 is a diagram for explaining an interface between a memory controller and a memory module in the nonvolatile memory unit.
FIG. 4 is an explanatory diagram of the address space of the nonvolatile memory unit.
FIG. 5 is a diagram for explaining the principle of data restoration using parity data.
FIG. 6 is a schematic diagram of a data structure held in the nonvolatile memory.
FIG. 7 is an image diagram of handling of defective blocks in the nonvolatile memory unit.
FIG. 8 is a diagram showing an outline of data restoration after device replacement in the nonvolatile memory unit.
FIG. 9 is a configuration diagram of the shared memory unit.
(I) Outline of Configuration of Nonvolatile Memory Unit The configuration of the nonvolatile memory units 8a, 8b, and 8c is divided into main parts of the I / F adapter unit 30, the memory controller 31, and the nonvolatile memory module 32 as shown in FIG.
(II) I / F adapter unit The I / F adapter unit 30 decodes the interface and accesses the internal non-volatile memory module 32 when receiving / transmitting data to / from the non-volatile memory module from the path inside the connected device. Control under the direction of the memory controller 31.

  That is, the I / F adapter unit 30 is connected to the upper I / F path 9, analyzes the protocol of each interface, and provides a control signal to the memory controller unit. Here, the type of the upper I / F path 9 to be connected may be the internal path if the nonvolatile memory unit 8a, the cache memory path 16, the shared memory path 17 and the nonvolatile memory unit 8c if the nonvolatile memory unit 8b. Drive I / F2.

  Variations 8a, 8b, and 8c can be created by changing the adapter control unit 302 in the I / F adapter unit 30 according to the I / F to which this unit is connected.

  In the I / F adapter unit, the data sent from the connection path 9 is received by the packet buffer 301 connected in the I / F adapter unit 30 under the control of the adapter control unit 302. In addition, transmission data from the memory module 33 is transmitted from the packet buffer 301.

Although not shown, the address / command analysis unit 302a in the adapter control unit includes a buffer for storing addresses and commands, an address extraction unit, and a command extraction unit. The address extraction unit and the command extraction unit transmit a control signal to the memory controller unit 31 based on the analysis result.
(III) Configuration of Memory Unit to be Connected in the Case of Nonvolatile Memory Unit 8a In the case of the nonvolatile memory unit 8a, it is necessary to provide a connection path for the cache unit 14 and the shared memory unit 15 in FIG. Therefore, in this case, it is necessary to change the path control inside the cache unit 14 and the shared memory unit 15.

That is, the nonvolatile memory path 18 is provided inside the shared memory unit 15 as shown in FIG. (Also, the cache memory unit 14 can be realized in substantially the same manner.)
Hereinafter, the configuration of the shared memory unit 15 will be described.

  The shared memory unit 15 includes a plurality of memory modules 159, a path I / F unit 150, a packet buffer 153, a data error check unit 150, a memory control unit 157, an address / command analysis unit 155, And a data transfer control unit 152.

  The packet buffer 153 is a part for temporarily storing the selector 156 and data. The memory control unit 157 is a part that controls access to the memory module 159. The address / command analysis unit 155 analyzes the address and command sent from the shared memory path 17.

  The data transfer control unit 152 uses the arbiter 158 to arbitrate between the access request from the shared memory path 17 analyzed by the address / command analysis unit 155 and the access request from the nonvolatile memory path 18 connected to the shared memory unit. 156 is switched. The access request from the nonvolatile memory path 18 is a unique part of the present invention.

  The address / command analysis unit 155 includes a buffer, an address extraction unit, and a command extraction unit (not shown). The address / command analysis unit 155 stores the address and command in the buffer allocated to the shared memory path 17. (For this path, four independent systems are shown in FIG. 9.) The address extraction unit and command extraction unit determine the address of the memory to be accessed and the type of access, and send it to the memory control unit 157. Further, an access request from the shared memory path 17 is sent to the arbiter 158 in the data transfer control unit 152. At this time, the memory module 159 is normally accessed. However, in the access mode to the nonvolatile memory unit, the selector 156 is switched, and switching to the nonvolatile memory path 18 connected to the path I / F unit 151 is performed.

  Further, the data transfer control unit 152 has a function of directly transferring the data of the shared memory module 158 to the nonvolatile memory path 18 without depending on the shared memory access through the host I / F unit and the drive I / F unit. Try to have it.

  This is an effective function for shortening the time when urgently transferring the shared memory data to the nonvolatile memory unit.

This function can be realized by having the data transfer control unit 152 as a transfer master under the control of the selector 156 in this case, although the normal transfer master is a host I / F unit and a drive I / F unit.
(IV) Memory Controller Unit The memory controller unit 31 includes an error check circuit unit 311, a transmission buffer 312, and a transmission / reception selector 313, which have a connection path to the nonvolatile memory module unit 32. .

  Similarly, the transmission path to the I / F adapter unit is connected from the selector unit 313, and an error check circuit unit 311 exists between them.

  The memory control unit 314 controls the control line to the non-volatile memory module unit 32, and the transmission buffer 312 is based on the signal from the control line from the command address analysis unit 302 in the I / F adapter unit 30 described above. And outputs a signal to the selector unit 313. This memory control unit has an address conversion function for converting a logical address to be accessed into an internal physical address, and a lock function for protecting each accessed address.

  Also, the VPP control unit 315 functions when necessary for controlling the write power source of a memory module such as a nonvolatile EEPROM.

  This memory control unit 314 controls access to a plurality of nonvolatile memory arrays in the nonvolatile memory module 32 and has an arithmetic circuit 316 for data guarantee.

The arithmetic circuit 316 is a circuit that restores data from parity data and a protection code, which will be described in detail later.
(V) Nonvolatile Memory Module Unit The nonvolatile memory module unit 32 has an array of a plurality of media as components as shown in FIG. This is to enable maintenance of a single medium. An indicator (LED or the like) indicating a failure or maintenance target medium can be replaced and maintained when the indicator of the part is ON. In addition, it has a structure that allows media to be upgraded to a type with a different capacity.

There are three types of memory devices mounted on the nonvolatile memory module unit 32: data storage, data storage spare, and parity data storage.
(VI) Interface between Memory Controller and Nonvolatile Memory Module Next, an interface between the memory controller 31 and the nonvolatile memory module 32 will be described with reference to FIG.

In FIG. 3, a memory controller unit 31 and five memory module units 32 are connected. Each data is transmitted / received via the ADDRESS / DATA bus, and device selection is realized by asserting a chip enable (CE) signal. The write enable (WE) signal and output enable (OE) signal select whether to write / read, and write / read to the device in synchronization with the CLK signal or the like.
(VII) Address Space of Non-Volatile Memory Unit The ADDRESS data signal and physical address space use an indirect addressing system in which a logical address is converted into a physical address in an address table inside the controller. As a result, the logically accessible address space is expanded.

  As shown in the image of FIG. 4, the address space is a mechanism that can cope with the increase in the capacity of the device by the expansion space. That is, actual data and blocks are stored in a page, and the pages gather to form a frame.

  The conversion from the logical address to the physical address is to indirectly link to the physical address of the device by an internal address table. A method is also conceivable in which an address table is written in a fixed area of the device, not in a register provided in the memory control unit 31, and the fixed area is accessed so that the information can be read at once to perform address calculation. It is done.

The advantage of accessing with a logical address is that the interface can be designed from outside without being aware of the internal physical structure.
(VIII) Protect function and count of the number of write operations The memory accessed in the nonvolatile memory section should have a write / read protect (lock) function for each block. This is to protect data that cannot be rewritten, and to prevent data from being modified by other accesses when the contents of the address are being restored by the original data during the memory recovery process. Is also a necessary function. It is also important to control with the write protection in mind when the data is used for storing data with a strong read characteristic, such as when storing a processor program in the nonvolatile memory unit 8b. .

  In addition, a writing number counter is configured for each block included in the device, and the count value is incremented by 1 after writing is completed. When the counter value exceeds a predetermined threshold value (Shikiichi), a function of automatically performing write protection is provided. Alternatively, the replacement warning may be indicated in advance. This makes it possible to check the number of times of writing to the nonvolatile memory and predict the maintenance replacement time.

  Regarding the number of times of writing, there are a method of providing a register for storing information in an internal circuit and a method of saving data in the nonvolatile memory itself. Similarly, information for address conversion can be stored in the nonvolatile memory itself.

Furthermore, in order to cope with a failure in the address table, it is possible to select a method of storing data in the controller unit register and the device itself twice.
(IX) Normal access to the nonvolatile memory unit Data is stored in the nonvolatile memory unit in units of blocks. The capacity size of the transmission buffer 312 in FIG. 2 is a size that can include a plurality of block capacities, and it is desirable that a dedicated buffer is provided for each device. Some non-volatile memory devices, for example, non-volatile EEPROMs, must be erased and written, and have a characteristic that the write access processing time is slower than the read. In order to compensate for this drawback, when data arrives, if a plurality of blocks are stored in the transmission buffer 312 and the adapter unit 30 responds to the upper side, an apparent appearance when performing a write process to the device The above access time can be shortened.

Also, the transfer throughput can be improved by writing / reading a plurality of devices in parallel. An example implemented in parallel is shown in FIG. 3, according to which the non-volatile memory module unit 32 becomes D3, D2, D1 and parity data Q for data storage, and these become unusable, Further, spare locations SP when replacement is impossible are arranged as spares.
(X) Parity Data Next, the principle of data restoration using parity data used in the nonvolatile memory device of the present invention will be described with reference to FIG.

  Parity data is redundant data. In the example of FIG. 5A, Q data is generated as an exclusive OR operation result from D3 to D1.

  As for the restoration, as shown in the example of FIG. 5B, the restoration data can be calculated by calculating the exclusive OR of the parity data Q and the normal device data D3 and D1.

Since this exclusive OR operation is performed for each bit, it is possible to restore the bit based on the parity data.
(XI) Maintenance and Recovery Process When Failure Occurs Next, how to restore and recover data when maintenance and failure of the nonvolatile memory unit of the present invention occur will be described.

  In the memory device of the nonvolatile memory module unit 32, data is divided and stored in units of blocks.

  As shown in FIG. 6, the data is managed with the total of block data and parity data stored in D3, D2, and D1 as one page and a plurality of pages as one frame.

  The unit block data stored in D3, D2, and D1 is composed of real data having a plurality of bytes and a block code unique to the block.

  The block code unique to the block is described as a unique ID number (Logical ID) of the block data and an update count (Write Number, hereinafter referred to as “WN”) that is a history of how many times the corresponding block area has been written on the device. ) And a data protection code such as CRC calculated from the data. By checking this block code, the correct data is stored in the correct location, and the number of updates is limited by the nonvolatile memory. It can be judged whether the specified value lower than the number of times is satisfied.

  For block data in which a failure is found by this check, the access is switched to the spare location. At that time, the LI number takes over the number of the failed block, and the WN is updated to a value for the corresponding block in the spare location. FIG. 7 shows an example of replacing failed block data with a spare location device.

  If the number of replacement blocks exceeds a certain level, it is possible that the device has deteriorated considerably. Therefore, in order to suggest the device replacement to the person who is maintaining, it is reported to the management information register in the control unit 31, and an indicator or alarm is turned on as a warning. When replacing a defective device, as soon as a failure occurs, writing to the nonvolatile memory unit is temporarily stopped, and the logical address for the corresponding area is write-locked or read-locked.

  Then, after replacing the defective device with a new normal device, as shown in FIG. 8, the replacement data in the spare device is copied, and the block having no replacement data in the spare device reads the data from D3, D1, and Q. The data is restored by performing the parity calculation described in (X).

  At this time, the update data of the new device is reset to the initial value, and the copy block data is deleted from the spare device, but the WN is updated. When a failed device is replaced, this can be detected by a control signal (SY / RY in FIG. 3), and a recovery process can be automatically performed. The data restored by the data parity calculation and the block data replaced with the spare device are stored in a new device, and when it is confirmed that the device has been recovered, the indicator LED is displayed in a normal state.

  Non-volatile memory is based on the premise that data is non-volatile, but it cannot be said that there is no possibility of data loss due to secular changes such as semiconductor soft errors. There is a concern that the number of times of writing or the number of times of writing is approaching an allowable value.

  Checks for maintenance replacement in advance are also necessary for stable operation of the system, and it is effective to rewrite regularly. In the periodic rewrite mode, a circuit for performing a read / write check for each page / block is built in the memory controller 314 (not shown). The rewrite mode is started by setting an address range and issuing a rewrite mode command. Controls reading to the data buffer and writing the data to the original location.

  This rewrite check is performed only when the area is not in use or forcibly locked. In this rewrite check, reading is performed after rewriting, an exclusive OR operation is performed by a parity operation circuit, and the data is compared to perform the check again. It is also possible to reduce the overhead for inspection by checking only the protection code.

  The maintenance target device of the failure can be identified by the lighting of the LED as an indicator to indicate, and the number of times more than the specified number is detected by the write count counter value, etc., and the error information in the memory controller is monitored. Let the LED light up. The LED illuminates, locking the site access and preventing access to the device until maintenance replacement. When a failed device is replaced, this can be detected by a control signal (SY / RY in FIG. 3), and a recovery process can be automatically performed. When it is confirmed that the interpolated data has been recovered by the data parity calculation, the indicator LED is displayed in a normal state.

[Advantages of using non-volatile memory for disk controller]
As represented by a flash EEPROM, a nonvolatile memory has a capacity smaller than that of an HDD, but its cost is decreasing year by year, and the capacity per device is also increasing. There is no mechanical part like HDD, and it has an advantage as a storage device in terms of mounting space and low power consumption.

  In the present invention, a nonvolatile memory part is partially used as a storage area in the disk storage control device. Instead of storing a part of the data in the storage device and having a battery as a backup power source for the volatile memory in the cache memory unit, emergency evacuation can be made to the nonvolatile memory, reducing the capacity of the battery and reducing the power consumed by the device be able to.

  In addition, since multiple non-volatile memory devices are arranged, maintenance can be performed on a failed device basis, and only the non-volatile memory device is replaced and maintained rather than dismantling the HDD and repairing the disk inside. Repair costs are also reduced. As a secondary storage area or as a storage device that replaces the HDD, it can be expected to contribute to the reduction in the price of the apparatus, the reduction in power consumption, and the improvement in maintainability.

It is a block diagram of the disk control apparatus which concerns on this invention. It is a block diagram of a non-volatile memory part. It is a figure for demonstrating the interface of the memory controller and memory module in a non-volatile memory part. It is explanatory drawing of the address space of a non-volatile memory part. It is a figure for demonstrating the principle of the data restoration by parity data. It is a schematic diagram of the data structure hold | maintained in a non-volatile memory. It is an image figure of handling of the bad block of a non-volatile memory part. It is a figure which shows the outline | summary of the data restoration after the device replacement | exchange of a non-volatile memory part. It is a block diagram of a shared memory part. It is a block diagram of the disk control apparatus which concerns on a prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Disk control apparatus, 2 ... Drive I / F, 3 ... Host I / F, 4 ... Cache memory control part, 5 ... Shared memory access control part, 6 ... Microprocessor part, 8a ... Nonvolatile memory part, 8b ... Nonvolatile Memory unit, 8c ... Nonvolatile memory unit, 9 ... Memory module, 10 ... Battery unit, 11 ... Host adapter unit, 12 ... Disk adapter unit, 13 ... Nonvolatile memory path, 14 ... Cache memory unit, 15 ... Shared memory unit, 16 DESCRIPTION OF SYMBOLS ... Cache memory path, 17 ... Shared memory path, 20 ... Magnetic disk device part, 30 ... I / F adapter part, 301 ... Packet buffer, 302 ... Adapter control part, 302a ... Command / address analysis part, 31 ... Memory controller part 311 ... Error check circuit unit, 312 ... Transmission buffer, 313 ... Selector, 314 ... Memory control unit, 315 ... VPP control unit, 316 ... arithmetic circuit, 32 ... nonvolatile memory module part, 40 ... shared memory memory path, 150 ... error check circuit part, 151 ... path I / F part, 152 ... data transfer control part 153, a packet buffer, 155, an address command analysis unit, 157, a memory control unit, 158, an arbiter, 159, a memory module, 50, a host computer.

Claims (15)

A host interface connected to the computer;
A cache memory unit connected to the host interface unit and storing data accessed from the computer;
A disk interface unit connected to the host interface unit and the cache memory unit and controlling input / output of data accessed from the computer;
A plurality of disk devices connected to the disk interface unit and storing data accessed from the computer;
A flash memory unit connected to the disk interface unit and storing data accessed from the computer;
The disk interface unit includes first and second disk interface units, and is connected to a plurality of first communication paths connected to the first disk interface unit and the second disk interface unit. A plurality of second communication paths,
The flash memory unit is a storage medium for replacement of the plurality of disk devices,
At least one of the disk device and the flash memory unit is connected to each of the plurality of first communication paths, and each of the plurality of second communication paths is connected to the first communication path. A storage system, wherein at least one of the disk device and the flash memory unit are connected. A host interface connected to the computer;
A cache memory unit connected to the host interface unit and storing data accessed from the computer;
A disk interface unit connected to the host interface unit and the cache memory unit and controlling input / output of data accessed from the computer;
A plurality of disk devices connected to the disk interface unit for storing data accessed from the computer;
A non-volatile memory unit that is connected to the disk interface unit and stores data accessed from the computer;
The nonvolatile memory unit includes an interface adapter unit, a plurality of nonvolatile memory devices that store data, and a controller unit that controls writing or reading of data with respect to the plurality of nonvolatile memory devices,
The interface adapter unit analyzes a protocol used with the disk interface unit, transmits a control signal and data transmitted from the disk interface unit to the controller unit, and the controller unit receives the control signal according to the control signal. An error check is performed on the data, and the data is written to the plurality of nonvolatile memory devices. The storage system according to claim 2,
The disk interface unit is a first and second disk interface unit,
A plurality of first communication paths connected to the first disk interface unit;
A plurality of second communication paths connected to the second disk interface unit,
At least one of the disk device and the nonvolatile memory unit is connected to each of the plurality of first communication paths, and each of the plurality of second communication paths is connected to the first communication path. A storage system, wherein the at least one disk device and the nonvolatile memory unit are connected. A host interface connected to the computer;
A cache memory unit connected to the host interface unit and storing data accessed from the computer;
A disk interface unit connected to the host interface unit and the cache memory unit and controlling input / output of data accessed from the computer;
A plurality of disk devices connected to the disk interface unit for storing data accessed from the computer;
A non-volatile memory unit that is connected to the disk interface unit and stores data accessed from the computer;
The plurality of disk devices and the nonvolatile memory unit constitute a RAID (Redundant Arrays of Inexpensive Disks) group as a part of an array of storage media composed of the plurality of disk devices,
The nonvolatile memory unit is a spare storage medium for replacement of any one of the plurality of disk devices,
When a failure occurs in any of the disk devices belonging to the RAID group, the access from the computer to the disk device in which the failure has occurred is switched to the access to the nonvolatile memory unit belonging to the RAID group, and from the computer A storage system that stores data to be transmitted and received in the nonvolatile memory unit. The storage system according to claim 4,
A storage system comprising the non-volatile memory unit as part of an array of storage media comprising the plurality of disk devices. The storage system according to claim 4,
A non-volatile memory unit connected to the disk interface unit stores data stored in the cache memory unit. The storage system according to claim 4,
Having a shared memory unit for storing control information transmitted and received in the storage system;
A non-volatile memory unit connected to the disk interface unit stores the control information. The storage system according to claim 4,
A non-volatile memory unit connected to the disk interface unit stores a program executed by a microprocessor mounted on the disk interface unit. The storage system according to claim 4,
A non-volatile memory unit connected to the disk interface unit stores access log information and failure log information for the disk device of the computer. A host interface connected to the computer;
A cache memory unit connected to the host interface unit and storing data accessed from the computer;
A disk interface unit connected to the host interface unit and the cache memory unit and controlling input / output of data accessed from the computer;
A plurality of disk devices connected to the disk interface unit for storing data accessed from the computer;
A non-volatile memory unit that is connected to the disk interface unit and stores data accessed from the computer;
The nonvolatile memory unit includes a plurality of nonvolatile memory devices mounted in parallel in the nonvolatile memory unit,
A controller that performs data operation using data stored in the plurality of nonvolatile memory devices and parity data stored in any one of the plurality of nonvolatile memory devices;
Each of the plurality of nonvolatile memory devices includes, for each minimum block unit, data, a logical management ID of the data, a protection code for determining whether the minimum block unit is good or bad, and an update incremented at the time of update Count information and
The controller monitors the update number information, and when the update number information exceeds a certain threshold, updates the protection code with the smallest block unit as a defective block, and reads data corresponding to the smallest block. A storage system characterized by rewriting. The storage system according to claim 10, wherein
The nonvolatile memory unit has an indicator corresponding to each of the plurality of nonvolatile memory devices, and when a failure occurs in one nonvolatile memory device of the plurality of nonvolatile memory devices, the nonvolatile memory device A storage system displayed on the indicator, wherein the one non-volatile memory device is physically replaceable. The storage system according to claim 10, wherein
When replacing the one non-volatile memory device, the non-volatile memory unit is configured such that the minimum block unit of data to be restored in the one non-volatile memory device is transferred to another non-volatile memory device of the plurality of non-volatile memory devices. When created as a spare, the smallest block unit of the spare is used as a replacement block unit, and when not created as a spare in the other nonvolatile memory device, the memory device in any one of the plurality of nonvolatile memory devices The storage system is characterized in that a minimum block unit of the restoration target data is created as a replacement block unit using the data and parity data, and the restoration target data is restored using the replacement block unit. The storage system according to claim 10, wherein
The non-volatile memory unit has a conversion table that associates the logical address and physical address of data stored in the non-volatile memory unit, and when there is an input / output request for the data from the computer, A storage system for converting a logical address of the data included in an entry output request into a physical address. The storage system according to claim 10, wherein
The storage system, wherein the nonvolatile memory unit executes read protection and write protection for each minimum block unit of divided data of the plurality of nonvolatile memory devices. 15. The storage system according to claim 14, wherein
The nonvolatile memory unit has a data buffer, and at an arbitrary timing, reads data from a certain logical address in a nonvolatile memory device of the plurality of nonvolatile memory devices, stores the data in the data buffer, and stores the data buffer. When the data stored in the logical address is written to the logical address and read protection or write protection is executed on the data, the data written to the logical address and another nonvolatile memory of the plurality of nonvolatile memory devices A storage system characterized in that a bad block is determined by comparing with data created by performing parity operation on data in a device.

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