JP4113225B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device such as a NAND flash memory, and more particularly to a semiconductor device having an error correction function in a chip.

It is known that NAND-type flash memory has cell characteristics that deteriorate when rewriting is repeated and that data becomes garbled when left for a long time. Therefore, in order to increase the reliability of this type of NAND flash memory, conventionally, a semiconductor memory equipped with an ECC (Error Correcting Code) circuit for error detection and correction in the chip has been proposed (for example, Japanese Open 2 000 No. -348497, JP open 2 001-14888 No., etc.).

  FIG. 21 is a block diagram schematically showing a configuration of a conventional NAND flash memory equipped with an ECC circuit.

This memory, eight memory cell area 1 _0, 1 _1, ..., and a 1 _7. Each memory cell area 1 _{0-1 7} includes a plurality of memory cells (not shown) are arranged in a matrix, through the 528 bit lines to the connected 528 memory cells to a common word line 528 bits of data (= 1 page) can be written and read at once. Page buffers 2 ₀ to 2 ₇ for holding 528 bits of write data and read data are connected to the memory cell areas 1 ₀ to ₁₇ , respectively. A page buffer 2 _{0-2 7,} between the I / O terminals 4 _{0-4 7} provided in each memory cell area 1 _0-1 every _7, ECC for each memory cell area 1 _{0-1 7} circuit 3 _{0-3 7} are provided.

Each of the ECC circuits 3 _{0 to} 3 ₇ encodes a check bit (ECC) having a predetermined number of bits to one page (528 bits) of information bits stored in the memory cell areas 1 ₀ to ₁₇ . And a decoding function that performs error detection and error correction for a predetermined number of bits from information bits with check bits added. For example, error correction codes can be used for error correction of multiple bits with a relatively small circuit scale. Possible BCH (Bose-Chaudhuri-Hocquenghem) codes are used. Between the outside and the memory, for example, data is read / written in units of 8 bits corresponding to the number of memory cells. Therefore, the ECC circuits 3 _{0 to} 3 ₇ receive data one bit at a time, circulate the internal cyclic shift register one bit at a time, and output one bit at a time, thereby executing the encoding process and the decoding process. Is done.

Next, a description will be given of encoding and decoding operation of a conventional ECC circuit 3 _{0-3 7} using BCH codes.

  Note that the number of check bits of a BCH code that performs 528 bits of information and performs 2-bit error correction and 3-bit error detection is 21 bits, but here, for simplicity of explanation, the number of information bits k = 7, the code length An error detection / correction method using a BCH code capable of 2-bit error correction and 3-bit error detection with n = 15 and the number of correction bits t = 2 will be described as an example.

  It is generally known that a generator polynomial necessary for encoding and decoding in this case is as follows.

[Equation 1]
Primitive polynomial: F (X) = X ⁴ + X + 1
Minimum polynomial of α: M ₁ (x) = X ⁴ + X + 1
Minimum polynomial of α ³ : M ₃ (x) = X ⁴ + X ³ + X ² + X + 1
Generator polynomial: G (x) = M ₁ M ₃ = X ⁸ + X ⁷ + X ⁶ + X ⁴ +1
(1) Encoding Circuit FIG. 22 is a block diagram showing an encoding circuit 10 functionally configured inside a conventional ECC circuit 3i (i = 0, 1,..., Or 7). The encoding circuit 10 includes a shift register 11 composed of registers D ₇ , D ₆ , D ₅ , D ₄ , D ₃ , D ₂ , D ₁ , and D ₀ and XOR circuits 12 ₁ and 12 that perform modulo 2 operations. ₂ , 12 ₃ , 12 ₄ and change-over switches SW1, SW2.

  The operation of moving the shift register 11 once corresponds to multiplying the value of the shift register 11 by X times. Now, the value of the data stored in the shift register 11 is expressed as follows.

[Equation 2]
a ₀ X ⁰ + a ₁ X ¹ + a ₂ X ² + a ₃ X ³ + a ₄ X ⁴ + a ₅ X ⁵ + a ₆ X ⁶ + a ₇ X ⁷
[Where a _i is a value stored in the register D _i and a _i = 0 or 1 (i = 0 to 7)]
By shifting this once,
[Equation 3]
a ₀ X ¹ + a ₁ X ² + a ₂ X ³ + a ₃ X ⁴ + a ₄ X ⁵ + a ₅ X ⁶ + a ₆ X ⁷ + a ₇ X ⁸
It becomes. Since there is a relationship of X ⁸ = X ⁷ + X ⁶ + X ⁴ +1 from the generator polynomial G (x) of Equation 1, Equation 3 is
[Equation 4]
a ₇ X ⁰ + a ₀ X ¹ + a ₁ X ² + a ₂ X ³ + (a ₃ + a ₇ ) X ⁴ + a ₄ X ⁵ + (a ₅ + a ₇ ) X ⁶ + (a ₆ + a ₇ ) X ⁷
It can be expressed as This is when the shifting each bit, and stores the value a ₇ of the register D ₇ to the register D _0, the register D _3, the value of D ₇ a _3, register crowded plus a ₇ in XOR circuit 12 ₁ D stored in the ₄ registers D _5, the value a ₅ + a ₇ of D ₇ is stored in the register D ₆ crowded adding an XOR circuit 12 _2, register D _6, the value of D ₇ a ₆ + a ₇ the XOR circuit 12 ₃ corresponds to storing crowded in the register D ₇ added in.

At the time of encoding, first, the switches SW1 and SW2 are connected to the ON side, and input data (information bits) I ₀ , I ₁ , I ₂ , I ₃ , I ₄ , I ₅ from the outside via the I / O terminal 4i. , I ₆ (I _{0 to} I ₆ = 0 or 1) are input bit by bit. Every time one bit of input data I _{0 to} I ₆ is input, the shift register 11 operates once. Because while the data I ₀ ~I ₆ is input switch SW1 is ON, the these data are output to the page buffer 2i bit by bit. At the same time, the data I _{0 to} I ₆ are added to the value a ₇ of the register D _{7 by} the XOR circuit 12 ₁ and sequentially stored in the shift register 11. When the input of the data I _{0 to} I _{6 to} the page buffer 2 i is completed, the registers D ₇ , D ₆ , D ₅ , D ₄ , D ₃ , D ₂ , D ₁ , D ₀ of the shift register 11 are inspected. Bits I ₇ , I ₈ , I ₉ , I ₁₀ , I ₁₁ , I ₁₂ , I ₁₃ , and I ₁₄ are stored. Then, switches SW1, SW2 are both connected to the OFF side, each time the shift register 11 is operated, via the switch SW1, the check bits I ₇ ~I ₁₄ is serially outputted to the page buffer 2i. Then, the information bits and check bits stored in the page buffer 2i are stored in the memory cell area 1i. At the same time, the value of the shift register 11 is reset.

(2) Decoding Circuit Next, the decoding circuit will be described. The decoding circuit includes a syndrome calculation circuit and an error position detection circuit. In the case of 2-bit error correction, it is known that two syndromes S ₁ and S ₃ are required for decoding, and these are obtained by the minimum polynomial M ₁ (x) = X ⁴ + X + 1. FIG. 23A is a diagram specifically illustrating the conventional S ₁ syndrome calculation circuit 20, and FIG. 23B is a diagram illustrating the conventional S ₃ syndrome calculation circuit 30.

The S ₁ syndrome calculation circuit 20 in FIG. 6A is based on the minimum polynomial M ₁ (x), and includes a shift register 21 composed of registers D ₃ , D ₂ , D ₁ , D ₀ and XOR circuits 22 ₁ , 22 ₂ . It is comprised by. Here, the operation of moving the shift register 21 once corresponds to multiplying the value of the shift register 21 by X times. Now, the value stored in the shift register 21 is expressed as follows.

[Equation 5]
a ₀ X ⁰ + a ₁ X ¹ + a ₂ X ² + a ₃ X ³
[Where a _i is a value stored in the register D _i and a _i = 0 or 1 (i = 0 to 3)]
By shifting this once, [Equation 6]
a ₀ X ¹ + a ₁ X ² + a ₂ X ³ + a ₃ X ⁴
However, since there is a relationship of X ⁴ = X + 1 from the minimum polynomial M ₁ (x) of α,
[Equation 7]
a ₃ X ⁰ + (a ₀ + a ₃ ) X ¹ + a ₁ X ² + a ₂ X ³
It becomes. This is when the shifting each bit, and stores the value a ₃ of register D ₃ to the register D _0, crowded adding value a _0, a ₃ register D _0, D ₃ at the XOR circuit 12 ₂ Register It corresponds to storing in D _1. The information bits I _{0 to} I ₆ and the check bits I _{7 to} I ₁₄ stored in the memory cell are input to the S ₁ syndrome calculation circuit 20 one by one in this order, and each time one bit is input, the shift register 21 Operates once. When all the bits I _{0 to} I ₁₄ are input, the syndrome S ₁ is generated in the shift register 21 (D _{0 to} D ₃ ).

Similarly to the S ₁ syndrome calculation circuit 20, the S ₃ syndrome calculation circuit 30 in FIG. 23B is also composed of a shift register 31 composed of D ₃ , D ₂ , D ₁ , D ₀ and XOR circuits 32 ₁ , 32 ₂ , 32 _3. , 32 ₄ , and is constituted by an X ³ circuit of the minimum polynomial M ₁ (x). In the S ₃ syndrome calculation circuit 30, the operation of moving the shift register 31 once corresponds to multiplying the value of the shift register 31 by X ³ . Now, represents the value stored in the shift register 31 as in equation 5, ^3-fold Then this X,
[Equation 8]
a ₀ X ³ + a ₁ X ⁴ + a ₂ X ⁵ + a ₃ X ⁶
However, since there is a relationship of X ⁴ = X + 1 from the minimum polynomial M ₁ (x) of α,
[Equation 9]
a ₁ X ⁰ + (a ₁ + a ₂ ) X ¹ + (a ₂ + a ₃ ) X ² + (a ₀ + a ₃ ) X ³
It becomes. This is when the shifting each bit, and stores the value a ₁ of the register D ₁ to the register D _0, crowded adding value a _1, a ₂ of the register D _1, D ₂ by XOR circuit 32 ₂ Register stored in D _1, register D _2, the value a _2, a ₃ of D ₃ is stored in the register D ₂ crowded adding an XOR circuit 32 _3, the register D _0, D ₃ values a _0, a ₃ to XOR corresponds to storing in the register D ₃ crowded added at circuit 32 _4. The S ₃ syndrome calculation circuit 30 also receives information bits I _{0 to} I ₆ and check bits I _{7 to} I ₁₄ stored in the memory cell one by one in this order, and every time one bit is input, The shift register 31 operates once. When all the bits I _{0 to} I ₁₄ are input, the syndrome S ₃ is generated in the shift register 31 (D _{0 to} D ₃ ).

FIG. 24 is a flowchart showing the algorithm of the decoding process. First, the syndromes S ₁ and S ₃ are calculated by the S ₁ and S ₂ syndrome calculation circuits 20 and 30 from the information bits read from the memory cell area 1 i and the check bits (step S 1). If the syndromes S ₁ and S ₃ are S ₁ = S ₃ = 0, the information bits read as no error are output as they are (steps S2, S3, S4). When only _{one of} the syndromes S ₁ and S ₃ is 0, the correction is impossible and the data is output as it is (steps S2, S3, S5, S6, S7). When S ₁ ≠ 0 and S ₃ ≠ 0, calculation is performed to obtain σ ₁ = S ₁ ² and σ ₂ = S ₁ ³ + S ₃ (steps S2, S6, S8). Here, when σ ₂ = 0 (step S9), since it is found that there is a 1-bit error, 1-bit correction is performed and output (step S10). When σ ₂ ≠ 0 (step S9), since it is found that there is a 2-bit error, the 2-bit error is corrected and output (step S11).

In general, the position of the error bit can be obtained by sequentially substituting Z = α ^I (I = 0, 1, 2, 3, 4, 5, 6) into the error position polynomial σ (Z) shown in Equation 10. Are known. i where σ (α ^I ) = 0 is the position of the error.

[Equation 10]
σ (Z) = S ₁ + σ ₁ × Z + σ ₂ × Z ²
The configuration of the error position detection circuit configured based on such points is shown in FIG. 25 and FIG. FIG. 25 shows a first calculation unit 40a that calculates and stores S ₁ , σ _1, and σ ₂ , and FIG. 26 performs calculation of Formula 10 based on the calculation result of the first calculation unit 40a. A second calculation unit 40b that outputs a detection signal indicating an error position of data is shown. First calculation unit 40a is configured by a shift register 41, X arithmetic circuit 42 and X ² arithmetic circuit 43 as shown in FIG. 25. The syndrome S ₁ is stored in the shift register 41a, and the calculation results of σ ₁ = S ₁ ² and σ ₂ = S ₁ ³ + S ₃ are stored in the shift registers 42a and 43a. Here, the value of the shift register 42a is set to
[Equation 11]
a ₀ X ⁰ + a ₁ X ¹ + a ₂ X ² + a ₃ X ³
[Where a _i is a value stored in the register D _i and a _i = 0 or 1 (i = 0 to 3)]
Then, since the X arithmetic circuit 42 multiplies this by X, the value of the shift register 42a is
[Equation 12]
a ₀ X ¹ + a ₁ X ² + a ₂ X ³ + a ₃ X ⁴
However, since there is a relationship of X ⁴ = X + 1 from the minimum polynomial M ₁ (x) of α,
[Equation 13]
a ₃ X ⁰ + (a ₀ + a ₃ ) X ¹ + a ₁ X ² + a ₂ X ³
It becomes. This is when the shifting each bit, and stores the value a ₃ of register D ₃ to the register D _0, the register D _0, D ₃ values a _0, crowded plus a ₃ in XOR circuit 42b register D Equivalent to storing in ₁ .

Further, since the X ² arithmetic circuit 43 multiplies the value of the shift register 43a by X ² , assuming that the value indicated by the equation 11 is stored in the value of the shift register 43a, the X ² arithmetic circuit 43 shifts the value by multiplying it by X ^2. The value of the register 43a is
[Formula 14]
a ₀ X ² + a ₁ X ³ + a ₂ X ⁴ + a ₃ X ⁵
However, since there is a relationship of X ⁴ = X + 1 from the minimum polynomial M ₁ (x) of α,
[Equation 15]
a ₂ X ⁰ + (a ₂ + a ₃ ) X ¹ + (a ₀ + a ₃ ) X ² + a ₁ X ³
It becomes. This is when the shifting each bit, and stores the value a ₂ of register E ₂ in the register E _0, stores the value a ₁ of the register E ₁ to the register E _3, register E _2, the value of E ₃ a _2, stores a ₃ to register E ₁ crowded adding an XOR circuit 43 b _1, register E _0, storing the values a _0, a ₃ of E ₃ in the register E ₂ crowded adding an XOR circuit 43 b ₂ It corresponds to.

When the 1-bit data I _{0 to} I ₆ is output, the shift register 41 a, 42 a, 43 a is operated once, whereby the term of σ ₁ is multiplied by Z in the X arithmetic circuit 42, and in the X ² arithmetic circuit 43, The term of σ ₂ is multiplied by Z ² times. In the NAND flash memory, the shift registers 41a, 42a, and 43a are moved in synchronization with a toggle signal when the information bits stored in the memory cells are output to the outside of the chip. As a result, in the second arithmetic unit 40b, the output of the result calculated by the XOR circuit 44 and the NOR gate 45 becomes 1 when the error position is reached, and the error is caused by inverting the corresponding data Ii with this output. Detection and correction are performed.

  As described above, in the conventional ECC circuit using the BCH code, one shift and calculation for a 1-bit input is a basic operation. In the NAND flash memory, data is input from the outside in units of 8 IO or 16 IO for one address, so that error correction is performed for each IO or 8 or 16 times during this one input. Must be calculated. However, performing 8 or 16 calculations during one input means that only this part is operated at high speed, and a special process is required, so that it cannot be performed in reality.

  Therefore, conventionally, an ECC circuit 3i is provided for each memory cell area 1i (each I / O) to perform error correction in units of each memory cell area 1i. In this case, in the NAND flash memory, data is read or programmed in units of one page (528 bytes), so if 2-bit error correction 3-bit error detection is performed for each I / O, the number of information bits is 528 bits and the number of inspection bits are 21 bits, and a total of 21 × 8 = 168 bits of extra inspection bits are required for the entire chip. This has been an impediment to increasing the integration density of the chip.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor device that can reduce the number of inspection bits with respect to the number of information bits and improve the integration degree of the chip.

The present invention relates to a plurality of memory cell areas in which a plurality of memory cells are arranged in a matrix, an encoder that generates and adds check bits for error correction to data to be written in the plurality of memory cell areas, and the generator In the semiconductor device including an error correction circuit including a decoder that performs error correction processing on data read from the plurality of memory cell areas using the check bits, the error correction circuit includes: The error correction circuit sequentially orders the order of k = b × c bits (c is an integer of 2 or more) of information bits over N (N is a natural number) memory cell areas among the plurality of memory cell areas. The c-bit data varied in parallel is input in parallel, and one h-bit (h is an integer of 2 or more) check bits are generated internally by b shift operations, and (k + h) -bit data is generated. And at the same time unit for writing and reading, the plurality of memory cell areas, after which said data outputted by c bits in synchronism with the shift operation of the error correction circuit, said b times the shift operation is completed The check bits output in the above are stored in page units .

The present invention also includes a plurality of memory cell areas in which a plurality of memory cells are arranged in a matrix, and an encoder that generates and adds check bits for error correction to data to be written in the plurality of memory cell areas. in the semiconductor device having an error correction circuit, the encoder of the plurality of the memory cell area, N (N is a natural number) over the memory cell area k = b × a bit (a of 2 or more 1 h) (h is an integer of 2 or more) check bits are added to the information bit data of the integer), and a-bit data having different orders in order is added to the encoder in parallel. input to the generating check bits therein in b times shift operation, the plurality of memory cell areas, the data and loaded by a bit in synchronism with the shift operation of the error correction circuit And to store the said b times said check bit shift operation is loaded in at the end of completion of the write operation in page units.

  The present invention provides a plurality of memory cell areas in which a plurality of memory cells are arranged in a matrix, and write data to the memory cell area and read data from the memory cell area provided in a data input / output section of each memory cell area. A plurality of input / output terminals for inputting data for writing to each memory cell area from the outside and outputting data read from each memory cell area to the outside, An encoder that is provided between a plurality of input / output terminals and the plurality of buffers, and generates and adds an error correction check bit to data to be written to the plurality of memory cell areas, and the generated check An error is provided with a decoder that performs error correction processing on data read from the plurality of memory cell areas using bits. In the semiconductor memory device including the correction circuit, the error correction circuit has M × N bits (N is 2 or more), where M is the number of data bits as a unit of writing and reading with respect to one memory cell area. 1) is assigned as one information bit length, and at least one of the encoding process and the decoding process is executed by processing N-bit data in parallel. .

  According to the present invention, information bits are conventionally generated for each M bits, which is a unit of access to each memory cell area. However, since N bits can be processed in parallel, M × N bits Thus, one check bit can be assigned to the total number of check bits, and the number of check bits for the total information bits can be reduced. Thereby, the integration degree of the chip can be improved while mounting the error correction circuit.

As an example, in a t-bit correction (t + 1) bit error detection BCH code,
[Equation 16]
Code length n = 2 ^m −1
Number of information bits k ≦ 2 ^m −1−m × t
Number of inspection bits mt + 1 ≦ n−k
Number of correction bits t
Therefore, if the number of m is increased, the code length and the number of information bits increase exponentially, but the number of check bits does not increase so much. For this reason, the ratio of the number of check bits to the number of information bits becomes smaller as the number of information bits is larger as long as it does not exceed 2 ^m −1−m × t. Therefore, it is advantageous to provide check bits for as many information bits as possible.

  For example, a NAND flash memory reads or programs in one page (528 bytes), but when 2-bit error correction and 3-bit error detection are performed for each IO (each memory cell area), the number of information bits is k = Since 528 bits and the number of check bits are 21 bits, a total of 21 × 8 = 168 extra check bits are required.

  However, when 2-bit error correction and 3-bit error detection are performed in one unit for one page, when the number of information bits is 4224 bits, the number of check bits may be 27 bits. Even for 3-bit error correction and 4-bit error detection, when the number of information bits is 4224 bits, the number of check bits is 40 bits.

In one embodiment of the present invention, N memory cell areas are provided. The encoder is composed of, for example, a shift register and an arithmetic circuit that generate a cyclic code derived from a generator polynomial G (X) defined by an information bit length k = M × N, a code length n, and a correction bit length t as check bits. The shift register inputs N bits of data of different orders in parallel, multiplies each data by X ^N by one shift operation, and generates the check bit internally by M shift operations To do.

In addition, the decoder receives, for example, the information bit and the check bit, calculates a syndrome, a syndrome calculation circuit, a first arithmetic unit that calculates an error locator polynomial term from the calculated syndrome, and a calculation An error position detection circuit comprising a second calculation unit for detecting an error position by calculating an error position polynomial from an error polynomial term, and the detection for the data read from the memory cell area via a buffer. A data inversion circuit that performs data inversion processing at the error position, and the syndrome calculation circuit has a minimum polynomial M of an α operator defined by an information bit length k = M × N, a code length n, and a correction bit length t. X) based on a shift register that generates a cyclic code as a syndrome and an arithmetic circuit, and the shift register has N bits with different orders. Data is input in parallel, each data is ^multiplied by X ^KN (K is an integer) in one shift operation, and all the information bits and check bits are input to generate a syndrome internally. It is.

The error position detection circuit includes a cyclic code based on a minimum polynomial M (X) of an α operator defined by an information bit length k = M × N, a code length n, and a correction bit length t. The shift register performs a shift operation in synchronization with the data output from the memory area, and each data is multiplied by X ^K (K is an integer). The error correction position is sequentially detected.

The encoder, the syndrome calculation circuit, and the first arithmetic unit may be configured by switching between a register and an arithmetic circuit constituting the arithmetic logic circuit. The decoder may further include a Galois arithmetic circuit used when calculating a syndrome or error locator polynomial term. Further, the second arithmetic unit, for example, N locators respectively provided for the N-bit data, and X ^L times the data to the adjacent locators inserted between adjacent locators X ^{And an L} arithmetic circuit (L is an integer).

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(1) First Embodiment First, in order to understand the present invention, as a first embodiment, as an example of 2-bit error correction with the number of information bits k = 7, the code length n = 15, and the number of correction bits t = 2 Will be described.
(1-1) when the input data I ₀ of the conventional coding circuit 10 shown in encoding circuit diagram 22 is input to the encoding circuit 10, the input data I ₀ is coded circuit by XOR circuit 12 ₄ are added up in the section of X ^7, is then X times. Since the value of each register 11 of the encoding circuit 10 is 0 in the initial state, when this value is (0), [Equation 17]
(0 + I ₀ X ⁷ ) X
It becomes. Next, when the input data I ₁ is input to the encoding circuit 10, the input data I ₁ is added to the term X ⁷ of the encoding circuit 10 and is then multiplied by X.
[Equation 18]
((0 + I ₀ X ⁷ ) X + I ₁ X ⁷ ) X
It becomes.

Next, when the input data I ₂ is input to the encoding circuit 10, the input data I ₂ is added to the term X ⁷ of the encoding circuit 10 and is then multiplied by X.
[Equation 19]
(((0 + I ₀ X ⁷ ) X + I ₁ X ⁷ ) X + I ₂ X ⁷ ) X
It becomes.

Similarly, when the input data I ₆ is input to the encoding circuit 10,
[Equation 20]
(((((((0 + I ₀ X ⁷ ) X + I ₁ X ⁷ ) X + I ₂ X ⁷ ) X + I ₃ X ⁷ ) X + I ₄ X ⁷ ) X
+ I ₅ X ⁷ ) X + I ₆ X ⁷ ) X
It becomes. When this equation is transformed, [Equation 21]
((((0 + I ₀ X ⁷ + I ₁ X ⁶ ) X ² + I ₂ X ⁷ + I ₃ X ⁶ ) X ² + I ₄ X ⁷ + I ₅ X ⁶ ) X ² + I ₆ X ⁷ ) X
This is because the input data I ₀ and I ₁ are respectively added to the X ⁷ and X ⁶ terms of the encoding circuit 10 and then multiplied by X ² , and then the input data I ₂ and I ₃ are respectively It is added to the terms X ⁷ and X ⁶ of the encoding circuit 10 and then multiplied by X ² , and then the input data I ₄ and I ₅ are added to the terms X ⁷ and X ⁶ of the encoding circuit 10 respectively. This means that it is multiplied by ² after this. That is, after 2-bit input, the data is multiplied by X ² by one operation of the shift register 11. However, the last I ₆ is a 1-bit input as usual, and is multiplied by X.

Here, assuming that the value of the shift register 11 is the value shown in Equation ^{2, and} multiplying this by X ² ,
[Equation 22]
a ₀ X ² + a ₁ X ³ + a ₂ X ⁴ + a ₃ X ⁵ + a ₄ X ⁶ + a ₅ X ⁷ + a ₆ X ⁸ + a ₇ X ⁹
However, since there is a relationship of X ⁸ = X ⁷ + X ⁶ + X ⁴ +1 from the generator polynomial G (x) of Equation 1, Equation 21 is
[Equation 23]
(A ₆ + a ₇ ) X ⁰ + a ₇ X ¹ + a ₀ X ² + a ₁ X ³ + (a ₂ + a ₆ + a ₇ ) X ⁴ + (a ₃ + a ₇ ) X ⁵ + (a ₄ + a ₆ + a ₇ ) X ⁶ + (a ₅ + a ₆ ) X ⁷
It becomes.

  FIG. 1 is a block diagram showing a configuration of an encoding circuit 50 according to this embodiment in which Equation 23 is specifically configured by a circuit.

The encoding circuit 50 includes a shift register 51 composed of registers D ₇ , D ₆ , D ₅ , D ₄ , D ₃ , D ₂ , D ₁ , D ₀ and XOR circuits 52 ₁ , 52 ₂ , 52 ₃ , 52. _4, and 52 _5, 52 _6, 52 _7, and an input four switches SW11 for switching the data and output data, SW12, SW21, SW22 Prefecture. As shown in FIG. 2, the shift register 51 is a four-stage transfer in which the data content is reset by a reset signal RSTn and 1-bit data is transferred from the input terminal IN to the output terminal OUT in synchronization with the clock signal CLK. A gate 51a and a necessary gate circuit 51b are included. As shown in FIG. 3, the XOR circuit 52 performs a modulo 2 operation on the data input to the input terminals IN1 and IN2, and outputs the result from the output terminal OUT.

The encoding circuit 50 based on the number 23, a single shift operation, the value a _6, a ₇ registers D _6, D ₇ and stored in the register D ₀ crowded added in XOR gate 52 _6, register D ₇ value a ₇ is stored in register D ₁ , register D ₀ value a ₀ is stored in register D ₂ , register D ₁ value a ₁ is stored in register D ₃ , and registers D ₂ , D ₆ , The values a ₂ , a ₆ and a ₇ of D ₇ are added by the XOR circuits 52 ₁ and 52 ₆ and stored in the register D _4. The values a ₃ and a ₇ of the registers D ₃ and D ₇ are added by the XOR circuit 52 ₂ . crowded added and stored in the register D _5, and stores the value a _4, a _6, a ₇ registers D _4, D _6, D ₇ to the register D ₆ crowded adding an XOR circuit 52 _3, 52 _6, register D _5, to store the value a _5, a ₆ in D ₆ to the register D ₇ crowded adding an XOR circuit 52 _5.

Input data (information bits) I ₀ , I ₁ , I ₂ , I ₃ , I ₄ , I ₅ , I ₆ input from the outside because they are written in the memory are input data I ₀ , I ₂ , I ₄ , The input data I ₁ , I ₃ , and I ₅ are divided into two, and the input data I ₀ , I ₂ , and I ₄ are input to the ON terminals of the switches SW11 and SW21, and the input data I ₁ , I ₃ , I ₄ are input. ₅ is input to the ON-side terminals of the switches SW12 and SW22. That is, input data is input in parallel in the order of (I ₀ , I ₁ ), (I ₂ , I ₃ ), (I ₄ , I ₅ ) in units of 2 bits, and the shift register 51 operates once after input. However, the shift register 51, because it is connected to every other data in a single shift operation is ^doubled X. While the data (I ₀ , I ₁ ), (I ₂ , I ₃ ), (I ₄ , I ₅ ) are being input, the switches SW11, SW21, SW12, SW22 are all ON, and these data are The two bits are output in parallel as they are. At the same time, the data I _0, I _2, I ₄ is added up by the XOR circuit 52 ₇ and the value a ₇ of the register D _7, stored sequentially in the shift register 51, data I _1, I _3, I ₅ are XOR are added up by the circuit 52 ₄ with the value a ₇ of the register D _7, it will be stored sequentially in the shift register 51. However, since the last I ₆ of the input data is a 1-bit input, the connection state is switched to the same connection state as that of the conventional encoding circuit 10 shown in FIG. Such switching is performed because k = 7 is selected as the number of information bits. When the input of the data I ₀ , I ₁ , I ₂ , I ₃ , I ₄ , I ₅ , I ₆ is completed, the registers D ₇ , D ₆ , D ₅ , D ₄ , D ₃ , D ₂ , In D ₁ and D ₀ , check bits I ₇ , I ₈ , I ₉ , I ₁₀ , I ₁₁ , I ₁₂ , I ₁₃ and I ₁₄ are stored. Thereafter, the switches SW11, SW21, SW12, and SW22 are all connected to the OFF side, and each time the shift register 51 is operated, the check bits I ₇ , I ₉ , I ₁₁ , and I ₁₃ are output to the output of SW ₁₁ . Check bits I ₈ , I ₁₀ , I ₁₂ , and I ₁₄ are output as outputs. At the same time, the value of the shift register 51 is reset. As a result, it is possible to generate check bits by parallel processing of 2-bit input.
(1-2) Decoding Circuit (1-2-1) S ₁ Syndrome Calculation Circuit In the conventional S ₁ syndrome calculation circuit 20 shown in FIG. 23A, first, the value in the S ₁ syndrome calculation circuit 20 is multiplied by X. Thereafter, the input data I ₀ is added to the term X ⁰ by the XOR circuit 22 ₁ . Since the value of the shift register 21 of the S ₁ syndrome calculation circuit 20 is 0 in the initial state, if this value is (0),
[Equation 24]
0 × X + I ₀
It becomes. Next, after the value in the S ₁ syndrome calculation circuit 20 is multiplied by X, the input data I ₁ is added to the term of X ⁰ .
[Equation 25]
(0 × X + I ₀ ) X + I ₁
It becomes. Subsequently, after the value in the S ₁ syndrome calculation circuit 20 is multiplied by X, the input data I ₂ is added to the term of X ⁰ .
[Equation 26]
((0 × X + I ₀ ) X + I ₁ ) X + I ₂
It becomes. When the input data I ₁₄ is input to the S ₁ syndrome calculation circuit 20 in this way,
[Equation 27]
((((((((((((0 × X + I ₀ ) X + I ₁ ) X + I ₂ ) X + I ₃ ) X + I ₄ ) X + I ₅ ) X
+ I ₆ ) X + I ₇ ) X + I ₈ ) X + I ₉ ) X + I ₁₀ ) X + I ₁₁ ) X + I ₁₂ ) X + I ₁₃ ) X + I ₁₄
It becomes. If this equation is transformed,
[Equation 28]
(((((((0 × X 2 + I 0 X + I 1) X 2 + I 2 X + I 3) X 2 + I 4 X + I 5) X 2 + I 6 X + I 7) X 2 + I 8 X + I 9) X 2 + I 10 X + I 11 ) X ² + I ₁₂ X + I ₁₃ ) X + I ₁₄
Becomes, which, after the value of the S ₁ syndrome calculation circuit 20 and ^two times X, the input data I _0, but the term X ^1, input data I ₁ are added up respectively in section X ^0, then after the value of the S ₁ syndrome calculation circuit 20 and ^two times X, the input data I _2, but X ¹ term, the input data I ₃ are added up respectively in section X ^0, then, S ₁ syndrome calculation after the value of the circuit 20 is ^doubled X, means that the input data I ₄ is the section X ^1, the input data I ₅ are added up respectively in section X ^0. That data in a single operation of the shift register is ^doubled X, after that, enter the 2-bit data. However, finally, after the value in the S ₁ syndrome calculation circuit 20 is multiplied by X, the input data I ₁₄ is added to the term of X ⁰ by 1-bit input.

Here, assuming that the value of the shift register 21 is the value shown in Equation 5 and is multiplied by X ² ,
[Equation 29]
a ₀ X ² + a ₁ X ³ + a ₂ X ⁴ + a ₃ X ⁵
However, since there is a relationship of X ⁴ = X + 1 from the minimum polynomial M ₁ (x) of α,
[Equation 30]
a ₂ X ⁰ + (a ₂ + a ₃ ) X ¹ + (a ₀ + a ₃ ) X ² + a ₁ X ³
It becomes.

FIG. 4A is a block diagram showing a configuration of the S ₁ syndrome calculation circuit 60 according to the present embodiment in which Equation 30 is specifically configured by a circuit.

The S ₁ syndrome calculation circuit 60 includes a shift register 61 composed of register D _0, D _1, D _2, D _3, and an XOR circuit 62 _1, 62 _2, 62 _3, 62 _4.

The S ₁ syndrome calculation circuit 60 based on the number 30, a single shift operation, and stores the value a ₂ of the register D ₂ to the register D _0, the value a _2, a ₃ register D _2, D ₃ crowded adding an XOR circuit 62 ₂ is stored in the register D _1, register D _0, the value of D ₃ a _0, and stores the a ₃ to register D ₂ crowded adding an XOR circuit 62 _4, the register D ₁ value a and stores ₁ in the register D _3.

Information bits I ₀ , I ₁ , I ₂ , I ₃ , I ₄ , I ₅ , I ₆ read from a memory cell area (not shown) and check bits I ₇ , I ₈ , I ₉ , I ₁₀ , I ₁₁ , I ₁₂ , I ₁₃ , I ₁₄ are I ₀ , I ₂ , I ₄ , I ₆ , I ₈ , I ₁₀ , I ₁₂ , I ₁₄ , I ₁ , I ₃ , I ₅ , I ₇ , I _{14 9} , I ₁₁ , and I _13, and the S ₁ syndrome calculation circuit 60 in the order of (I ₀ , I ₁ ), (I ₂ , I ₃ ), (I ₄ , I ₅ ),. The shift register 61 operates once after input in parallel. However, the shift register 61, because it is connected to every other data in a single shift operation is ^doubled X. Data _{I 0, I 2, I 4} , ..., I 14 is added up by the XOR circuit ₆₂₃ and the output a ₂ + a ₃ XOR circuits 62 _2, stored in the register D _1, data I _1, I _3, I _5, ..., I ₁₃ is added up by the XOR circuit 62 ₁ and the value a ₂ of the register D _2, is stored in the register D _0. However, since the last I ₆ of the information bits is a 1-bit input, it is switched to the same wiring as the circuit of FIG. Alternatively, I ₁₅ = 0 is input to the S ₁ syndrome calculation circuit 60 and shifted, and then the shift register is multiplied by X ⁻¹ . This enables parallel processing of 2-bit inputs.
(1-2-2) S ₃ Syndrome Calculation Circuit Next, the S ₃ syndrome calculation circuit 70 in FIG. 4B will be described. In the conventional S ₃ syndrome calculation circuit 30 of FIG. 23B, first, after the value in the S ₃ syndrome calculation circuit 30 is multiplied by X ³ , the input data I ₀ is input to the term X ⁰ by the XOR circuit 32 _1. I'm stuck. In the initial state, since the value of the shift register 31 of the S ₃ syndrome calculation circuit 30 is 0, when this value is (0), [Equation 31]
0 × X ³ + I ₀
It becomes. Next, after the value in the S ₃ syndrome calculation circuit 30 is multiplied by X ³ , the input data I ₁ is added to the term of X ⁰ .
[Formula 32]
(0 × X ³ + I ₀ ) X ³ + I ₁
It becomes. Subsequently, after the value in the S ₃ syndrome calculation circuit 30 is multiplied by X ³ , the input data I ₂ is added to the term of X ⁰ .
[Equation 33]
((0 × X ³ + I ₀ ) X ³ + I ₁ ) X ³ + I ₂
It becomes. In this way, when the input data I ₁₄ is input to the S ₃ syndrome calculation circuit 30,
[Formula 34]
(((((0X ³ + I ₀ ) X ³ + I ₁ ) X ³ + I ₂ ) X ³ + I ₃ ) X ³ + I ₄ ) X ³ + I ₅ ) X ³ + I ₆ ) X ³ + I ₇ ) X ³ + I ₈ ) X ³ + I ₉ ) X ³ + I ₁₀ ) X ³ + I ₁₁ ) X ³ + I ₁₂ ) X ³ + I ₁₃ ) X ³ + I ₁₄
It becomes. If this equation is transformed,
[Equation 35]
(((((0 × X ⁶ + I ₀ X ³ + I ₁ ) X ⁶ + I ₂ X ³ + I ₃ ) X ⁶ + I ₄ X ³ + I ₅ ) X ⁶ + I ₆ X ³ + I ₇ ) X ⁶ + I ₈ X ³ + I ₉ ) X ⁶ + I ₁₀ X ³ + I ₁₁ ) X ⁶ + I ₁₂ X ³ + I ₁₃ ) X ³ + I ₁₄
After the value in the S ₃ syndrome calculation circuit 30 is multiplied by X ⁶ , the input data I ₀ is added to the term of X ³ and the input data I ₁ is added to the term of X ⁰ . after the value of S ₃ syndrome calculation circuit 30 and ⁶ fold X, the input data I ₂ is X ³ sections, the input data I ₃ are added up respectively in section X ^0, then S ₃ syndrome calculation circuit 30 after the value was ⁶ times X, which means that the input data I ₄ the term of X ^3, the input data I ₅ are added up respectively in section X ^0. That data in a single operation of the shift register is ^six times X, after that, enter the 2-bit data. However, finally, after the value in the S ₃ syndrome calculation circuit 30 is multiplied by X ³ , the input data I ₁₄ is added to the term of X ⁰ by 1-bit input.

Here, assuming that the value of the shift register 31 is the value shown in Equation 5, and multiplying this by X ⁶ ,
[Equation 36]
a ₀ X ⁶ + a ₁ X ⁷ + a ₂ X ⁸ + a ₃ X ⁹
However, since there is a relationship of X ⁴ = X + 1 from the minimum polynomial M ₁ (x) of α,
[Equation 37]
(a ₁ + a ₂ ) X ⁰ + (a ₁ + a ₃ ) X ¹ + (a ₀ + a ₂ ) X ² + (a ₀ + a ₁ + a ₃ ) X ³
It becomes.

4 (b) is a block diagram showing the configuration of S ₃ syndrome calculation circuit 70 according to this embodiment constructed as specifically circuit number 37. The S ₃ syndrome calculation circuit 70 includes a shift register 71 composed of registers D ₀ , D ₁ , D ₂ , and D ₃ and XOR circuits 72 ₁ , 72 ₂ , 72 ₃ , 72 ₄ , 72 ₅ , and 72 _6. Has been.

The S ₃ syndrome calculation circuit 70 based on the number 37, a single shift operation, the value a _1, a ₂ of the register D _1, D ₂ stored in the register D ₀ crowded adding an XOR circuit 72 _1, the values a _1, a ₃ register D _1, D ₃ is stored in the register D ₁ crowded adding an XOR circuit 72 _6, crowded adding a value a _0, a ₂ registers D _0, D ₂ in XOR circuit 72 ₄ in stored in the register D _2, is stored in the register D _0, D _1, the value of _{D 3 a 0, a 1,} a 3 and the XOR circuit 72 _5, 72 crowded added at ₆ register D _3.

Information bits I ₀ , I ₁ , I ₂ , I ₃ , I ₄ , I ₅ , I ₆ read from a memory cell area (not shown) and check bits I ₇ , I ₈ , I ₉ , I ₁₀ , I ₁₁ , I ₁₂ , I ₁₃ , I ₁₄ are I ₀ , I ₂ , I ₄ , I ₆ , I ₈ , I ₁₀ , I ₁₂ , I ₁₄ , I ₁ , I ₃ , I ₅ , I ₇ , I _{14 9} , I ₁₁ , and I _13, and the S ₃ syndrome calculation circuit 70 in the order of (I ₀ , I ₁ ), (I ₂ , I ₃ ), (I ₄ , I ₅ ),. Input is performed in parallel, and the shift register 71 operates once after input. Data _{I 0, I 2, I 4} , ..., I 14 is added up by the XOR circuit 72 ₃ and output a ₁ + a ₃ XOR circuits 72 _6, stored in the register D _1, data I _1, I _3, I _5, ..., I ₁₃ is added up by the XOR circuit 72 ₂ and the output a ₁ + a ₂ XOR circuits 72 ₁ is stored in the register D _0. However, since the last I ₆ of the information bits is a 1-bit input, it is switched to the same wiring as the S ₃ syndrome calculation circuit 30 in FIG. Alternatively, I ₁₅ = 0 is input to the S ₃ syndrome calculation circuit 70 to perform a shift operation, and then the shift register is multiplied by X ⁻³ . This enables parallel processing of 2-bit inputs.

(1-2-3) Error Position Detection Circuit Next, the error position detection circuit will be described. In the error position detection circuit according to the present embodiment, the S ₁ and S ₃ syndrome calculation circuits 60 and 70 perform the conventional two shift operations by one shift operation. An operation corresponding to the shift operation for two times is performed. Now, the error locator polynomial of tens is
[Equation 38]
σ (Z) = S ₁ + σ ₁ × Z ² + σ ₂ × Z ⁴
And

5 and 6 are diagrams showing the configuration of the error position detection circuit configured based on the equation (38). The error position detection circuit 80 calculates and stores S ₁ , σ _1, and σ ₂ and detects the error position of the data based on Equation 38 and the first arithmetic unit 80a (FIG. 5), and outputs a detection signal. And a second arithmetic unit 80b for outputting. First calculation unit 80a is configured by a shift register 81, X ² arithmetic circuit 82, and X ⁴ arithmetic circuit 83 as shown in FIG. The shift register 81a is a syndrome S ₁ is stored as the initial state, the shift register 82a, σ ₁ = S ₁ ² as an initial state in 83a, the operation result of ^{_{σ 2 = S 1 3 + S}} 3 are stored. In the error position detection circuit 80, the output data _{I 0, I 1, I 2} , I 3, I 4, I 5, 1 every output data I ₀ of _{I 6, I 2, I 4} , I 6, in synchronism with, is performed error detection, shift registers 81a, 82a, by operating once 83a, X ² arithmetic circuit 82 in sigma ₁ term is Z ² times, the X ⁴ arithmetic circuit 83, sigma ₂ Are multiplied by Z ⁴ times. If there is an error, σ = 0.

Here, the X ² arithmetic circuit 82 has the same configuration as the X ² arithmetic circuit 43 in FIG. 25, the shift register 43a and the shift register 82a correspond to each other, and the XOR circuits 43b ₁ and 43b ₂ and the XOR circuits 82b ₁ and 82b. _{Since 2} corresponds, detailed description of the configuration is omitted.

Since the X ⁴ arithmetic circuit 83 multiplies the value of the shift register 83a shown in Equation 11 by X ^4, the value of the shift register 83a is
[Equation 39]
a ₀ X ⁴ + a ₁ X ⁵ + a ₂ X ⁶ + a ₃ X ⁷
However, since there is a relationship of X ⁴ = X + 1 from the minimum polynomial M ₁ (x) of α,
[Equation 40]
(A ₀ + a ₃ ) X ⁰ + (a ₀ + a ₁ + a ₃ ) X ¹ + (a ₁ + a ₂ ) X ² + (a ₂ + a ₃ ) X ³
It becomes. This is the X4 arithmetic circuit 83 based on the number 40, a single shift operation, the value a _0, a ₃ register E _0, E ₃ and stored in the register E ₀ crowded adding an XOR circuit 83 b ₁ , register E _0, E _1, and stores the value a _0, a _1, a ₃ of E ₃ in the register E ₁ crowded adding an XOR circuit 83 b _1, 83 b _2, register E _1, the value a ₁ of E _2, the a ₂ stored in the register E ₂ crowded adding an XOR circuit 83 b _3, and stores the values a _2, a ₃ register E _2, E ₃ in the register E ₃ crowded adding an XOR circuit 83 b _4.

6 includes a first detection unit 84 that detects error positions of the output data I ₀ , I ₂ , I ₄ , and I ₆ , and error positions of the data I ₁ , I ₃ , and I _5. a second detector 85 for detecting the data I _1, I _3, the sigma ₁ of terms and X arithmetic circuit 86 to Z times with respect to I _5, a data I _1, I _3, the sigma ₂ sections with respect to I ₅ Z ² consisting multiplies X ² arithmetic circuit 87.. The output of the result calculated by the XOR circuit 88 and the NOR gate 89 of each of the detection units 84 and 85 becomes 1 when the error position is reached, and the corresponding data Ii is inverted by this output, thereby shifting one time. In operation, it is possible to detect error positions in parallel at the same time by 2 bits. Although configuration of the X arithmetic circuit 86, X ² arithmetic circuit 87 is the same as the conventional circuit shown in FIGS. 25 and 26, no register for storing the data required.
(2) Second Embodiment FIG. 7 is a block diagram of a NAND flash memory according to a second embodiment in which an ECC circuit is mounted on a chip.

This memory, eight memory cell area 101 _0, 101 _1, ..., and a 101 _7. These memory cell area 101 _{0-101 7} temporary storage read data (D0 to D7) from the write data (D0 to D7) and the memory cell area 101 _{0-101 7} in the memory cell area 101 _{0-101 7} against eight page buffers 102 to _0, 102 _1, ..., 102 ₇ is provided. Between the page buffers 102 _{0 to} 102 ₇ and the I / O terminals 104 ₀ , 104 ₁ ,..., 104 ₇ , error correction check bits ECC for write data are generated and check bits (ECC) are used. Thus, an ECC circuit 103 that performs error correction of the read data is provided. Unlike the conventional circuit, this ECC circuit 103 is 528 bits × 8 I / O = 4224 bits (M = 528, N = read) written and written at once to all the memory cell areas 101 _{0 to} 101 ₇ . The data of 8) is used as information bits, and 40 common check bits are added to the information bits to perform error detection and correction.

The address and control signal input from the I / O terminal 105 are supplied to the control signal operation circuit 106 and the address decoder 107, respectively. The control signal operation circuit 106 inputs various control signals ALE, CLE, CE, WE, RE, WP and the like to generate a control voltage to be supplied to each part, and outputs a READY / BUSY signal to an external circuit. The address decoder 107 temporarily stores an address input from the outside via the I / O terminal 105 and drives the column decoder 108 and the block selection circuit 109. The column decoder 108 activates each one of the page buffers 102 _{0 to} 102 ₁ . The block selection circuit 109 applies a voltage necessary for reading, writing or erasing to the word lines in the memory cell areas 101 _{0 to} 101 ₁ .

Each memory cell area 101j (where j = 0 to 7) is configured by arranging electrically rewritable nonvolatile memory cells MC in a matrix as shown in FIG. In this example, 16 memory cells MC are connected in series as one unit, the drain of the memory cell MC at one end is connected to the bit line BL via the selection gate transistor SG1, and the memory at the other end is connected. The source of the cell MC is connected to the common source line SL via the selection gate transistor SG2. The control gates of the memory cells MC in the row direction are connected to the common word line WL, and the gate electrodes of the selection gate transistors SG1 and SG2 in the row direction are connected to the common selection gate lines SGL1 and SGL2. In this embodiment, 528 bits of data stored in the odd-numbered and even-numbered memory cells MC out of 1056 memory cells MC along the control gate line are written and read once. One page is a unit. In this example, data for 16 pages adjacent in the column direction is one block which is a unit of one erase. However, the memory cell area 101 _7, other memory cells MC for 1056 (528 × 2) information bits stored along the word line WL, and the detection bit 80 (40 × 2) for error correction bits A memory cell MC for storing is provided.

  As shown in FIG. 8, each page buffer 102j includes 528 data storage circuits 121, and each data storage circuit 121 is connected to two bit lines BLi and BLi + 1, and is selected by an address. The data of the memory cell MC in the memory cell area 101j is read via the one bit line BL, the state of the memory cell in the memory cell area MC is detected via the bit line BL, and the data via the bit line BL is detected. Writing is performed to the memory cell MC by applying a write control voltage to the memory cell MC in the memory cell area 101j. One of the 528 data storage circuits 121 is selected by the column decoder 108, and only the selected data storage circuit 121 is connected to the ECC circuit 103.

Therefore, in the entire memory, the data storage circuit 121 for 8 bits (8 IOs) indicating the same column address is connected to the ECC circuit 103 by the column decoder 108. In the read operation, one page of memory cells MC indicated by the dotted line in FIG. 8 is selected, and 528 × 8-bit data is stored in all the data storage circuits 121 at a time. The column decoder 108 increments the column address one by one in synchronization with a read enable (RE) signal input from the outside. As a result, a total of eight data storage circuits 121 are selected one by one in each of the memory cell areas 101 _{0 to} 101 ₇ , and data for 8 bits (8 IOs) is sequentially output to the ECC circuit 103. . Similarly, during the write operation, data of 8 bits (8 IO) is sequentially input from the outside to the ECC circuit 103 via the I / O terminals 104 _{0 to} 104 _7, and data of 8 bits is sequentially input from the ECC circuit 103. Is output. The column decoder 108 increments the column address by one in synchronization with a write enable (WE) signal input from the outside. As a result, a total of eight data storage circuits 121 are selected one by one for each of the memory cell areas 101 _{0 to} 101 ₇ , and 8-bit data from the ECC circuit 103 is input to the selected storage circuit 121. To go.

  Next, the ECC circuit 103 will be described in detail.

FIG. 9 is a block diagram showing details of the ECC circuit 103. The ECC circuit 103 includes an arithmetic logic circuit 131 including a plurality of stages of registers, XOR circuits, switches, a Galois arithmetic circuit 132 used for syndrome calculation, and an error position detection circuit 133 (mainly a second circuit) that operates during decoding. And a data inversion circuit 134. The arithmetic logic circuit 131 constitutes a check bit generation circuit when the ECC circuit 103 functions as an encoding circuit, and mainly functions as a syndrome arithmetic circuit and an error position detection circuit when the ECC circuit 103 functions as a decoder. A first arithmetic unit is configured.
(2-1) Coding Circuit In this ECC circuit 103, data is input 8 bits (D0 to D7), and error detection and correction are performed in units of 528 × 8 = 4224 bits. For example, when considering a BCH code with 3-bit correction and 4-bit error detection, information bit k = 4224, code length n = 8191, correction bit t = 3, m = 13, and a generator polynomial necessary for encoding and decoding is as follows: It becomes like this.

[Equation 41]
Primitive polynomial: F (X) = X ¹³ + X ⁴ + X ³ + X + 1
Parity polynomial: M ₀ (x) = X + 1
Minimum polynomial of α: M ₁ (x) = X ¹³ + X ⁴ + X ³ + X + 1
Minimum polynomial of α ³ : M ₃ (x) = X ¹³ + X ¹⁰ + X ⁹ + X ⁷ + X ⁵ + X ⁴ +1
Minimum polynomial of α ⁵ : M ₅ (x) = X ¹³ + X ¹¹ + X ⁸ + X ⁷ + X ⁴ + X ¹ +1
Generator polynomial: G (x) = M ₀ M ₁ M ₃ M ₅
= X ⁴⁰ + X ³⁹ + X ³⁸ + X ³⁵ + X ³⁴ + X ³³
+ X ³² + X ²⁸ + X ²⁷ + X ²⁶ + X ²⁵ + X ²³ + X ²²
+ X ²⁰ + X ¹⁸ + X ¹⁷ + X ¹⁶ + X ¹⁵ + X ¹⁴ + X ¹⁰
+ X ⁹ + X ⁵ + X ⁴ + X ² + X ¹ +1
As in the first embodiment, Equation 42 is transformed to obtain Equation 43.

[Formula 42]
(((((0 + I ₀ X ³⁹ ) X + I ₁ X ³⁹ ) X + I ₂ X ³⁹ ) X + I ₃ X ³⁹ ) ...
) X + I ₅₂₇ X ³⁹ ) X
[Equation 43]
(((((0 + I ₀ X ³⁹ + I ₁ X ³⁸ + I ₂ X ³⁷ ...... I ₇ X ³² ) X ⁸ + (I ₈ X ³⁹ ......
I ₁₅ X ³² )) X ⁸ ......... (I ₅₂₀ X ³⁹ + I ₅₂₁ X ³⁸ ...... I ₅₂₇ X ³² ) X ⁸
The meaning of Equation 43 is as follows. First, 8-bit data D0 to D7 = I ₀ , I ₁ , I ₂ ,..., I ₇ input to the clock of one WE signal are respectively X ³⁹ , X ³⁸ , X ³⁷ ,. ³² multiplied by summation in an internal register values, then the value of register X ^8. Subsequently, 8-bit data D0 to D7 = I ₈ , I ₉ , I ₁₀ ,..., I ₁₅ input to the clock of the next WE signal are respectively added to X ³⁹ , X ³⁸ , X ³⁷ ,. ³² multiplied by summation in an internal register values, then the value of register X ^8. This is repeated 528 times until the last 8-bit data D0 to D7 = I ₄₂₁₆ , I ₄₂₁₇ , I ₄₂₁₈ ,..., I ₄₂₂₃ .

FIG. 10 shows 40 stages of registers REG0, REG1,..., REG39 provided in the arithmetic logic circuit 131. These constitute the cyclic shift register of the encoding circuit. These registers REG0 to REG39 have inputs B0, B1,..., B39, and outputs A0, A1,. The arithmetic logic circuit 131 executes the XOR operation represented by the following equations 45 and 46 with one data input based on the generator polynomial of the equation 41 and the equation 43. The XOR operation used here is shown in Equation 44. Before the outputs A32 to A39 are output, the registers REG32 to REG39 are outputs obtained by adding 8-bit data D0 to D7 input from the outside to the register values by the XOR operation, as shown in Expression 45. AA32 to AA39 are output. The outputs A0 to A31 and AA32 to AA39 are connected to the XOR circuit, and the results B0 to 39 of the XOR operation represented by the equation 46 are connected to the inputs of the registers REG0 to REG39 and are captured in synchronization with the clock of the shift register. When this operation is repeated 528 times, 40 check bits I ₄₂₂₄ , I ₄₂₂₅ , I ₄₂₂₆ ,..., I ₄₂₆₄ are generated in the arithmetic logic circuit 131 registers REG0 to REG39.

  FIG. 11 is a flowchart showing the encoding process of the ECC circuit 103, and FIG. 12 is a timing chart of the encoding process.

First, when a data input command (80h) is input from the outside (S21), the registers REG0 to REG40 in the arithmetic logic circuit 131 are reset (S22), and then an address (Add) is given. Subsequently, a WE (write enable) signal is inputted from the outside, and data is loaded into the page buffer 102j 8 bits at a time in synchronization with this (S23, S24, S25). At the same time, the data is sent to the arithmetic logic circuit 131 and the check bit ECC is calculated. When the column address reaches the final 528 (S25), the data load is terminated. Subsequently, a program command (10h) is input from the outside, whereby a boosting operation by a charge pump (not shown) for writing data to the memory cell MC is started. At the same time, before performing the write operation, the check bits one by 5 bytes REG0~REG39 of 40 bits by an internal oscillator (not shown) or the like is output and stored in the data storage circuit 121 of the page buffer 102 _7. Thereafter, the data stored in the data storage circuit 121 is stored in the memory cell MC of one page (indicated by a dotted line in FIG. 8) selected by the external address Add.
(2-2) decrypt circuit (2-2-1) syndrome calculation circuit 3-bit error correction, it for 4-bit error detection requires four syndromes _{S 0, S 1, S 3} , S 5 It has been known. The syndrome S ₀ is obtained by the minimum polynomial M ₀ (x) = x + 1. When x ¹⁰ = x ³ +1 obtained by the minimum polynomial M ₁ (x) = x ¹⁰ + x ³ +1 is an α operator, the syndrome S ₁ is from the α operator, and the syndrome S ₃ is from the α ³ operator to the syndrome S. ₅ is obtained from the α ⁵ operators. In the conventional decoding circuit, only one bit can be input with respect to the clock of one WE signal, but it is the same as when the first embodiment is changed from Equation 27 to Equation 28 and from Equation 34 to Equation 35. In other words, 8-bit data can be captured with respect to a single WE signal clock. Accordingly, the syndrome S ₁ is obtained from the α ⁸ operator, the syndrome S ₃ is obtained from the α ²⁴ operator, and the syndrome S ₅ is obtained from the α ⁴⁰ operator.

FIG. 13 shows 40-stage registers REG0 to REG39 provided in the arithmetic logic circuit 131. The register REG0 constitutes the cyclic shift register of the S ₀ syndrome calculation circuit, the registers REG1 to 13 constitute the cyclic shift register of the S ₁ syndrome calculation circuit, and the registers REG14 to 26 constitute the cyclic shift register of the S ₃ syndrome calculation circuit. and, register REG27~39 constitute a cyclic shift register of the S ₅ syndrome calculation circuit. Here, the input of the register REG0 is PP0, the output is P0, the inputs of the registers REG1 to REG13 are AA0, AA1,..., A12, the outputs are A0, A1, ..., A12, and the inputs of the registers REG14 to 26 are BB0, BB1, .., BB12, the outputs are B0, B1,..., B12, the inputs of the registers REG27-39 are CC0, CC1,. The arithmetic logic circuit 131 executes the following mathematical expressions 47, 48, 49, and 50 with one data input. The 8-bit data D0 to D7 read from the data storage circuit 121 and the outputs P0, A0 to 13, B0 to 13, and C0 to 13 of the respective registers REG0 to REG39 are added by the XOR circuit, and the XOR The circuit outputs PP0, AA0 to 13, BB0 to 13, and CC0 to 13, which are connected to the inputs of the registers REG0 to REG39 and are captured in synchronization with the clock of the shift register. The XOR circuit connected to the register REG1~13 with alpha ⁸ calculation circuit, the input data D0~D7 is applied. The XOR circuit connected to the register REG14~REG26 with alpha ²⁴ calculation circuit, the input data D0~D7 is applied. The XOR circuit connected to the register REG27~39 with alpha ⁴⁰ calculation circuit, the input data D0~D7 is applied. However, since the α ⁴⁰ arithmetic circuit has a large circuit scale, α ⁴⁰ is input to one input of the Galois arithmetic circuit 132 shown in FIG. 9, and the output and data D0 to D7 are appropriately calculated by the XOR circuit. You can also

(2-2-2) Error position detection circuit (first arithmetic unit)
FIG. 14 is a flowchart showing the decoding process of the ECC circuit 103.

After inputting the data read command (00h) from the outside, the read operation is started by inputting the read address (Add) (S31). First, the data of the memory cells MC for one page (528 bytes) selected by the address are read out to the page buffers 102 _{0 to} 102 ₇ (S32). Thereafter, in synchronization with the signal oscillated by the internal oscillator, the data D0 to D7 are input to the ECC circuit 103 byte by byte, and the syndrome is calculated (S33). As shown in the equations 47 to 50 , after calculating the syndromes S ₀ , S ₁ , S ₃ , S ₅ , when S ₁ = S ₃ = S ₅ = 0 (S 34), S ₀ = 0 (S35) No error (normal output: S36). If S ₀ ≠ 0 (S35), correction is impossible (S37). When S ₁ = S ₃ = S ₅ = 0 is not satisfied (S 34), σ ₂ = S ₁ ² S ₃ + S ₅ and σ ₀ = S ₁ ³ + S ₃ are calculated (S 38). When σ ₀ = 0 (S39), and when σ ₂ = 0 and S ₀ = 0 (S40), since there is a 1-bit error, the process proceeds to a 1-bit correction algorithm (S41). When σ ₂ = 0 and S ₀ = 0 are not satisfied (S40), correction is impossible (S42). When σ ₀ ≠ 0 (S39), σ ₁ = S ₁ (S ₁ ³ + S ₃ ) and σ ₃ = (S ₁ ³ + S ₃ ) ² + S ₁ (S ₁ ² S ₃ + S ₅ ) are calculated (S43). ). When σ ₃ = 0 (S44), and when σ ₂ ≠ 0 and S ₀ = 0 (S45), since there is a 2-bit error, the process proceeds to an algorithm that corrects 2-bit (S46). If σ ₂ ≠ 0 and S ₀ = 0, correction is impossible (S47). When σ ₃ ≠ 0 (S44) and S ₀ = 1 (S48), there is a 3-bit error, so the process shifts to an algorithm for 3-bit correction (S49). However, the 2-bit correction and 3-bit correction algorithms are the same. If S ₀ ≠ 1 (S48), correction becomes impossible (S50).

FIG. 15 shows an error position detection circuit for performing these calculations. This error position detection circuit includes a first calculation unit including four 13-bit registers R, A, B, and C incorporated in the calculation logic circuit 131 and an XOR circuit (not shown), and a Galois calculation circuit 132. When connects × inserted between the eight locator 141 and these locators 141 alpha, a second arithmetic unit 133 consisting × alpha ^2, the arithmetic circuit 142 for performing an operation of × alpha ^3, between these 13 Bit buses BUSR, BUSA, BUSB, and BUSC are provided. The output of the Galois operation circuit 132 is connected to the register R.

FIG. 16 shows an algorithm for calculating σ ₀ , σ ₁ , σ ₃ , and σ ₂ that are terms of the error locator polynomial. The syndromes S ₁ , S ₃ , and S ₅ are stored in the registers A, B, and C, respectively, and if these are all 0, there is no error, so this calculation is not executed (S61). Otherwise, the operation of σ ₂ = S ₁ ² S ₃ + S ₅ is performed, the operation results are sequentially stored in the register R, and the operation result obtained at the end is transferred from the register R to the register C (S62). ). Next, an operation of σ ₀ = S ₁ ³ + S ₃ is performed, the operation results are sequentially stored in the register R, and the operation result obtained last is transferred from the register R to the register B (S63). If the calculation results obtained in the registers B and C are both 0, a 1-bit error is stored (S64), 1 is stored in the register R (S65), and if not, σ ₁ = S ₁ (S ₁ ³ + S ₃ ) and σ ₃ = (S ₁ ³ + S ₃ ) ² + S ₁ (S ₁ ² S ₃ + S ₅ ) are calculated (S 66, S 67, S 68).

On the other hand, in this embodiment, the information bit k = 4224 (528 × 8 bits) is corrected in the code length n = 8191. However, the code having the code length n = 8191 is originally checked as an information bit. It can have 8151 bits excluding 40 bits. Therefore, error location, 8151-4224 + 1 = 3928 will be are shifted by bits, when reading from the column address 0, the sigma ₁ alpha ^3928, the ^{_{σ 2 α 7856 (= 3928 ×}} 2), σ 3 ^Is multiplied by α ^{3593 (= 3928} × ^3-8191) (S69, S70, S71). Similarly, when reading from the column address address i, the sigma ₁ alpha ^{3928 + i,} the ^{_{σ 2 α 7858 (= (3928}} + i) × 2), the ^{_{σ 3 α 3596 (= (3928}} + i) × 3- ⁸¹⁹¹⁾ is multiplied. Coefficients such as α ^{3928 + i} are written in a ROM, for example. Since these coefficients depend on the column address i, they are stored in the vicinity of the column data storage selected by the column decoder 108 in FIG. Alternatively, only the coefficient at the column address 0 may be stored, and when another address is accessed, the error position detection operation may be moved with a dummy to match the coefficients.

  FIG. 17 is a block diagram showing details of the Galois arithmetic circuit 132.

  Now, the 13-bit inputs A and B shown in FIG.

[Formula 51]
A = a ₀ X ⁰ + a ₁ X ¹ + a ₂ X ² +... + A ₁₂ X ¹²
B = b ₀ X ⁰ + b ₁ X ¹ + b ₂ X ² +... + B ₁₂ X ¹²
In this case, A × B is as shown in Formula 52.

[Formula 52]
A × B = A (b ₀ X ⁰ + b ₁ X ¹ + b ₂ X ² +... + B ₁₂ X ¹² )
= Ab ₀ + X (Ab ₁ + X (Ab ₂ + X (Ab ₃ +...
_{... + X (Ab 12))} ))))))))))
When this is expressed as a circuit, the configuration shown in FIG. A and bi are ANDed by AND circuit 151, the result is multiplied by X by X multiplier circuit 152, and the XOR circuit 153 performs an XOR operation with the next AND result of A and bi + 1. Here, X multiplication circuit 152, as shown in FIG. (C), the minimum polynomial M ₁ of α number 41 (X), since there is a ^{X 13 = X 4 + X 3} + X + 1 relationship, the X ¹² performed with claim shifts in the section X ^0, the XOR circuit 154, are added up in terms of X ^3, X ^1, X ^0, the operation that is stored in the section X ^4, X ^3, X ¹ respectively .

As a result of the above calculation, σ ₁ , σ ₃ , σ ₂ , and σ ₀ are given as initial values to the 13-bit registers A, B, C, and R, respectively.

(2-2-3) Error position detection circuit (second arithmetic unit)
It is known that the detection of the error bit position follows the error position polynomial of the following equation 53 in the case of 3-bit correction and 4-bit correction.

[Formula 53]
σ (Z) = S ₁ + σ ₁ × Z + σ ₂ × Z ² + σ ₃ × Z ³
Z = α ^I (I = 0, 1, 2, 3...) Is sequentially substituted into the equation 53, and i where σ (α ^I ) = 0 is the error position. In this embodiment, since 8-bit data is output for one WE clock, the equation 53 is changed into the following equation 54 as in the first embodiment, which is transformed from the equation 10 into the equation 38. Deform.

[Formula 54]
σ (Z) = σ ₀ + σ ₁ × Z ⁸ + σ ₂ × Z ¹⁶ + σ ₃ × Z ²⁴
Thus, error detection is performed at the same time every 8 bits by 8 bits. That is, error detection is performed on I / O0 of the output data for 8 I / O, and if there is an error, σ = 0. As a result of the operation shown in FIG. 16, the shift of the arithmetic logic circuit 131, in which σ ₁ , σ ₃ , σ ₂ , and σ ₀ are given as initial values to the 13-bit shift registers A, B, C, and R, respectively. XOR circuit alpha ⁸ calculation circuit connected to the register a, XOR is alpha ²⁴ calculation circuit connected to the shift register B, the XOR lead to shift register C constituting the alpha ¹⁶ arithmetic circuits. Register AA0, AA1, ..., A12, output A0, A1, ..., A12, register B input BB0, BB1, ..., BB12, output B0, B1, ..., B12, register C input Are CC0, CC1,..., CC12, and outputs are C0, C1,..., C12, and these α ⁸ , α ¹⁶ , α ²⁴ arithmetic circuits perform arithmetic operations of 55, 56 and 57, respectively.

FIG. 18 is a circuit diagram showing a specific configuration of locator 141. Locator 141 consists XOR circuits 1 61 and NOR circuit 162. calculates the sigma (Z), and outputs the H and there is an error in the I / O0 (j = 0~7) (σ = 0). Thus, the data inversion circuit 134 of FIG. 9, the data of the data storage circuit 121 of the page buffer 102 ₀ at this time is output after being inverted.

On the other hand, for the I / O1 data, the σ ₁ term of σ (Z) is Z times, the σ ₂ term is Z ² times, and the σ ₃ term is Z ³ times. Is equipped with an arithmetic circuit 142 ₁ for calculating the term σ ₁ × X, the term σ ₂ × X ² , and the term σ ₃ × X ^3, and outputs the locator to solve the error locator polynomial. 141 ₁ is supplied. When an error is detected (σ = 0), the output becomes H. These X arithmetic circuit, X ² arithmetic circuit, X ³ the input of the arithmetic circuit X0～X12, when an output Y0～Y12, these arithmetic circuit performs the following operation. These arithmetic circuits do not need a register for storing data.

Next, regarding the I / O2 data, the σ ₁ term of σ (Z) is a value obtained by multiplying Z ² times, the σ ₂ term is Z ⁴ times, and the σ ₃ term is Z ⁶ times. When an arithmetic circuit that calculates the term σ ₁ × X ² on the basis of / O 0, the term σ ₂ × X ⁴ , and the term σ ₃ × X ⁶ is installed, the arithmetic circuit of a large multiple such as X ⁶ The circuit scale becomes large. For this reason, in this embodiment, an arithmetic circuit 141 ₁ is provided that causes the output of the arithmetic circuit 142 ₁ to be again XX, × X ² , and XX ³ . In the same manner to place the arithmetic circuit 142 ₇ until the data of I / O7.

  If the signal propagation delay time up to I / O 7 becomes a problem, as shown in FIG. 19, the eight locators 141 constituting the error position detection circuit (second arithmetic unit) 133 are connected to an arithmetic logic circuit. It is only necessary to halve the signal propagation path to the locator 141 by dividing it into four on both sides of 131.

  FIG. 20 is a timing chart when the ECC circuit 103 is decoded. FIG. 4A shows a case where data reading and error correction are performed after all the terms of the error position polynomial are calculated.

After inputting the data read command (00h) from the outside and inputting the address (Add) to be read, the READY / BUSY signal becomes active and the read operation is started. First, the data of the memory cell MC for one page (528 bytes) selected by the address is read to the page buffers 102 _{0 to} 102 ₇ . Subsequently, in synchronization with the signal oscillated by the internal oscillator, the data D0 to D7 are input to the ECC circuit 103 byte by byte, the syndrome is calculated, and the calculated syndromes S ₀ , S ₁ , S ₃ , S ₅ are stored. To compute the term of the error locator polynomial. After that, data is read in synchronization with the write enable (RE) signal, and at the same time, error correction processing is executed. In this case, compared to the case where the ECC circuit 103 is not provided, the additional amount of the busy time is calculated for the syndrome calculation and the error correction operator, which is 50 ns for one syndrome calculation and the operator calculation time. Assuming 3.6 μs, 528 × 50 ns + 3.6 μs = 30 μs.

FIG. 6B shows an example in which the syndromes S ₀ , S ₁ , S ₃ , and S ₅ are calculated simultaneously with the data read. The read operation is started in the same manner as described above, and one page (528 bytes) is shown. of the data of the memory cell MC is read to the page buffer 102 _{0-102 7,} the syndrome in the ECC circuit 103 together with the data D0~D7 from the page buffer 102 _{0-102 7} in synchronization with the RE signal is output byte by byte Calculation is performed. If an error is detected as a result of the syndrome calculation, the status / fail command (70h) becomes active, so an operator for error correction is calculated, and then the data is output again to correct the error. Do. In this case, if there is no error, the addition of the total busy time is zero.

  By the way, when the information bit is set to 528 bits and the information bit is set to 4224 bits, when 2-bit error correction and 3-bit error detection are performed, the number of allowable random defects (when the device defect probability is 1 ppm) The number of random defects) is naturally better when the information bits are 528 bits. Table 1 shows the case where this is applied to a NAND flash memory having a storage capacity of 256 Mbits. Table 1 shows, from the left side, the number of random defects in 256M bits, the required code length per page, and the number of defects when the device defect probability is 1 ppm.

  According to Table 1, in the 2-bit corrected BCH code having the number of information bits of 528 bits, the allowable number of random defects is 100 bits. If the number of information bits is 4224 bits, only 30 bits are allowed. In the information bit number 4224 bits, random defects are allowed up to 300 bits, and the necessary code is as short as 40 bits. Furthermore, with the 4-bit corrected BCH code and the number of information bits of 4224 bits, random defects are allowed up to 1000 bits, and the necessary code is also as short as 53 bits.

[Table 1]
2 bit correction BCH code (number of information bits: 528 bits) 21 x 8 = 168 bits 100 bits
2-bit correction BCH code (number of information bits: 4224 bits) 27 bits 30 bits
3-bit correction BCH code (number of information bits: 4224 bits) 40 bits 300 bits
4-bit correction BCH code (number of information bits: 4224 bits) 53 bits 1000 bits Here, when an ECC circuit is not installed in a 128-Mbit and 512-Mbit NAND flash memory, when a 2-bit correction ECC is installed, Table 2 below shows a comparison of chip sizes with the 2-bit correction ECC circuit according to this embodiment mounted.

[Table 2] 128M (0.16μm) 512M (0.16μm)
No ECC circuit 41.88mm ² (100.0%) 136.99mm ² (100.0%)
Conventional ECC circuit 44.72mm ² (106.8%) 143.96mm ² (105.1%)
This embodiment ECC circuit 43.21mm ² (103.2%) 140.42mm ² (102.5%)
As described above, in the flash memory equipped with the ECC circuit according to this embodiment, the conventional ECC circuit mounted memory has an increase in chip size of 6.8% (128M) and 5.1% (512M), respectively. On the other hand, in the ECC circuit mounted memory of this embodiment, the increase in chip size was 3.2% (128M) and 2.5% (512M), half of that.

1 is a block diagram showing a configuration of an encoder used in an ECC circuit mounted on a flash memory according to a first embodiment of the present invention. It is a block diagram which shows the structure of the shift register used for the encoder. It is a truth table of the XOR circuit used for the encoder. It is a block diagram which shows the syndrome calculation circuit in the decoder used for the ECC circuit. It is a block diagram which shows the 1st calculating part which comprises the error position detection circuit used for the decoder. It is a block diagram which shows the 2nd calculating part which comprises the position detection circuit. FIG. 4 is a block diagram of a NAND flash memory according to a second embodiment of the present invention. 3 is a circuit diagram showing a configuration of a memory cell area of the flash memory. FIG. It is a block diagram which shows the ECC circuit of the same flash memory. It is a figure which shows the register | resistor which comprises the logic circuit for an operation at the time of the encoding in the ECC circuit. It is a flowchart which shows the encoding process of the encoding circuit. It is a timing chart of the encoding process. It is a figure which shows the register | resistor which comprises the arithmetic logic circuit at the time of decoding in the ECC circuit. It is a flowchart which shows the decoding process. It is a block diagram of an error position detection circuit in the ECC circuit. It is a flowchart which shows the calculation algorithm of each term of an error position polynomial in the error position detection circuit. It is a block diagram of a Galois arithmetic circuit in the ECC circuit. It is a figure which shows the 2nd calculating part of the error position detection circuit. It is a block diagram which shows the other example of the error position detection circuit in the same ECC circuit. It is a timing chart of the decoding process in the ECC circuit. It is a block diagram which shows the structure of the NAND type flash memory carrying the conventional ECC circuit. It is a block diagram which shows the structure of the encoder in the conventional ECC circuit. It is a block diagram which shows the syndrome calculation circuit in the decoder of the conventional ECC circuit. It is a flowchart which shows the decoding algorithm of the conventional ECC circuit. It is a block diagram which shows the 1st calculating part of the error position detection circuit of the conventional ECC circuit. It is a block diagram which shows the 2nd calculating part of the error position detection circuit of the conventional ECC circuit.

Explanation of symbols

1 _{0-1 7,} 101 _{0-101 7} ... memory cell area 2 _{0-2 7,} 102 _{0-102 7} page buffer 3 ₀ ~3 _7, 103 ... ECC circuit 4 _{0-4 7,} 104 _{0-104 7} , 105 ... I / O terminals 10, 50 ... encoder 20, 60 ... S ₁ syndrome calculation circuit 30, 70 ... S ₃ syndrome calculation circuit 40, 80, 133 ... error position detection circuit 40 a, 80 a ... first Arithmetic units 40b, 80b ... second arithmetic unit 131 ... logic circuit for calculation,
132 ... Galois arithmetic circuit 134 ... Data inversion circuit

Claims (9)

A plurality of memory cell areas in which a plurality of memory cells are arranged in a matrix; and
An encoder that generates and adds check bits for error correction to data to be written to the plurality of memory cell areas, and data read from the plurality of memory cell areas using the generated check bits In a semiconductor device provided with an error correction circuit including a decoder that performs error correction processing on
The error correction circuit sequentially orders the order of k = b × c bits (c is an integer of 2 or more) of information bits over N (N is a natural number) memory cell areas among the plurality of memory cell areas. C bits of data that are different from each other are input in parallel, one h bit (h is an integer of 2 or more) is generated internally by b shift operations, and (k + h) bits of data are written simultaneously. And a unit for reading ,
In the plurality of memory cell areas, the data output in units of c bits in synchronization with the shift operation of the error correction circuit and the check bits output after the b-th shift operation is completed in page units. As a semiconductor device.   2. The semiconductor device according to claim 1, wherein N = c. The decoder inputs a syndrome bit and calculates a syndrome by inputting the information bit and the check bit;
Error position detection comprising a first calculation unit for calculating an error locator polynomial term from the calculated syndrome and a second calculation unit for calculating an error locator polynomial from the calculated error polynomial term and detecting an error position Circuit,
The semiconductor device according to claim 1, further comprising: a data inversion circuit that performs data inversion processing on the data read from the memory cell area at the detected error position.   4. The semiconductor device according to claim 3, wherein the encoder, the syndrome calculation circuit, and the first arithmetic unit are configured by switching between a register and an arithmetic circuit constituting the arithmetic logic circuit.   4. The semiconductor device according to claim 3, further comprising a Galois arithmetic circuit used when calculating a term of the syndrome or error locator polynomial. A plurality of memory cell areas in which a plurality of memory cells are arranged in a matrix; and
In a semiconductor device comprising: an error correction circuit including an encoder that generates and adds a check bit for error correction to data to be written to the plurality of memory cell areas;
The encoder is 1 for data of information bits of k = b × a bits (a is an integer of 2 or more) over N (N is a natural number) memory cell areas among the plurality of memory cell areas. A check bit of two h bits (h is an integer of 2 or more) is added, and a-bit data having different orders in order is input in parallel to the encoder, and an internal operation is performed by b shift operations. Generating the check bit ,
In the plurality of memory cell areas, the data loaded bit by bit in synchronism with the shift operation of the error correction circuit and the check bit loaded after the b-th shift operation is completed are page units. A semiconductor device which stores data by a write operation .   7. The semiconductor device according to claim 6, wherein N = a. The second arithmetic unit is composed of a plurality of locators and a plurality of arithmetic units connected between the locators,
It said first operation unit, according to claim 3 Symbol mounting semiconductor device, characterized in that it is connected by the second arithmetic unit and a plurality of buses. It said second operation unit, according to claim 3 Symbol mounting semiconductor device characterized in that it is arranged by dividing both sides of the first arithmetic unit.