JP3966342B2 - Digital signal reproduction device - Google Patents

Description

  The present invention relates to a digital signal reproducing apparatus, and more particularly to a resampling operation for resampling a run length limited code reproduced from a recording medium such as an optical disc at a desired bit rate to generate resampling data and outputting the resampled data to an equalizer. The present invention relates to a digital signal reproducing apparatus provided with a phase locked loop circuit.

  FIG. 10 is a block diagram showing an example of a conventional digital signal reproducing apparatus. In the figure, a digital signal recorded on a recording medium 51 such as an optical disk and obtained by digitally modulating an information signal is reproduced by reproducing means (not shown), preamplified by a preamplifier 52, and A / After being sampled by the D converter, the direct current component (DC component) is blocked by the ATC circuit 53, and automatic gain control (AGC) is performed by the AGC circuit 54 so that the amplitude becomes constant. The PLL circuit 55 generates digital data obtained by resampling the input signal input from the AGC circuit 54 at a desired bit rate, and supplies the digital data to an adaptive equalizer (crosstalk canceller (CTC)) 56.

  The adaptive equalizer 56 performs waveform equalization by giving, for example, a partial response (PR) characteristic to the input signal. The output signal of the adaptive equalizer 56 is supplied to the decoding circuit 57, where it is subjected to, for example, known Viterbi decoding and then supplied to the ECC circuit 58, and the error correction code in the decoded data string is used for the error correction code. The code error of the generated element is corrected, and decoded data with reduced errors is output.

  However, the conventional digital signal reproducing apparatus shown in FIG. 10 has the following problems especially when the recording medium 51 is an optical disc on which a run-length limit code is recorded.

  The first problem is that the level of the signal with a short inversion interval is small due to the high frequency attenuation characteristic of the digital signal reproducing device, and an inversion interval that does not exist in the recording signal may occur. It means that the reliability is low. This has a greater effect as the recording density of the recording medium 51 is increased. If an erroneous phase error is fed back, the error rate naturally deteriorates.

  The second problem is that since the phase error accumulates as the inversion interval of the recorded run-length limit code is longer, bit slip is more likely to occur. When a bit slip occurs, the phase error shows a completely different value, so there is a high possibility of inducing a phase fluctuation by itself. That is, a phase error near a signal with a very long inversion interval is also unreliable. This phenomenon has an influence especially at the stage of frequency pull-in, and in the worst case, a state in which pull-in cannot be performed also occurs.

  The third problem is that in a DVD (Digital Versatile Disc) or the like, a synchronization signal used for an error correction code (ECC) or the like has a pattern that does not exist within the run length limit of the signal (for a run length limit from 3T to 11T). 14T; T is the channel clock period), and it is easy to detect. However, the longer the inversion interval, the larger the DC component of the signal, and therefore the easier it is to deviate from the correct inversion position. is there. That is, a correct phase error cannot be obtained, and the phase fluctuation tends to occur by feedback control.

  When a phase fluctuation occurs in the vicinity of the synchronization signal and a bit slip or the like occurs, all the synchronization signal blocks are detected as erroneous data, resulting in a burst error, and the bit error rate and the like are significantly deteriorated. If this happens frequently, the system is fatal.

  The present invention has been made in view of the above points, and provides a digital signal reproducing apparatus capable of reliably reproducing recorded information on a recording medium while performing stable phase tracking without inducing phase fluctuation or bit slip by itself. The purpose is to provide.

  Another object of the present invention is to provide a digital signal reproducing apparatus capable of accurately reproducing recorded information of a high-density recording medium using partial response equalization.

The present invention comprises the following means 1) or 2) in order to solve the above problems.
That is,

1) The generation position of the bit clock signal is adjusted from the digital reproduction signal obtained by reproducing the recording signal recorded based on the run length restriction rule, and the generation position of at least one bit clock signal is the digital reproduction signal. A resampling operation phase-locked loop circuit that generates the bit clock signal so as to coincide with the zero-cross position of the signal and outputs a resampled digital reproduction signal resampled using the bit clock signal, and the resampled digital In a digital signal reproducing apparatus having a Viterbi decoding circuit that performs Viterbi decoding by performing partial response equalization on a reproduced signal, the resampling operation phase locked loop circuit includes a bit clock immediately before and after the zero-cross position of the resampled digital reproduced signal. An interpolator that outputs an interpolation data value for estimating a zero-crossing point of the resampled digital reproduction signal using a level value of the resampled digital reproduction signal at the position of the signal, and the interpolation data value output from the interpolator. A phase detector that outputs a phase error signal based on a time shift between the zero cross position on the time axis and the bit clock position immediately before the zero cross position or the bit clock position immediately after the zero cross position; and the digital reproduction When the time interval of the zero cross point of the signal exceeds a predetermined time interval determined by the run length restriction rule, the phase error signal at both of the zero cross points exceeding the predetermined time interval becomes an invalidation signal. Replace the phase error signal as a new phase error signal An error selection circuit that generates and outputs, a loop filter that integrates the new phase error signal output from the error selection circuit, and an output signal of the loop filter, receives the output signal of the loop filter, and generates the bit clock to the interpolator Provided is a digital signal reproducing apparatus characterized by comprising a timing generator for output.

2) The error selection circuit includes a counter circuit that counts the number of bit clocks output from the phase detector at the time interval of the zero cross point, and the number of bit clocks counted by the counter circuit is the run-length limit. It is determined whether or not the predetermined time interval determined by the rule indicates that the number of bit clocks counted by the counter circuit is within the predetermined time interval. Select and output a phase error signal, indicating that a predetermined time interval has been exceeded, selecting an error selection control signal generator that selects logic "0", and selecting the phase error signal and logic "0" The digital signal reproducing apparatus as described in the above item 1), comprising a switching circuit for switching.

  According to the present invention, only a valid component of the phase error signal is selected, and a new phase error signal is generated by invalidating the phase error signal generated both before and after the inversion interval outside the set range. Since the resampling operation based on an uncertain phase error is not performed by outputting the signal, it is possible to follow the stable phase without inducing its own phase fluctuation or bit slip compared to the conventional method. The recorded information on the recording medium can be surely reproduced by the stable performance.

  As a result, according to the present invention, the Viterbi decoding circuit in the latter stage of the equalizer that performs partial response equalization can exhibit a high error rate reduction effect that is close to the theoretical value.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of a digital signal reproducing apparatus. In the figure, a signal reproduced from an optical disk by a known optical head is supplied to an A / D converter 11, where it is sampled by a master clock and converted into a digital signal, and the AGC / ATC circuit 12 at the next stage. Here, automatic amplitude control (AGC) in which the amplitude is controlled to be constant and automatic threshold control (ATC) in which the threshold of the binary comparison is appropriately controlled (DC) are performed.

  The output signal of the AGC / ATC circuit 12 is supplied to the resampling DPLL 14 through a subtraction circuit 13 described later. The resampling DPLL 14 is a digital PLL (phase locked loop) circuit in which a loop is completed in its own block, and is generated by resampling (decimating interpolation) an input signal at a desired bit rate. (That is, resampling data of 180 ° out of the phase 0 ° and 180 ° of the resampling data) is supplied to the transversal filter and the error calculator 15 in the equalizer 16, respectively.

  Further, the resampling DPLL 14 detects a zero cross of the resampling data having a phase of 0 °, and supplies 0 point information obtained thereby to the tap delay circuit in the equalizer 16 and the error calculator 15. The 0 point information indicates the point at which bit sampling data crosses the zero level in bit clock units. Further, the resampling DPLL 14 locks the resampling timing, that is, the frequency and phase so that it becomes 0 based on the value of the 180 ° phase resampling data corresponding to the zero cross point indicated by the 0 point information. Let

  For example, the resampling DPLL 14 is configured as shown in the block diagram of FIG. In this figure, an interpolator 141 receives an input digital signal from the subtracting circuit 13 in FIG. 1 and a signal from a timing generator 145 (described later) as input signals, and data point phase information and bits input from the timing generator 145. The data value of the phase point data is estimated by interpolation from the clock and output. The output data value of the interpolator 141 is supplied to the phase detector 142.

  The phase detector 142 generates 180 ° resampled data from the input data value, that is, 0 ° phase resampled data, and outputs it. For example, by calculating (Dt-1 + Dt) / 2 with respect to data Dt-1 one bit before and data Dt at the present time, resampled data having a phase of 180 ° is obtained. Further, the phase detector 142 detects the zero cross point from the input data value, that is, the sampling data of the phase 0 °, and outputs the phase error using the data value at the zero cross point. For example, the phase error can be obtained by detecting the zero cross point from the data Dt-1 one bit before and the data Dt at the present time and multiplying the polarity of Dt-1 by (Dt-1 + Dt) / 2.

  Conventionally, only the phase error is output from the phase detector, but in this embodiment, 0 point information indicating the zero cross point is also output from the phase detector 142. This 0 point information indicates the timing at which the sample point of the above-described phase of 180 °, which corresponds to the zero cross point that the resampling DPLL 14 should lock.

  The phase error signal and the 0 point information output from the phase detector 142 are supplied to the error selection circuit 143. The error selection circuit 143 counts the bit sampling interval of the timing of the above 0 point information. If the count value Tcount does not exist in the set range (maximum value Tcmax, minimum value Tcmin), immediately after or immediately before and immediately after A new phase error signal is generated by invalidating the phase error signal output to, and supplied to the loop filter 144. That is, the phase error signal generated both immediately after the inversion interval outside the set range or immediately before and after the inversion interval is invalidated to generate a new phase error signal and supply it to the loop filter 144.

  The phase error signal integrated by the loop filter 144 is supplied to the timing generator 145, where the next data point phase of the output of the loop filter 144 is estimated, and this data point phase information is also generated. A bit clock is supplied to the interpolator 141.

  Returning to FIG. 1 again, the error calculator 15 extracts only the DC offset information from the output signal of the resampling DPLL 14 based on the 0 point information, and uses the integration processing as the DC shift component to obtain the subtraction circuit 13. To supply. The subtracting circuit 13 removes the DC component from the output signal of the AGC / ATC circuit 12 and supplies it to the resampling DPLL 14. The resampling DPLL 14 supplies the equalizer 16 with resampling data generated by resampling (decimating interpolation) the input signal from the subtraction circuit 13 at a desired bit rate.

  The equalizer 16 imparts a partial response (PR) characteristic to the output signal of the resampling DPLL 14 to equalize the waveform, and then supplies it to a Viterbi decoding circuit (not shown) for Viterbi decoding. The circuit configuration of this Viterbi decoding is well known. For example, a branch metric calculation circuit that calculates a branch metric from sample values of an equalized reproduction waveform, and a path metric is calculated by accumulating the branch metric every clock. A path metric calculation circuit and a path memory for storing a signal for selecting a most probable data series having a minimum path metric. The path memory stores a plurality of candidate sequences, and outputs the candidate sequences selected according to the selection signal from the path metric calculation circuit as a decoded data sequence.

Next, the configuration and operation of the resampling DPLL 14 that forms the main part of the signal reproduction apparatus will be described in more detail.
FIG. 3 shows a block diagram of an embodiment of the error selection circuit 143 constituting the resampling DPLL 14. As shown in the figure, the error selection circuit 143 includes a T count circuit 21 that obtains a count value Tcount of a bit sampling interval corresponding to a time interval of 0 point information output from the phase detector 142, and the count value Tcount is An error selection control signal generator 22 that outputs an error selection control signal having a different logical value depending on whether or not it is within a set range between the maximum value Tcmax and the minimum value Tcmin, and 0 that generates a fixed value 0 The generator 24 and the switch circuit 23 that selects either the phase error signal from the phase detector 142 or the fixed value 0 from the zero generator 24 by the error selection control signal and outputs it as a new phase error signal. Has been.

  The T count circuit 21 includes a switch circuit 211, a 1 generator 212, an adder 213, a 0 generator 214, a D-type flip-flop (D-FF) as shown in the block diagram of FIG. ) 215, the bit clock BCLK is input from the phase detector 142 to the enable terminal of the D-FF 215, and the master clock MCLK from the oscillator provided in the reproducing device is input to the clock terminal CLK. It is made like that. The output signal of the D-FF 215 is output as the count value Tcount, and is fed back to the adder 213.

  Further, as shown in FIG. 5, the error selection control signal generator 22 generates a logic when the count value Tcount satisfies the inequality Tcmin ≦ Tcount <Tmax, that is, when the count value Tcount exists within the set range. It is configured to output an error selection control signal of “1” and logic “0” otherwise.

  Next, the operation of this embodiment will be described with reference to the time chart of FIG. The case where the output signal of the resampling DPLL 14 when the error selection circuit 143 is turned off is the resampling data of the phase 180 ° indicated by x or ◯ of the signal as indicated by the solid line in FIG. Then, a phase error signal as schematically shown in FIG. 6B is extracted from the phase detector 142 in FIG. 2 and input to the error selection circuit 143. In FIG. 6B, E1 to E6 indicate phase error values.

  On the other hand, the D-FF 215 shown in FIG. 4 in the T count circuit 21 latches the signal input from the switch circuit 211 to the data terminal D by the master clock MCLK while the bit clock BCLK input to the enable terminal EN is active. To do. Here, the switch circuit 211 receives the fixed 0 value from the 0 generator 214 input to the terminal a and the output signal of the adder 213 input to the terminal b as inputs, and receives the 0 from the phase detector 142. Only when the point information is “1” (in this case, it indicates a zero cross point and indicates the timing at which a sample point formed by resampling exists), “0” input to the terminal a is selected, When the 0 point information is “0”, a value obtained by adding the output value of the D-FF 215 and the output of the 1 generator 212 by the adder 213 is selected.

  Therefore, the D-FF 215 latches 0 when the 0 point information is “1” (when data corresponding to the zero cross point indicated by a circle in FIG. 6A is input), and latches FIG. ) Is input with the other samples indicated by x, the output value of the adder 213 is latched, and the count value Tcount shown in FIG. 6C is output with a delay of one bit clock. The count value Tcount is reset to 0 when a zero-cross sample is input, and is incremented by one in the bit clock period, that is, every time sample data is input until the next zero-cross sample is input. The number of bit clocks (number of samples other than zero cross samples) in the time interval between two matching 0 point information is shown.

  The error selection control signal generator 22 is configured to output an error selection control signal of logic “1” when the count value Tcount satisfies the inequality Tcmin ≦ Tcount <Tmax, and logic “0” otherwise. Therefore, when the maximum value Tmax is set to “9” and the minimum value Tmin is set to “3”, an error selection control signal shown in FIG. 6D is output.

  The switch circuit 23 receives this error selection control signal as a switching signal, and the phase error signal schematically shown in FIG. 6B is input from the phase detector 142 to the terminal 23a, and from the 0 generator 24 to the terminal 23b. When logic “0” is input and the error selection control signal is “1”, that is, when the count value Tcount is within the set maximum and minimum values, the phase error signal input to the terminal 23a is selected. When the error selection control signal is “0”, that is, when the count value Tcount is not within the set maximum and minimum values, “0” input to the terminal 23b is selected and output. Therefore, the switch circuit 23 outputs a signal as schematically shown in FIG. 6E as a new phase error signal, which is input to the interpolator 141 through the loop filter 144 and the timing generator 145 of FIG. Is done.

  As described above, when the time interval between two adjacent zero cross points is the bit clock time interval within the set maximum value and minimum value range, the error selection circuit 143 outputs the output phase error signal of the phase detector 142. Outputs an output phase error signal from the phase detector 142, and if the bit clock time interval is outside the set maximum and minimum values, the phase detector 142 Since the output phase error signal 142 is not certain, it is invalidated and “0” is output.

  As a result, the output signal of the resampling DPLL 14 is as shown in FIG. 6 (F), which is a zero-cross sample that is output assuming that the black circle indicates a substantially correct phase error, and the white triangle mark is invalidated. Samples of the resulting phase error output timing are shown, and x indicates other sample data. As a result, the recorded information on the recording medium can be reliably reproduced while performing stable phase tracking without inducing phase fluctuation or bit slip.

  FIG. 7 shows error rate measurement results when the error selection circuit 143 is turned on and off, the vertical axis indicates the bit error rate (BER), and the horizontal axis indicates time. The bit error rate can be measured, for example, by reproducing the known data from the optical disc, passing it through the reproducing apparatus shown in FIG. 1, and comparing the decoded data obtained by Viterbi decoding with the known recording data.

  As indicated by I in FIG. 7, the BER with the error selection circuit 143 turned on is extremely small and stable, whereas the error selection circuit 143 is turned off (the same as the conventional digital signal reproducing apparatus). The BER of the state) is sometimes significantly degraded as shown by II and III. This is because a bit slip occurred in the vicinity of the synchronization signal having an inversion interval of 14T, and errors increased for the entire synchronization signal block. Such a burst error cannot be corrected even if a later-stage Viterbi decoder or error correction circuit is used, which causes an obstacle to the system.

  As described above, according to the present embodiment, the BER is stable at a small value, and does not induce phase fluctuations, bit slips, etc., and reliably tracks the recorded information on the recording medium while following the phase. It can be seen that can be played.

Next, another embodiment of the error selection circuit 143 will be described.
FIG. 8 is a circuit diagram showing another embodiment of the error selection circuit according to the present invention. In the figure, the same components as those in FIG. In FIG. 8, a first D-FF 26 and a two-input AND circuit 27 are provided between the error selection control signal generator 22 and the switch circuit 23, and the output phase error signal switch circuit of the phase detector 142. The second D-FF 28, the switch circuit 29, and the 0 generator 30 are provided in the signal path to 23. In this embodiment, only effective components of the phase error signal are selected, and inaccurate phase error signals generated before and after the inversion interval other than the set range are invalidated.

  Next, the operation of this embodiment will be described with reference to the time charts of FIGS. 9A to 9D are the same signals as those in FIGS. 6A to 6D, and description thereof is omitted. In the D-FF 26 shown in FIG. 8, 0 point information is input to the enable terminal EN, a master clock MCLK is input to the clock terminal CLK, and 0 point information of logic “1” is output from the phase detector 142 (in this case, zero cross point). The error selection control signal input from the error selection control signal generator 23 to the data input terminal is latched each time the input is input. Therefore, when the 0 point information has the waveform shown in FIG. 9E, the signal shown in FIG. 9F is extracted from the output terminal of the D-FF 26.

  The AND circuit 27 receives the output signal of the D-FF 26 and the error selection control signal from the error selection control signal generator 22 as inputs, and performs a logical product operation of these signals to finally obtain the signal shown in FIG. As an error selection control signal, it is supplied to the switch circuit 23 as a switching signal.

  Here, since the output signal of the D-FF 26 is a signal obtained by delaying the output error selection control signal of the error selection control signal generator 22 until the next zero cross point input time, the output signal of the AND circuit 27 is adjacent. The previous (past) error selection control signal indicating whether the time interval between the first and second zero cross points is within the set maximum value and minimum value among the three zero cross points that match. Logic “1” only when the current error selection control signal indicating whether the time interval between the second and third zero cross points is within the set maximum value and minimum value is both logic “1”. "

  On the other hand, the D-FF 28 is output from the phase detector 142 every time 0 point information is input to the enable terminal EN, the master clock MCLK is input to the clock terminal CLK, and 0 point information of logic “1” is input. The phase error signal schematically shown in FIG. 9B is latched. The D-FF 28 delays the phase error signal to the next zero cross point for time alignment with the output signal of the D-FF 26. The output signal of the D-FF 28 is next to the logic "1". It is held for a period until 0 point information is input.

  Therefore, the delay phase error signal output from the D-FF 28 and input to the terminal 29a is selected by the switch circuit 29 during the period when the 0 point information is logic “1”, and the 0 point information is logic “0”. During the period, by selecting the signal of the value “0” input from the 0 generator 30 to the terminal 29b, a phase error signal indicating phase error information can be obtained only during the period of 0 point information of logic “1”. . Therefore, when the zero point information has the waveform shown in FIG. 9E, the phase error signal schematically shown in FIG. 9H is output from the switch circuit 29 and input to the terminal 23a of the switch circuit 23. .

The switch circuit 23 performs the same operation as in FIG. 3, and when the error selection control signal from the AND circuit 27 is “1”, that is, within the range between the maximum value and the minimum value set by the two count values Tcount. Is selected, the phase error signal input to the terminal 23a is selected, and when the error selection control signal is “0”, that is, one or both of the two count values Tcount are set to the maximum value and the minimum value. When the value is not within the range, the value “0” input to the terminal 23b is selected and output.

  Therefore, the switch circuit 23 outputs a signal as schematically shown in FIG. 9I as a new phase error signal, which is input to the interpolator 141 through the loop filter 144 and the timing generator 145 of FIG. Is done.

  In this way, the error selection circuit 143 configured as shown in FIG. 8 has a bit clock in which the current zero cross point time interval and the previous zero cross point time interval are within the range of the maximum value and the minimum value set together. When it is time, it is determined that the output phase error signal of the phase detector 142 indicates a substantially accurate phase error, and the output phase error signal of the phase detector 142 is output. When the bit clock time is out of the range between the value and the minimum value, the output phase error signal of the phase detector 142 is invalid and is invalidated, and “0” is output. That is, an inaccurate phase error signal generated before and after the inversion interval outside the set range is invalidated.

  As a result, the output signal of the resampling DPLL 14 is as shown in FIG. 9 (J), which is a zero cross sample that is output assuming that the black circle indicates a substantially correct phase error, and the white triangle mark is invalidated. Samples of the resulting phase error output timing are shown, and x indicates other sample data. As a result, the recorded information on the recording medium can be reliably reproduced while performing stable phase tracking without inducing phase fluctuation or bit slip.

  The present invention is not limited to the above embodiment, and for example, the subtraction circuit 13 and the error calculator 15 of FIG. Further, the present invention can be applied not only to recording media such as optical disks but also to transmission of non-DC free signals that cause band limitation.

  The present invention can be applied to a digital signal reproducing apparatus provided with a re-sampling calculation phase locked loop circuit for performing a Viterbi decoding by resampling a run length limited code reproduced from a recording medium such as an optical disk.

It is a block diagram of one embodiment of a signal reproducing device. It is a block diagram of an example of resampling DPLL which is the principal part of a signal reproducing | regenerating apparatus. FIG. 3 is a block diagram of an embodiment of an error selection circuit in FIG. 2. FIG. 4 is a block diagram of an example of a T count circuit in FIG. 3. It is operation | movement explanatory drawing of the error selection control signal generator in FIG. FIG. 4 is a time chart for explaining operations in FIGS. 2 and 3. FIG. It is explanatory drawing of the effect of one Embodiment of this invention apparatus. FIG. 4 is a circuit diagram of another embodiment of the error selection circuit in FIG. 2. FIG. 9 is a time chart for explaining operations in FIGS. 2 and 8. FIG. It is a block diagram of an example of a general digital signal reproducing device.

Explanation of symbols

11 A / D converter 12 AGC / ATC circuit 14 Resampling DPLL circuit 16 Equalizer 21 T count circuit 22 Error selection control signal generator 23, 29, 211 Switch circuit 24, 30, 2140 Generator 26, 28, 215 D Type flip-flop (D-FF)
27 2-input AND circuit 141 Interpolator 142 Phase detector 143 Error selection circuit 144 Loop filter 145 Timing generator 212 1 generator 213 Adder

Claims (2)

The generation position of the bit clock signal is adjusted from the digital reproduction signal obtained by reproducing the recording signal recorded based on the run length restriction rule, and the generation position of at least one bit clock signal is the zero cross of the digital reproduction signal. A resampling operation phase-locked loop circuit that generates the bit clock signal so as to match the position and outputs a resampled digital reproduction signal resampled using the bit clock signal, and the resampled digital reproduction signal In a digital signal reproducing apparatus having a Viterbi decoding circuit that performs partial response equalization and Viterbi decoding,
The resampling calculation phase locked loop circuit is:
An interpolator that outputs an interpolation data value for estimating a zero-cross point of the resampled digital reproduction signal using a level value of the resampled digital reproduction signal at a bit clock position immediately before and after the zero-cross position of the resampled digital reproduction signal; ,
A phase error based on a time shift between the zero cross position on the time axis and the bit clock position immediately before the zero cross position or the bit clock position immediately after the zero cross position on the time axis using the interpolation data value output from the interpolator. A phase detector that outputs a signal;
When the time interval of the zero cross point of the digital reproduction signal exceeds a predetermined time interval determined by the run length restriction rule, the phase error signal at both the zero cross points exceeding the predetermined time interval is invalidated An error selection circuit that generates and outputs the phase error signal as a new phase error signal instead of an error signal;
A loop filter for integrating the new phase error signal output from the error selection circuit;
A digital signal reproducing apparatus comprising: a timing generator that receives an output signal of the loop filter, generates the bit clock, and outputs the bit clock to the interpolator. The error selection circuit includes a counter circuit that counts the number of bit clocks output from the phase detector at the time interval of the zero cross point, and the number of bit clocks counted by the counter circuit is determined according to the run length restriction rule. The phase error of the phase detector is determined when it is determined whether the bit clock number counted by the counter circuit is within the predetermined time interval by determining whether the predetermined time interval is satisfied An error selection control signal generator for selectively outputting a logic "0" when a signal is selected and output, indicating that a predetermined time interval has been exceeded, and a selection switch between the phase error signal and the logic "0" 2. The digital signal reproducing apparatus according to claim 1, further comprising a switch circuit for performing the operation.

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