JP3919766B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus that converts an image signal having various formats into an image signal of a desired format or combines the image signals.

  With the recent development of multimedia, there are increasing opportunities for displays with various image signal formats. In particular, the TV set and personal computer (PC) display used to be completely different from each other. However, the fusion of each other has progressed, and a TV that can display PC images and a PC that can input TV signals have appeared. I came. In addition, with the advent of new digital format video sources such as digital television and MPEG, and the advancement of three-dimensional graphics, the ratio of displaying moving images is increasing even for PC displays.

  FIG. 6 shows a block diagram of such a conventional display. In the figure, 1-1 is an input terminal for an analog image signal, 1-2 is a horizontal synchronization signal (IHD) input terminal for the input signal, and 1-3 is a vertical synchronization signal (IVD) input for the input signal. Terminal. An AD converter 2 converts an analog image signal input to the input terminal 1-1 into an n-bit digital signal. 3 is an input system image processing unit, 4 is a memory control unit, 5 is a memory unit for storing image data, 6 is an output system image processing unit, and 7 is an image display unit. Reference numerals 20-1, 20-2, 20-3, and 20-4 denote data buses that transmit n-bit digital signals to the respective units. Reference numeral 21 denotes a control bus composed of memory control lines and address lines, and reference numeral 22 denotes a memory data bus.

  Reference numeral 8 denotes a PLL (Phase Locked Loop) circuit, and ICK is an input system clock synchronized with the input IHD. An oscillation circuit 12 generates an output system clock OCK. Reference numeral 11 denotes an H and V counter circuit, which generates an output system horizontal synchronization signal OHD and a vertical synchronization signal OVD from the output system clock OCK. Reference numeral 9 denotes a microcomputer (μCOM) unit, and 19 denotes m control buses for controlling each unit.

  Before the digital image signal is stored in the memory unit 5, the input system image processing unit 3 performs processing such as image quality adjustment and image reduction conversion, and is transferred to the memory control unit 4. The memory control unit 4 stores the image data in the memory unit 5 at a timing corresponding to the input synchronization signals (IHD, IVD) and the input system clock ICK, and outputs the output system clock OCK, the horizontal synchronization signal OHD, and the vertical synchronization signal OVD. At the timing, the image data is read from the memory unit 5 and transferred to the output system image processing unit 6. The image processing unit 6 performs image quality adjustment, image enlargement conversion, and the like. As a result, input images in various formats of the input system are converted into image signals in a format suitable for the image display unit 7 via the memory.

  Furthermore, recently, in a large-screen display device such as a wide-capable TV, plasma display, rear projection TV, and projection projector, various displays such as movies, TV, home videos, presentations, TV conferences, and various materials are displayed. Increasingly, video sources are used in offices and homes. Further, among such forms, there is a multi-screen display device that displays a plurality of different input source images in one screen.

As an example of a display conventionally used in such a scene in FIG. 13, one system is an input of a digital computer image signal, and the other system has two PC inputs which are an input of an analog computer image signal. FIG. 2 is a block diagram of an image processing unit of an image display apparatus that controls output of a memory to perform synthesis and performs two-screen multi-screen display on one image display unit.

In FIG. 13, reference numeral 1-1a denotes an input terminal for a q-bit digital computer image signal (IDATA1) of the first system (PC1). Here, there should be three systems of red, blue, and green (RGB) originally, but in order to simplify the description of the configuration, one system is shown (the same applies hereinafter). 1-1b is an input signal horizontal synchronization signal (IHD1) input terminal, and 1-1c is an input signal vertical synchronization signal (IVD1) input terminal. Reference numeral 1-1d denotes an image signal clock (ICK1) input terminal, and reference numeral 1-1e denotes a DDC (DDC1) input / output terminal. Reference numerals 20-1a-1 and 20-1a-2 denote data buses for transmitting q-bit digital image signals to the respective units. Reference numerals 20-1b, 20-1c, 20-1d, and 20-1e denote signal lines for IHD1, IVD1, ICK1, and DDC1, respectively.
DDC is a standard for communication means for a computer to recognize and control a display device, recommended by VESA (Video Electronic Standard Association), which is a standardization organization.

1-2a is an input terminal for an analog computer image signal (IDATA2) of the second system (PC2). 1-2b is an input signal horizontal synchronizing signal (IHD2) input terminal, and 1-2c is an input signal vertical synchronizing signal (IVD2) input terminal. 1-2e is a DDC (DDC2) input / output terminal.
An AD converter 2 converts an analog image signal (IDATA2) into an n-bit digital signal. Reference numeral 8 denotes a PLL circuit which generates an input system clock (ICK2) on the PC2 side synchronized with the horizontal synchronizing signal (IHD2) input from the terminal 1-2b.

  20-2a-0 is an analog signal line, and 20-2a-1 and 20-2a-2 are n-bit digital signal lines. Reference numerals 20-2b, 20-2c, 20-2d, and 20-2e denote signal lines for IHD2, IVD2, ICK2, and DDC2, respectively.

  Reference numeral 3-1 denotes an image processor of the input system of the PC1, and 3-2 denotes an image processor of the input system of the PC2. 4 is a memory control for controlling the image signals input from the two input image processing units to be temporarily stored in a memory and output to the output image processing unit in order to output them as a multi-screen. Part. Reference numerals 5-1 and 5-2 denote frame memories (memory A and memory B) respectively corresponding to the input systems PC1 and PC2. 21-1 and 21-2 are control buses for the memories A and B, respectively, and 22-1 and 22-2 are data buses for the memories A and B, respectively.

Reference numeral 9 denotes a microcomputer unit for controlling the system, and reference numerals 19-1 and 19-2 denote microcomputer buses (MB) including control lines and data lines from the microcomputer to each unit. An oscillation circuit 12 generates an output system clock (OCK).
Reference numeral 11 denotes an H / V counter circuit which counts an output system clock (OCK) and creates an output system horizontal synchronizing signal (OHD) and a vertical synchronizing signal (OVD).

Reference numeral 6 denotes an output image processing unit, and 7 denotes an image display unit such as a liquid crystal display, a plasma display, or a CRT.
1-f is an input terminal of an image display unit for image display digital data (ODATA), 1-g is an input terminal of an image display unit for a horizontal synchronization signal (OHD) of an output signal, and 1-h is an output. This is an input terminal of an image display unit for a vertical synchronizing signal (OVD) of the signal. 1-i is an input terminal of the image display unit of the clock (OCK) of the output image signal, and 1-j is an input terminal of the image display unit of the microcomputer bus (MB).

  20-f-1, 20-f-2, and 20-f-3 are k-bit ODATA signal lines. Reference numerals 20-g-1 and 20-g-2 denote OHD signal lines. Reference numerals 20-h-1 and 20-h-2 denote OVD signal lines. Reference numerals 20-i-1 and 20-i-2 denote OCK signal lines.

Before the digital image signal input from the image input terminal 1-1a is stored in the memory unit A of 5-1, processing such as image quality adjustment and image reduction conversion is performed by the input system image processing unit 1 of 3-1. Is transferred to the memory control unit 4.
The analog image signal input from the image input terminal 1-2a is converted into digital data by the AD converter 2 in synchronization with the clock generated by the PLL circuit 8. The digital image signal thus obtained is subjected to processing such as image quality adjustment and image reduction conversion in the input system image processing unit 2 in 3-2 before being stored in the memory unit B in 5-2. 4 is transferred to the memory control unit.

  The memory control unit 4 stores the image data in the memory unit A of 5-1 at the timing corresponding to the input synchronization signal (IHD1, IVD1) and the input system clock ICK1 based on the signal obtained by processing the IDATA1, and the digital data from the IDATA2 Is converted into image data in the memory section B of 5-2 at a timing corresponding to the input synchronization signal (IHD2, IVD2) and the input system clock ICK2. Further, the memory units 5-1 and 5-2 store two pieces of image data at a timing that matches the relationship between the size and display position of a predetermined image synchronized with the output system clock OCK, horizontal synchronization signal OHD, and vertical synchronization signal OVD. Are transferred to the output system image unit 6. The image processing unit 6 performs image quality adjustment, image enlargement conversion, and the like. As a result, input images in various formats of the input system are converted into image signals in a format suitable for the image display unit 7 via a memory, and image data input from two inputs is combined on one screen. Perform multi-screen display.

  7 and FIG. 13, when the resolution of the image display unit 7 is XGA (horizontal 1024 pixels × vertical 768 pixels) and the display vertical frequency is 75 Hz, the input signal (the input signal of FIG. Operation when (1) VGA (horizontal 640 pixels × vertical 480 pixels) 100 Hz and (2) SVGA (horizontal 800 pixels × vertical 600 pixels) 60 Hz are input as the PC1 input or PC2 input in FIG. An example of timing is given. In the description of FIG. 7, the apparatus of FIG. 13 is described as being the same because both the PC1 input system and the PC2 input system operate in the same manner.

  In FIG. 7, reference numerals 30, 31 and 32 denote a vertical synchronization signal IVD (IVD, IVD1 or IVD2), a horizontal synchronization signal IHD (IHD, IHD1 or IHD2) and a clock ICK (ICK, ICK1 or ICK2) when the input is VGA 100 Hz. ICK2). The IVD is a period of (480 + α1) IHDs in which one cycle is 1/100 sec and includes a blanking period α1. One cycle of IHD is a period of (640 + β1) CLK of ICK including the blanking period of β1.

  Reference numerals 33, 34 and 35 denote IVD (IVD, IVD1 or IVD2), IHD (IHD, IHD1 or IHD2) and ICK (ICK, ICK1 or ICK2) when the input is SVGA 60 Hz. The IVD is a period corresponding to (600 + α2) IHDs, in which one cycle is 1/60 sec and includes a blanking period α2. Further, one cycle of IHD is a period of (800 + β2) CLK of ICK including β2 of the blanking period.

Reference numerals 36, 37 and 38 denote an output system vertical synchronization signal OVD, horizontal synchronization signal OHD and clock OCK when the output is XGA 75 Hz. The OVD is a period of (768 + α3) OHDs in which one cycle is 1/75 sec and includes a blanking period α3. OHD is a period of (1024 + β3) CLK of OCK, in which one period includes β3 corresponding to the blanking period.

  As described above, the horizontal synchronizing signal, the vertical synchronizing signal, and the input clock of the input system have different periods depending on the resolution. In the apparatus of FIG. 6, the microcomputer unit 9 determines the resolution and format from the IHD, IVD, etc., sets the frequency division ratio of the PLL circuit 8, and generates ICK corresponding to each format. On the other hand, the output system is asynchronous with the input system signal, and operates with OHD and OVD created with a constant counter value by the counter circuit 11 from the output clock OCK. In this manner, the vertical frequency of the input system and the output system, that is, the screen update frequency (frame rate) is converted.

  In the apparatus of FIG. 13, in the case of the input system 1 (PC1 input), the input signal processing system is operated in synchronization with IHD1, IVD1, and ICK1, and recorded in the memory A. In the case of the input system 2 (PC1 input), first, the microcomputer unit 9 determines the resolution and format based on the information exchanged by the IHD2, IVD2 and DDC2, and the PLL circuit 8 determines the ICK2 corresponding to each format. generate. Next, in synchronization with IHD2, IVD2, and ICK2, the input signal processing system is operated to record an image in the memory B.

On the other hand, the output system is asynchronous with the signal of the input system, OHD and OVD are created with a constant counter value from the output clock OCK by the counter circuit, and at the timing synchronized with OCK, OHD and OVD from the memory A and memory B. Two systems of images are read out, combined, and sent to an output image processing unit and an image display unit. In this way, resolution conversion and vertical frequency, that is, screen update frequency (frame rate) conversion between the input system and the output system are performed.
Japanese Patent Laid-Open No. 10-319928

  However, in this frame rate conversion, there is a problem of image quality degradation of moving images as shown in a specific example in FIG. In the description of FIG. 8, the same phenomenon occurs with respect to FIG. 13 because the PC1 input system and the PC2 input system operate in the same manner. Here, a case where the ratio of the input vertical frequency to the output vertical frequency is 5: 4 (for example, 100 Hz and 80 Hz) is shown as an example. In FIG. 8, reference numeral 41 denotes five consecutive (a to e) frame images that are input, and reference numeral 42 denotes four consecutive (f to 1) frame images that are output to the display device during the same period. The moving arrow is moving from left to right on the screen.

  Since one screen is read while writing to the same memory area, when the timing to rewrite one screen happens to be similar to the timing to read as shown in (a) and (f), (e) and (i), the change on the screen Although it does not appear, when the screen is rewritten while reading the screen as shown in (g) and (h), the previous and next screens are switched in the middle of one screen, and the moving images are shifted at the top and bottom of the screen. I can see. This is called “image overtaking”, and is a phenomenon in which the quality of an image is degraded when displaying a moving image. Conversely, the same phenomenon appears when the vertical frequency of the output is faster than the vertical frequency of the input.

  This phenomenon is more noticeable when a relatively large geometric object is moving horizontally relative to the screen, but it is less noticeable in natural images, etc. In addition, conventional PCs are word processors, spreadsheets, and drawings. Because there are many uses for still images, it was not a big problem. However, as described above, even for a PC, recently, there are more opportunities to display moving images, and more screens on which geometric graphics move are increasing, so the demand for moving images is also increasing.

  As a countermeasure against such a problem, there is a method called double buffering. This is because the memory area is prepared for two screens instead of one screen, and the memory areas are alternately switched and written every other screen, and reading is always performed in order to prevent overtaking of the screen. This is a method for controlling the memory area to be selected so that the scanning has a relationship preceding the scanning of writing in the memory area.

  For example, when storing data of the number of pixels of XGA (1024 × 768), as shown in the memory map of FIG. 9, even-numbered fields such as m, m + 2, m + 4... Field are stored in the first memory area at addresses 00000h to BFFFFh. And the input images of odd-numbered fields such as m + 1, m + 3, m + 5... Fields are stored in the second memory area of C0000h to 17FFFFh. FIG. 10 shows a timing chart of the memory write and read operations at this time. Reference numeral 61 denotes an input vertical synchronization signal (IVD), and reference numeral 64 denotes an output vertical synchronization signal (OVD). Since the description here is also common to the PC1 input and PC2 input with respect to FIG. 13, IVD indicates IVD1 or IVD2 (or both), and the first memory area and the second memory area are the memory A or memory B ( Or both).

  Each time the IVD 61 enters, the input field is updated as m, m + 1, m + 2,..., And every time the OVD 64 enters, the output field is updated as n, n + 1, n + 2,. 62 indicates a signal (WE1) indicating that the first memory area is to be written, 63 indicates a signal (WE2) indicating that the second memory area is to be written, and 65 indicates the first memory area. A signal (RE1) indicating that reading is performed is indicated by 63, and a signal (RE2) indicating that reading of the second memory area is performed is indicated by 63. Here, it is shown as active high.

  As described above, the writing is alternately written into the first and second memory areas at the even and odd numbers of the input field, but the reading is performed by selecting a field that is not displayed during writing. Here, since the vertical frequency on the output side is higher than the input, when the input field when the output VD becomes High writes the first memory area, the second memory area is read and the second memory area is read. Is written, the first memory area is controlled to be read so that the overtaking phenomenon does not appear. When the vertical frequency on the output side is low, it is necessary to perform control so that overtaking does not occur while looking at the relationship between the input VD (IVD) and the output VD (OVD). In any case, the read timing of the first memory and the second memory is always scanned according to the relationship between the input and output frequencies and the relationship between the synchronization signals. The memory area is set to be switched so that the relationship precedes the scanning.

However, this double buffering method also has the following problems with moving images.
In the case of double buffering, the other memory area is selected so that the memory area currently being written is not displayed. For example, as shown in FIG. 11, a person on the input screen 71 (a) to (d) When there is a continuous motion screen like turning one hand, the same image as shown in (e) and (f) in the output with the frame rate converted as shown in 72 (e) to (i). When there is a “frame duplication” in which two fields are continuous or a screen such as the input screens 81 (a) to (d) as shown in FIG. 12, the frame rate is as shown in 82 (e) to (g). As shown in (c), “frame missing” occurs in which the corresponding field disappears, as shown in (c).

Further, as a method of improving the moving image quality by a method different from the double buffering, there is a method of synchronizing the input vertical frequency and the output vertical frequency. In the case of a display unit of XGA (1024 × 768 pixels), when a 50 Hz input signal such as VGA (640 × 480) or SVGA (800 × 600) is received, it is converted to XGA 50 Hz and displayed. When the input signal is input, it is converted to XGA 100 Hz and displayed.

  In such a case, the writing and reading cycles of the memory coincide with each other, so that the problem of movement does not occur. However, when the input signal source has a low frequency, such as 50 Hz, the display with the polarity reversed for each field, such as a liquid crystal device, displays half the frequency. There is a problem in image quality that causes a flicker phenomenon in which the rewriting cycle is delayed and the entire surface flickers. Also, when the frequency is fast, such as 100 Hz, even if the number of pixels is low, such as VGA, the speed is about 2.6 times that of the input when converted to the output of the number of pixels of XGA, even if the speed is not great. Therefore, there is a problem that the operating speed of the entire output system must be increased. For example, the XGA 60 Hz clock rate is about 65 MHz, and the XGA 100 Hz is about 108 MHz, exceeding 100 MHz. In order to solve this problem, it is necessary to use high-speed parts, develop new parts, and divide the operating system into a circuit configuration that lowers the speed, leading to increased costs and increased circuit scale. End up.

  In addition to the above problems, there are problems due to the fact that there are two or more inputs. As shown in the example of FIG. 13, since the input system operates in synchronization with each input signal, the PC1 input and the PC2 input are basically asynchronous, while the output system has two systems at the same timing. In order to synthesize and output an image on one screen, the method of synchronizing the vertical frequency of input and output can be implemented for either one system, but cannot be applied to two systems at the same time. This problem is a big problem for multi-screen applications where the number of input systems increases and the quality of each moving image is important.

  Furthermore, for multiple image inputs, as well as the image quality of moving images, is it possible to optimize only one input system that is unique to multiple screens in terms of various image quality characteristics such as color, brightness, and contrast? Alternatively, there is a problem that the circuit scale increases when optimization is performed.

Here, an example of a problem related to gradation of image quality such as image contrast, brightness, and gamma characteristics is shown in the circuit of FIG.
FIG. 14 shows a gray scale signal in which the gradation changes in eight steps in the horizontal direction as one of the video signals input to the image processing apparatus such as FIG. 14-1 is a display screen in gray scale, and 14-2 is a signal at this time. In 14-2, the horizontal axis represents the time of one horizontal scanning period, and the vertical axis represents the signal level. 14-3 is a horizontal synchronizing signal of the input signal at this time. Here, in one horizontal period, from 0% to 100% changes equally in 8 steps.

  FIG. 15 shows the luminance characteristics of the display screen with respect to the input signal in the image display unit 7 of FIG. This characteristic is, for example, a light transmittance characteristic with respect to an input voltage for a transmissive liquid crystal, and a light reflectance characteristic with respect to an input voltage for a reflective device. This characteristic differs depending on the image display unit 7 shown in FIG. Here, two types of characteristics 15-1 and 15-2 will be described as examples. In 15-1 and 15-2, the horizontal axis indicates the level of the input signal of the screen display unit, the vertical axis indicates the level of display luminance, and a, b, and c each indicate a certain level of the input signal.

Here, it is assumed that input signals having different signal levels, such as 16-1A and 16-1B shown in FIG. 16, are input to the two systems of input IDATA1 and IDATA2 of PC1 and PC2 in FIG.
FIG. 16 shows display luminance levels 16-4A and 16-4B in two systems of signals when the image display unit having the characteristic indicated by 15-1 in FIG. 15 is used. As shown in 16-4A and 16-4B, even when the input signal has the same number of gradations, although 16-4B of IDATA2 is crushed in white 100% black 0%, the luminance level is almost 0% to 100%. On the other hand, the other 16-4A is an image in which black is shifted to the white side to about 60% and floated white. For this reason, when two screens are simultaneously displayed on the same display device, two screens having different black levels and different contrasts are mixed, so that the screen display is very difficult to see.

  Here, when the AGC (Auto-Gain-Control) circuit is provided in the input system image processing unit 1 (3-1) and the input system image processing unit 2 (3-2) in FIG. Correction is performed for signals having different levels and amplitudes. However, when the image display unit is replaced with a display unit having the characteristic 15-2 of FIG. 15, the signal is not corrected for the change in the characteristic.

17 and 18 show input signals and luminance levels when the characteristics of the display unit are 15-1 and 15-2 in FIG. 17 and 18, input signals 16-1A and 16-1B to be input to two systems of input IDATA1 and IDATA2, an input system image processing unit 1 (3-1), and an input system image processing unit 2 (3-2). ), The signal levels 16-2A and 16-2B after passing through the AGC circuit, and the luminance levels 16-4A and 16-4B of the display unit when this signal is input are shown. As indicated by 16-4A and 16-4B in FIG. 17, in the input / output characteristics of 15-1, gradations appear from 0% to 100% due to AGC.
However, as shown by 16-4A and 16-4B in FIG. 18, the gradation is only from 0% to 60% in the input / output characteristics of 15-2, and the white side is a whiteout image. End up.

  For such an exchange of the characteristics of the image display unit, it is conceivable that the output system image processing unit 6 in FIG. 13 has a correction characteristic for the characteristics of the image display unit. FIG. 19 shows the input signal and the luminance level when the characteristic of the display unit is 15-2 in FIG. Input signals 16-1A and 16-1B input to the two systems of input IDATA1 and IDATA2, and the input system image processing unit 1 (3-1) and the input system image processing unit 2 (3-2) after passing through the AGC circuit In addition to the signal levels 16-2A and 16-2B, the signal levels after passing through the output system image processing unit are 16-3A and 16-3B, and the luminance level of the display unit 7 when this signal is input is 16 -4A and 16-4B.

  As described above, the input system image processing unit of each signal has the correction characteristic of the input signal, and the output system image processing unit has the correction characteristic of the display unit. Multi-screen display with little influence of variation is realized. Examples of correction characteristics include brightness (bright), light and dark (contrast), gamma characteristics, and white balance resulting from differences in each color system.

However, providing image signal correction characteristics in both the input system and the output system in this way requires the preparation of a plurality of similar circuits, which increases the circuit scale and the number of adjustment items, and increases costs. . This becomes a problem particularly in a configuration having a large number of inputs.
Furthermore, such a configuration also causes image degradation by passing a digital processing system for characteristic correction twice or more. FIG. 20 shows a conceptual diagram for this explanation. In FIG. 20, the x-axis indicates the level of the input signal, and the y-axis indicates the input level of the output signal. In this figure, in the 8-bit 256-stage digital processing system, (1) y = x input / output characteristics, (2) y = x ² characteristic 1 table and (3) y = x ^1/2 The input / output characteristics of (4) y = [x ² ] * [x ^1/2 ] ≈x after passing through the characteristic 2 table shown in FIG. Originally, (4) and (1) should match, but the output is normalized to 8 bits at each stage of the computation pass of characteristic 2 of (2) and characteristic 2 of (3). In this case, a calculation error occurs. In (4) after synthesis, 0 to 5
The bit error of y for x of about 0 is large.

If this is applied to the conventional example, this corresponds to giving characteristic conversion as shown in (2) in the input system and giving characteristic conversion as shown in (3) in the output system. In this case, the output image As a result, the gradation of the black level of the image quality deteriorates, and image quality deterioration such as a pseudo contour occurs in the image.
In order to avoid this phenomenon, there is a method of increasing the number of operation bits, but this causes an increase in cost and the scale of the processing system.

  As described above, in the conventional multi-screen display in which images of a plurality of input signal sources are displayed on the same display unit, the configuration for converting the characteristics of different input images into the same display characteristics with respect to changes in the characteristics of the display unit is large. There is a problem in that the cost increases and the cost increases. In addition, the circuit configuration has a large bit error, which causes a problem of image quality deterioration. For this reason, the brightness, contrast, gradation, color, etc. of each input system cannot be easily arranged.

  In addition, when the AGC circuit is provided in the input image processing device, the dynamic range of the signal can be secured, but since the correction is performed automatically, the signal level to be originally displayed is also corrected and the intention of the signal transmission side is set. There was also a problem to ignore.

  An object of the present invention is to provide a multi-screen display image processing apparatus that displays input images from a plurality of input signal sources on the same screen, and the difference in the format of input signals from each input system and the characteristics of display contents An object of the present invention is to realize an image processing apparatus that performs processing suitable for moving image quality flexibly with respect to characteristics of an image display unit at low cost.

In order to achieve the above object, in the present invention, at least one signal input unit to which video signals of a plurality of systems are input, a memory unit having a storage area for storing an image for at least one screen, and at least one image display An image processing means for synthesizing the video signals of the plurality of systems on the memory part and outputting them to the signal output part, and an image having a control means for controlling the image processing means In the processing device, the control means has a communication means for making a change request of image characteristics for at least one of the plurality of video signals to be input, from the image characteristic information of the video signals of the plurality of systems, Select a priority video signal, change the operation of the image processing means to an operation suitable for the priority system video signal, and at least other than the priority system video signal. The video signal of one line, characterized in that requesting to change the image characteristics suitable for operation of the image processing unit.
Alternatively, the control means includes communication means for requesting change of image characteristics for at least one of the plurality of video signals to be input, and the image characteristic information and the signal output of the video signals of the plurality of systems Select the priority video signal from the characteristic information of the image display unit connected to the unit, and the operation of the image processing means is suitable for the video signal of the priority system and the image display unit connected to the signal output unit And at least one system video signal other than the priority system video signal is requested to change to an image characteristic suitable for the operation of the image processing means.
Alternatively, the control means gives priority to image characteristic information of the video signals of the plurality of systems, arrangement conditions on the screen to be output to the signal output unit, and characteristic information of the image display unit connected to the signal output unit. By selecting a video signal, the operation of the image processing means connected to the signal output unit is changed to an operation suitable for the video signal of the priority system and the image display unit connected to the signal output unit. And
Alternatively, the control means has communication means for requesting change of image characteristics for at least one of the plurality of video signals to be input, and the image characteristic information of the video signals of the plurality of systems and the signal A priority video signal is selected from the arrangement conditions on the screen to be output to the output unit, and the operation of the image processing means is changed to an operation suitable for the priority system video signal. The video signal of at least one system other than is required to be changed to an image characteristic suitable for the operation of the image processing means.
Alternatively, the control means includes communication means for requesting change of image characteristics for at least one of the plurality of video signals to be input, and the image characteristic information and the signal output of the video signals of the plurality of systems A priority video signal is selected from the arrangement conditions on the screen to be output to the unit and the characteristic information of the image display unit connected to the signal output unit, and the operation of the image processing means Image characteristics suitable for the operation of the image processing means for the video signal of at least one system other than the video system of the priority system are changed to an operation suitable for the image display unit connected to the signal output unit It is required to change to

The operation to be optimized by the image processing means is, for example, an update cycle of the display screen of the display unit. Further, the image characteristic information referred to when selecting the priority input video signal in the control means is, for example, an input image update period, moving image still image discrimination information, usage and type information. Also, refer to the resolution of the input image, gamma characteristic information, color information, brightness (bright) and brightness (contrast) information, respectively, display resolution, gamma correction, color correction, brightness and brightness correction, respectively. You may make it optimize .

The present invention relates to an image display device capable of displaying a plurality of input images, such as a CRT, a transmissive display device, a reflective display device, a liquid crystal display device, a PDP (plasma display) and a charge emission display device, and an image signal processing circuit thereof. Applicable to any image processing apparatus with processing for displaying a plurality of input images such as a circuit for performing graphic processing of a computer, a set top box for receiving a signal distributed from digital TV broadcasting or IEEE 1394 and displaying it on a display is there.

  According to the present invention, in an image processing device for multi-screen display that displays an input image from each input signal source on the same screen, the format and characteristics of the input signal of each input system and the display contents, and the image display unit Compare the characteristics, select a priority input signal, and set the operation mode and image quality characteristics of the image display unit. In addition, the input system other than the priority system is adjusted again for the operation and image quality adjustment according to the operation mode and image characteristics of the applied image display unit. Alternatively, a setting change request is made to each input signal source via the communication means such as DDC or IEEE 1394 for the operation mode and image quality adjustment according to the operation mode and image characteristics of the applied image display unit. As a result, an image processing apparatus that flexibly optimizes moving image quality and image quality characteristics can be realized at low cost even for a plurality of input signals.

Furthermore, optimization can be performed in consideration of the characteristics of each input signal even when the image display apparatus is changed or characteristics are changed.
Specifically, the output system can be switched between synchronous and asynchronous with respect to the vertical synchronization signal of each input system, and the video quality can be improved depending on the contents of the input signal format such as the vertical frequency and the motion component of the input signal. The priority input system is selected and synchronized with the vertical synchronization signal to optimize the video quality of the priority system. Also, other input systems can be adjusted to the operation mode such as double buffering among the selected operation modes, or matched to the operation mode and image characteristics of the applied image display unit via communication means such as DDC. Requests change of input source setting for operation and image quality adjustment. As a result, the configuration of the output system is operated with a single clock, and the synchronization relationship between the output systems and the outputs is optimized, and the entire system is configured to be strong against moving images, and to be a simple and inexpensive circuit configuration. Can do.

  Also, the input system that prioritizes display image quality is selected according to the input signal format, image quality characteristics, display content, etc., and the input image quality characteristics that are prioritized and the image quality characteristics of the output system are combined and applied to the output image adjustment unit. As a result, an image quality with little bit error is realized with respect to the prioritized system. In addition, for the output image adjustment in which other input systems are also set, an auxiliary adjustment is performed by the input image adjustment unit, or the output image adjustment of the applied image display unit is adjusted via communication means such as DDC. Requests to change the input source setting for image quality adjustment. As a result, it is possible to easily and inexpensively realize a circuit that optimizes the image quality difference between the plurality of input systems and the output image quality relationship, and makes the image quality of the entire system uniform.

Hereinafter, embodiments of the present invention will be described with reference to Examples and Reference Examples.
(Reference Example 1)
FIG. 1 is a block diagram for explaining the first reference example of the present invention. In the figure, 1-1 is an input terminal for an analog image signal, 1-2 is a horizontal synchronization signal (IHD) input terminal for the input signal, and 1-3 is a vertical synchronization signal (IVD) input for the input signal. Terminal. Reference numeral 2 denotes an AD converter that converts an input analog image signal into an n-bit digital signal. 3 is an input system image processing unit, 4 is a memory control unit, 5 is a memory unit for storing image data, 6 is an output system image processing unit, and 7 is an image display unit. Reference numerals 20-1, 20-2, 20-3, and 20-4 denote data buses that transmit n-bit digital signals to the respective units. Reference numeral 21 denotes a control bus composed of memory control lines and address lines, and reference numeral 22 denotes a memory data bus.

Reference numeral 8 denotes a PLL circuit, and ICK is a clock synchronized with the input horizontal synchronization signal IHD. An oscillation circuit 12 generates an output system clock OCK. Reference numeral 9 is a microcomputer (μCOM) section, and 19 is a control bus for controlling m sections.

  Before the digital image signal is stored in the memory unit 5, the input system image processing unit 3 performs processing such as image quality adjustment and image reduction conversion, and is transferred to the memory control unit 4. The memory control unit 4 stores image data in the memory unit 5 at a timing corresponding to the input synchronization signals (IHD, IVD) and the input system clock ICK, and also outputs the output system clock OCK, the horizontal synchronization signal OHD, and the vertical synchronization signal OVD. The image data is read from the memory unit 5 and transferred to the output system image processing unit 6. In the image processing unit 6, image quality adjustment, image enlargement conversion, and the like are performed as in the conventional example of FIG.

  In FIG. 1, reference numeral 10 denotes a synchronization control unit, which is a block that determines an output frame rate. Here, input synchronization signals IHD and IVD and output system clock OCK are input, and output system horizontal synchronization signal OHD, vertical synchronization signal OVD, write field control signal WE, and read field control signal RE are output. These controls are controlled by a microcomputer bus 19.

FIG. 2 shows a circuit configuration example of the synchronization control unit 10.
In FIG. 2, 901 is an H counter that counts OCK, 902 is a first V counter that counts OHD, 904 is a second V counter that counts IHD, and 905, 906, and 907 are counters The first, second, and third decoders decode the outputs of 901, 902, and 904 to generate arbitrary pulses. Reference numerals 903 and 910 denote D-input flip-flops (D-FF). Reference numerals 908 and 909 denote first and second switches (SW1 and SW2) that switch and output input pulses. Reference numeral 911 denotes an inverter that inverts logic. Also, 912 is an IHD, 913 is an IVD, 914 is an OCK input terminal, 915 is an OHD, 916 is an OVD, 917 is an RE, and 918 is an output terminal for the WE. In addition, reference numerals 919 and 920 are input terminals of signal lines for switching each of the microcomputer control buses, and 921, 922 and 923 are microcomputer control buses for setting the values of the first to third decoders. Input terminal.

  Reference numerals 925, 926, and 927 are clock input terminals of the counters, 930, 931, and 932 are clock enable terminals of the counters, and 934, 935, and 936 are output terminals of the counters. Reference numeral 950 denotes an H counter reset terminal. The output terminals 934, 935, 936, and 937 are also connected to the input terminals of the decoders, and 938, 939, and 940 are output terminals of the decoders.

  Reference numerals 928 and 929 denote clock terminals of the D-FFs 903 and 910, reference numeral 933 denotes a clock enable terminal, and reference numerals 941 and 942 denote input terminals of the D-FF. Reference numerals 943 and 944 are non-inverted output terminals of the D-FF, and 952 is an inverted output terminal.

  Reference numerals 947 and 948 denote input terminals IN1 and IN2 of the first switch 908, and reference numeral 949 denotes an output terminal. Reference numerals 940, 945, and 946 denote input terminals IN3, IN4, and IN5 of the second switch 909, and reference numeral 951 denotes an output terminal.

Here, the OCK is counted and decoded by the H counter 901 and the decoder 905 to generate an OHD and output from the 915, and the generated OHD is counted and decoded by the first V counter 902 and the decoder 906. The result is output to the input terminal 947 of the switch. On the other hand, the input IVD passes through the D-FF 903 and is input to the input terminal 948 of the first switch 908. The signals input to the input terminals 947 and 948 are selected and switched according to the operation mode by a control signal from the microcomputer input to the terminal 919, and one of them is output to the terminal 916 as OVD.

  The output of the D-FF 903 is also input to the enable terminal 933 of the D-FF 910, and a memory write signal WE whose polarity is inverted every time IVD is input to the terminal 933 is output to the terminal 918. The memory write signal WE and its inverted logic signal are input to the input terminals 945 and 946 of the second switch 909 as memory read signal candidate signals. Further, the output results of both the IHD counter 904 and the OHD counter 902 are decoded by the decoder 907, and a signal determined by the relationship between them is also input to the input terminal 940 of the second switch 909 as a candidate signal for the memory read signal. According to the control signal from the microcomputer to the terminal 920, one of these three inputs is selected according to the operation mode, and is output from the terminal 917 as the memory read signal RE.

  In this reference example, the correspondence table between the operation mode with respect to the frequency of the input signal and the signal output by switching the first and second switches is shown in Table 1, and the timing chart at that time is shown in FIG.

  Table 1 shows whether the vertical frequency of the output is synchronized with the input signal with respect to the vertical frequency range of the input signal, whether to double buffer, and SW1 in FIG. 2 for realizing the operation. , SW2 signals to be switched and output.

  In FIG. 3, A1, A2, A3, A4, and A5 are input vertical synchronization signals IVD when the input vertical frequency is 100 Hz, 80 Hz, 75 Hz, 60 Hz, and 50 Hz, respectively, and A6 and A7 are when the input frequency is 80 Hz. Output vertical synchronization signal and output horizontal synchronization signal. A8 and A9 are an output vertical synchronizing signal and an output horizontal synchronizing signal when the input frequency is 75 Hz. A10 and A11 are an output vertical synchronizing signal and an output horizontal synchronizing signal when the input frequency is 60 Hz. A12 and A13 are an output vertical synchronizing signal and an output horizontal synchronizing signal when the input frequency is 50 Hz and 100 Hz.

  In this reference example, a mode in which an output vertical synchronization signal OVD is synchronized with an input vertical synchronization signal IVD in response to an input signal with a vertical frequency of 60 Hz to 80 Hz, which is frequently used, A mode for selecting an output vertical synchronization signal regardless of the input vertical synchronization signal is selected.

For this reason, in response to an input signal having a vertical frequency of 60 Hz to 80 Hz, a double buffering is not used (which may be used), and the video is overtaken by a method synchronized with the vertical synchronization of the input, Duplex and image quality without missing are realized. At this time, the first switch selects the IN2 side, and the second switch selects IN5 (may be IN4).

  When the frequency is less than 60 Hz, to prevent flicker, the SW1 is set to the IN1 side to improve the moving image quality by double buffering, and the input is asynchronous. When the input vertical frequency is lower than the output frequency, if the memory area opposite to the write memory area is used as a read field, the write scan does not overtake the memory read scan, so SW2 is set to the IN4 side.

  On the other hand, in order to suppress the operation speed of the output system at 80 Hz or higher, the moving image quality is improved by double buffering with SW1 as the IN1 side, and is asynchronous with respect to the input. When the vertical frequency of the input is higher than the output frequency, even if the memory area opposite to the write memory area is used as a read field, the write scan may overtake the memory read scan. A memory read signal is output at a timing at which no overtaking occurs due to the relationship of the output OHD.

  At this time, the frequency of the oscillator (OSC) 12 in FIG. 1 is designed according to the clock frequency at the time of XGA 80 Hz which is the maximum vertical frequency of the output system. That is, since 1 field = 1V period = 1S / 80 = 12.5 mS, for example, 1V = (768 + α) H = 808H, 1H period = 15.5 μS, 1H = (1024 + α) CLK = 1344CLK, and 1CLK = 1.11. 5 nS, and the frequency of the oscillator 12 is 1 / 11.5 nS = 87 MHz. In FIG. 3, when an 80 Hz IVD of A2 is input, its output OVD = IVD, and IHD for one period of OVD is set to 768 + α = 808.

  Also, when 75 Hz and 60 Hz IHDs of A3 and A4 are input, the corresponding OHDs A8 and A9 have the same period as the IHD, and the OCK and OHD periods during one OVD period are kept constant. Therefore, the number of OHDs during one OVD period increases in proportion. The display unit is driven on the assumption that the blanking period increases for the period exceeding 768 + α = 808.

  On the other hand, when the input IHD is A1 of 100 Hz or A5 of 50 Hz, the vertical frequency of the output is set asynchronously with the input. Therefore, as shown in OVD of A12 and OHD of A13, the same OVD and OHD cycle as in the case of 80 Hz are shown. In addition, it is self-running asynchronously with the input. The frequency of 60 to 80 Hz is the most widespread frequency band such as the current PC, WS (workstation), DTV (digital television), etc. On the other hand, the video source of video from TV is also 60 Hz, Since it is in this range, the frequency of use is very high and it is highly meaningful to give priority to moving images.

  On the other hand, the flicker phenomenon of low frequency such as 50Hz is very difficult to see regardless of the moving image or the still image. And improved video quality.

For signals with a high vertical frequency such as 100 Hz, it is important to consider that the operation speed exceeding 100 MHz places a heavy burden on the circuit. The reduction and stable operation are compatible with the improvement of video quality. In particular, display elements such as liquid crystals and PDPs require a high driving voltage of several tens of volts to several tens of volts, so that when the speed per pixel is increased, the video signal system and the driver circuit operate very high. Bandwidth and slew rate are required. Even in the present situation, the parts that cannot follow such high speed drive are divided and driven in multiple parts, but further speeding up of the output system is changed to faster parts, development of new parts, change of division number As a result, not only the cost increases due to the circuit change, but also the operation margin of the circuit is narrowed, which makes it difficult to achieve stable operation. This problem is particularly important when driving a display element, such as SXGA or UXGA, that has a pixel number several times larger than the current state. In order to increase the number of pixels in the future, it is important that cost reduction and stable operation can be compatible with improvement of moving image quality.

  By adopting the configuration as shown in this reference example, the overall operation of the system is strong against moving images, achieving motion-free operation especially in the frequently used vertical frequency band, and other vertical operations. In the frequency band, the circuit configuration is simplified and the cost is reduced by simply performing a strong operation against moving images.

  Here, frequencies other than the frequently used vertical frequency band are double-buffered. However, double buffering requires a double memory area and a control circuit portion therefor, so it is omitted as a function. It is also possible. While a specific vertical frequency band is synchronized with the input vertical frequency, it is judged that the frequency of use other than that band is low, and it operates as a product, but it is also inexpensive to switch to a simple asynchronous operation that does not improve the video quality This is an option in terms of providing products.

  In this reference example, it is selected whether the output system is synchronized with the input system or asynchronous depending on the vertical frequency of the input signal, but here, it is selected whether the output system is synchronized with the input system or asynchronous. In addition to the vertical frequency of the input signal, the reference to be switched includes other items of the input signal format, system operation mode, and user settings. . Reference example 2 shows an example in which a moving image or a still image is selected as a reference as such a reference.

(Reference Example 2)
In the reference example 1, the example in which the V-synchronization of the output system is switched to the input synchronization signal or to be asynchronous according to the vertical frequency of the input signal is shown. An example of switching between synchronous and asynchronous is shown. FIG. 4 shows a block diagram of Reference Example 2.

  Here, there are two input systems, which are synthesized by the memory control unit. As shown in FIG. 5, for example, an output screen such as a PC graph or table is displayed on the entire screen (C1), and a moving image such as an image of a videophone is output to the sub-screen portion (C2). The circuit configuration assumes a composite screen of different input sources. In such a case, there is generally no synchronization relationship between the two signals. There are various combinations of moving images and still images depending on the connected input source.

  In FIG. 4, 3-1 is an input A system image processing unit, 1-4 is a q-bit digital image signal input terminal, and 1-5 is an input signal horizontal synchronizing signal (IHD1) input terminal. 1-6 is an input signal vertical synchronization signal (IVD1) input terminal, and 1-7 is an input signal synchronization clock (ICK1) input terminal. 3-2 is an input B system image processing unit, 1-8 is an analog image signal input terminal, 1-9 is an input signal horizontal synchronization signal (IHD2) input terminal, Reference numeral 10 denotes an input signal vertical synchronizing signal (IVD2) input terminal. Reference numeral 2 denotes an AD converter that converts a B-system analog signal into an n-bit digital signal. 4-2 is a memory control unit, 5 is a memory unit for storing image data, 6 is an output system image processing unit, and 7 is an image display unit. Reference numerals 20-5 and 20-6 denote data buses for q-bit digital signals, and reference numerals 20-7 and 20-8 denote data buses for transmitting n-bit digital signals. Reference numerals 20-9 and 20-10 denote data buses for transmitting r-bit digital signals. Reference numeral 21 denotes a control bus composed of memory control lines and address lines, and reference numeral 22 denotes a memory data bus.

Further, 1-11 and 1-12 are DDC (Display) for the input A system and B system, respectively.
Data Channel) terminal for transmitting display information to an input signal source. The DDC is a standard for communication between a computer display and a host system standardized by VESA (Video Electronics Standards Association).

  Reference numeral 8 denotes a PLL circuit, and ICK2 is a clock synchronized with the input B system horizontal synchronizing signal IHD2. An oscillation circuit 12 generates an output system clock OCK. Reference numeral 9 is a microcomputer (μCOM) section, and 19 is a control bus for controlling m sections.

  Before the digital image signal is stored in the memory unit 5, the input system image processing units 3-1 and 3-2 perform processing such as image quality adjustment and image reduction conversion, and are transferred to the memory control unit 4-2. The The input image processing units 3-1 and 3-2 also perform motion detection and send the result to the microcomputer 9 via the microcomputer bus 19. The memory control unit 4 stores the image data in the memory unit 5 at a timing corresponding to the input synchronization signal (IHD1, IHD2, IVD1, IVD2) and the input system clocks ICK1, ICK2, and outputs the output system clock OCK, the horizontal synchronization signal OHD, Image data is read from the memory unit 5 at the timing of the vertical synchronization signal OVD, and the data is transferred to the output system image processing unit 6. In the image processing unit 6, image quality adjustment, image enlargement conversion, and the like are performed as in the conventional example of FIG.

  In FIG. 4, reference numeral 10 denotes a synchronization control unit, which is a block for determining an output frame rate. Here, two input system synchronization signals IHD1, IVD1, IHD2, and IVD2 and an output system clock OCK18 are input, an output system horizontal synchronization signal OHD and vertical synchronization signal OVD, a write field control signal WE, and a read A field control signal RE is output. These controls are controlled by a microcomputer bus 19.

  Here, an operation example of the synchronization control unit 10 is shown in Table 2. As in Reference Example 1, the output vertical synchronization signal is switched between input and output using a switch. The difference from Reference Example 1 is that there are two systems of input and that the synchronization relationship is switched depending on the state of the moving image and still image of the two input sources in addition to switching the synchronization relationship depending on the frequency.

In response to the result of motion detection of the input image processing units 3-1 and 3-2, the operation mode is switched as shown in Table 2 by a control signal from the microcomputer unit 9. When one is a moving image and the other is a still image, the OVD is synchronized with the input vertical synchronization signal of the moving image. When both systems are moving images, IVD1 and IVD2 are compared and OVD is synchronized with a vertical synchronization signal with a fast cycle.
Also, if the application is fixed, such as a stationary TV conference system, where the A system is a PC and the B system is a TV output, it is synchronized with the IVD1 of the A system by manual setting, or the IVD2 of the B system It is possible to determine whether to synchronize or to generate OVD asynchronously for both A and B.

  Furthermore, in this reference example, the control described below is also performed using a control line for transmitting information on the display side such as DDC to an input signal source such as a PC. That is, in the initial state, when only one is operating and one is not connected, for example, assuming that only the B system is connected and operating, the synchronization control unit 10 is OVD with respect to IVD2 as in Reference Example 1. Are set as shown in Table 1.

  Next, when one system is connected later (A system in this case), the microcomputer requests a signal having the same vertical frequency as the current OVD cycle to the input signal source via the A system DDC terminal 1-11. To do. In response to this, the input signal source of the A system sets the signal of the required vertical frequency, and as a result, the two systems of the input have the same frequency, and both images are set to output settings strong against the moving image. It can be made possible.

  Also, if the new A system does not accept DDC, the microcomputer unit makes a determination and resets the output synchronization OVD to the setting synchronized with IVD1 of the A system connected later, while the same vertical frequency as this OVD cycle. Is requested to the B system input signal source via the B system DDC terminal 1-12. Upon receiving this, the input signal source of the B system resets the signal of the required vertical frequency, and the two systems of the input are set to the same frequency.

  By adopting such a configuration, even in a system where a plurality of input signals with different periods are mixed, the configuration of the output system is realized with a simple and inexpensive circuit configuration while operating with a single clock system. can do.

Example 1
FIG. 21 shows a first embodiment of the display to which the present invention is applied. One system has two PC inputs, which are digital computer image signal inputs, and the other system has analog computer image signal inputs. Then, a block diagram of an image processing unit of an image display device that performs synthesis by controlling the output of the frame memory to perform two-screen multi-screen display on one image display unit is shown.

  In the figure, reference numeral 1-1a denotes an input terminal for a q-bit digital computer image signal (IDATA1) in the first system. Here, there should be three systems of red, blue, and green (RGB) originally, but in order to simplify the description of the configuration, one system is shown (the same applies hereinafter). 1-1b is an input signal horizontal synchronization signal (IHD1) input terminal, and 1-1c is an input signal vertical synchronization signal (IVD1) input terminal. Reference numeral 1-1d denotes an image signal clock (ICK1) input terminal, and reference numeral 1-1e denotes an input / output terminal for a DDC signal (DDC1). Reference numerals 20-1a-1 and 20-1a-2 denote data buses for transmitting q-bit digital image signals to the respective units. Reference numerals 20-1b, 20-1c, 20-1d, and 20-1e denote signal lines for IHD1, IVD1, ICK1, and DDC1, respectively.

  1-2a is an input terminal for the second analog computer image signal (IDATA2). 1-2b is an input signal horizontal synchronizing signal (IHD2) input terminal, and 1-2c is an input signal vertical synchronizing signal (IVD2) input terminal. 1-2e is an input / output terminal for a DDC signal (DDC2).

An AD converter 2 converts an analog image signal (IDATA2) into an n-bit digital signal. Reference numeral 8 denotes a PLL (Phase Locked Loop) circuit that generates an input system clock (ICK2) on the PC2 side synchronized with the horizontal synchronizing signal (IHD2) input from 1-2b.

  20-2a-0 is an analog signal line, and 20-2a-1 and 20-2a-2 are n-bit digital signal lines. Reference numerals 20-2b, 20-2c, 20-2d, and 20-2e denote signal lines for IHD2, IVD2, ICK2, and DDC2, respectively.

Reference numeral 3-1 denotes an input image processing unit 1 of the PC 1, and 3-2 denotes an input image processing unit 2 processing unit of the PC 2.
10-3 is an image comparison unit, and 20-REF-1 and 20-REF-2 are comparisons extracted from the image signals output from the input system image processing unit 1 and the input system image processing unit 2 for comparison. It is a signal line of a signal.

4 is a memory control that performs control to store image signals input from two input image processing units in a memory, synthesize images for output as a multi-screen, and output them to an output image processing unit. Part. Reference numerals 5-1 and 5-2 denote frame memories (memory A and memory B) respectively corresponding to the input systems PC1 and PC2. 21-1 and 21-2 are control buses for the memories A and B, respectively, and 22-1 and 22-2 are data buses for the memories A and B, respectively.
Reference numeral 6 denotes an output image processing unit. Reference numeral 7 denotes an image display unit such as a liquid crystal display, a plasma display, or a CRT.

  1-f is an input terminal of the image display unit for digital data (ODATA) of the image display unit, 1-g is an input terminal of the image display unit for the horizontal synchronization signal (OHD) of the output signal, and 1-h is This is an input terminal of the image display unit for the vertical synchronizing signal (OVD) of the output signal. 1-i is an input terminal of the image display unit of the clock (OCK) of the output image signal, and 1-j is an input terminal of the image display unit of the microcomputer bus (MB). 1-s is an input / output terminal for a DDC signal (DDC3) to the image display unit, and 20-s-1 and 20-s-2 are signal lines of the DDC3. Reference numerals 20-f-1, 20-f-2, and 20-f-3 denote signal lines for k-bit digital image data (ODATA).

  An oscillation circuit 12 generates an output system clock (OCK). Reference numerals 20-i-1 and 20-i-2 denote OCK signal lines.

  10-2 is a synchronization control unit, 20-WE-1 is a write field control signal WE-A of the memory A, and 20-RE-1 is a read field control signal RE-A, 20-WE-2 of the memory A. Is a write field control signal WE-B of the memory B, and 20-RE-2 is a read field control signal RE-B of the memory B. Reference numerals 20-g-1 and 20-g-2 denote signal lines for an output system horizontal synchronizing signal (OHD). Reference numerals 20-h-1 and 20-h-2 denote signal lines for the output system vertical synchronizing signal (OVD).

  Reference numeral 9 denotes a microcomputer unit for controlling the system. Reference numerals 19-1 and 19-2 denote microcomputer buses (MB) including control lines and data lines from the microcomputer to the respective units.

  Before the digital image signal input from the image input terminal 1-1a is stored in the memory unit A of 5-1, processing such as image quality adjustment and image reduction conversion is performed by the input system image processing unit 1 of 3-1. Is transferred to the memory control unit 4. Also, a signal for comparing image quality from the input system image processing unit 1 is selected by the microcomputer and sent to the image comparison unit.

The analog image signal input from the image input terminal 1-2a is converted into digital data by the AD converter 2 in synchronization with the clock generated by the PLL circuit 8. The digital image signal thus obtained is subjected to processing such as image quality adjustment and image reduction conversion in the input system image processing unit 2 in 3-2 before being stored in the memory unit B in 5-2. 4 is transferred to the memory control unit.
Also, a signal for comparing image quality from the input system image processing unit 2 is selected by the microcomputer and sent to the image comparison unit.

  In the memory control unit 4, the image data is stored in the memory unit A of 5-1 at the timing corresponding to the input synchronization signal (IHD 1, IVD 1) and the input system clock ICK 1, and digitally transmitted from the IDATA 2. The converted signal stores image data in the memory section B of 5-2 at a timing corresponding to the input synchronization signal (IHD2, IVD2) and the input system clock ICK2.

  In this embodiment, both the memory part A and the memory part B secure a memory area that can be double buffered, and the memory write signal and read signal (20-WE-1, 20-WE-2, 20-RE-1 and 20-RE-2), the write memory area and the read memory area are switched and controlled.

  Further, in synchronization with the output system clock OCK and the horizontal synchronization signal OHD and vertical synchronization signal OVD from the synchronization control unit, the two image data 5-1 are obtained at a timing that matches the relationship between the predetermined image size and display position. And 5-2, and the data is transferred to the output system image unit 6.

  The image processing unit 6 performs image quality adjustment, image enlargement conversion, and the like. Finally, these image data, a synchronizing signal, and a clock are transmitted to the image display unit, and image display is performed.

  In this embodiment, the synchronization control unit 10-2 creates an output synchronization signal and a memory control signal in accordance with the frame rate selected as the output, and performs selection switching. Here, input synchronization signals IHD1, IHD2, IVD1, and IVD2 and an output system clock OCK are input, and an output system horizontal synchronization signal OHD (20-g-1) and a vertical synchronization signal OVD (20-h-1). ), The write field control signal WE-A (20-WE-1), the read field control signal RE-A (20-RE-1) of the memory A, and the write field control signal WE-B (20-) of the memory B. WE-2) and read field control signal RE-B (20-RE-2) are output. These controls are controlled by the microcomputer bus 19-1.

  In this embodiment, the image comparison unit 10-3 compares the image quality of each input system, and the microcomputer outputs information for controlling the image quality of the output system and each input system. The calculation result of the comparison information obtained from the comparison signals 20-REF-1 and 20-REF-2 extracted for comparison from the image signals output from the input system image processing unit 1 and the input system image processing unit 2 is a microcomputer. It is transmitted to the microcomputer via the bus 19-1.

In this embodiment, the microcomputer unit receives the synchronization signals IHD1, IHD2, IVD1, and IVD2 of each input system, and in addition to comparing the operation timing of each input signal by the synchronization signal, the DDC3 and other communication paths, Comparison is made in consideration of the characteristics and conditions of the display unit given by the initial information, the system operation timing is determined to control the synchronization control unit, and the operation timing of the input signal source is also controlled via DDC1 and DDC2. . As for image quality, in addition to the comparison result of the image quality characteristics of each input system obtained from the image comparison unit, comparison is made with the characteristics and conditions of the display unit given by the DDC 3, other communication paths, initial information, etc. The internal image processing units (input system image processing unit 1, input system image processing unit 2, output system image processing unit) are controlled, and the image quality of the input signal source is controlled via DDC1 and DDC2.

  As a result, when multi-screen display is performed by combining input images of various formats and image quality characteristics of a plurality of input systems on one screen, depending on the image quality of each input system and the output display section and the characteristics of the moving image, The operation timing and image quality of the entire system are optimized.

FIG. 22 shows a circuit configuration example of the synchronization control unit 10-2.
In FIG. 22, 901 is an H counter that counts OCK, 902 is a first V counter that counts OHD, and 904-1 is a second V counter that counts IHD1. Reference numeral 904-2 denotes a third V counter that counts IHD2.

  Reference numerals 903-1, 903-2 and 910-1, 910-2, 957-1, and 957-2 are D input flip-flops (DFF), and 905, 906, 907-1, and 907-2 are counter outputs of the respective counters. Are the first, second, third, and fourth decoders that generate arbitrary pulses. Reference numerals 908, 909-1, and 909-2 denote first (SW1), second (SW2-1), and third (SW2-2) switches that switch and output input pulses. Reference numerals 911-1 and 911-2 denote inverters that invert logic.

  912-1, 912-2 are IHD1, IHD2, 913-1, 913-2 are IVD1, IVD2, 914 is an OCK input terminal, 915 is an OHD, 916 is an OVD, 917-1 , 917-2 are output terminals of RE-A and RE-B, and 918-1 and 918-2 are output terminals of WE-A and WE-B. Reference numerals 919, 920-1, and 920-2 are input terminals of signal lines for switching the first to third SWs of the microcomputer control bus, and 921, 922, 923-1, and 923-2 are the first terminals. It is an input terminal of the control bus of the microcomputer for setting the values of the first to fourth decoders.

  Reference numerals 925, 926, 927-1, and 927-2 are clock input terminals of the counters. Reference numerals 930, 931, 932-1, and 932-2 are clock enable terminals of the counters. 934, 935, and 936 -1,936-2 are output terminals of the counters. Reference numeral 950 denotes an H counter reset terminal. The output terminals 934, 935, 936-1, and 936-2 of each counter are input to the input terminals 953, 954, 955-1, 955-2, 956-1, 956-2, 937-1, and 937- of the respective decoders. 2 and 938, 939, 940-1, and 940-2 are output terminals of the respective decoders.

  Further, 928-1, 928-2, 929-1, 929-2, 958-1, 958-2 are clock terminals of each DFF, and 933-1, 933-2, 959-1, 959-2 are Clock enable terminals 941-1, 941-2, 942-1, 942-2, 960-1, and 960-2 are D input terminals. Reference numerals 943-1, 943-2, 944-1, 944-2, 961-1, and 961-2 are DFF output terminals, and 952-1 and 952-2 are inverted output terminals.

  Reference numerals 947, 948-1, and 948-2 are input terminals IN1, IN2-1, and IN2-2 of the first switch 908, and 949 is an output terminal. 962-1, 945-1, and 946-1 are input terminals IN3-1, IN4-1, and IN5-1 of the second switch (SW2-1) 909-1, and 951-1 is an output terminal. 962-2, 945-2, and 946-2 are input terminals IN3-2, IN4-2, and IN5-2 of the third switch (SW2-2) 909-2, and 951-2 is an output terminal.

The OCK is counted and decoded by the H counter 901 and the decoder 905 to generate an OHD, and output from the terminal 915. The generated OHD is counted and decoded by the first V counter 902 and the decoder 906, and the first switch The result is output to the input terminal 947.

  On the other hand, the input IVD1 passes through the DFF 903-1 and is input to the input terminal 948-1 of the first switch. The input IVD2 passes through the DFF 903-2 and is input to the input terminal 948-2 of the first switch. The signals input to the input terminals 947 and 948-1 and 948-2 are selected and switched according to the operation mode by a control signal from the microcomputer at the terminal 919, and one of them is output to the terminal 916 as OVD.

  The output of the DFF 903-1 is also input to the enable terminal 933-1 of the DFF 910-1, and the memory write signal WE-A whose polarity is inverted every time IVD1 is input to the terminal 933-1 is output to the terminal 918-1. To do. The output of the DFF 903-2 is also input to the enable terminal 933-2 of the DFF 910-2, and a memory write signal WE-B whose polarity is inverted every time IVD2 is input to the terminal 933-2 is output to the terminal 918-2. To do.

  The memory write signal WE-A and its inverted logic signal are input to the input terminals 945-1 and 946-1 of the second switch (SW2-1) 909-1 as a candidate signal for the memory read signal. Further, an output terminal of a decoder 907-1 that decodes three values of an IHD1 counter 904-1 output, an IHD2 counter 904-2 output, and an OHD counter 902 output in a relationship determined by a control signal 923-1 from the microcomputer. The signal from 940-1 is also input to the input terminal 962-1 of the second switch (SW2-1) 909-1 as a candidate signal for the memory read signal, and according to the control signal from the microcomputer at the terminal 920-1, One of these three inputs is selected depending on the operation mode. The result is latched by the DFF 957-1 at the timing of OVD and output from the terminal 917-1 as the memory read signal RE-A.

  Further, the memory write signal WE-B and its inverted logic signal are input to the input terminals 945-2 and 946-2 of the third switch (SW2-2) 909-2 as candidate signals for the memory read signal. Further, an output terminal 940 of the decoder 907-2, which decodes the three values of the IHD1 counter 904-1 output, the IHD2 counter 904-2 output, and the OHD counter 902 in a relationship determined by the control signal 923-2 from the microcomputer. -2 is also input to the input terminal 962-2 of the third switch (SW2-2) 909-2 as a candidate signal for the memory read signal, and operates according to the control signal from the microcomputer at the terminal 920-2. One of these three inputs is selected depending on the mode. The result is latched by the DFF 957-2 at the timing of OVD and output from the terminal 917-2 as the memory read signal RE-B.

  Table 3 shows a correspondence table between the operation mode with respect to the frequency of the input signal and the signal output by switching each switch in this embodiment. The timing chart at that time is the same as that shown in FIG.

Table 3 shows the frequency fIN1 of the vertical synchronization signals (IVD1, IVD2) of the two input signals.
, FIN2 to which input signal the vertical frequency of the output is synchronized, whether to double buffer, and SW1, SW2-1, SW2- in FIG. 21 for realizing the operation 2 shows a signal to be switched and output.

  In FIG. 3, A1, A2, A3, A4, and A5 are input vertical synchronization signals IVD (IVD1 and IVD2) when the input vertical frequencies are 100 Hz, 80 Hz, 75 Hz, 60 Hz, and 50 Hz, respectively, and A6 and A7 are inputs. An output vertical synchronization signal (OVD) and an output horizontal synchronization signal (OHD) when the frequency is 80 Hz. A8 and A9 are an output vertical synchronizing signal (OVD) and an output horizontal synchronizing signal (OHD) when the input frequency is 75 Hz. A10 and A11 are an output vertical synchronizing signal (OVD) and an output horizontal synchronizing signal (OHD) when the input frequency is 60 Hz. A12 and A13 are an output vertical synchronizing signal (OVD) and an output horizontal synchronizing signal (OHD) when the input frequency is 50 Hz and 100 Hz.

  In the present embodiment, for an input signal having a vertical frequency of 60 Hz to 80 Hz, which is frequently used, an image strong against moving images is used as a mode in which the output vertical synchronization signal OVD is synchronized with the input vertical synchronization signals IVD1 and IVD2. Display. Further, when both IVD1 and IVD2 have a high vertical frequency of 60 Hz to 80 Hz, the microcomputer determines the nature of the input image (for example, the image 10-3 in FIG. The screen on the foremost side is selected by the user's settings, according to the ratio of the display area of each input image on the display screen, or when multiple window screens are open on the screen. Or the like, the input of which of the two systems is preferentially selected to be synchronized.

  Therefore, it is not necessary to use a double buffering for an input signal with a vertical frequency of 60 Hz to 80 Hz (it does not matter), and the video is overtaken by a method synchronized with the vertical synchronization of the input, Realizes image quality without duplication and loss. When synchronizing with IVD1 ((3) in Table 3, (4), (5), (6), (9)), SW1 selects the IN2-1 side, and switch SW2-1 of the system to synchronize selects IN5-1. . When synchronizing with IVD2 ((2), (7), (8), (11) in Table 3), SW1 selects the IN2-2 side, and switch SW2-2 of the system to synchronize selects IN5-2. .

  In addition, when the vertical frequency of the input is less than 60 Hz ((1) to (3) in Table 3 for IVD1, (1), (4), (10) for IVD2), SW1 is set to prevent flicker. The video quality is improved by double buffering on the IN1 side, the output is output at a constant 80 Hz, and is asynchronous with respect to the input. When the vertical frequency of the input is lower than the output frequency, the write scan does not overtake the memory read scan if the memory area opposite to the write memory area is used as the read field, so SW2 (SW2-1 or SW2-2) Is the IN4 (IN4-1 or IN4-2) side.

  On the other hand, when the input vertical frequency IVD (IVD1, IVD2) is 80 Hz or more (for IVD1, (10) to (12) in Table 3, and for IVD2, (3), (9), (12)) In order to suppress the operation speed, the moving image quality is improved by double buffering with SW1 as the IN1 side, the output is output at a constant 80 Hz, and is asynchronous with respect to the input. When the input vertical frequency is higher than the output frequency, the write scan may overtake the memory read scan even if the memory area opposite to the write memory area is used as the read field, so SW2 (SW2-1 or SW2-2). Is the IN3 (IN3-1 or IN3-2) side, and a memory read signal is output at a timing at which no overtaking occurs from the relationship between the input IVD1 and IVD2 and the output OVD.

In the case where both IVD1 and IVD2 have a vertical frequency of 60 Hz to 80 Hz, which is frequently used, when the input vertical frequency is lower than the output system in the system selected in the mode not synchronized with the output, the write memory If the memory area opposite to the area is used as a read field, the write scan does not overtake the memory read scan, so SW2 (SW2-1 or SW2-2) is set to the IN4 (IN4-1 or IN4-2) side. Conversely, when the input vertical frequency is higher than that of the output system, the write scan may overtake the memory read scan even if the memory area opposite to the write memory area is used as the read field, so SW2 (SW2-1 or SW2 -2) is set to IN3 (IN3-1 or IN3-2), and a memory read signal is output at a timing at which no overtaking occurs from the relationship between the input IVD1 and IVD2 and the output OVD.

  At this time, the frequency of the oscillator OSC12 in FIG. 21 is designed in accordance with the clock frequency when the maximum vertical frequency of the output system is XGA 80 Hz (for example, 87 MHz, 1 field = 1 V period = 12.5 mS, 1 V = (768 + α ) H = 808H, 1H period = 15.5 μS, 1H = (1024 + α) CLK = 1344CLK, 1CLK = 11.5 nS).

  In FIG. 3, when an A2 80 Hz IVD is input, its output OVD = IVD, and IHD during that interval is set to 768 + α = 808.

  In addition, when 75 Hz and 60 Hz IHDs of A3 and A4 are input, the corresponding OHDs A8 and A9 have the same period as the IHD, and the period of OCK and OHD between them is kept constant. The number of OHD in between increases proportionally. The display unit 7 is driven on the assumption that the blanking period increases for the period exceeding 768 + α = 808.

  On the other hand, when the input IHD is A1 of 100 Hz or A5 of 50 Hz, the vertical frequency of the output is set asynchronously with the input. Therefore, as shown in OVD of A12 and OHD of A13, the same OVD and OHD cycle as in the case of 80 Hz are shown. In addition, it is self-running asynchronously with the input.

  A specific example of operation will be described with reference to FIGS. 23 to 26, (a) is the vertical synchronization signal IVD1 of the input system 1, (b) is the write signal WE-A of the memory A created by the circuit of FIG. 22, and (c) is the input system. 2 is a vertical synchronization signal IVD2 of FIG. 2, (d) is a write signal WE-B of the memory B created by the circuit of FIG. 22, and (e) is a vertical synchronization signal OVD of the output created by the circuit of FIG. (F) is a read signal RE-A of the memory A created by the circuit of FIG. 22, and (g) is a read signal RE-B of the memory B created by the circuit of FIG. Ta1 to Ta9 indicate the rising timing of the output vertical synchronization signal from the LOW level to the HIGH level, and the circuit of FIG. 22 holds the signal polarities of WE-A and WE-B at this timing. , RE-A and RE-B signal polarities are determined.

  First, FIG. 23 shows a state before the optimization in this embodiment is performed. For example, when power is turned on or immediately before signals from the input systems 1 and 2 (PC1 input and PC2 input) are transmitted. First, assuming that the operation range of the image display unit of this image display apparatus is in the range of 50 Hz to 85 Hz and a display unit having a recommended operation timing of 75 Hz is connected, the OVD is first set to 75 Hz as an output. Is set. In addition, immediately after this, a signal having a vertical frequency of 50 Hz and a signal having a vertical frequency of 60 Hz are input as IVD1 and IVD2, respectively. In this state, the circuit has not been optimized yet, and the memory is driven in accordance with each frequency, and the display by the double buffer is performed.

Next, FIG. 24 shows the operation when it is determined that 60 Hz of the input system 2 is given priority in moving image display as the first stage. For this selection, for example, the microcomputer section performs synchronization determination of two input signals from the synchronization signals IHD1, IHD2, IVD1, and IVD2 input to the microcomputer in FIG. Then, the operation of (2) in Table 3 is selected with reference to the table in the microcomputer unit. Alternatively, in the image comparison unit 10-3 in FIG. 21, it is determined that the IVD2 system is a moving image in which a TV interlace signal such as NTSC is non-interlaced for a PC, and the IVD1 system is a still image. In this case, the same decision is made. In FIG. 22, SW2, SW2-1, and SW2-2 are selected as IN2-2, IN4-1, and IN5-2, respectively. Thereby, as shown in FIG. 24E, the output vertical synchronization signal OVD is synchronized with IVD2. As a result, the moving image quality of the IVD2 system is ensured, and a smooth screen that does not cause doubled frames or missing frames, which is a drawback of double buffering, is realized. Further, since the IVD1 system is converted from 50 Hz to 60 Hz, image quality deterioration due to flicker can be avoided in the display unit.

  Furthermore, as a second stage in FIG. 25, the image comparison unit 10-3 in FIG. 21 detects that the input system of the IVD1 has also sent the video source of the video, and the microcomputer unit determines the video quality of the input system of the IVD1. An example of a case where it is determined that improvement should be made, or a case where the software of the microcomputer unit is designed so that the moving image quality is always set to the best state in each system by setting the system is shown. The microcomputer unit 9 in FIG. 21 requests the input signal source of IVD1 to change the vertical frequency from 50 Hz to 60 Hz via DDC1, and the input signal source of IVD1 changes the setting of the vertical frequency to 60 Hz. As a result, IVD1 is not in phase with IVD2 or OVD, but the frequency is the same, so that a smooth screen without duplicated frames or missing frames can be realized even with double buffering. . As a result, a display device with optimized moving image quality is realized in both systems.

  Further, FIG. 26 shows a case where the image display unit is changed as a third stage. For example, a system that used a rear projection display can be replaced with a plasma display, an old display can be replaced with a new one, and the operating range can be varied from 50 Hz to 85 Hz. A case where the display is changed from 70 Hz to 100 Hz can be considered.

  At this time, the microcomputer unit of the system of FIG. 21 detects that it does not operate at 60 Hz from the operating range of the display newly connected via the DDC 3 and changes the operating frequency of the output system to 70 Hz or higher. And In addition, the microcomputer unit determines that the moving image quality of the IVD2 system should be given priority over the IVD1 system from the information on the DDC and the input image quality. Therefore, the microcomputer unit of this embodiment can output new vertical frequency candidates that are close to the original IVD2 vertical frequency period (screen update period) and whose ratio is an integer to integer ratio. (For example, 75 Hz is selected. The ratio of the period with the original 60 Hz is T (60 Hz): T (75 Hz) = 5: 4), and IVD2 is transmitted via IVD2 system DDC communication. It is examined whether or not the system can operate at the vertical frequency as the next optimal frequency after 60 Hz. If the IVD2 side is operable, the IVD2 system operating frequency is set to the newly selected vertical frequency of 75 Hz, and the vertical frequency of the image display unit is also set to 75 Hz synchronized with the IVD2 vertical synchronizing signal. Again, SW1-2, SW2-1, and SW2-2 in FIG. 22 are selected as IN2-2, IN4-1, and IN5-2, respectively. As a result, as shown in FIG. 26, the output vertical synchronization signal OVD is synchronized with IVD2. Along with this, the operating frequency of the IVD1 system is reset to 75 Hz via the DDC1 in order to improve the moving image quality. As a result, the operation is changed to 75 Hz for both the input system and the output system.

As described in the embodiment, the frequency of 60 to 80 Hz is the most widespread frequency band such as the current PC, WS (workstation), DTV (digital television), etc. Since the video source of NTSC is in the range of 60 Hz, the frequency of use is very high, and it is highly meaningful to give priority to moving images.

  On the other hand, the flicker phenomenon of low frequency such as 50Hz is very difficult to see regardless of the moving image or the still image. And improved video quality.

  For signals with a high vertical frequency such as 100 Hz, it is important to consider that the operation speed exceeding 100 MHz places a heavy burden on the circuit. The reduction and stable operation are compatible with the improvement of video quality. In particular, a display element such as a liquid crystal display or a PDP requires a high drive voltage of several tens of volts to several tens of volts. Therefore, when the speed per pixel is increased, the video signal system and driver circuit have a very high bandwidth. Or slew rate is required. Even in the present situation, parts that cannot follow such high speed drive are divided into multiple parts, but further speeding up the output system is changing to faster parts, developing new parts, This not only increases costs due to circuit changes such as changes, but also narrows the operation margin of the circuit and makes stable operation difficult. This problem is particularly important when driving a display element, such as SXGA or UXGA, which has a pixel number several times larger than the current state. In order to increase the number of pixels in the future, it is important that cost reduction and stable operation can be compatible with improvement of moving image quality.

  Furthermore, when optimizing the vertical frequency, only one of the multiple systems can perfectly match the vertical synchronization of the output. By making it possible to select whether to ensure video quality by matching the synchronization, even if the input system that emphasizes video quality among multiple systems changes due to application software or programs, etc., it is inexpensive, A system that can respond flexibly can be constructed.

  In addition, for the input system that is not synchronized with the selected output synchronization frequency, the input signal source is requested to change the input frequency via the DDC or the like, and is changed to a frequency that matches the output frequency. As a result, video quality is optimally displayed on multiple-screen input systems, so it is inexpensive in multi-screen display devices that display various video sources such as digital TV and PC graphic game software and digital video. However, it is possible to provide a device that can sufficiently satisfy the video quality.

  In addition, when the image display unit is changed to a different type of display (for example, from a rear-type projection display to a plasma display, etc.), the applicable operating frequency band is also changed via DDC or other communication. In addition to changing the internal output frequency selection range and selection method, the contents required for a plurality of input signal systems are also changed via the DDC. In this way, it is possible to realize a device that is inexpensive and flexible with respect to future system changes and system expansion, and that is optimal in moving image quality.

In the present embodiment, DDC (DDC1, DDC2) is shown as a communication means from a device connected to a plurality of inputs, and DDC (DDC3) is shown as a communication means with an image display device for output. The VESA standard (currently issued by DDCver.3.0 1997.12.15) is the most widely used means for communicating display information to a PC. Any means capable of communicating information between image processing devices such as serial communication and parallel communication means may be used. In particular, the VESA standard has been sequentially revised, but at present, it is not assumed that a plurality of host devices (signal generators and PCs) and display devices are connected as in the present invention. There is no concept of mediation. Further, since the communication time is limited at the time of activation on the host (PC) side, it cannot be used in the present invention as it is. In this embodiment, as an example of a method for realizing the communication means, three systems DDC1, DDC2, and DDC3 are prepared as I ² C two-wire serial buses having the same communication line form as DDC, and the data format (format) is also DDC. The standard EDID (currently published by EDID ver. 3.0 1997.11.13) is used. As a result, the plurality of input devices use the image processing apparatus of this embodiment as a display and communicate DDC information as a host. In addition, the image processing apparatus according to the present embodiment treats the display apparatus connected thereto as a host and the display apparatus as a display, and communicates DDC information. The arbitration between the addresses of the plurality of input devices and the display device and the switching of the host role are not defined by the original DDC, and are therefore controlled by the microcomputer 9 of FIG. Further, detection and control that enable communication not only when the host is started but also when the connection of the device is switched are not defined by the DDC, and are therefore handled by the microcomputer 9 of FIG. In this way, the present invention is realized. The same applies to other embodiments.

  Here, the vertical frequency bands that are frequently used are synchronized and the other frequencies are double-buffered. However, double buffering requires double the memory area and a control circuit part for that purpose. Therefore, if the number of input systems increases, it becomes expensive, so it is possible to omit it as a function. While adopting a method of matching the synchronization only in a specific vertical frequency band or a method of double buffering, it is judged that the frequency of use other than that band is low, and switching to a simple asynchronous operation that does not improve the video quality, multiple inputs A method for ensuring the quality of moving images by selecting and switching only systems that prioritize moving images is one form of this embodiment in the sense of providing inexpensive products.

  In this embodiment, the output system is selected to be synchronized or asynchronous with the input system depending on the vertical frequency of the input signal. However, in the present embodiment, the optimum output from the operation modes and image quality characteristics of a plurality of input systems. System operation mode and image quality characteristics, and the output system operation mode and image quality characteristics including the display unit and multiple input system operation modes and image quality characteristics. It is characterized by having a circuit for determining and a circuit for requesting a change in the operation mode and image quality characteristics of an arbitrary input system according to the determination, and the reference for switching is not limited to the vertical frequency of the input signal. In other items of the format, image information extracted from the input image, signal content of the input image, system operation mode, screen display ratio and arrangement conditions, user settings If due to the power saving mode and also include a.

In addition, as an object to be switched, the present embodiment exemplifies the vertical frequency by paying attention to the quality of the moving image. However, for other image quality characteristics, other items of the format of the input signal, such as the resolution, the display position of the image, and the image The same applies to the size, hue, chromaticity, white balance, brightness (bright), brightness (contrast), gradation (gamma characteristics), dynamic range, and the like.
In the second embodiment, an example of gradation is shown as one of the examples.

(Example 2)
The second embodiment will be described with reference to FIG. 21 which is the same as that of the first embodiment. Here, the configuration and operation of each part in FIG. 21 are the same as those in the first embodiment.
In this embodiment, the image comparison unit 10-3 compares the image quality of each input system, and the microcomputer outputs information for image quality control of the output system and each input system. The calculation result of the comparison information obtained from the comparison signals 20-REF-1 and 20-REF-2 extracted for comparison from the image signals output from the input system image processing unit 1 and the input system image processing unit 2 is a microcomputer. It is transmitted to the microcomputer via the bus 19-1.

In this embodiment, in addition to the comparison result of the image quality characteristics of each input system obtained from the image comparison section, the comparison is made with the characteristics and conditions of the display section given by the DDC 3, other communication paths, initial information, etc. The image processing units (input system image processing unit 1, input system image processing unit 2, output system image processing unit) are controlled, and the image quality of the input signal source is controlled through DDC1 and DDC2.

  Here, the main image quality adjustment unit in the present embodiment exists in the output system image processing unit 6, and the image quality adjustment units of the input image processing units 3-1 and 3-2 exist in an auxiliary manner. This is in order to avoid an increase in the bit error of the image. The system that prioritizes image quality bypasses the image quality adjustment unit of the input image processing unit and is suitable for the image display unit only by the adjustment unit of the output system. Converted to characteristics. In addition, the other system also adjusts the image quality of the input image processing unit in an auxiliary manner so that the image quality is the same as that of the priority system. Alternatively, the non-prioritized system is the same as the prioritized system by issuing a request to change the image quality of the input signal to the input signal source via the DDC instead of adjusting the image quality in the input image processing unit. The image quality is adjusted.

  As a result, when an input image having various image quality characteristics of a plurality of input systems is combined on a single screen for multi-screen display, the image quality of the entire system can be reduced according to the image quality characteristics of each input system and output display section. Optimized.

The operation of this embodiment will be described with reference to FIGS.
FIG. 27 shows a first stage state in which image quality optimization is performed according to this embodiment. At this time, the display characteristic of the display unit is 15-1 in FIG. 15. In FIG. 27, 16-1 A and 16-1 B indicate signal levels input from two systems of input IDATA 1 and IDATA 2, and 16-3 A and 16-3 B indicate signal levels after passing through the output image processing unit 6. 16-4A and 16-4B indicate the luminance levels of the display unit at this time.

  As a first step, the microcomputer unit receives the image quality information (20-REF-1, 20-REF-2) from the input system image processing unit 1 (3-1) and the input system image processing unit 2 (3-2). Priority is given to the image quality from the results of the image comparison unit (10-3) obtained by comparison and the input / output characteristics of the image display unit obtained from the table stored in the memory attached to the microcomputer unit via the DDC3 in advance. Determine the input system to be used. Here, it is determined that the input system 2 (IDATA2) is given priority. Here, unlike the conventional example, the conversion of the characteristics of the priority system input signal with respect to the display unit is performed collectively by the output system image quality processing unit, not by the input system image quality processing unit. The conversion coefficient synthesizes the characteristics of the input system 2 and the characteristics of the output system in advance on a microcomputer and applies them to the output system image processing unit, thereby halving the number of digital processing passes and reducing bit errors. . At this time, since the same combined conversion coefficient is applied to the image of the input system 1, the image quality of the input system 1 is not optimized as in 16-3A.

  Next, as a second stage, FIG. 28 shows a state in which the microcomputer unit optimizes the image quality even for the input 1 system that has no priority. In FIG. 28, 16-1A and 16-1B indicate signal levels input from the two systems of input IDATA1 and IDATA2, and 16-2A and 16-2B indicate the input image processing unit 1 (3-1) and the input system image. Each signal level after passing through the processing unit 2 (3-2) is shown. Reference numerals 16-3A and 16-3B denote signal levels after passing through the output image processing unit 6. 16-4A and 16-4B indicate the luminance levels of the display unit at this time.

In contrast to the IDATA2 system (16-1B to 16-4B) adjusted in the first stage, the IDATA1 system is adjusted in the second stage. At this time, since the conversion characteristic of the output image processing unit 6 is determined by the input 2 (IDATA2), the input correction difference of the input 1 (IDATA1) with respect to this characteristic is input to the input image processing unit 1 (3-1). Apply. As a result, the signal level 16-2A after passing through the input image processing unit 1 (3-1) is substantially equal to the signal level 16-2B after passing through the input image processing unit 2 (3-2), and the output image processing unit Above, it is output at a signal level 16-3A that is substantially the same as 16-3B, and is displayed at a luminance level 16-4A that is substantially the same as 16-4B.
As described above, although the bit error becomes large for a system that does not have priority, adjustment can be made to the same characteristics as those of the system that has priority.

  Further, as a third stage, FIG. 29 shows a case where the image display unit 7 is changed to one having the characteristic 15-2 in FIG. In FIG. 29, 16-1A and 16-1B indicate signal levels inputted from the two systems of input IDATA1 and IDATA2, and 16-3A and 16-3B indicate signal levels after passing through the output image processing unit 6. . 16-4A and 16-4B indicate the luminance levels of the display unit at this time.

  As the image display unit is changed, the microcomputer unit rereads the output characteristics of the changed image display unit obtained from the DDC 3 or from a table or the like stored in advance in a memory attached to the microcomputer unit. From this information and the image quality information of each input system, the input system giving priority to the image quality is determined again.

  Here, it is assumed that the input 2 (IDATA2) is determined to be given priority again. The conversion coefficient is applied to the output image processing unit by combining the characteristics of the input system 2 and the characteristics of the new output system on the microcomputer, and 16-3B is output. As a result, the luminance level optimized for the display characteristics of the image display unit is selected (16-4B). Further, in the third stage, in order to reduce the bit error of the image quality for the input system 1 as well, the conversion by the input signal processing unit for the input system 1 as in the second stage is not performed, and the DDC 1 The input signal source 1 is requested to match the signal amplitude and level with the input signal source 2 via the input signal source 1, and the characteristics of the input signal of the input system 1 as in 16-1A are changed to 16-1B. It is made to be equal to the characteristics of the input signal of the input system 2. By matching the signal levels of the two input systems at the input signal stage, the number of digital processing passes is halved in both systems to reduce bit errors.

  As described above, in addition to the comparison result of the image quality characteristics of each input system obtained from the image comparison unit, comparison is made with the characteristics and conditions of the display unit given by DDC, other communication paths, initial information, etc. In addition to controlling each internal image processing unit (input system image processing unit 1, input system image processing unit 2, output system image processing unit), image quality control of an input signal source is performed via communication means such as DDC. As a result, even in multi-screen display that displays multiple input signals on a single screen, while providing an inexpensive and simple circuit configuration, high-quality display of the priority system is achieved and the image quality of other systems is also at a certain level. A system that satisfies the requirements can be realized.

  In the present embodiment, for the sake of simplicity, an example in which the gray level signal is used to optimize the DC level and amplitude of the signal as the image quality has been described. However, in practice, gamma correction for correcting the characteristics of the display element is performed. The present invention can also be applied to non-linear correction such as reverse gamma correction that cancels gamma correction applied to a video signal for CRT. In addition, with regard to white balance deviation and color characteristics caused by these characteristics being different for each of red, blue, and green, by applying this embodiment, a priority input system is selected and output system characteristics are selected. In addition, the balance of each color is adjusted, and other systems use an auxiliary means or send a control signal to the input signal source to adjust to meet a certain level to optimize the system. The same can be done. The causes of variations in the characteristics of each color include the variation in the gamma characteristics of the liquid crystal elements for each color as seen in a three-plate projector using different liquid crystal panels for red, blue and green, There are variations in characteristics of each optical element for separation into primary colors, characteristics of light emitters such as backlights, LEDs, and lamps, and variations in signal processing systems for each color.

In particular, the variation in the signal processing system may be surprisingly large even in each signal source and the processing system before the signal data is sent to the signal source, and this rarely has a unique color to the device. Absent. This is omitted because it is a manufacturer's intentional adjustment that a certain color looks stronger as a display, or because it reduces costs by reducing the man-hours for adjusting the signal processing system for each color in production. It may be a variation due to accumulation.

  Furthermore, such intentional adjustments and variations due to man-hour reduction are not limited to colors. In particular, PC graphic screen, digital TV, video conference video received via communication, image information via the Internet, video game graphic image, digital video camera video received via USB or IEEE 1394, etc. With the diversification of the types of sources and transmission forms, these characteristic differences between devices are spreading. In addition, differences in display operations such as resolution and screen refresh rate are diversified. On the other hand, the display device moves in the direction of displaying these various input sources on the same screen, and in this sense, the effectiveness of the present embodiment is also widened.

  In the first and second embodiments, an example in which two systems of PCs are connected as a plurality of input signal sources has been described. However, the third embodiment shows an application example between such diversified devices. .

(Example 3)
FIG. 30 shows an example of a system in which an image processing input / output board is provided on a PC (personal computer) and a display device is displayed as an application example among diversified devices as the third embodiment. As an input, in addition to two systems of digital inputs for directly connecting another PC or the like to the image processing board, a graphic image drawn by an application executed by the CPU of the PC main body and a communication IF are received. It can handle image information such as video conferences, and signals such as DVDs, digital videos, and digital TVs input via IEEE1394. In addition to the display device directly connected to the image processing board, the output signal can be sent to an external digital television or video recording server via IEEE1394.

  In FIG. 30, 9-1 is a CPU (central processing unit) of a PC, 9-2 is a memory / bus controller called a chipset, which controls a memory around the CPU and a bus controlled by peripheral devices, Reference numeral -3 denotes a main memory of the PC main body. Reference numeral 9-4 denotes a PC communication interface unit, which is connected to an external communication line via a terminal 1-t. 19-2 and 19-3 are PC system control buses, and 19-4 is a graphic unit control bus. An area surrounded by a one-dot chain line 25 is an image processing board, and is connected to the graphic control bus 19-4 via a terminal 1-4 with the PC main body.

  Reference numeral 1-1a denotes an input terminal for a q-bit digital image signal (IDATA1) as an input of the first system. 1-1b is an input signal horizontal synchronization signal (IHD1) input terminal, and 1-1c is an input signal vertical synchronization signal (IVD1) input terminal. Reference numeral 1-1d denotes an image signal clock (ICK1) input terminal, and reference numeral 1-1e denotes an input / output terminal for a DDC signal (DDC1). Reference numerals 20-1a-1 and 20-1a-2 denote data buses for transmitting an n-bit digital image signal to each unit. Reference numeral 20-1bcd denotes an IHD1, IVD1, ICK1 signal line group. Reference numeral 20-1e denotes a signal line of the DDC1.

  1-2a is an input terminal for an n-bit digital image signal (IDATA2) as an input of the second system. 1-2b is an input signal horizontal synchronizing signal (IHD2) input terminal, and 1-2c is an input signal vertical synchronizing signal (IVD2) input terminal. 1-2d is an image signal clock (ICK2) input terminal, and 1-2e is an input / output terminal for a DDC signal (DDC2). Reference numerals 20-2a-1 and 20-2a-2 denote data buses for transmitting an n-bit digital image signal to each unit. Reference numeral 20-2bcd denotes an IHD2, IVD2, ICK2 signal line group. Reference numeral 20-2e denotes a signal line of the DDC2.

  Reference numeral 3-1 denotes an image processing unit A of the input system 1, and 3-2 denotes an image processing unit B of the input system 2.

  1-3 is an input / output terminal of IEEE1394 that functions as an input and an external output of the third system. Reference numeral 23 denotes an IEEE 1394 processing block, and reference numeral 24 denotes an encoder / decoder for converting and inversely converting the IEEE 1394 signal into a video signal and a synchronization signal handled internally. Reference numeral 3-3 denotes an image processing unit C for an input IEEE 1394 image, and reference numeral 6-3 denotes an output image processing unit B before output as an IEEE 1394 signal.

  20-3 is an IEEE 1394 signal line, and 20-3a-1 is an r-bit digital image signal after conversion. Reference numeral 20-3bcd denotes a signal line group such as a synchronization signal and CLK reproduced from the IEEE1394 signal.

  Also, as the fourth system input, the graphic information generated by the PC application program from the graphic control bus 19-4 and the external device via the communication line are input to the PC via the terminal 1-4. Image information is input. Reference numeral 9-6 denotes a graphic generation / control unit D that outputs graphic data from these pieces of information. Reference numeral 20-4a-1 denotes a signal line group of v-bit graphic data. Reference numeral 20-4bcd denotes a group of signal lines for the synchronization signal and clock of the graphic image. Reference numeral 19-5 denotes an internal bus for graphic control connected to the external bus 19-4 via a terminal 1-4. The overall control of the image processing board is performed via this bus via the CPU of the PC main body. And the graphic generation / control unit.

4 temporarily stores the image signals input from the four systems of the three input image processing units 3-1, 3-2 and 3-3 and the graphic generation / control unit 9-6 in a memory and outputs them as a multi-screen. In order to achieve this, the memory control unit performs control for synthesizing images and outputting them to the image processing unit of the output system. 5-1, 5-2, 5-3, and 5-4 are frame memories (memory A, memory B, memory C, and memory D) respectively corresponding to the input system 1, the input system 2, the input system 3, and the graphic generation unit. It is. 21-1, 21-2, 21-3, and 21-4 are control buses for the memories A, B, C, and D, respectively, and 22-1, 22-2, 22-3, and 22-4 are the memories A, respectively. , B, C, D data buses.
Reference numeral 6-1 denotes an output image processing unit A, and 7 denotes an image display unit such as a liquid crystal display, a plasma display, or a CRT.

  1-f is an input terminal of the image display unit for k-bit digital data (ODATA) of the image display unit, and 1-g is an input terminal of the image display unit for the horizontal synchronization signal (OHD) of the output signal. -H is an input terminal of the image display unit for the vertical synchronizing signal (OVD) of the output signal. 1-i is an input terminal of the image display unit for the clock (OCK) of the output image signal. Reference numerals 20-f-1, 20-f-2, and 20-f-3 denote signal lines for k-bit digital image data (ODATA). Reference numerals 20-g-2, 20-h-2, and 20-i-2 denote signal lines of a horizontal synchronizing signal, a vertical synchronizing signal, and a clock to the external display device. 1-s is an input / output terminal of a DDC signal (DDC3) to the image display unit, and 20-s-1 and 20-s-2 are signal lines of the DDC3.

  An oscillation unit 12 generates an output system clock (OCK). Reference numeral 20-i-1 denotes an OCK signal line. The oscillating unit 12 includes an oscillating circuit such as a crystal or a PLL (Phase-Locked-Loop) circuit.

  Reference numeral 10-4 denotes internal and external synchronization control units, 20-WE denotes a write field control signal group of the memories A to D, and 20-RE denotes a read field control signal group of the memories A to D. Reference numeral 20-ghi denotes an output system horizontal synchronizing signal, vertical synchronizing signal, and clock signal line group. Reference numeral 20-CNT-6 is a control line for controlling the synchronization signal and clock of the IEEE1394 signal processing block 23.

  Reference numeral 10-5 denotes an image comparison unit and internal and external image quality control units. 20-CNT-1 and 20-CNT-2 denote data lines of image extraction information from the input system image processing units A and B, and A signal line group including control lines for controlling the image quality of the input system image processing units A and B. 20-CNT-3 is a data line of image extraction information from the input image processing unit C and the output system image processing unit B in the IEEE 1394 signal processing block 23, and the image quality of the input system image processing unit C and the output system image processing unit B. It is a signal line group consisting of control lines for controlling. 20-CNT-4 is a signal line group including a data line for image extraction information from the graphic generation / control unit and a control line for controlling the image quality of the graphic generation / control unit. Reference numeral 20-CNT-5 denotes a signal line group including a data line of image extraction information from the output system image processing unit A and a control line for controlling the image quality of the output system image processing unit A.

  Further, 9-5 cooperates with the internal / external synchronization control unit (10-4) and the internal / external image quality control unit (10-5) to input DDC signals DDC1 and DDC2 as input signals and DDC of the image display unit. This is an interface unit for DDC for transmitting and receiving the signal DDC3. Reference numerals 20-u-1 and 20-u-2 denote data lines between the internal / external synchronization control unit (10-4) and the internal / external image quality control unit (10-5) and the DDC interface unit. Control line.

  Before the digital image signal input from the image input terminal 1-1a is stored in the memory unit A of 5-1, processing such as image quality adjustment and image reduction conversion is performed in the input system image processing unit A of 3-1. Is transferred to the memory control unit 4. Further, a signal for comparing the image quality is sent from the input system image processing unit A to the image comparison unit. The synchronization signal and the clock are transmitted to the internal / external synchronization control unit 10-4.

  The digital image signal input from the image input terminal 1-2a is subjected to processing such as image quality adjustment and image reduction conversion in the input system image processing unit 3-2 before being stored in the memory unit B 5-2. Is transferred to the memory control unit 4. Also, a signal for comparing image quality is sent from the input system image processing unit B to the image comparison unit. The synchronization signal and the clock are transmitted to the internal / external synchronization control unit 10-4.

The IEEE 1394 signal input from the IEEE 1394 input / output terminal 1-3 is converted into an image signal and a synchronization signal that can be handled internally. Before being stored in the memory section 5-3, the input image processing section C-3 performs processing such as image quality adjustment and image reduction conversion, and then transferred to the memory control section 4. . Also, a signal for comparing the image quality is sent from the input system image processing unit C to the image comparison unit.
Further, when outputting as IEEE1394 externally, the image information in the output image processing unit B is also sent to the image comparison unit. The synchronization signal and the clock are transmitted to the internal / external synchronization control unit 10-4.

  The graphic generation / control unit 9-6 receives the synchronization signal and clock generated by the internal / external synchronization control unit (10-4) and generates a graphic signal in accordance with the instructions of the application software or graphic driver software. Are transferred to the memory control unit 4 for storage in the memory unit D of 5-4. At this time, the image quality is controlled by the internal / external image quality control unit (10-5).

In the memory control unit, signals are read from the memories A to D in accordance with the output synchronization signal and clock generated by the internal / external synchronization control unit (10-4) and synthesized. At this time, the image information in the output system image processing unit A is also sent to the image comparison unit (10-5).
In this embodiment, each of the memory units A to D secures a memory area that can be double-buffered, and is written by the control line group (20-WE, 20-RE) of the memory write signal and read signal of the synchronization control unit. The memory area to be read is switched and controlled.

Further, four sets of image data are synchronized with the output clock OCK, the horizontal synchronization signal OHD, and the vertical synchronization signal OVD from the internal / external synchronization control unit at a timing that matches the size and display position of a predetermined image. Is read from the memory unit, and the data is transferred to the output system image unit 6-1.
The image processing unit 6-1 performs image quality adjustment, image enlargement conversion, and the like. Finally, these image data, a synchronizing signal, and a clock are transmitted to the image display unit 7 to perform image display.

  Also in the present embodiment, the internal / external synchronization control unit 10-4 can select an input system that gives priority to a moving image as in the first embodiment, thereby optimizing the operation of the entire system. Here, a synchronization signal and a clock of the input system 1, the input system 2, and the input system 3 are input. Further, the image display unit and the DDCs of the input system 1 and the input system 2 are connected via the DDC interface unit. In addition, application software executed by the graphic creation / control unit and request contents of an image display operation from communication are input via the internal bus 19-5. Further, image characteristic information is obtained from the image extraction information of the input systems 1 to 3 by the image quality comparison unit 10-5. From these information, the internal / external synchronization control unit determines the operation timing of the four input systems, the moving image quality characteristic of the image, and the operation characteristic of the image display unit, and an output system suitable for the moving image of the input system to be prioritized. A memory control signal, an output synchronization signal, and a clock are generated so as to operate. In addition, a timing signal synchronized with the output is sent to the synchronization signal and clock of the graphic creation / control unit. Further, when it is necessary to optimize the operation for the other input systems, the operation of the input signal source is changed for the input systems 1 and 2 via communication means such as DDC. Make a request. In the case of the input system 3, the encoder / decoder unit 24 converts the request signal into an IEEE 1394 signal through the control line 20-CNT-6, and this signal further controls the signal source device through the IEEE 1394 signal. Change the source behavior.

  Also in this embodiment, the internal / external image quality control unit 10-5 can select the input system giving priority to the image quality and optimize the image quality of the entire system as in the second embodiment. Here, image information extracted from the input system image processing units A to C is input, and image information extracted from the graphic generation / control unit is also input. In addition, image extraction information from the output system image processing unit A and display characteristics obtained from the image display unit 7 via the DDC interface are input. Further, the image extraction information from the output system image processing unit B and the display characteristics of another display device connected via IEEE1394 obtained through IEEE1394 are also input. From these pieces of information, the internal / external image quality control unit determines and gives priority to the image quality characteristics of the four input systems, the image quality display characteristics of the image display unit 7 and the image quality display characteristics of another display device connected via IEEE1394. The output system image processing unit A or the output system image processing unit B is controlled so that the image quality characteristic suitable for the power input system is obtained. Further, when it is necessary to optimize the image quality for other input systems, the image processing unit of each input system adjusts the image quality. Alternatively, the input systems 1 and 2 are requested to change the image quality to the input signal source via communication means such as DDC. In the case of the input system 3, the encoder / decoder unit 24 converts the request signal into an IEEE 1394 signal through the control line 20-CNT-6, and this signal further controls the signal source device through the IEEE 1394 signal. Change the image quality of the signal from the source.

In this embodiment, the determination of the optimization of the entire system that performs the optimization by selecting the priority input system is performed by the internal / external synchronization control unit 10-4 or the internal / external image quality control unit 10-5. 9-6 graphic generation / control unit or 9
Needless to say, the CPU -1 may be executed in software by application software or graphic control driver software.

  As a result, when multi-screen display is performed by combining input images of various formats and image quality characteristics of a plurality of input systems on one screen, depending on the image quality of each input system and the output display section and the characteristics of the moving image, The operation timing and image quality of the entire system are optimized.

  Here, the consistency of each input system has been considered, but in reality, the signal from each signal source is not necessarily only the output from one type of signal source. For example, IEEE 1394 is connected to a plurality of devices such as DVD and digital video, satellite broadcasting, cable television, terrestrial broadcasting and other set top boxes. In this embodiment, a plurality of pieces of image information mixed in one input can also be considered as each of the input signal sources, and signals from such a plurality of devices input from the IEEE 1394 terminal and the like can be applied. It is possible to optimize the entire system of moving image quality and image quality characteristics by selecting a priority signal after arranging the signals of the input system in the same row.

  The selection of the input image to be prioritized is performed not only based on the image extraction information and the format of the image signal, but also based on the use and type of the image to be input, the automatic setting or the arrangement condition of each image on the display screen set by the user. . For example, in this embodiment, consider a screen on which input video signals are combined and displayed as shown in FIG. 31 and Table 4.

  In Table 4, each column indicates the use and type of the signal of each signal input source. Here, as an example, (1) a digital TV signal via IEEE 1394, (2) a TV phone via a communication IF, and (3) an internet image input from an external PC input is given. Yes. Further, in the row of Table 4, an image that is automatically set depending on the application or selected as the screen that the user who is viewing the display device most pays attention to according to the application, for example, is arranged according to the arrangement condition It is shown. (A) to (d) in Table 4 correspond to (a) to (d) in FIG. The circles are input signal sources that are preferentially selected by the circuit of the present embodiment in terms of the use, type and arrangement conditions of the signals of the input sources.

  In FIG. 31 and Table 4, first, on the display screen of (a), the digital television screen is arranged on the forefront. At this time, the Internet screen is also displayed as a child screen on the image display unit, but it is not the display object that attracts the most attention, and is mainly a still image. In addition, although an image of a TV phone is input, it is not currently received. Therefore, the synchronization control unit and the image quality control unit select a digital television signal as a priority input system and optimize the system operation.

In the display screen of (b), a TV phone screen is arranged on the foreground. At this time,
In the image display unit, the Internet screen is also displayed as a sub-screen. However, it is not the display object that attracts the most attention, and is mainly a still image. In addition, although an image on a digital television screen is input, it is currently displayed in a small size. Therefore, the synchronization control unit and the image quality control unit select the TV phone screen signal as a priority input system to optimize the system operation.

  In the display screen of (c), the Internet screen is arranged in the foreground. At this time, other images of the digital television are displayed in a small screen on the image display unit. Moreover, although the image of the videophone is also input, it is in a state where it is currently displayed small. Here, the synchronization control unit and the image quality control unit select a digital television image signal as a priority input system and optimize the system operation. This is because, as an arrangement condition, the Internet screen is the foreground, but the content is mainly a still image, so that the digital television is determined to be the highest priority input.

  On the other hand, on the display screen of (d), an Internet screen is arranged in the foreground, and an image of a digital TV and a videophone are also input to the image display unit. The difference from (c) is that the video information distributed on the Internet screen is displayed in a small window (4). Here, the synchronization control unit and the image quality control unit select a signal on the Internet screen as a priority input system, and optimize the system operation. This is because the Internet screen is at the forefront as the arrangement condition, and the content is mainly a moving image, so that the Internet screen is determined to be the highest priority over the digital television.

  In this way, the system operation with priority given to the signal source is optimized according to the arrangement condition and the contents of the signal in which the subject viewed by the user is changed. In addition, the user can store the input signal and the setting state in the arrangement condition in the system memory unit of FIG. 30, and this allows the optimization relationship between the user's various video devices and the image display unit to be implemented. Can be stored in the image processing apparatus.

  According to the first and second reference examples, the output system can be switched between synchronous and asynchronous with respect to the vertical synchronization signal of the input system, and can be switched according to the format of the input signal such as the vertical frequency. The system as a whole is strong against moving images, achieving operation that does not have any problems with moving images, especially in the frequently used vertical frequency band. An image processing apparatus that achieves both a solution and an operation margin and performing a stable operation can be realized simply and inexpensively. Further, in the future, it is possible to easily realize an inexpensive and strong circuit for moving images with the same configuration for signal processing applications such as UXGA, which has a number of pixels several times larger than the current state. Further, even in a system in which a plurality of input signals having different periods are mixed, the output system can be switched between synchronous and asynchronous with respect to the vertical synchronization signals of a plurality of input systems. By configuring so that the vertical frequency of the input signal source can be set, the output system configuration can be operated with one system clock, while optimizing the synchronization relationship between the multiple input systems and the output, It is possible to make a simple and inexpensive circuit configuration that is strong against moving images.

According to the first to third embodiments of the present invention, in the image processing apparatus for multi-screen display that displays the input image from each input signal source on the same screen, the format and characteristics of the input signal of each input system The display contents are compared with the characteristics of the image display unit, the priority input signal is selected, and the operation mode and image quality characteristic of the image display unit are set. In addition, the input system other than the priority system is adjusted again for the operation and image quality adjustment according to the operation mode and image characteristics of the applied image display unit. Alternatively, a setting change request is made to each input signal source via the communication means such as DDC or IEEE 1394 for the operation mode and image quality adjustment according to the operation mode and image characteristics of the applied image display unit. As a result, an image processing apparatus that flexibly optimizes moving image quality and image quality characteristics can be realized at low cost even for a plurality of input signals.

Furthermore, optimization can be performed in consideration of the characteristics of each input signal even when the image display apparatus is changed or characteristics are changed.
Specifically, the output system can be switched between synchronous and asynchronous with respect to the vertical synchronization signal of each input system, and the video quality can be improved depending on the contents of the input signal format such as the vertical frequency and the motion component of the input signal. The priority input system is selected and synchronized with the vertical synchronization signal to optimize the video quality of the priority system. Also, other input systems can be adjusted to the operation mode such as double buffering among the selected operation modes, or matched to the operation mode and image characteristics of the applied image display unit via communication means such as DDC. Requests change of input source setting for operation and image quality adjustment. As a result, the configuration of the output system is operated with a single clock, and the synchronization relationship between the output systems and the outputs is optimized, and the entire system is configured to be strong against moving images, and to be a simple and inexpensive circuit configuration. Can do.

  Also, the input system that prioritizes display image quality is selected according to the input signal format, image quality characteristics, display content, etc., and the input image quality characteristics that are prioritized and the image quality characteristics of the output system are combined and applied to the output image adjustment unit. As a result, an image quality with little bit error is realized with respect to the prioritized system. In addition, for the output image adjustment in which other input systems are also set, an auxiliary adjustment is performed by the input image adjustment unit, or the output image adjustment of the applied image display unit is adjusted via communication means such as DDC. Requests to change the input source setting for image quality adjustment. As a result, it is possible to easily and inexpensively realize a circuit that optimizes the image quality difference between the plurality of input systems and the output image quality relationship, and makes the image quality of the entire system uniform.

1 is a block diagram of an image processing apparatus according to a first reference example of the present invention. It is a block diagram of the synchronous control part in the apparatus of FIG. It is a timing chart for demonstrating operation | movement of the apparatus of FIG. It is a block diagram of the image processing apparatus which concerns on the 2nd reference example of this invention. 5 is an image display example in the apparatus of FIG. It is a block diagram of an image processing device for explaining a conventional example. 7 is a timing chart showing an operation of the image processing apparatus in the conventional example of FIG. It is explanatory drawing of the problem in the moving image in the prior art example of FIG. It is a figure which shows the memory area at the time of performing double buffering. 6 is a timing chart showing the operation of the image processing apparatus in double buffering. It is explanatory drawing of the problem in the moving image in double buffering. It is explanatory drawing of the problem in the moving image in double buffering. It is a block diagram of the image processing apparatus for demonstrating a 2nd prior art example. It is a figure for demonstrating the problem regarding the gradation property of the image quality in the 2nd prior art example. It is a figure for demonstrating the problem regarding the gradation property of the image quality in the 2nd prior art example. It is a figure for demonstrating the problem regarding the gradation property of the image quality in the 2nd prior art example. It is a figure for demonstrating the problem regarding the gradation property of the image quality in the 2nd prior art example. It is a figure for demonstrating the problem regarding the gradation property of the image quality in the 2nd prior art example. It is a figure for demonstrating the problem regarding the gradation property of the image quality in the 2nd prior art example. It is a conceptual diagram for demonstrating the gradation bit error in the 2nd prior art example. It is a block diagram of the image processing apparatus which concerns on the 1st and 2nd Example of this invention. It is a block diagram of the synchronous control part in the apparatus of FIG. It is a timing chart for demonstrating operation | movement of the 1st Example of this invention. It is a timing chart for demonstrating operation | movement of the 1st Example of this invention. It is a timing chart for demonstrating operation | movement of the 1st Example of this invention. It is a timing chart for demonstrating operation | movement of the 1st Example of this invention. It is a figure for demonstrating the operation | movement with respect to the gradation property of the image quality of 2nd Example of this invention. It is a figure for demonstrating the operation | movement with respect to the gradation property of the image quality of 2nd Example of this invention. It is a figure for demonstrating the operation | movement with respect to the gradation property of the image quality of 2nd Example of this invention. It is a block diagram of the image processing apparatus as a 3rd Example of this invention. It is a conceptual diagram for demonstrating operation | movement of the 3rd Example of this invention.

Explanation of symbols

  3, 3-1 and 3-2: input system image processing unit, 4: memory control unit, 5: memory unit, 6: output system image processing unit, 7: image display unit, 8: PLL, 9: microcomputer, 10 : Synchronization control unit, 12: oscillator (second clock generation unit), ICK, ICK1, ICK2: input system clock (first clock), IHD, IHD1, IHD2: input system horizontal synchronization signal (first image synchronization signal) ), IVD, IVD1, IVD2: input system vertical synchronization signal (first image synchronization signal), OCK: output system clock (second clock), OHD: output system horizontal synchronization signal (second image synchronization signal), OVD: output system vertical synchronization signal (second image synchronization signal), RE: read field control signal, WE: write field control signal.

Claims (7)

Having at least one signal input unit to which video signals of a plurality of systems are input, a memory unit having a storage area for storing at least one screen image, and at least one signal output unit for image display; In the image processing unit having the image processing unit that synthesizes the video signals of the plurality of systems on the memory unit and outputs the synthesized signal to the signal output unit, and the control unit that controls the image processing unit,
The control means has communication means for making a request for changing image characteristics for at least one of the plurality of video signals to be input, and the video signal to be prioritized from the image characteristic information of the video signals of the plurality of systems. And the operation of the image processing means is changed to an operation suitable for the video signal of the priority system, and the image processing is performed on the video signal of at least one system other than the video signal of the priority system. An image processing apparatus which requests to change to an image characteristic suitable for the operation of the means. Having at least one signal input unit to which video signals of a plurality of systems are input, a memory unit having a storage area for storing at least one screen image, and at least one signal output unit for image display; In the image processing unit having the image processing unit that synthesizes the video signals of the plurality of systems on the memory unit and outputs the synthesized signal to the signal output unit, and the control unit that controls the image processing unit,
The control means includes a communication means for requesting change of image characteristics for at least one of the plurality of video signals to be input, and includes image characteristic information of the video signals of the plurality of systems and the signal output unit. Select a priority video signal from the characteristic information of the connected image display unit, and operate the image processing means in accordance with the priority system video signal and the image display unit connected to the signal output unit. And at least one system video signal other than the priority system video signal is requested to change to an image characteristic suitable for the operation of the image processing means. . Having at least one signal input unit to which video signals of a plurality of systems are input, a memory unit having a storage area for storing at least one screen image, and at least one signal output unit for image display; In the image processing unit having the image processing unit that synthesizes the video signals of the plurality of systems on the memory unit and outputs the synthesized signal to the signal output unit, and the control unit that controls the image processing unit,
The control means has priority video signals based on image characteristic information of the video signals of the plurality of systems, arrangement conditions on the screen to be output to the signal output unit, and characteristic information of the image display unit connected to the signal output unit. And the operation of the image processing means connected to the signal output unit is changed to an operation suitable for the video signal of the priority system and the image display unit connected to the signal output unit. Image processing device. Having at least one signal input unit to which video signals of a plurality of systems are input, a memory unit having a storage area for storing at least one screen image, and at least one signal output unit for image display; In the image processing unit having the image processing unit that synthesizes the video signals of the plurality of systems on the memory unit and outputs the synthesized signal to the signal output unit, and the control unit that controls the image processing unit,
The control means has communication means for making a request for changing image characteristics for at least one of the plurality of video signals to be input, and the image characteristic information of the video signals of the plurality of systems and the signal output unit The priority video signal is selected from the on-screen layout conditions to be output, and the operation of the image processing means is changed to an operation suitable for the priority system video signal, and other than the priority system video signal. An image processing apparatus characterized by requesting at least one system of video signals to be changed to an image characteristic suitable for the operation of the image processing means. Having at least one signal input unit to which video signals of a plurality of systems are input, a memory unit having a storage area for storing at least one screen image, and at least one signal output unit for image display; In the image processing unit having the image processing unit that synthesizes the video signals of the plurality of systems on the memory unit and outputs the synthesized signal to the signal output unit, and the control unit that controls the image processing unit,
The control means includes a communication means for requesting change of image characteristics for at least one of the plurality of video signals to be input, and includes image characteristic information of the video signals of the plurality of systems and the signal output unit. A priority video signal is selected from the arrangement conditions on the screen to be output and the characteristic information of the image display unit connected to the signal output unit, and the operation of the image processing means is performed with respect to the priority video signal and the signal. The operation is changed to an operation suitable for the image display unit connected to the output unit, and at least one system video signal other than the priority system video signal is changed to an image characteristic suitable for the operation of the image processing means. An image processing apparatus characterized by requesting to be performed. In the control means, the image characteristic information referred to when selecting the priority input video signal is information on moving image still image discrimination of the input image, and the operation of the image processing means is optimized by a display unit. the image processing apparatus according to claim 1, any one of 5, characterized in that an update cycle of the display screen. In the control means, the image characteristic information referred to when selecting the priority input video signal is information on the use and type of the input image, and the operation of the image processing means is optimized by the display unit. the image processing apparatus according to any one of claims 1-5, characterized in that an update cycle of the display screen.

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