JP3918077B2 - Storage controller control method - Google Patents

Description

Technical field
The present invention relates to a control method of a control device that intervenes in data transfer between a central processing unit and a storage device.
Background art
A conventional control device includes a cache memory that temporarily stores data in a storage device, a host-side processor that executes data transfer between the cache memory and the central processing unit, and data between the cache memory and the storage device. The storage device side processor that executes the transfer and the shared memory that stores the management information of the cache memory. Both the host-side processor and the storage device-side processor can access the shared memory.
In the above configuration, each processor in the control device shares data and management information on the cache memory. Therefore, each processor can access data in any storage device via the cache memory. The processors on the host side and the storage device side can operate independently. That is, the hit processing to the cache memory by the host side processor and the write processing to the storage device by the storage device side processor can be executed in parallel.
In the conventional configuration in which one shared memory and cache memory are mounted on the control device, accesses from each processor are concentrated on the shared memory. For this reason, there is a problem that access control to the shared memory becomes a bottleneck.
An object of the present invention is to provide a storage control device and a control method therefor that can eliminate an access bottleneck to a shared memory and a cache memory.
Disclosure of the invention
The cache memory is for temporarily storing data on the storage device, and basically only needs to exist for the storage device. Similarly, the cache management information stored in the shared memory only needs to exist corresponding to the storage device. Based on the above idea, in order to achieve the above object, in the present invention, for each storage device, one or more storage device side processors that can access this storage device are allocated as one group, and cache memory and shared A memory is allocated to each group, and each storage device processor in the group manages the cache management information allocated to this group. As a result, a plurality of cache memories and a plurality of shared memories can be operated simultaneously, and a bottleneck can be eliminated. However, this grouping may be a grouping for a plurality of storage devices.
In the control device according to the present invention, the host-side processor specifies a storage-device-side processor in a group that can access the storage device based on the storage device that stores the data requested to be accessed from the central processing unit. In response to an access request from the host processor, the specified storage device processor accesses the shared memory assigned to this group and determines whether the target data exists in the cache. If there is data in the cache, the host side processor is notified of the cache address storing the data. As a result, the host side processor accesses the notified cache address.
Through the above processing, only the storage device side processor belonging to one group to which the shared memory is allocated accesses the single shared memory allocated to each group. As a result, the number of accesses to one shared memory can be reduced. As a result, contention for access to the shared memory can be suppressed. Further, since a plurality of shared memories and a plurality of cache memories are held in the system, the access performance to the shared memory and the cache memory in the entire system can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration example of a computer system to which the present invention is applied.
FIG. 2 is a diagram showing the configuration of the storage device.
FIG. 3 is a diagram showing management information and a management method for the cache memory.
FIG. 4 is a diagram showing a processing outline of the read hit processing.
FIG. 5 is a flowchart of the processing of the host side processor that has received the read processing request from the central processing unit.
FIG. 6 is a flowchart of the processing of the host processor that has received the reconnection request from the storage device processor.
FIG. 7 is a flowchart of the processing of the storage device side processor in the read processing.
FIG. 8 is a flowchart of the processing of the host side processor in the write processing.
FIG. 9 is a flowchart of the processing of the storage device side processor in the write processing.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.
As shown in FIG. 1, the computer system includes a central processing unit 100, a control unit 180, and a storage unit 170. The control device 180 includes one or more host processors 111 that control data transfer between the cache memory 140 and the central processing unit 100, and one or more storage devices that control data transfer between the storage device 170 and the cache memory 140. Side processor 152.
Further, all the storage device side processors 152 that can access the same storage device 170 are set as the same processor group 190, and one shared memory 160 and cache memory 140 are provided for each group. The storage device side processor 152 in each group 190 can access the shared memory 160 via the shared memory access path 165. Each storage device side processor 152 accesses the storage device 170 via the storage device access path 175. In the storage device access path 175, it is assumed that a plurality of storage devices 170 are connected in a vine shape on one path. In addition, for the sake of simplicity, only one storage device access path 175 is shown from each storage device side processor 152, but a single storage device side processor 152 has a plurality of storage device access paths. 175 may be connected.
Next, the storage device 170 will be described with reference to FIG. In the present invention, it is assumed that the storage device 170 is a magnetic storage device including a rotating storage medium. The storage device 170 exists for each of the plurality of storage media 400 and the storage media 400, and performs data transfer between the plurality of heads 420 that perform data transfer between the storage medium 400 and the storage device interface 440, and between the head 420 and the outside of the storage device. Storage device interface 440.
The heads 420 are numbered in ascending order from the top. Data cannot be read or written from a plurality of storage media 400 at the same time. That is, at most one head 420 becomes active. Moving the head 420 over the storage medium to access the target data is called seeking, and waiting after the seek is completed until the target data passes under the head 420 is called searching. An area on the storage medium 400 that can be accessed while the head 420 rotates once is called a track 410. An area (collection of tracks 410) that passes under all the heads 420 during one rotation of the storage medium 400 is called a cylinder 430, and is numbered in ascending order from the outside to the inside of the storage medium 400. Yes. The track 410 is specified by the combination of the cylinder number and the head number. Further, the data storage area of the storage medium 400 is divided into 512-byte small areas, which are called sectors. The sectors are uniquely numbered within the track 410, and are uniquely numbered within the track 410 in ascending order from the top of the track 410.
Next, a method for managing the cache memory 140 will be described with reference to FIG. The cache memory 140 is divided for each group 190, but is logically viewed as a continuous address space. That is, if a certain cache address is determined, it can be specified which area belongs to which group 190. In order to realize this, for example, the group 190 number may be embedded in the cache address and recognized by hardware that executes data transfer.
The cache memory 140 is divided into areas called segments 530, for example, of 16 KB (fixed size by the system), and one segment management table 520 exists on the shared memory 160 for each segment. The segment management table 520 stores a cache address 522 of the segment 530, a bitmap 523 indicating dirty data, a bitmap 524 indicating clean data, and a pointer 521 to another segment management table. Here, dirty data is updated on the cache 140, but is not yet reflected in the storage device 170, and clean data is data that matches the content of the storage device 170 existing on the cache 140. To express. Further, the segment 530 is divided every 512 bytes, for example, and a bit map is created in which 1 bit is associated with this area. If dirty data or clean data exists in the corresponding area, the corresponding bit of the dirty bitmap 523 or the clean bitmap 524 is set to 1. In order to manage the data area more finely as described above, the dirty bitmap 523 and the clean bitmap 524 are used.
When allocating a cache area corresponding to a continuous area or a nearby area on the storage device 170, it is more convenient to manage a plurality of segments 530 together. In the present invention, the cache area corresponding to one track 410 minutes is managed by the slot management table 510. Here, the slot management table 510 stores a storage device number 512, a track number 513, a pointer 515 to the first segment management block, and lock information 514. The storage device number 512 and the track number 513 can specify which track 410 data is stored in which storage device. Further, by tracing the pointer 515 and referring to the segment management block 520, which track 410 can be identified. Whether a sector is stored and whether the sector is dirty can be specified. The lock information 514 is used when the slot is exclusively processed.
Here, an example of how cache management is performed when there is an access request to certain data on a certain track 410 of a certain storage device 170 is shown. First, as an access request, a read / write type, a logical storage device number, a track number, the first sector of the target data, and a length (number of sectors) are given. First, it is checked whether the target slot management block 510 exists based on the storage device number and the track number. One example of this technique is a hash. That is, when the storage device number and the track number are given to the hash function, the corresponding entry in the hash table 500 is output, and the address of the slot management table 510 is stored in this entry. If this is null (no address), it is a miss. If it is not null, this pointer is traced to check whether the storage device number 512 and the track number 513 match what is being searched for. If they do not match, the pointer to the slot management block 510 is followed, and the comparison between the storage device number 512 and the track number 513 is repeated. In this way, it is searched whether or not the target slot management block 510 exists.
If the slot management block 510 exists on the shared memory 160, it is checked whether there is a sector range to be accessed. For this purpose, first, the start segment number and the start bit position, and the end segment and the end bit position are calculated from the start sector number and the number of sectors of the target data. For example, when reading 12 sectors starting from the 60th sector, bit 9 of the third segment is calculated from bit 29 of the second segment. Based on this, it is determined by examining the clean bitmap 524 or the dirty bitmap 523 whether there is data in this bit range. If there is data over the entire target range, it is a hit, and if there is no part, it is a miss. In the case of a hit, the access can be continued as it is. In the case of a miss, the slot management table 510 does not exist and the slot management table 510 exists, but if part or all of the segment management table 520 does not exist, all the segment management tables 520 exist, but the data does not exist. It may not exist on the cache 140. If the data does not exist on the cache 140, the data may be read from the storage device 170 to the cache 140. If the segment management table 520 does not exist, the necessary number of new segment management tables 520 are allocated and connected to the slot management table 510. At this time, the dirty bitmap 523 and the clean bitmap 524 are initialized. If the slot management table 510 does not exist, the slot management table 510 and the segment management table 520 are allocated as many as necessary, and the address of the slot management table 510 is stored in the corresponding hash table 500 entry. At this time, the logical storage device number 512 and the track number 513 are updated.
When the target slot is found to be a hit or when it is found to be a mistake and the slot management table 510 is newly assigned, a slot lock is secured. If the slot is already locked, the process waits until the lock of the slot is released. When the cache operation is completed and the slot is no longer needed, the slot lock is released. Also in this case, the target slot is searched from the logical storage device number and the track number as in the case of hit miss determination. Alternatively, a method may be used in which the address of the slot is stored at the time of hit miss determination and the slot management table 510 is obtained from the address at the time of release. When the target slot management table 510 is obtained, the slot lock is released and the slot release processing is completed.
Hereinafter, a processing method for an access request from the central processing unit 100 will be described. The data access protocol between the central processing unit 100 and the control device 180 includes a CKD protocol used in a general-purpose machine, a SCSI protocol used in a workstation, and the like. In this embodiment, the data access protocol will be described on the assumption of the CKD protocol.
Among the commands used in the CKD protocol, those related to the present invention include a DX (Define Extent) command indicating an access valid range and a cache access mode, a LOC (Locate) command indicating an access position and the number of records to be accessed, There are an RDD (Read Data) command for reading, a WRD (Write Data) command for writing, and the like. When accessing a certain record, a plurality of commands such as DX, LOC, and RDD are continuously executed. This is called a command chain. Further, a plurality of continuous records can be accessed by issuing commands such as DX, LOC, RDD. In the DX command, there is a mode for designating whether to read records sequentially. As positioning information transferred by the LOC command, a cylinder number, a head number, a sector number, and a record number are designated. The storage device number is specified when establishing a connection with the control device in order for the central processing unit to issue a command.
First, the outline of the entire process will be described with reference to FIG.
FIG. 4 shows a schematic diagram of the read hit process. When the host-side processor 111 receives a read request from the central processing unit 100, the storage-side processor 152 that can access the storage device 170 to be read is selected by the following method, and a read message is transmitted.
Each processor maintains a storage device access table 600 on its local memory. Each entry is composed of a pair of storage device side processor numbers and states that can access each storage device 170. In this example, at most two storage device side processors 152 can access each storage device 170. Yes. The state is either normal or blocked, and the processor 152 cannot access the storage device 170 in the blocked state. This table is created in the shared memory 160 at the time of system construction, and each processor holds a copy in the local memory. When the storage device side processor 152 and the inter-storage device access path 175 are blocked due to a failure, or when access is temporarily disabled due to maintenance, the state of the corresponding entry in the storage device access table 600 is blocked.
The host-side processor 111 looks at an entry corresponding to the storage device number to be accessed in the storage device access table 600, obtains the storage device-side processor 152 that can access the storage device 170, and determines any storage device-side processor. In response to this, a processing request message is issued. The message includes an access type, a storage device number, a cylinder number, a head number, a sector number, and a sector number. Here, the access type to the sector number are designated by the central processing unit. The number of sectors is calculated from the number of records specified by the LOC command and the record length. For example, when reading 3 records of 4 kilobytes with 512 bytes per sector, 4096 × 3 ÷ 512 = 24 sectors.
In response to a read request from the host-side processor 111, the storage-side processor 152 accesses the shared memory and executes hit / miss determination, and the address of the cache area storing the data and valid data on the cache 140 The length is returned to the host processor 111. In response to this, the host-side processor 111 reads data from the address and performs data transfer to the central processing unit 100. When the above processing is completed, the normal end is reported to the central processing unit 100, the access completion is reported to the storage device side processor 152, and the processing ends. In response to this, the storage device-side processor 152 releases the secured cache area.
The outline of the processing method for the read request from the central processing unit 100 has been described above. Details of the read and write processes will be described below with reference to a process flowchart.
First, the read processing method will be described with reference to FIGS.
FIG. 5 shows the processing of the host processor 111. When a read processing request is received from the central processing unit 100 in step 700, in step 720, the storage device side processor 152 is selected by the method described above and a read processing request is issued. In step 730, a response from the storage device side processor 152 is awaited.
In step 900 of FIG. 7, when the storage device side processor 152 receives a processing request from the host side processor 111, a hit miss determination is performed in step 910. As a result, if it is found that the hit occurs, the following report is made to the host processor 111 that issued the message in step 920.
(1) Hit miss determination result: hit.
(2) Segment address list: A list of segment addresses storing data.
(3) Offset within segment: Offset within the first segment of the first sector storing the data.
Here, the segment address is stored in the segment management table 520. The intra-segment offset returns the bit position corresponding to the first sector storing the target data in the dirty bitmap 523 or the clean bitmap 524 of the segment management table 520.
When the host processor 111 recognizes that it is a hit, the cache address where the target data is stored is known from the segment address list and the intra-segment offset, and the data is transferred to the central processing unit 100 in step 740. Thereafter, in step 750, the storage device side processor 152 is notified of the access completion, and the processing is completed. The message transmitted at this time includes a storage device number, a cylinder number, a head number, dirty presence / absence information, a head dirty segment, an intra-segment offset, and the number of dirty sectors. Here, the dirty presence / absence information stores “no dirty”, and the head dirty segment, the intra-segment offset, and the number of dirty sectors store invalid values. In step 930 of FIG. 7, when the storage device side processor 152 receives an access completion report from the host side processor 111, the lock of the currently secured slot is released and the processing is terminated.
If there is a cache miss, the storage device side processor 152 newly allocates the slot management table 510 and the segment management table 520 in the hit miss determination process at step 910 in FIG. Subsequently, after reporting the hit / miss determination result (miss) to the host processor 111 in step 950, in step 960, a read request is issued to the storage device 170 storing the data and waits until the read is completed.
When the host-side processor 111 recognizes that there is a read error in step 735 of FIG. 5, the host-side processor 111 interrupts the processing once and disconnects from the central processing unit 100 (step 770).
When the data transfer from the storage device 170 to the cache memory 140 is completed, the storage device processor 152 retransmits the host processor 152 waiting for reading from the storage device 170 in step 970 in FIG. Issue a connection request.
When the host processor 111 detects a reconnection request from the storage device processor 152 at step 800 in FIG. 6, a reconnection process is executed between the host processor 111 and the central processing unit 100 at step 810. When this is completed, in step 830, the completion of reconnection is reported to the storage device side processor 152.
In response to this, in step 990 of FIG. 7, the storage device side processor 152 transmits the segment address list storing the request data and the intra-segment offset. The subsequent processing is the same as the read hit processing, and is therefore omitted.
If the result of the hit miss determination is a write miss, the response varies depending on whether the request from the host-side processor 111 requires a read at the time of a miss or is unnecessary. If it is necessary to read at the time of a miss, data is stored from the storage device 170 to the cache 140 as in the case of the read miss. During this time, the host processor 111 disconnects the connection with the central processing unit 100 and executes the write process in the restart process. The write process here is the same as the write process at the time of hit. If reading is not necessary at the time of a miss, the storage device side processor 152 and the host side processor 111 perform the same processing as the write hit processing.
Next, the write processing method will be described with reference to FIGS.
When the host-side processor 111 receives a write processing request from the central processing unit 100 in step 1000 of FIG. 8, in step 1020, the storage-side processor 152 is selected by the method described in FIG. And waits for a response from the storage device side processor 152 in step 1030.
The storage device side processor 152 executes hit / miss determination in step 1110 of FIG. Here, if it is a miss, the slot management table 510 and the segment management table 520 are allocated as necessary in the hit miss determination process. Subsequently, in step 1120, the segment address list and the intra-segment offset are transferred to the host side processor, and then in step 1130, the host side processor 111 waits for a slot release request.
When the host-side processor 111 receives the hit / miss determination result and the cache address from the storage-side processor 152 in step 1040 of FIG. 8, the host-side processor 111 stores the data transferred from the central processing unit 100 in the cache area. . When the data transfer is completed, the host processor 111 transmits access completion to the storage device processor 152 in step 1050. The message transmitted at this time includes a storage device number, a cylinder number, a head number, dirty presence / absence information, a head dirty segment, an intra-segment offset, and a dirty sector length. Here, dirty presence / absence information is stored as dirty. The head dirty segment and the intra-segment offset include the segment address holding the head dirty sector, the sector offset within the segment, and the number of dirty segments from the central processing unit 100. Stores the number of segments written.
Receiving the access completion report, the storage device side processor 152 obtains the target slot management table 510 by the above-described method in step 1140 of FIG. 9, and when this is the case, the dirty bitmap of the segment management table 520 corresponding to the first dirty segment is obtained. Bits corresponding to the number of dirty segments are set to 1 from the bits corresponding to the intra-segment offset at 523 (step 1140). At this time, depending on the number of dirty sectors, the dirty bitmap 523 may be set to 1 over a plurality of segments. In this case, the next segment pointer is traced and the dirty bitmap is sequentially set to 1. When this processing is completed, the slot lock is released, a completion report is sent to the host processor 111, a write request is issued to the storage device 170, and data is written.
Industrial applicability
As described above, the storage control device and the control method thereof according to the present invention form a group with a plurality of storage device side processors, a shared memory, and a cache memory, and permit access to the shared memory only within the group. Storage control device capable of improving throughput of entire storage control device by simplifying control and reducing shared memory access bottleneck, and having shared memory and cache memory distributed to each group, and control thereof Suitable for building methods.

Claims (4)

A control method for a storage system having a plurality of host-side processors connected to a central processing unit and a plurality of storage units for storing data from the central processing unit,
Here, the plurality of host-side processors have a plurality of local memories, and one host-side processor has one local memory,
The plurality of storage devices are divided into a plurality of groups, and each of the plurality of groups further stores a cache memory and management information regarding the presence or absence of data stored in the cache memory. And at least one storage device side processor that controls data transfer between the storage devices belonging to the group and the cache memory allocated to the group ,
Each of said plurality of host side processor to said local memory to which the host processor has to store the correspondence between each said plurality of storage device side processor of the plurality of storage devices,
When the host-side processor receives an access request from the central processing unit, the host-side processor that has received the access request has a storage-device-side processor corresponding to the access-target storage device specified by the access request. Determine by referring to the correspondence in the local memory,
The host-side processor that has received the access request performs data transfer between the cache memory included in the group to which the determined storage-device-side processor belongs and the central processing unit that has issued the access request. A control method of a storage device system. A method for controlling a storage system according to claim 1 , comprising:
If the access request is a read request,
The host-side processor that has received the read request issues a read request together with the storage device address, data position, and read range to the determined storage device-side processor,
The storage device-side processor that has received the read request accesses the management information of the shared memory to determine whether the read target data exists on the cache,
When the read target data is present on the cache, the storage device side processor notifies the cache address and valid data length of the read target data to the host side processor that issued the read request,
The storage processor system control method, wherein the host side processor receiving the notification reads the read target data from the notified cache address and transfers the data to the central processing unit. A method for controlling a storage system according to claim 1 , comprising:
If the access request is a read request,
The host-side processor that has received the read request issues a read request together with the storage device address, data position, and read range to the determined storage device-side processor,
The storage device-side processor that has received the read request accesses the management information of the shared memory to determine whether the read target data exists on the cache,
When the read target data does not exist in the cache, the storage device side processor notifies the host side processor that issued the read request of a read miss and notifies the storage device of the group to which the storage device side processor belongs. Issue a read request,
The host-side processor that has received the notification of the read miss disconnects the connection between the storage device-side processor and the central processing unit, and the data is transferred from the storage device to the cache and reconnected from the storage-device processor that has notified the read miss. In response to the request being issued, the CPU executes reconnection processing with the central processing unit, and further reports completion of reconnection to the storage device side processor that has issued the reconnection request,
The storage-side processor that has received the reconnection completion report notifies the host-side processor that has reported the reconnection completion to the cache address and valid data length in which the data is stored,
The method of controlling a storage system, wherein the host side processor receiving the cache address and the effective data length reads data from the cache address and transfers the data to the central processing unit. A method for controlling a storage system according to claim 1 , comprising:
If the access request is a write request,
The host side processor that has received the write request issues a write request together with a storage device address, a data position, and a write range to the determined storage device side processor,
The storage device-side processor that has received the write request secures a cache area for storing write data, and notifies the host-side processor of a cache address for storing data,
The host-side processor that has received the cache address stores the write data transferred from the central processing unit at the notified cache address, and stores the write data for the storage-side processor. Send cache address and data length,
The storage device-side processor that has received the cache address and the data length writes the write data stored in the cache to the storage device included in the group to which the storage device processor belongs. Device system control method.

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