JP3915396B2 - Network quality evaluation equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a network quality evaluation apparatus that takes in a communication packet propagating on a communication network and evaluates the communication quality of the communication network based on the information, and particularly relates to a network quality evaluation apparatus that improves communication packet filtering.
[0002]
[Prior art]
Conventional network quality evaluation devices measure communication packets propagating on a communication network at each point of the communication network, evaluate the communication quality of the communication network line based on the measured communication packet, monitor traffic, etc. Is what you do.
[0003]
For example, as such a network quality evaluation apparatus, there are “Japanese Patent Application No. 11-274273” and “Japanese Patent Application No. 11-304215” related to the application of the present applicant.
[0004]
FIG. 6 is a configuration block diagram showing an example of such a conventional network quality evaluation apparatus. In FIG. 6, 1 is a physical layer circuit, 2 is a sampling control circuit, 3 is a filter circuit, 4 is a memory control circuit, 5 is a storage circuit, 6 is an external communication circuit, 7 is a data processing circuit, 100 is a communication packet signal, 101 Is a measurement data signal. 1 to 6 constitute the packet capture means 50.
[0005]
The communication packet signal 100 is input to the physical layer circuit 1, and the output of the physical layer circuit 1 is connected to the sampling control circuit 2. The output of the sampling control circuit 2 is connected to the memory control circuit 4 through the filter circuit 3, and the memory control circuit 4 is connected to the storage circuit 5.
[0006]
The output of the memory control circuit 4 is connected to the external communication circuit 6, and the measurement data signal 101 that is the output of the external communication circuit 6 is connected to the data processing circuit 7.
[0007]
Here, the operation of the conventional example shown in FIG. 6 will be described. The communication packet signal 100 propagating through the communication network is received by the physical layer circuit, and is subjected to time division capture (sampling measurement) in the sampling control circuit 2.
[0008]
In this time division capture, the communication packet signal 100 propagating through the communication network is not always captured, but is captured at regular time intervals at regular intervals. FIG. 7 is an explanatory diagram for explaining an example of such time-division capture.
[0009]
For example, when capturing for 2 minutes at intervals of 5 minutes, the communication packet signal is captured during the period indicated by “T001” in FIG. 7, and the communication packet signal is not captured during the period indicated by “T002” in FIG. Then, such a pattern is sequentially repeated.
[0010]
The communication packet signal thus time-captured is filtered by the filter circuit 3. Examples of filter processing performed by the filter circuit 3 include packet filter processing and data filter processing. The former extracts only a specific packet signal, and the latter extracts only specific information (value) in the packet signal. Is done.
[0011]
The filtered data is stored in the memory circuit 5 together with a time stamp and the like in the memory control circuit 4. Further, the memory control circuit 4 reads data stored from the storage circuit 5 as necessary and outputs it to the external communication circuit 6.
[0012]
The external communication circuit 6 that has received the data from the memory control circuit 4 transmits the data as a measurement data signal 101 to the data processing circuit 7 provided outside via the communication network.
[0013]
The data processing circuit 7 receives and analyzes the measurement data signal 101 transmitted from the packet capture means 50 and evaluates the communication quality of the communication network.
[0014]
As a result, by installing the packet capture means 50 at each point of the communication network and obtaining the measurement data signal 101 of the communication packet at that point, it is possible to evaluate the communication quality of the communication network.
[0015]
[Problems to be solved by the invention]
However, in the conventional example shown in FIG. 6, when it is intended to specify a large number of filter processing conditions, the filter circuit 3 must be arranged in parallel by the number of conditions, which increases the size of the filter circuit. There was a problem.
Therefore, the problem to be solved by the present invention is to realize a network quality evaluation apparatus capable of specifying a large number of filter processing conditions with a small-scale filter circuit.
[0016]
[Means for Solving the Problems]
In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a network quality evaluation apparatus that takes in a communication packet propagating on a communication network and evaluates the communication quality of the communication network based on the information,
A physical layer circuit that receives the communication packet; a sampling control circuit that captures the received communication packet in a time-division manner; and a filter circuit that performs filter processing by switching filter conditions in a time-division manner with respect to the output of the sampling control circuit; By providing the memory circuit and the memory control circuit for writing the output data of the filter circuit to the memory circuit, it becomes possible to designate a large number of filter processing conditions with a small-scale filter circuit.
[0018]
The invention according to claim 2
In the network quality evaluation apparatus according to claim 1 ,
The filter circuit is
First and second filter condition storage circuits in which different filter conditions are stored, and a selection circuit for selecting the first filter condition storage circuit or the second filter condition storage circuit in a time-sharing manner under the control of the sampling control circuit And a filter processing circuit that performs filter processing based on the output of the selection circuit, it is possible to specify a large number of filter processing conditions with a small-scale filter circuit.
[0019]
The invention described in claim 3
In the network quality evaluation apparatus according to claim 1 ,
The filter circuit is
A first and second filter condition storage circuit; a selection circuit that selects the first filter condition storage circuit or the second filter condition storage circuit in a time-sharing manner under the control of the sampling control circuit; and an output of the selection circuit A filter processing circuit for performing a filter process based on the second storage circuit, a second storage circuit storing a plurality of filter conditions, and reading out one of the plurality of filter conditions from the second storage circuit and selecting the selection circuit by the selection circuit By comprising the filter condition writing circuit that writes to the filter condition storage circuit that has not been performed, it becomes possible to specify a large number of filter processing conditions with a small-scale filter circuit.
[0020]
The invention according to claim 4
In the network quality evaluation apparatus which is the invention according to claim 2 or claim 3 ,
By having three or more filter condition storage circuits, a large number of filter processing conditions can be specified with a small-scale filter circuit.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a network quality evaluation apparatus according to the present invention.
[0023]
In FIG. 1, 1, 2, 4, 5, 6, 7 and 100 are assigned the same reference numerals as in FIG. 6, 8 is a filter processing circuit, 9 is a storage circuit, 10 is a filter condition writing circuit, 11 and 12 Is a filter condition storage circuit, 13 is a selection circuit, and 101a is measurement data.
[0024]
1, 2 and 4-13 constitute a packet capture means 51, and 8 and 10-13 constitute a filter circuit 52, respectively.
[0025]
The communication packet signal 100 is input to the physical layer circuit 1, and the output of the physical layer circuit 1 is connected to the sampling control circuit 2. The output of the sampling control circuit 2 is connected to the memory control circuit 4 via the filter process 8, and the memory control circuit 4 is connected to the storage circuit 5.
[0026]
The output of the memory control circuit 4 is connected to the external communication circuit 6, and the measurement data signal 101 a that is the output of the external communication circuit 6 is connected to the data processing circuit 7.
[0027]
The output of the storage circuit 9 storing various filter conditions is connected to the input terminal of the filter condition writing circuit 10, and one output terminal of the filter condition writing circuit 10 is connected to the input terminal of the filter condition storage circuit 11. The other output terminal is connected to the input terminal of the filter condition storage circuit 12.
[0028]
The output terminals of the filter condition storage circuits 11 and 12 are connected to two input terminals of the selection circuit 13, respectively, and the output of the selection circuit 13 is connected to the filter processing circuit 8. The control signal of the sampling control circuit 2 is connected to the filter condition writing circuit 10 and the control input terminal of the selection circuit 13, respectively.
[0029]
Here, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a timing chart for explaining the operation of the embodiment. For example, consider a case in which capture is performed for 5 minutes at intervals of 10 minutes, and the four filter conditions “A”, “B”, “C”, and “D” are switched in a time division manner. However, the description of the same operation as the conventional example is omitted.
[0030]
2, (a) is the timing of time-division capture, (b) is the operation of the filter condition writing circuit 10, (c) is the content of the filter condition storage circuit 11, (d) is the content of the filter condition storage circuit 12, (E) is the operation of the selection circuit 13, and (f) is the filter condition used by the filter processing circuit 8.
[0031]
The filter conditions “A” to “D” are stored in advance in the storage circuit 9, and the selection circuit 13 selects the filter condition storage circuit 11 at the capture timing indicated by “T101” in FIG. Filter processing is performed on the communication packet signal captured based on the filter condition selected by the selection circuit 13.
[0032]
For example, since the filter condition “A” is written in the filter condition storage circuit 11 at the timing indicated by “T101” in FIG. 2, the filter processing circuit 8 performs the filter process according to the filter condition “A”.
[0033]
At the same time, the filter condition writing circuit 10 writes the filter conditions stored in the storage circuit 9 to the filter condition storage circuit 12 at the capture timing indicated by “T101” in FIG.
[0034]
For example, the filter condition writing circuit 10 selects the filter condition storage circuit 12 and reads the filter condition “B” from the storage circuit 9 and writes it to the filter condition storage circuit 12. For this reason, the contents stored in the filter condition storage circuit 12 are rewritten to the filter condition “B”.
[0035]
The selection circuit 13 selects the filter condition storage circuit 12 at the capture timing indicated by “T102” in FIG. 2, and the filter processing circuit 8 applies the communication packet signal captured based on the filter condition selected by the selection circuit 13. Perform filtering.
[0036]
For example, since the filter condition “B” is written in the filter condition storage circuit 12 at the timing indicated by “T102” in FIG. 2, the filter processing circuit 8 performs the filter process according to the filter condition “B”.
[0037]
At the same time, the filter condition writing circuit 10 writes the filter conditions stored in the storage circuit 9 to the filter condition storage circuit 11 at the capture timing indicated by “T102” in FIG.
[0038]
For example, the filter condition writing circuit 10 selects the filter condition storage circuit 11, reads the filter condition “C” from the storage circuit 9, and writes it in the filter condition storage circuit 11. Therefore, the contents stored in the filter condition storage circuit 11 are rewritten to the filter condition “C”.
[0039]
The selection circuit 13 selects the filter condition storage circuit 11 at the capture timing indicated by “T103” in FIG. 2, and the filter processing circuit 8 applies the communication packet signal captured based on the filter condition selected by the selection circuit 13. Perform filtering.
[0040]
For example, since the filter condition “C” is written in the filter condition storage circuit 11 at the timing indicated by “T103” in FIG. 2, the filter processing circuit 8 performs the filter process according to the filter condition “C”.
[0041]
At the same time, the filter condition writing circuit 10 writes the filter conditions stored in the storage circuit 9 to the filter condition storage circuit 12 at the capture timing indicated by “T103” in FIG.
[0042]
For example, the filter condition writing circuit 10 selects the filter condition storage circuit 12 and reads the filter condition “D” from the storage circuit 9 and writes it to the filter condition storage circuit 12. For this reason, the contents stored in the filter condition storage circuit 12 are rewritten to the filter condition “D”.
[0043]
The selection circuit 13 selects the filter condition storage circuit 12 at the capture timing indicated by “T104” in FIG. 2, and the filter processing circuit 8 applies the communication packet signal captured based on the filter condition selected by the selection circuit 13. Perform filtering.
[0044]
For example, since the filter condition “D” is written in the filter condition storage circuit 12 at the timing indicated by “T104” in FIG. 2, the filter processing circuit 8 performs the filter process according to the filter condition “D”.
[0045]
At the same time, the filter condition writing circuit 10 writes the filter conditions stored in the storage circuit 9 to the filter condition storage circuit 11 at the capture timing indicated by “T104” in FIG.
[0046]
For example, the filter condition writing circuit 10 selects the filter condition storage circuit 11, reads the filter condition “A” from the storage circuit 9, and writes it in the filter condition storage circuit 11. Therefore, the content stored in the filter condition storage circuit 11 is rewritten to the filter condition “A”.
[0047]
By sequentially performing such time division capture, the filter condition changes in time division as shown in FIG.
[0048]
As a result, the filter condition stored in the storage circuit 9 is written to one filter condition storage circuit, and the filter condition stored in the other filter condition storage circuit is selected and processed by the filter processing circuit 8 alternately. By performing the above, it is possible to change the filter processing conditions in a time-sharing manner at each capture timing.
[0049]
In the embodiment shown in FIGS. 1 and 2, four filter conditions “A” to “D” are illustrated for simplicity of explanation, but of course, there is no limitation on the number of filter conditions.
[0050]
Further, if the number of filter conditions and the number of filter condition storage circuits are the same, the storage circuit 9 and the filter condition writing circuit 10 are unnecessary.
[0051]
In the embodiment shown in FIG. 1, for the sake of simplicity of explanation, the processing is performed by the filter processing circuit 8 after processing by the sampling control circuit 2, but the processing by the sampling control circuit 2 is performed after processing by the filter processing circuit 8. It may be configured to do.
[0052]
In the description of the embodiment shown in FIG. 1, the external communication circuit 6 is provided to communicate with the external data processing circuit 7. However, when the internal data processing circuit is provided, the external communication circuit 7 is not necessary. In addition, when the data is stored in the storage circuit 5 and carried, the internal data processing circuit itself becomes unnecessary.
[0053]
In the embodiment shown in FIGS. 1 and 2, the four filter conditions “A” to “D” are sequentially switched in a time-division manner for the sake of simplicity, but the order of the filter conditions can be arbitrarily set. .
[0054]
In the embodiment shown in FIGS. 1 and 2, different filter conditions are used for each capture timing for simplicity of explanation, but the same filter conditions may be used over two or more capture timings.
[0055]
Further, in the embodiment shown in FIG. 1, when a plurality of filter conditions are stored for each packet capture means 51 by storing a storage circuit 9 and 1, 2, 8 to 13 are integrated as filter processing ICs, If the memory circuit 9 is provided inside the filter processing IC, the cost of the IC increases. For this reason, the filter condition may be written from an external storage circuit.
[0056]
FIG. 3 is a block diagram showing the configuration of an embodiment of such a network quality evaluation apparatus. In FIG. 3, 1, 2, 8, 10, 11, 12, 13 and 100 are assigned the same reference numerals as in FIG. 1, 14 is an external storage circuit, 15 is a control circuit such as a CPU, and 16 is in a filter IC. It is the interface circuit provided in.
[0057]
1, 2, 8, 10-13 and 16 constitute an IC filter processing IC53.
[0058]
The connection relationship is almost the same as that of the embodiment shown in FIG. 1, except that the interface circuit 16 is connected to the input terminal of the filter condition writing circuit 10, and the interface circuit 16 is connected to the storage circuit 14 and the control via a bus or the like. This is a point connected to the circuit 15.
[0059]
Here, the operation of the embodiment shown in FIG. 3 will be described. However, description of operations similar to those in the embodiment shown in FIG. 1 is omitted.
[0060]
The control circuit 15 reads out the filter condition stored in the storage circuit 14 and supplies it to the filter condition writing circuit 10 via the interface circuit 16. Then, the filter condition writing circuit 10 writes the filter condition in the filter condition storage circuit based on the capture timing.
[0061]
In this case, since it is not necessary to provide a storage circuit inside the filter processing IC 53, the cost can be reduced even when the filter processing portion is integrated into an IC.
[0062]
Further, in the embodiment shown in FIG. 1, the two filter condition storage circuits 11 and 12 are illustrated, but of course, three or more filter condition storage circuits may be provided.
[0063]
FIG. 4 is a configuration block diagram showing an embodiment of a network quality evaluation apparatus having such a plurality of filter condition storage circuits. 4, 8 and 9 are given the same reference numerals as in FIG. 1, 10a is a filter condition writing circuit, 13a is a selection circuit, and 17a, 17b and 17c are n filter condition storage circuits. In addition, 8, 10a, 13a, and 17a to 17c constitute a filter circuit 52a.
[0064]
The connection relationship is almost the same as that of the embodiment shown in FIG. 1 except that the n output terminals of the filter condition writing circuit 10a are connected to the input terminals of the filter condition storage circuits 17a, 17b and 17c. The output terminals of the condition storage circuits 17a to 17c are connected to the n input terminals of the selection circuit 13a.
[0065]
In the embodiment shown in FIG. 1, the filter circuit 52 is used. However, a plurality of filter circuits may be provided in parallel. FIG. 5 is a configuration block diagram showing an embodiment of a network quality evaluation apparatus having a plurality of such filter circuits.
[0066]
In FIG. 5, 1, 2, 4, 5, 6, 7 and 100 are assigned the same reference numerals as in FIG. 1, 18a, 18b and 18c are n filter circuits, and 101b is a measurement data signal. 1, 2, 4, 5, 6, 7 and 18a to 18c constitute a packet capture means 54.
[0067]
The connection relationship is almost the same as that of the embodiment shown in FIG. 1, and the difference is that filter circuits 18a, 18b and 18c are connected in parallel instead of the filter circuit 52. However, the description of the memory circuit 9 is omitted.
[0068]
【The invention's effect】
As is apparent from the above description, the present invention has the following effects.
According to the first to fourth aspects of the present invention, the filter condition stored in the storage circuit is written into one filter condition storage circuit, and the filter condition stored in the other filter condition storage circuit is selected to filter Filter processing with a small-scale filter circuit by alternately performing processing with the processing circuit, or by alternately selecting filter conditions stored in the filter condition storage circuit and processing with the filter processing circuit It is possible to specify a number of conditions.
[Brief description of the drawings]
FIG. 1 is a configuration block diagram showing an embodiment of a network quality evaluation apparatus according to the present invention.
FIG. 2 is a timing chart for explaining the operation of the embodiment.
FIG. 3 is a configuration block diagram showing an embodiment of a network quality evaluation apparatus.
FIG. 4 is a configuration block diagram showing an embodiment of a network quality evaluation apparatus having a plurality of filter condition storage circuits.
FIG. 5 is a configuration block diagram showing an embodiment of a network quality evaluation apparatus having a plurality of filter circuits.
FIG. 6 is a configuration block diagram showing an example of a conventional network quality evaluation apparatus.
FIG. 7 is an explanatory diagram illustrating an example of time-division capture.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Physical layer circuit 2 Sampling control circuit 3, 18a, 18b, 18c Filter circuit 4 Memory control circuit 5, 9, 14 Storage circuit 6 External communication circuit 7 Data processing circuit 8 Filter processing circuit 10, 10a Filter condition writing circuit 11, 12, 17a, 17b, 17c Filter condition storage circuit 13, 13a Selection circuit 15 Control circuit 16 Interface circuit 50, 51, 54 Packet capture means 52, 52a Filter circuit 53 Filter processing IC
100 Communication packet signal 101, 101a, 101b Measurement data signal

Claims (4)

In a network quality evaluation apparatus that takes in a communication packet propagating on a communication network and evaluates the communication quality of the communication network based on the information,
A physical layer circuit for receiving the communication packet;
A sampling control circuit that captures the received communication packet in a time-sharing manner;
A filter circuit that performs filter processing by switching filter conditions in time division with respect to the output of the sampling control circuit;
A memory circuit;
A network quality evaluation apparatus comprising: a memory control circuit for writing output data of the filter circuit to the storage circuit. The filter circuit is
First and second filter condition storage circuits in which different filter conditions are stored;
A selection circuit that selects the first filter condition storage circuit or the second filter condition storage circuit in a time-sharing manner under the control of the sampling control circuit;
And a filter processing circuit that performs filter processing based on the output of the selection circuit.
The network quality evaluation apparatus according to claim 1. The filter circuit is
First and second filter condition storage circuits;
A selection circuit that selects the first filter condition storage circuit or the second filter condition storage circuit in a time-sharing manner under the control of the sampling control circuit;
A filter processing circuit for performing filter processing based on the output of the selection circuit;
A second memory circuit storing a plurality of filter conditions;
And a filter condition writing circuit that reads out one of the plurality of filter conditions from the second storage circuit and writes it into the filter condition storage circuit that is not selected by the selection circuit.
The network quality evaluation apparatus according to claim 1. Having three or more filter condition storage circuits
The network quality evaluation apparatus according to claim 2 or claim 3.

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