JP3909086B2 - Electronic equipment - Google Patents

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JP3909086B2
JP3909086B2 JP52744596A JP52744596A JP3909086B2 JP 3909086 B2 JP3909086 B2 JP 3909086B2 JP 52744596 A JP52744596 A JP 52744596A JP 52744596 A JP52744596 A JP 52744596A JP 3909086 B2 JP3909086 B2 JP 3909086B2
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film
conductive film
pad
resistor
power supply
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豊 秋庭
和彦 堀越
利行 荒井
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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Description

技術分野
本発明は、特にＩＣ、ＬＳＩ素子や回路の高速化、高密度化で増々重要となるＥＭＣ対応の電子機器に係り、不要輻射ノイズの抑制手段を必要とするデバイス、回路基板、及び電子装置に関する。
背景技術
不要輻射を抑制するため、通常ノイズ発生源のもとになっているＬＳＩデバイス等の電源端子（パッド）とグランド端子（パッド）との間に周波数特性の良いバイパスコンデンサが挿入されている。ＬＳＩの外部にコンデンサを接続する場合、バイパスコンデンサの容量を十分に大きくしても、半導体チップからパッケージリードまでの電流ループが大きいため不要輻射が多く、対策上一定の限界がある。これに対し、特開平５−２６７５５７号公報は、ＬＳＩの内部にバイパスコンデンサを内臓し電流ループの長さ（面積）を減少させる方法をとっている。しかし、電流ループに流れる共振電流により電源パッドとグランドパッドとの間に電位変動が発生するため、パッドに接続された配線からの輻射を取り除くことができない。電位変動を抑制、吸収する手段が必要とされる。
本発明は、ＬＳＩ素子等のスイッチング時におけるグランドパッドに対する電源パッドの電位変動（交流成分）をＥＭＩ対策部品を用いずにジュール熱に変換し、高密度実装を実現すると共に不要輻射を効果的に抑制する低ＥＭＩデバイスの提供を目的とする。
発明の開示
本発明は、ＬＳＩデバイス（素子）の活性面上に形成したバイパスコンデンサと抵抗を等価的に並列接続して、高密度実装を実現すると共にバイパスコンデンサのＱ値を低下させることより、ＬＳＩデバイスの電源パッドとグランドパッドの間に発生する電位変動を熱変換、吸収して不要輻射を抑制する。
ＬＳＩデバイスの表面上で、電源パッドとグランドパッドに接続した第１のバイパスコンデンサＣｌに対して、第２のバイパスコンデンサＣ２と抵抗Ｒを直列に接続した回路を並列に接続させることにより、電源パッドとグランドパッドとの間から見た回路のＱに対して、直流分カットと同時に交流成分に対する低Ｑ化（１０以下の値）を得ている。
第２のバイパスコンデンサＣ２と抵抗Ｒを直列に接続した回路を、必要とする周波数領域（ω１≦ω≦ω２）に対して、第２のバイパスコンデンサのインピーダンス│Ｚ c2│（＝１／ωＣ２）を抵抗Ｒに比べて十分に小さくして等価的に抵抗Ｒで与える。この時、電源パッドとグランドパッドとの間から見た回路のＱは、第１のバイパスコンデンサＣｌと抵抗Ｒを並列に接続した等価回路のＱ（＝ωＣｌＲ）で与えられる。この時、回路的に直流バイアス成分をカットしながら交流成分（高周波成分）に対する低Ｑ化を得ている。回路のＱを１０以下にすることにより、電源パッドとグランドパッドとの間に発生する電位変動（交流成分）を効果的に吸収できる。
一方、誘電体にｔａｎ（δ）の大きい材料を用いたバイパスコンデンサ単体の場合、或は回路的にバイパスコンデンサと抵抗とを直接並列接続した場合、低Ｑ化において直流電圧印加に対するリーク電流等の問題が発生する。本発明は、第２のバイパスコンデンサＣ２により、この問題を解決している。
【図面の簡単な説明】
第１図は、本発明の一実施例であり、ＬＳＩデバイス（チップ）の表面上に回路を形成した低ＥＭＩデバイスの断面図を示す。第２図は、第１図の低ＥＭＩデバイスを活性面上から見た平面図を示す。第３図は、ＬＳＩデバイス（チップ）の表面上に形成した回路モデル図を示す。
第４図は、第３図の回路モデルで制約条件を設けた場合の回路モデル図を示す。第５図は、本発明の一実施例であり、低ＥＭＩデバイスの製造プロセス工程図を示し、（ａ）、（ｂ）は各々各工程での断面図、平面図を示す。第６図は、本発明の他の一実施例であり、低ＥＭＩデバイスの製造プロセス工程図を示し、（ａ）、（ｂ）は各々各工程での断面図、平面図を示す。
第７図は、本発明の他の一実施例であり、低ＥＭＩデバイスの製造プロセス工程図を示し、（ａ）、（ｂ）は各々各工程での断面図、平面図を示す。
第８図は、本発明の他の一実施例であり、低ＥＭＩデバイスの製造プロセス工程図を示し、（ａ）、（ｂ）は各々各工程での断面図、平面図を示す。
第９図は、本発明の他の一実施例であり、低ＥＭＩデバイスの製造プロセス工程図を示し、（ａ）、（ｂ）は各々各工程での断面図、平面図を示す。
第１０図は、本発明の他の一実施例であり、低ＥＭＩデバイスの製造プロセス工程図を示し、（ａ）、（ｂ）は各々各工程での断面図、平面図を示す。
第１１図は、本発明の他の一実施例であり、低ＥＭＩデバイスの製造プロセス工程図を示し、（ａ）、（ｂ）は各々各工程での断面図、平面図を示す。
発明を実施するための最良の形態
以下、本発明の実施例を説明する。
第１図は、本発明の一実施例であり、ＬＳＩデバイス（チップ）の表面上にバイパスコンデンサと抵抗で回路を形成した低ＥＭＩデバイス１の断面図を示す。第２図は、第１図に示した低ＥＭＩデバイス１を上部から見た平面図を示す。
第１図において、ＬＳＩチップ２は最表面が酸化シリコンのパッシベーション膜により覆われ、周囲に外部回路と接続するためのグランドパッド１１、電源パッド１２（図示せず）、及び信号パッド１３（図示せず）等の電極端子をもつ。低ＥＭＩデバイス１は、電極端子を形成したＬＳＩチップ２の面上に、第１の絶縁膜３、第１の導体膜４、第１の誘電体膜５、抵抗体膜６、第２の導体膜７、第２の誘電体膜８、第３の導体膜９、第２の絶縁膜１０を形成した回路構造をもつ。特に、電極端子の内側に回路を形成することによりＬＳＩチップ２の外形形状、面積に影響を与えていない。
第１のバイパスコンデンサＣｌは第１の誘電体膜５を第１の導体膜４と第２の導体膜７とで挾み込んで形成され、第２のバイパスコンデンサＣ２は第２の誘電体膜８を第２の導体膜７と第３の導体膜９とで挾み込んで形成されている。抵抗Ｒは、抵抗体膜６を第１の導体膜４と第３の導体膜９とで挾み込みにより形成される。
第２図に示すように、第１の導体膜４、第２の導体膜７のリードパターン１４、１５は、各々ＬＳＩチップ２のグランドパッド１１、電源パッド１２に対して最短距離で取り出し、かつ複数の箇所で接続されている。バイパスコンデンサの取付け時に形成される電流ループ長さ、面積、及びインダクタンス成分を大幅に減少させて共振等による電位変動を抑制している。
第３図は、ＬＳＩチップ２の表面上に形成した回路のモデルを示す。ＬＳＩチップ２のグランドパッド１１と電源パッド１２から見ると、第１のバイパスコンデンサＣｌ １７に第２のバイパスコンデンサＣ２ １８と抵抗Ｒ１９とを直列に接続した回路を並列に接続した回路となる。
第４図は、第３図の回路モデルに制約条件を設けた場合の回路モデルを示す。第３図において、第２のバイパスコンデンサＣ２ １８のインピーダンス│Ｚ c2│（＝１／ωＣ２）を抵抗Ｒ１９に比べて十分に小さくし、第１のバイパスコンデンサＣｌ １７と抵抗Ｒ１９の並列接続で与えている。この回路は、第２のバイパスコンデンサＣ２ １８による直流成分カットと同時に交流成分に対する低Ｑ（＝ωＣｌＲ）化を得ている。
第５図から第１１図に、低ＥＭＩデバイス１の製造プロセス工程図を示す。図中の（ａ）、（ｂ）は、各々断面図、平面図を示す。
第５図は、ＬＳＩチップ２の面上に形成した第１の絶縁膜３の工程図を示す。パッシベーション膜としてＬＳＩチップ２の全面にＣＶＤ法を用いて厚さ１μｍの酸化シリコンを成膜する。次に、フォトプロセス及びドライエッチング法を用いて、ＬＳＩチップ２のグランドパッド１１等の電極パッドを除いた領域に第１の絶縁膜３を形成する。ＬＳＩチップ２の面上に形成される薄膜の歪がＬＳＩ活性面に及ぼす影響を吸収、緩和するために、パッシベーション膜を多層構造にする場合もある。
第６図は、第１の絶縁膜３の後に形成した第１の導体膜４の工程図を示す。第１の絶縁膜３の形成後、第１のバイパスコンデンサＣｌ １７の電極層として、ＬＳＩチップ２の全面にスパッタ法を用いて厚さ５００ｎｍの白金薄膜を形成する。これを、フォトプロセス及び反応性ドライエッチング法により、グランドパッド１１と接続されるリードパターン１４及びＬＳＩチップ２の中央パッシベーション膜上の部分からなる第１の導体膜４を残して除去する。
第７図は、第１の導体膜４の後に形成した抵抗体膜６の工程図を示す。第１の導体膜４の形成後、クロムと酸化シリコンとのサーメット抵抗材料を用い、抵抗薄膜としてスパッタ法により９００ｎｍの厚さでＬＳＩチップ２の全面に成膜する。これをフォトプロセス及びウェットエッチング法により、ＬＳＩチップ２の４辺に沿った矩形形状に抵抗薄膜を加工し抵抗体膜６を形成する。抵抗体膜６の形状は矩形形状に限らないが、近接するグランドパッド１１と電源パッド１２から見込んだバイパスコンデンサの電気特性を等しくするため対称形をとっている。
第８図は、抵抗体膜６の後に形成した第１の誘電体膜５の工程図を示す。
抵抗体膜６の形成後、ＬＳＩチップ２の全面にスパッタ法を用いて厚さ２００ｎｍの酸化タンタル膜を成膜する。これを、フォトプロセス及びウエットエッチング法により、第１の導体膜４の上に抵抗体膜６及びグランドパッド１１の領域を除いて第１の誘電体膜５を形成する。この場合、ＬＳＩチップ２のグランドパッド１１等の電極パッドに隣接する４辺において、第１の誘電体膜５が第１の導体膜４を覆うように形成する。第１の誘電体膜５の厚さは、耐圧や容量値を考慮して設定される。５０ｎｍ工程を２〜４回繰り返す場合もある。誘電体材料として、比誘電率を上げるためチタン酸バリウムＢａＴｉＯ３やチタン酸ストロンチウムＳｒＴｉＯ３を用いる場合もある。プロセスとして、組成制御、特性再現を考慮し、スパッタ法に代わりスピンコート法を用いる。
第９図は、第１の誘電体膜５の後に形成した第２の導体膜７の工程図を示す。第１の誘電体膜５の形成後、ＬＳＩチップ２の全面にスパッタ法を用いて厚さ５００ｎｍの白金簿膜を成膜する。これを、フォトプロセス及びドライエッチング法により、第１のバイパスコンデンサＣｌ １７と第２のバイパスコンデンサＣ２ １８の電極層として、第１の誘電体膜５の上に第２の導体膜７を形成する。この場合、第２の導体膜７は電源パッド１２との接続を取るリードパターン１５を有する。電源の種類が複数ある場合は、電源パッド１２の配置条件を考慮し、第１のバイパスコンデンサＣｌ １７を平面的に分割して複数個形成する。第１の導体膜４を共通グランド電極とし、第２の導体膜７により、複数の電源電極を形成する。
第１０図は、第２の導体膜７の後に形成した第２の誘電体膜８の工程図を示す。第２の導体膜７を形成後、ＬＳＩチップ２の全面にスパッタ法を用いて厚さ２００ｎｍの酸化タンタル薄膜を成膜する。成膜工程として、５０ｎｍ工程を２〜４回繰り返す場合もある。これを、フォトプロセス及びウエットエッチング法により、抵抗体膜６の一部やＬＳＩチップ２のグランドパッド１１等の電極パッドの上面を除去する。更に、第２の誘電体膜８は、第１の導体膜４と第２の導体膜７を覆うように形成される。抵抗体膜６の面上に設けられた第２の誘電体膜８の開口部１６は、その形状により抵抗Ｒ１９の値を制御する手段の一つとしている。誘電体材料として、比誘電率を上げるためチタン酸バリウムＢａＴｉＯ３やチタン酸ストロンチウムＳｒＴｉＯ３を用いる場合もある。
第１１図は、第２の誘電体膜８の後に形成した第３の導体膜９の工程図を示す。第２の誘電体膜８を形成後、ＬＳＩチップ２の全面にスパッタ法を用いて厚さ５００ｎｍの白金薄膜を成膜する。これを、フォトプロセス及びドライエッチング法により、第２のバイパスコンデンサＣ２ １８と抵抗Ｒ１９の電極層として、第２の誘電体膜８と抵抗体膜６の上に形成する。この場合、ＬＳＩチップ２のグランドパッド１１等の電極パッドに隣接する４辺において、第３の導体膜９が第２の誘電体膜８の外にはみ出さないように形成する。
最後は、第１図に示すように第３の導体膜９を形成後、パッシベーション膜としての第２の絶縁膜１０を形成する。ＬＳＩチップ２の全面にＣＶＤ法を用いて厚さ１μｍの酸化シリコンを成膜する。これを、フォトプロセス及びドライエッチング法により、ＬＳＩチップ２のグランドパッド１１等の電極パッドを除いた領域に形成する。耐湿性を向上させるため、パッシベーション膜を２層にする場合もある。
産業上の利用可能性
本発明は、ＬＳＩデバイスの表面上で、電源パッドとグランドパッドに接続した第１のバイパスコンデンサＣｌに対して、第２のバイパスコンデンサＣ２と抵抗Ｒを直列に接続した回路を並列に接続させ、第２のバイパスコンデンサＣ２のインピーダンスを抵抗Ｒに対して十分に小さくした。これにより、電源パッドとグランドパッドとの間から見たバイパスコンデンサ回路のＱを直流成分をカットさせると同時に交流成分（高周波成分）に対して低Ｑ化（１０以下の値）し、パッド間に発生する電位変動を吸収しＬＳＩデバイス自身及びこれに接続された配線からの電磁放射を大幅に抑制する効果がある。TECHNICAL FIELD The present invention relates to an EMC-compatible electronic device that is becoming increasingly important for increasing the speed and density of ICs, LSI elements and circuits, in particular, a device, a circuit board, and an electronic device that require a means for suppressing unwanted radiation noise. Relates to the device.
Background Technology A bypass capacitor with good frequency characteristics is inserted between a power supply terminal (pad) and a ground terminal (pad) of an LSI device or the like, which is usually a source of noise, in order to suppress unnecessary radiation. . When a capacitor is connected outside the LSI, even if the capacity of the bypass capacitor is sufficiently large, there is a large amount of unnecessary radiation due to the large current loop from the semiconductor chip to the package lead, and there is a certain limit for countermeasures. On the other hand, Japanese Patent Laid-Open No. 5-267557 employs a method of reducing the length (area) of the current loop by incorporating a bypass capacitor in the LSI. However, since the potential fluctuation occurs between the power supply pad and the ground pad due to the resonance current flowing in the current loop, radiation from the wiring connected to the pad cannot be removed. A means for suppressing and absorbing potential fluctuations is required.
The present invention converts the potential fluctuation (alternating current component) of the power supply pad with respect to the ground pad at the time of switching of an LSI element or the like into Joule heat without using an EMI countermeasure component, thereby realizing high-density mounting and effectively eliminating unnecessary radiation. An object is to provide a low EMI device to be suppressed.
DISCLOSURE OF THE INVENTION The present invention is equivalent to parallelly connecting a bypass capacitor and a resistor formed on the active surface of an LSI device (element) to achieve high-density mounting and lowering the Q value of the bypass capacitor. Unwanted radiation is suppressed by thermally converting and absorbing potential fluctuations generated between the power supply pad and the ground pad of the LSI device.
By connecting a circuit in which a second bypass capacitor C2 and a resistor R are connected in series to a first bypass capacitor Cl connected to the power supply pad and the ground pad on the surface of the LSI device, the power supply pad is connected. With respect to the Q of the circuit viewed from between the ground and the ground pad, a low Q (value of 10 or less) for the AC component is obtained simultaneously with the DC component cut.
A circuit in which the second bypass capacitor C2 and the resistor R are connected in series has an impedance | Z c2 | (= 1 / ωC2) of the second bypass capacitor with respect to a necessary frequency region (ω1 ≦ ω ≦ ω2). Is made sufficiently smaller than the resistance R and equivalently given by the resistance R. At this time, Q of the circuit viewed from between the power supply pad and the ground pad is given by Q (= ωClR) of an equivalent circuit in which the first bypass capacitor Cl and the resistor R are connected in parallel. At this time, a low Q for the AC component (high frequency component) is obtained while cutting the DC bias component in a circuit. By setting the Q of the circuit to 10 or less, potential fluctuation (alternating current component) generated between the power supply pad and the ground pad can be effectively absorbed.
On the other hand, in the case of a single bypass capacitor using a material with a large tan (δ) for the dielectric, or when the bypass capacitor and the resistor are directly connected in parallel in a circuit, the leakage current with respect to DC voltage application at low Q A problem occurs. The present invention solves this problem by the second bypass capacitor C2.
[Brief description of the drawings]
FIG. 1 shows an embodiment of the present invention, and shows a cross-sectional view of a low EMI device in which a circuit is formed on the surface of an LSI device (chip). FIG. 2 shows a plan view of the low EMI device of FIG. 1 as viewed from above the active surface. FIG. 3 shows a circuit model diagram formed on the surface of an LSI device (chip).
FIG. 4 shows a circuit model diagram when a constraint condition is provided in the circuit model of FIG. FIG. 5 shows an embodiment of the present invention and shows manufacturing process steps of a low EMI device. FIGS. 5A and 5B are cross-sectional views and plan views of the respective steps, respectively. FIG. 6 shows another embodiment of the present invention, and shows a manufacturing process step diagram of a low EMI device, and (a) and (b) show a sectional view and a plan view in each step, respectively.
FIG. 7 shows another embodiment of the present invention, and shows manufacturing process steps of a low EMI device, and (a) and (b) show cross-sectional views and plan views in the respective steps.
FIG. 8 shows another embodiment of the present invention and shows a manufacturing process diagram of a low EMI device, wherein (a) and (b) show a sectional view and a plan view in each step, respectively.
FIG. 9 shows another embodiment of the present invention, and shows manufacturing process steps of a low EMI device, and (a) and (b) show cross-sectional views and plan views in the respective steps.
FIG. 10 shows another embodiment of the present invention and shows a manufacturing process step diagram of a low EMI device, and (a) and (b) show a sectional view and a plan view in each step, respectively.
FIG. 11 shows another embodiment of the present invention, and shows manufacturing process steps of a low EMI device, and (a) and (b) show a cross-sectional view and a plan view in each step, respectively.
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
FIG. 1 is a cross-sectional view of a low EMI device 1 according to an embodiment of the present invention, in which a circuit is formed by a bypass capacitor and a resistor on the surface of an LSI device (chip). FIG. 2 shows a plan view of the low EMI device 1 shown in FIG. 1 as viewed from above.
In FIG. 1, the LSI chip 2 is covered with a silicon oxide passivation film on the outermost surface, and a ground pad 11, a power pad 12 (not shown) and a signal pad 13 (not shown) are connected to an external circuit. Z). The low EMI device 1 includes a first insulating film 3, a first conductor film 4, a first dielectric film 5, a resistor film 6, and a second conductor on the surface of the LSI chip 2 on which electrode terminals are formed. It has a circuit structure in which a film 7, a second dielectric film 8, a third conductor film 9, and a second insulating film 10 are formed. In particular, the external shape and area of the LSI chip 2 are not affected by forming a circuit inside the electrode terminals.
The first bypass capacitor Cl is formed by sandwiching the first dielectric film 5 with the first conductor film 4 and the second conductor film 7, and the second bypass capacitor C2 is formed with the second dielectric film. 8 is sandwiched between the second conductor film 7 and the third conductor film 9. The resistor R is formed by squeezing the resistor film 6 between the first conductor film 4 and the third conductor film 9.
As shown in FIG. 2, the lead patterns 14 and 15 of the first conductor film 4 and the second conductor film 7 are respectively taken out at the shortest distance from the ground pad 11 and the power supply pad 12 of the LSI chip 2, and Connected at multiple locations. The current loop length, area, and inductance component formed when the bypass capacitor is attached are greatly reduced to suppress potential fluctuations due to resonance and the like.
FIG. 3 shows a model of a circuit formed on the surface of the LSI chip 2. When viewed from the ground pad 11 and the power supply pad 12 of the LSI chip 2, a circuit in which a second bypass capacitor C2 18 and a resistor R19 are connected in series to the first bypass capacitor Cl 17 is connected in parallel.
FIG. 4 shows a circuit model when a constraint condition is provided in the circuit model of FIG. In FIG. 3, the impedance | Z c2 | (= 1 / ωC2) of the second bypass capacitor C2 18 is made sufficiently smaller than the resistor R19, and is given by the parallel connection of the first bypass capacitor Cl 17 and the resistor R19. ing. This circuit obtains a low Q (= ωClR) for the AC component simultaneously with the DC component cut by the second bypass capacitor C218.
5 to 11 show manufacturing process steps of the low EMI device 1. (A), (b) in a figure shows sectional drawing and a top view, respectively.
FIG. 5 shows a process chart of the first insulating film 3 formed on the surface of the LSI chip 2. As a passivation film, a silicon oxide film having a thickness of 1 μm is formed on the entire surface of the LSI chip 2 using the CVD method. Next, the first insulating film 3 is formed in a region excluding electrode pads such as the ground pad 11 of the LSI chip 2 using a photo process and a dry etching method. In order to absorb and alleviate the influence of the distortion of the thin film formed on the surface of the LSI chip 2 on the LSI active surface, the passivation film may have a multilayer structure.
FIG. 6 shows a process diagram of the first conductor film 4 formed after the first insulating film 3. After the formation of the first insulating film 3, a platinum thin film having a thickness of 500 nm is formed on the entire surface of the LSI chip 2 as an electrode layer of the first bypass capacitor Cl17 by sputtering. This is removed by a photo process and a reactive dry etching method, leaving the lead pattern 14 connected to the ground pad 11 and the first conductor film 4 composed of the portion on the central passivation film of the LSI chip 2.
FIG. 7 shows a process chart of the resistor film 6 formed after the first conductor film 4. After the formation of the first conductor film 4, a cermet resistance material of chromium and silicon oxide is used, and a resistance thin film is formed on the entire surface of the LSI chip 2 with a thickness of 900 nm by sputtering. This is processed into a rectangular shape along the four sides of the LSI chip 2 by a photo process and a wet etching method to form a resistor film 6. The shape of the resistor film 6 is not limited to a rectangular shape, but has a symmetrical shape in order to equalize the electrical characteristics of the bypass capacitor as viewed from the adjacent ground pad 11 and power supply pad 12.
FIG. 8 shows a process diagram of the first dielectric film 5 formed after the resistor film 6.
After the resistor film 6 is formed, a tantalum oxide film having a thickness of 200 nm is formed on the entire surface of the LSI chip 2 by sputtering. The first dielectric film 5 is formed on the first conductor film 4 except for the regions of the resistor film 6 and the ground pad 11 by a photo process and a wet etching method. In this case, the first dielectric film 5 is formed so as to cover the first conductor film 4 on four sides adjacent to the electrode pads such as the ground pad 11 of the LSI chip 2. The thickness of the first dielectric film 5 is set in consideration of the withstand voltage and the capacitance value. The 50 nm process may be repeated 2-4 times. As the dielectric material, barium titanate BaTiO3 or strontium titanate SrTiO3 may be used to increase the relative dielectric constant. In consideration of composition control and characteristic reproduction, a spin coating method is used instead of the sputtering method.
FIG. 9 is a process diagram of the second conductor film 7 formed after the first dielectric film 5. After the formation of the first dielectric film 5, a platinum book film having a thickness of 500 nm is formed on the entire surface of the LSI chip 2 by sputtering. The second conductor film 7 is formed on the first dielectric film 5 as an electrode layer of the first bypass capacitor Cl 17 and the second bypass capacitor C2 18 by using a photo process and a dry etching method. . In this case, the second conductor film 7 has a lead pattern 15 for connecting to the power supply pad 12. When there are a plurality of types of power supplies, the first bypass capacitor Cl 17 is divided into a plurality of planes and formed in consideration of the arrangement condition of the power supply pads 12. The first conductor film 4 is used as a common ground electrode, and the second conductor film 7 forms a plurality of power supply electrodes.
FIG. 10 shows a process chart of the second dielectric film 8 formed after the second conductor film 7. After forming the second conductor film 7, a 200 nm thick tantalum oxide thin film is formed on the entire surface of the LSI chip 2 by sputtering. As the film forming process, the 50 nm process may be repeated 2 to 4 times. Then, a part of the resistor film 6 and the upper surface of the electrode pad such as the ground pad 11 of the LSI chip 2 are removed by a photo process and a wet etching method. Further, the second dielectric film 8 is formed so as to cover the first conductor film 4 and the second conductor film 7. The opening 16 of the second dielectric film 8 provided on the surface of the resistor film 6 is one of means for controlling the value of the resistor R19 according to its shape. As the dielectric material, barium titanate BaTiO3 or strontium titanate SrTiO3 may be used to increase the relative dielectric constant.
FIG. 11 is a process diagram of the third conductor film 9 formed after the second dielectric film 8. After forming the second dielectric film 8, a platinum thin film having a thickness of 500 nm is formed on the entire surface of the LSI chip 2 by sputtering. This is formed on the second dielectric film 8 and the resistor film 6 as an electrode layer of the second bypass capacitor C2 18 and the resistor R19 by a photo process and a dry etching method. In this case, the third conductor film 9 is formed so as not to protrude from the second dielectric film 8 on the four sides adjacent to the electrode pads such as the ground pad 11 of the LSI chip 2.
Finally, as shown in FIG. 1, after forming the third conductor film 9, a second insulating film 10 as a passivation film is formed. A silicon oxide film having a thickness of 1 μm is formed on the entire surface of the LSI chip 2 by CVD. This is formed in a region excluding electrode pads such as the ground pad 11 of the LSI chip 2 by a photo process and a dry etching method. In order to improve moisture resistance, the passivation film may be formed in two layers.
INDUSTRIAL APPLICABILITY The present invention is a circuit in which a second bypass capacitor C2 and a resistor R are connected in series to a first bypass capacitor Cl connected to a power supply pad and a ground pad on the surface of an LSI device. Are connected in parallel, and the impedance of the second bypass capacitor C2 is made sufficiently small with respect to the resistor R. As a result, the Q of the bypass capacitor circuit viewed from between the power supply pad and the ground pad is cut from the direct current component, and at the same time, the alternating current component (high frequency component) is lowered (value of 10 or less), and between the pads. There is an effect of absorbing the generated potential fluctuation and greatly suppressing electromagnetic radiation from the LSI device itself and wiring connected thereto.

Claims (4)

グランドパッド並びに電源パッドを含む電極パッドが周縁に配置され且つ該電極パッドを除いた部分には第１絶縁膜が形成された表面を有するＬＳＩデバイス、
前記第１絶縁膜上に形成され且つ前記グランドパッドに電気的に接続された第１導電膜、
前記第１導電膜上に形成された抵抗体膜、
前記第１導電膜上の前記グランドパッド並びに前記抵抗体膜と接する領域を除く全域に形成された第１誘電体膜、
前記第１誘電体膜上に該第１誘電体膜を前記第１導電膜とともに挟み込むように形成され且つ前記電源パッドに電気的に接続された第２導電膜、
前記第１導電膜並びに前記第２導電膜を含む前記ＬＳＩデバイスの表面の前記電極パッドの形成部分を除く全域に該第２導電膜を覆うように形成され且つ前記抵抗体膜を露出する開口部を有する第２誘電体膜、及び
前記第２誘電体膜上に前記第２導電膜と前記開口部から露出された前記抵抗体膜とを覆い且つ該第２誘電体膜の外にはみ出さないように形成された第３導電膜を備え、
前記第１導電膜と前記第２導電膜とはその間に前記第１誘電体膜を挟んで前記グランドパッドと前記電源パッドとに接続した第１バイパスコンデンサＣ１を成し、前記第１導電膜、前記抵抗体膜、並びに前記第３導電膜はこの順に積層されて抵抗Ｒを成し、前記第３導電膜と前記第２導電膜とはその間に前記第２誘電体膜を挟んで前記抵抗Ｒと直列に接続され且つ前記グランドパッドと前記電源パッドとの間に前記第１バイパスコンデンサＣ１と並列に接続される第２バイパスコンデンサＣ２を成し、
前記第２バイパスコンデンサＣ２のインピーダンスは前記抵抗Ｒに比べて前記グランドパッドと前記電源パッドとの間に前記第１バイパスコンデンサＣ１と該抵抗Ｒとが直接並列接続された等価回路が形成されたと見なされる程小さく、該等価回路により該グランドパッドと該電源パッドとの間に生じる電位変動を吸収し、且つ該第２バイパスコンデンサＣ２により該グランドパッドと該電源パッドとの間に直流電圧印加で生じるリーク電流を抑えることを特徴とする電子装置。An LSI device having a surface in which an electrode pad including a ground pad and a power supply pad is arranged at a peripheral edge and a first insulating film is formed on a portion excluding the electrode pad;
A first conductive film formed on the first insulating film and electrically connected to the ground pad;
A resistor film formed on the first conductive film;
A first dielectric film formed all over the ground pad on the first conductive film and a region in contact with the resistor film;
A second conductive film formed on the first dielectric film so as to sandwich the first dielectric film together with the first conductive film and electrically connected to the power supply pad;
An opening formed on the surface of the LSI device including the first conductive film and the second conductive film so as to cover the second conductive film over the entire area except the electrode pad forming part and exposing the resistor film. Covering the second conductive film and the resistor film exposed from the opening, and does not protrude from the second dielectric film. A third conductive film formed as described above,
The first conductive film and the second conductive film form a first bypass capacitor C1 connected to the ground pad and the power supply pad with the first dielectric film interposed therebetween, the first conductive film, The resistor film and the third conductive film are stacked in this order to form a resistance R, and the third conductive film and the second conductive film sandwich the second dielectric film between them and the resistance R And a second bypass capacitor C2 connected in series with the first bypass capacitor C1 between the ground pad and the power supply pad.
Compared with the resistor R, the impedance of the second bypass capacitor C2 is regarded as an equivalent circuit in which the first bypass capacitor C1 and the resistor R are directly connected in parallel between the ground pad and the power supply pad. The potential fluctuation generated between the ground pad and the power supply pad is absorbed by the equivalent circuit, and a DC voltage is applied between the ground pad and the power supply pad by the second bypass capacitor C2. An electronic device characterized by suppressing leakage current. 前記等価回路は、前記グランドパッドと前記電源パッドとの間に生じる前記電位変動を熱に変換して吸収することを特徴とする請求の範囲第１項に記載の電子装置。The electronic device according to claim 1, wherein the equivalent circuit converts the potential fluctuation generated between the ground pad and the power supply pad into heat and absorbs it. 前記第１導電膜、前記第２導電膜、並びに前記第３導電膜は白金薄膜で形成され、前記抵抗体膜はクロムと酸化シリコンとのサーメット抵抗材料で形成され、前記第１誘電体膜と前記第２誘電体膜とはチタン酸バリウムＢａＴｉＯ3又はチタン酸ストロンチウムＳｒＴｉＯ3で形成されていることを特徴とする請求の範囲第１項又は第２項に記載の電子装置。The first conductive film, the second conductive film, and the third conductive film are formed of a platinum thin film, the resistor film is formed of a cermet resistance material of chromium and silicon oxide, and the first dielectric film and 3. The electronic device according to claim 1, wherein the second dielectric film is formed of barium titanate BaTiO 3 or strontium titanate SrTiO 3. 4 . 第２の絶縁膜が前記第３導電膜を含む前記ＬＳＩデバイスの表面の前記電極パッドの形成部分を除く全域に形成されていることを特徴とする請求の範囲第１項乃至第３項のいずれかに記載の電子装置。4. The method according to claim 1, wherein the second insulating film is formed on the entire surface of the LSI device including the third conductive film except for a portion where the electrode pad is formed. An electronic device according to any of the above.
JP52744596A 1995-03-15 1995-03-15 Electronic equipment Expired - Lifetime JP3909086B2 (en)

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SG73610A1 (en) * 1998-10-07 2002-01-15 Agilent Technologies Inc Integrated circuit die with directly coupled noise suppression and/or other device
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JP5304460B2 (en) * 2009-06-11 2013-10-02 日本電気株式会社 Printed wiring board power circuit design apparatus, printed wiring board power circuit design method and program

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