JP3897115B2 - Semiconductor element sealing method - Google Patents

Semiconductor element sealing method Download PDF

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JP3897115B2
JP3897115B2 JP2003194402A JP2003194402A JP3897115B2 JP 3897115 B2 JP3897115 B2 JP 3897115B2 JP 2003194402 A JP2003194402 A JP 2003194402A JP 2003194402 A JP2003194402 A JP 2003194402A JP 3897115 B2 JP3897115 B2 JP 3897115B2
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sealing
semiconductor element
resist layer
resin
circuit portion
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JP2005032872A (en
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利夫 塩原
努 柏木
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Shin Etsu Chemical Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations

Description

【０００１】
【発明の属する技術分野】
本発明は、基板表面に１又は複数の回路と電極とを形成してなる半導体素子の上記回路部分を樹脂封止する方法に関する。なお、本発明において、半導体素子とは光半導体素子を含む意味で用いる。
【０００２】
【従来の技術】
従来、半導体素子表面を透明な樹脂で直接封止する方法としては、感光性の透明樹脂を用い、フォトマスクを使用し、透明樹脂を感光させることにより封止している。この方法では、感光性樹脂として、通常、アクリル変性したシリコーン樹脂組成物や、光カチオン重合を利用したシリコーン樹脂組成物などが一般に利用されている。この種の材料は透明であるが、アクリル変性の場合は耐熱性が悪く、長期間高温下や紫外線照射下で使用した場合、容易に変色する問題があった。また、光カチオン重合を利用する場合、光照射でカチオンが発生する触媒はイオン性不純物が多く、かつアルミニウムなどの電極を容易に腐食するものがほとんどで、半導体素子の封止には問題がある。
【０００３】
一方、熱硬化性や室温硬化性のシリコーン樹脂組成物は、高純度でかつ耐熱性も良好な材料であり、また透明性や接着性も良好なことから、従来より広く半導体素子の封止に使用されている。しかしながら、この種の材料を紫外線等の光を用いて直接描画することで所定の部分のみを封止することはできず、この方法において、この種の材料は全く使用されていなかった。
【０００４】
なお、この発明に関連する先行技術文献としては、下記のものがある。
【非特許文献１】
エポキシ樹脂ハンドブック第４７７〜４８４頁（日刊工業新聞社）
【０００５】
【発明が解決しようとする課題】
本発明は、上記事情に鑑みなされたもので、耐熱性、透明性及び接着性に優れた有機樹脂封止材を基板上の回路部分に選択的に直接描画封止することができる半導体素子の封止方法を提供することを目的とする。
【０００６】
【課題を解決するための手段】
本発明者は、上記目的を達成するために鋭意検討を行った結果、基板上に形成された回路部分を樹脂封止する場合、基板表面にレジスト材料を塗布してレジスト層を形成し、これを選択的に露光、現像して、樹脂封止すべき回路部分に対応するレジスト層のみを除去し、次いで該回路部分に樹脂封止材を塗布、硬化させ、更に残存レジスト層を除去することにより、回路部分のみが樹脂封止材にて封止され、従って今まで使用できなかった耐熱性、透明性及び接着性に優れる硬化性の有機樹脂封止材を用いて半導体素子表面を封止できることを知見した。
【０００７】
即ち、この方法を用いることにより、数十μｍレベルでの封止が可能となり、また封止材として、透明性や接着性の良好なシリコーン樹脂組成物やエポキシ樹脂組成物等の硬化性有機樹脂組成物が使用できることから、長期にＵＶＬＥＤ、青色ＬＥＤなどの光素子を封止しても透過率の低下がほとんどないものが得られることを知見し、本発明をなすに至った。
【０００８】
従って、本発明は、下記の半導体素子の封止方法を提供する。
［Ｉ］基板表面に１又は複数の回路と電極とを形成してなる半導体素子の上記回路部分を樹脂封止する方法において、
（１）上記回路及び電極が設置された基板表面にポジ型レジスト材料を５〜１００μｍの厚みで塗布し、レジスト層を形成する工程、
（２）樹脂封止すべき回路部分のレジスト層のみ露光して、回路部分が現像液で除去されるようにレジスト層を選択的に露光し、次いで現像を行う工程、
（３）レジスト層が選択的に現像、除去されて露呈した樹脂封止すべき回路部分に付加反応硬化型もしくは室温硬化型シリコーン樹脂組成物又はエポキシ樹脂組成物からなる樹脂封止材をレジスト層と同じ膜厚になるように塗布し、この封止材を硬化させる工程、
（４）上記回路部分を封止する硬化樹脂層を溶解させず、残存レジスト層を溶解可能な溶剤を用いて残存レジスト層を除去する工程
を備えたことを特徴とする半導体素子の封止方法。
［ＩＩ］基板表面に１又は複数の回路と電極とを形成してなる半導体素子の上記回路部分を樹脂封止する方法において、
（１）上記回路及び電極が設置された基板表面にネガ型レジスト材料を５〜１００μｍの厚みで塗布し、レジスト層を形成する工程、
（２）樹脂封止すべき回路部分のレジスト層のみ露光せずに、回路部分が現像液で除去されるようにレジスト層を選択的に露光し、次いで現像を行う工程、
（３）レジスト層が選択的に現像、除去されて露呈した樹脂封止すべき回路部分に付加反応硬化型もしくは室温硬化型シリコーン樹脂組成物又はエポキシ樹脂組成物からなる樹脂封止材をレジスト層と同じ膜厚になるように塗布し、この封止材を硬化させる工程、
（４）上記回路部分を封止する硬化樹脂層を溶解させず、残存レジスト層を溶解可能な溶剤を用いて残存レジスト層を除去する工程
を備えたことを特徴とする半導体素子の封止方法。
［ＩＩＩ］半導体素子が複数の回路と電極とが形成されたものであり、上記工程（４）を行った後、樹脂封止した各回路部分を個別細片化するように基板を切断することを特徴とする［Ｉ］又は［ＩＩ］記載の半導体素子の封止方法。
［ＩＶ］樹脂封止材が、無機蛍光体及び／又は光散乱剤を含有することを特徴とする［Ｉ］〜［ＩＩＩ］のいずれかに記載の半導体素子の封止方法。
［Ｖ］樹脂封止材が、透明であることを特徴とする［Ｉ］〜［ＩＶ］のいずれかに記載の半導体素子の封止方法。
［ＶＩ］半導体素子がＬＥＤ光デバイスであることを特徴とする［Ｉ］〜［Ｖ］のいずれかに記載の半導体素子の封止方法。
【０００９】
【発明の実施の形態及び実施例】
以下、本発明について詳細に説明する。
本発明の半導体素子（光半導体素子を含む）の封止方法は、先ず、１又は複数の回路とこれに連絡する電極とが表面に形成された基板の該表面上にレジスト材料を塗布し、レジスト層を形成する（工程１）。
この場合、レジスト材料としては、ポジ型でもネガ型でもよく、公知のものが使用され、例えばアルカリ可溶性ノボラック樹脂と感光剤としてナフトキノンジアジドスルホニルクロライド等のキノンジアジド類とを含むｉ線、ｇ線等用のレジスト材料、或いは化学増幅型レジスト材料が用いられる。この場合、レジスト材料としては、市販品を使用してもよい。更に、本発明において、半導体素子（光半導体素子を含む）としては、ＵＶＬＥＤ、青色ＬＥＤ、可視光ＬＥＤ、ＩＲＬＥＤ、レーザーＬＥＤ等が挙げられる。なお、基板としては、シリコン、ガリウムヒ素、ガリウムアルミニウムヒ素、チン化ガリウム、サファイア等が挙げられる。
【００１０】
上記基板表面に、上記レジスト材料を塗布する際、レジスト材料は、通常、膜厚として５〜１００μｍ、特に１０〜５０μｍ程度の厚みで塗布することが好ましい。膜厚が５μｍ未満では有機樹脂封止材を十分な厚みをもって半導体素子に被覆、封止し得ない場合があり、十分な信頼性が確保できないおそれがある。また、１００μｍを超える厚みを得ようとしても、現状では適切なレジスト材料が市販されていない。
【００１１】
レジスト材料の塗布方法としては、スピンコート法、スクリーン印刷法等が挙げられる。
レジスト材料の塗布後は、これを乾燥し、更に必要により６０〜２００℃で１０秒〜１０分間程度のプリベークを行うことができる。
【００１２】
次いで、樹脂封止すべき回路部分のレジスト層のみが現像液で除去されるように、フォトマスクを使用してレジスト層を選択的に露光し、現像を行う（工程２）。
【００１３】
この場合、ポジ型レジスト材料では、封止材で封止すべき部分のみを感光させ、一方ネガ型レジスト材料では、封止材で封止すべきでない部分のみを感光させる。なお、本発明においては、封止する部分の大きさに合わせ、光遮蔽部の大きさを調整すれば、どのようなものでも封止することができる。光遮蔽部の間隔は、最終工程で素子を切断する場合であれば、この際に必要な幅が確保できればよい。
【００１４】
露光する場合の波長は、レジスト材料の種類に応じて適宜選定されるが、一般に、波長４００ｎｍ以下で、紫外線、遠紫外線、エキシマレーザー、Ｘ線、電子線等が挙げられ、通常ｉ線、ｇ線やＫｒＦ、ＡｒＦ等のエキシマレーザーなどを使用し、公知の方法で露光することができる。
【００１５】
光照射後、必要に応じ４０〜１５０℃で１０秒〜５分間程度のポストエクスポージャーベークを行い、現像するが、現像液としては、ポジ型レジスト材料の場合であれば、露光部分のみを溶解し、非露光部分は溶解させない現像液が、ネガ型レジスト材料であれば、露光部分は溶解させず、非露光部分のみを溶解させる現像液が用いられ、公知の現像液が使用される。例えば、現像液として、０．１〜５％のテトラメチルアンモニウムヒドロキサイド溶液等の公知のアルカリ現像液を使用することができる。なお、現像方法及び条件としては、公知の方法、条件を採用し得る。
【００１６】
次に、上記工程（２）により、レジスト層が選択的に現像、除去されて外部に露呈した樹脂封止すべき回路部分に有機樹脂封止材を塗布し、この封止材を硬化させる（工程３）。
【００１７】
本発明で使用する有機樹脂封止材としては、特に限定されるものでないが、硬化性有機樹脂組成物を用いることが好ましい。硬化性有機樹脂組成物としては、シリコーン樹脂組成物やエポキシ樹脂組成物などを代表的な材料として例示することができる。
【００１８】
シリコーン樹脂組成物としては、ビニル基含有オルガノポリシロキサンとヒドロシリル基を含有するオルガノポリシロキサンを白金触媒で反応させることによって硬化させることができる熱硬化型（付加反応硬化型）のものや、シラノール基やアルコキシ基を好ましくは分子鎖末端に含有するオルガノポリシロキサンを縮合触媒存在下、縮合反応によって硬化する室温硬化型のもの等を使用することが好ましい。
【００１９】
エポキシ樹脂組成物としては、いかなるものでも使用できるが、エポキシ樹脂と硬化剤として酸無水物を用いたエポキシ樹脂組成物や、自己重合性エポキシ樹脂を単独重合させたものが、硬化後の透明性を維持できる点から望ましいものである。
【００２０】
ＬＥＤなどの光デバイスを封止する場合は、硬化性有機樹脂組成物の硬化物が透明であるものを用いることが好ましく、特に３５０ｎｍ以上の波長で透明性を示す硬化性シリコーン樹脂組成物や、脂環式のエポキシ樹脂を酸無水物で硬化させた透明なエポキシ樹脂組成物等から選択することが好ましい。
【００２１】
これらの硬化性有機樹脂組成物には、膨張係数を調整するためにシリカなどの無機質充填剤や、光デバイスにおいては、光を散乱させるための光散乱剤、ＬＥＤなどのデバイスの封止には、無機蛍光体などを本発明の目的を損なわない範囲で添加することができる。
【００２２】
硬化性有機樹脂組成物の塗布方法としては、スピンコート法、印刷法等が挙げられる。なお、このような組成物の塗布は、上記半導体素子部分のみに行うことが好ましい。この場合、スピンコート法を用いると、封止材は上記レジスト層が除去されて凹形状となった半導体素子部分に入り込む一方、残存レジスト層上の封止材は、実際上、スピン力で吹き飛ばされて残存レジスト層上に残らないものである。
【００２３】
なお、硬化性有機樹脂組成物を塗布する際に、塗布量が最適化されておらず、レジスト層上に硬化性有機樹脂組成物が多量に残存したまま硬化した場合、次工程で残存レジスト層を除去した場合、該レジスト層上の硬化樹脂が残り、レジスト層のみが除去されて、その部分が空洞となってしまうことがある。そのため、硬化性有機樹脂組成物の塗布量は、レジスト層と同じ膜厚となるように調整することが望ましく、特にスピンコート時には、使用する硬化性有機樹脂組成物の粘度にあわせた最適な回転数を選択することが望ましい。
【００２４】
硬化性有機樹脂組成物の硬化方法及び硬化条件としては、用いる硬化性有機樹脂組成物により異なるが、加熱硬化型の場合、６０〜２００℃の温度で硬化させることができ、また室温硬化型の場合、２０〜６０℃の温度で硬化させることができる。
【００２５】
硬化性有機樹脂組成物を硬化させた後、半導体素子基板に残存する未反応のレジスト層を溶剤を用いて除去する（工程４）。ここで使用する溶剤は、回路部分を封止する硬化樹脂層を溶解せず、残存レジスト層を溶解可能なものであれば、いずれの溶剤でもよく、具体的には、メタノール、イソプロピルアルコール、アセトン等が用いられる。
【００２６】
レジスト層除去後、接着力向上、硬化物性向上の点から半導体素子基板を乾燥させることが好ましい。乾燥条件としては、８０〜２００℃、特に１００〜１８０℃で、３０分〜４時間、特に３０分〜２時間とすることができる。
【００２７】
以上のようにして、例えば図１４に示すように、必要部分を有機樹脂封止材７にて封止された基板１を得ることができる。
【００２８】
本発明においては、複数の回路と電極が設置され、各回路が上記のように樹脂封止されている場合において、このようにして得られた樹脂封止半導体素子基板を切断、例えば、ダイシングテープに樹脂封止半導体素子基板を貼り付けてダイシングソーを用い、有機樹脂封止材で封止されていない部分を切断し、各回路部分を互いに切り離すことにより、個別細片化された封止デバイスを得ることができる。
【００２９】
本発明の方法により得られた封止デバイスは、ダイボンド剤を用いてパッケージに搭載することができる。搭載後、金線で半導体素子の電極とパッケージ間を接続し、場合によっては、このパッケージに他の樹脂をポッティングしたり、セラミックス等の蓋をパッケージに接着剤等で貼り付けることにより、半導体装置を得ることができる。
【００３０】
また、半導体素子がＬＥＤのような光デバイスの場合は、透明なガラスの蓋を接着剤で接着させることや、透明性を有するシリコーン樹脂、或いはエポキシ樹脂等の樹脂でポッティングすることにより、パッケージを完成させることができる。
【００３１】
更に、ＬＥＤや光発光素子を内在するような封止デバイスをフリップチップ方式で基板上に実装する場合は、該封止デバイスを個別細片化した後、或いは細片化前に半田ボールなどの接続端子を半導体素子や半導体素子基板上の電極につけ、その後、該封止デバイスを光・電子複合基板等の有機基板やパッケージに半田ボールを介して接続することにより、光を透過する樹脂で封止した半導体素子を簡単に実装することができる。
【００３２】
このように、本発明によれば、光・電子複合基板上に搭載可能な光半導体デバイスを容易に封止することができる。
また、本発明によれば、白色光を得るために、予め蛍光体や光散乱材を含有した有機樹脂組成物を用いてＬＥＤを封止することができ、容易にＬＥＤを組み立てることができる。
【００３３】
本発明によれば、従来不可能であった熱や縮合反応で硬化するシリコーン樹脂組成物などの有機樹脂封止材を用い、ウエハレベルで半導体素子部分のみを高精度に封止保護することが可能となる。
【００３４】
以下、実施例を図面に基づいてより具体的に説明する。図１〜７は、本発明の半導体素子の封止方法を示すものである。
【００３５】
まず、図１は、本発明に用いられる半導体素子基板の一例を示す概略断面図であり、基板１上に複数の電極２及び回路部３が形成されているものである。
【００３６】
図２に示すように、半導体基板１表面にポジ型レジスト材料（ＳＩＰＲ−９２７１信越化学（株）製）を、スピンコータを用い、回転数２０００ｒｐｍで塗布し、厚み２０μｍのレジスト層４を形成した。
【００３７】
図３に示すように、この基板１上に、３ｍｍ×２ｍｍの光遮蔽部と光遮蔽部間の間隔（光透過部）とがそれぞれ０．５ｍｍのフォトマスク５を用い、光６を照射し、上記回路部３に対応する部分のみを露光した。この時の光波長は３６５ｎｍ、また照射時間は３０秒である。
【００３８】
なお、ここで使用した半導体素子基板は、回路部周辺部分に金線を接続する接続パッド部（電極）を有するものであり、有機樹脂封止材で封止する部分は、この接続パッドの存在しない部分であり、このためこの部分を光透過部としたフォトマスクを用いた。
【００３９】
光照射後、現像液（２．４％テトラメチルアンモニウムヒドロキサイド溶液）を用い、パドル法にて現像を行い、光照射部分のレジスト層のみを除去した。これにより、有機樹脂封止材を注型する部分のみが現像されてレジスト層が除去された半導体素子基板（図４）を作製した。
【００４０】
次に、図５に示すように、この半導体素子基板１をスピンコータにのせ、回転数２０００ｒｐｍで回転させながら熱硬化性の液状シリコーン樹脂組成物７を厚さ２０μｍとなるように塗布した。ここで使用した液状シリコーン樹脂組成物は、下記式
【化１】

Figure 0003897115
で示されるポリシロキサン５０質量部に、ＳｉＯ2単位５０モル％、（ＣＨ3）3ＳｉＯ0.5単位４２．５モル％及び（ＣＨ2＝ＣＨ）（ＣＨ3）2ＳｉＯ0.5単位７．５モル％からなるレジン構造のビニルメチルシロキサン（ＶＭＱ）５０質量部、下記式
【化２】
Figure 0003897115
で示されるオルガノハイドロジェンポリシロキサン１０質量部、及び塩化白金酸のオクチルアルコール変性溶液０．０５質量部からなり、よく撹拌したものを用いた。
【００４１】
液状シリコーン樹脂組成物を塗布後、１５０℃で１時間加熱してシリコーン樹脂組成物を硬化させた。
【００４２】
硬化後、半導体素子基板１をアセトン溶液に浸せきさせることで、残存していたレジストを溶解させた（図６）。アセトン洗浄後、有機樹脂封止材７で封止された半導体素子基板１を１５０℃で１時間乾燥させた。
【００４３】
半導体素子基板を乾燥後、ダイシングテープに基板を貼り付け、ダイシングソーを用い、有機樹脂で封止されていない部分を切断することにより、各回路部分及びこれに連絡する電極が個別細片化された封止デバイス８を得た（図７）。
【００４４】
ここで得られた個別細片化された封止デバイス８を、エポキシダイボンド剤９を用いて有機基板（パッケージ）１０上に搭載した（図８）。
【００４５】
搭載後、金線１１で封止デバイス８と有機基板１０間を接続した（図９）。この後、図１０に示すように、透明なガラス蓋１２を接着剤で接着させることにより、パッケージを完成させた。或いは、接続後、図１１に示すように、シリコーン樹脂でポッティングすることにより、パッケージを完成させた。
【００４６】
また、ＬＥＤ、光発光素子（レーザー等）を内在する封止デバイスを個別細片化した後、半田ボール１４を半導体素子基板上１の電極につけ（図１２）、その後、該封止デバイス８を光・電子複合基板１５に半田ボールを介して接続したところ、簡単に光６を透過する樹脂で封止した半導体素子を実装することができた（図１３）。なお、図１３において、１６は光導波路である。
【００４７】
【発明の効果】
本発明の封止方法によれば、従来不可能であった熱や縮合反応で硬化するシリコーン樹脂組成物などの耐熱性、透明性及び接着性に優れる有機樹脂封止材を用い、ウエハレベルで回路部分のみを高精度に封止保護することができる。
【００４８】
【図面の簡単な説明】
【図１】本発明の実施例に用いる半導体素子基板の概略断面図である。
【図２】本発明の実施例において、レジスト層を形成した半導体素子基板の概略断面図である。
【図３】本発明の実施例における光照射工程を示す概略断面図である。
【図４】本発明の実施例において、光照射によりレジストを除去した半導体素子基板の概略断面図である。
【図５】本発明の実施例において、有機樹脂封止材を形成した半導体素子基板の概略断面図である。
【図６】本発明の実施例において、レジスト層を除去した半導体素子基板の概略断面図である。
【図７】本発明の実施例において、切断により個別細片化した封止デバイスの概略断面図である。
【図８】本発明で得られた封止デバイスをパッケージにダイボンドした一例を示す概略断面図である。
【図９】本発明の封止デバイスを基板にワイヤボンドした一例を示す概略断面図である。
【図１０】上記封止デバイスをガラス蓋でシールした一例を示す概略断面図である。
【図１１】上記封止デバイスを樹脂によりポッティングした一例を示す概略断面図である。
【図１２】本発明で得られた封止デバイスにバンプを形成した一例を示す概略断面図である。
【図１３】バンプ形成封止デバイスを基板に搭載した一例を示す概略断面図である。
【図１４】有機樹脂封止材で封止した半導体素子基板の一例を示す平面図（Ａ）及び断面図（Ｂ）である。
【符号の説明】
１ 基板
２ 電極
３ 回路部
４ ポジ型レジスト層
５ フォトマスク
６ 光
７ 有機樹脂封止材
８ 封止デバイス
９ ダイボンド剤
１０ パッケージ
１１ 金線
１２ ガラス蓋
１３ 透明樹脂
１４ バンプ
１５ 光・電子複合基板
１６ 光導波路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of resin-sealing the circuit portion of a semiconductor element formed by forming one or more circuits and electrodes on a substrate surface. In the present invention, the term “semiconductor element” is used to include an optical semiconductor element.
[0002]
[Prior art]
Conventionally, as a method for directly sealing a semiconductor element surface with a transparent resin, a photosensitive transparent resin is used, and a photomask is used to seal the surface by exposing the transparent resin. In this method, an acrylic-modified silicone resin composition or a silicone resin composition using photocationic polymerization is generally used as the photosensitive resin. This type of material is transparent, but has a problem of poor heat resistance in the case of acrylic modification and easily discolors when used for a long time under high temperature or ultraviolet irradiation. In addition, when using cationic photopolymerization, most of the catalysts that generate cations upon irradiation with light have many ionic impurities and easily corrode electrodes such as aluminum, which causes problems in sealing semiconductor elements. .
[0003]
On the other hand, thermosetting and room temperature curable silicone resin compositions are materials with high purity and good heat resistance, as well as good transparency and adhesiveness. in use. However, it is impossible to seal only a predetermined portion by directly drawing this kind of material using light such as ultraviolet rays, and this kind of material has not been used at all in this method.
[0004]
As prior art documents related to the present invention, there are the following.
[Non-Patent Document 1]
Epoxy resin handbook 477-484 (Nikkan Kogyo Shimbun)
[0005]
[Problems to be solved by the invention]
The present invention has been made in view of the above circumstances, and is a semiconductor element that can selectively draw and seal an organic resin sealing material excellent in heat resistance, transparency, and adhesiveness on a circuit portion on a substrate. An object is to provide a sealing method.
[0006]
[Means for Solving the Problems]
As a result of intensive studies to achieve the above object, the present inventor applied a resist material to the substrate surface to form a resist layer when resin-sealing a circuit portion formed on the substrate. Is selectively exposed and developed to remove only the resist layer corresponding to the circuit portion to be resin-sealed, then apply and cure the resin sealing material on the circuit portion, and further remove the remaining resist layer As a result, only the circuit part is sealed with a resin sealing material, and therefore the surface of the semiconductor element is sealed with a curable organic resin sealing material that has been excellent in heat resistance, transparency, and adhesiveness, which could not be used until now. I found out that I can do it.
[0007]
That is, by using this method, sealing at a level of several tens of μm is possible, and as a sealing material, a curable organic resin such as a silicone resin composition or an epoxy resin composition having good transparency and adhesiveness. Since the composition can be used, it has been found that even if an optical element such as a UV LED or a blue LED is sealed for a long period of time, it can be obtained that there is almost no decrease in transmittance, and the present invention has been made.
[0008]
Accordingly, the present invention provides the following semiconductor element sealing method.
[I] In a method of resin-sealing the circuit portion of a semiconductor element formed by forming one or more circuits and electrodes on a substrate surface,
(1) A step of applying a positive resist material to a thickness of 5 to 100 μm on the substrate surface on which the circuit and electrodes are installed, and forming a resist layer;
(2) a step of exposing only the resist layer of the circuit portion to be resin-sealed, selectively exposing the resist layer so that the circuit portion is removed with a developer, and then developing;
(3) Resin sealing layer made of addition reaction curable type or room temperature curable type silicone resin composition or epoxy resin composition is applied to the circuit portion to be encapsulated, which is exposed by selectively developing and removing the resist layer. The process of applying the same film thickness as this and curing this encapsulant,
(4) A method for sealing a semiconductor element, comprising: a step of removing the remaining resist layer using a solvent capable of dissolving the remaining resist layer without dissolving the cured resin layer for sealing the circuit portion. .
[II] In the method of resin-sealing the circuit portion of the semiconductor element formed by forming one or more circuits and electrodes on the substrate surface,
(1) A step of applying a negative resist material to a thickness of 5 to 100 μm on the surface of the substrate on which the circuit and electrodes are installed to form a resist layer;
(2) a step of selectively exposing the resist layer so that the circuit portion is removed with a developer without exposing only the resist layer of the circuit portion to be resin-sealed, and then developing;
(3) Resin sealing layer made of addition reaction curable type or room temperature curable type silicone resin composition or epoxy resin composition is applied to the circuit portion to be encapsulated, which is exposed by selectively developing and removing the resist layer. The process of applying the same film thickness as this and curing this encapsulant,
(4) A step of removing the remaining resist layer using a solvent capable of dissolving the remaining resist layer without dissolving the cured resin layer that seals the circuit portion.
A method for sealing a semiconductor element, comprising:
[ III ] A semiconductor element in which a plurality of circuits and electrodes are formed, and after performing the above step (4), the substrate is cut so that each resin-sealed circuit portion is individually cut into pieces. A method for sealing a semiconductor element according to [I] or [II] .
[ IV ] The method for sealing a semiconductor element according to any one of [I] to [ III ], wherein the resin sealing material contains an inorganic phosphor and / or a light scattering agent.
[V] The method for sealing a semiconductor element according to any one of [I] to [ IV ], wherein the resin sealing material is transparent.
[VI] The semiconductor element sealing method according to any one of [I] to [V], wherein the semiconductor element is an LED optical device .
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail.
In the method for sealing a semiconductor element (including an optical semiconductor element) of the present invention, first, a resist material is applied onto the surface of a substrate on which one or more circuits and electrodes connected to the circuit are formed. A resist layer is formed (step 1).
In this case, the resist material may be positive or negative, and known ones are used. For example, i-line, g-line, etc. containing an alkali-soluble novolak resin and a quinonediazide such as naphthoquinonediazidesulfonyl chloride as a photosensitizer. Or a chemically amplified resist material. In this case, a commercially available product may be used as the resist material. Furthermore, in the present invention, examples of the semiconductor element (including the optical semiconductor element) include UVLED, blue LED, visible light LED, IRLED, and laser LED. Examples of the substrate include silicon, gallium arsenide, gallium aluminum arsenide, gallium tantalum, and sapphire.
[0010]
When applying the resist material to the surface of the substrate, the resist material is usually preferably applied with a thickness of about 5 to 100 μm, particularly about 10 to 50 μm. If the film thickness is less than 5 μm, the organic resin sealing material may not be coated and sealed on the semiconductor element with a sufficient thickness, and sufficient reliability may not be ensured. Moreover, even if it is going to obtain the thickness exceeding 100 micrometers, the suitable resist material is not marketed at present.
[0011]
Examples of the resist material coating method include spin coating and screen printing.
After the application of the resist material, it can be dried and further pre-baked at 60 to 200 ° C. for about 10 seconds to 10 minutes if necessary.
[0012]
Next, the resist layer is selectively exposed using a photomask so that only the resist layer of the circuit portion to be resin-sealed is removed with a developer, and development is performed (step 2).
[0013]
In this case, in the positive resist material, only the portion that should be sealed with the sealing material is exposed, while in the negative resist material, only the portion that should not be sealed with the sealing material is exposed. In the present invention, any material can be sealed by adjusting the size of the light shielding portion in accordance with the size of the portion to be sealed. If the element is to be cut in the final process, the interval between the light shielding portions only needs to ensure a necessary width at this time.
[0014]
The wavelength for exposure is appropriately selected according to the type of resist material. Generally, the wavelength is 400 nm or less, and examples include ultraviolet rays, far ultraviolet rays, excimer lasers, X-rays, and electron beams. The exposure can be performed by a known method using an excimer laser such as KrF or ArF.
[0015]
After exposure to light, post-exposure baking is performed at 40 to 150 ° C. for about 10 seconds to 5 minutes as necessary, and development is performed. In the case of a positive resist material, only the exposed portion is dissolved. If the developer that does not dissolve the non-exposed portion is a negative resist material, a developer that dissolves only the non-exposed portion without dissolving the exposed portion is used, and a known developer is used. For example, a known alkaline developer such as a 0.1 to 5% tetramethylammonium hydroxide solution can be used as the developer. In addition, as a developing method and conditions, a well-known method and conditions can be employ | adopted.
[0016]
Next, an organic resin sealing material is applied to the circuit portion to be resin-sealed that is exposed to the outside after the resist layer is selectively developed and removed by the step (2), and the sealing material is cured ( Step 3).
[0017]
Although it does not specifically limit as an organic resin sealing material used by this invention, It is preferable to use a curable organic resin composition. As a curable organic resin composition, a silicone resin composition, an epoxy resin composition, etc. can be illustrated as a typical material.
[0018]
The silicone resin composition includes a thermosetting type (addition reaction curing type) that can be cured by reacting a vinyl group-containing organopolysiloxane and a hydrosilyl group-containing organopolysiloxane with a platinum catalyst, and a silanol group. It is preferable to use a room-temperature curing type or the like that cures by an condensation reaction in the presence of a condensation catalyst of an organopolysiloxane containing an alkoxy group, preferably at the molecular chain end.
[0019]
Any epoxy resin composition can be used, but an epoxy resin composition using an acid anhydride as an epoxy resin and a curing agent, or a homopolymerized self-polymerizable epoxy resin, is transparent after curing. It is desirable from the point that can be maintained.
[0020]
When sealing an optical device such as an LED, it is preferable to use a transparent curable organic resin composition, particularly a curable silicone resin composition exhibiting transparency at a wavelength of 350 nm or more, It is preferable to select from a transparent epoxy resin composition obtained by curing an alicyclic epoxy resin with an acid anhydride.
[0021]
These curable organic resin compositions include inorganic fillers such as silica for adjusting the expansion coefficient, light scattering agents for scattering light in optical devices, and sealing of devices such as LEDs. Inorganic phosphors and the like can be added within a range not impairing the object of the present invention.
[0022]
Examples of the method for applying the curable organic resin composition include a spin coating method and a printing method. In addition, it is preferable to apply | coat such a composition only to the said semiconductor element part. In this case, when the spin coating method is used, the encapsulant enters the recessed semiconductor element portion from which the resist layer is removed, while the encapsulant on the remaining resist layer is practically blown away by a spin force. Thus, it does not remain on the remaining resist layer.
[0023]
When the curable organic resin composition is applied, the coating amount is not optimized, and when the curable organic resin composition is cured with a large amount remaining on the resist layer, the remaining resist layer is used in the next step. When is removed, the cured resin on the resist layer remains, and only the resist layer is removed, and the portion may become a cavity. Therefore, it is desirable to adjust the coating amount of the curable organic resin composition so as to have the same film thickness as the resist layer, and especially at the time of spin coating, the optimum rotation according to the viscosity of the curable organic resin composition to be used. It is desirable to choose a number.
[0024]
The curing method and curing conditions of the curable organic resin composition vary depending on the curable organic resin composition to be used, but in the case of the thermosetting type, it can be cured at a temperature of 60 to 200 ° C. In this case, it can be cured at a temperature of 20 to 60 ° C.
[0025]
After the curable organic resin composition is cured, the unreacted resist layer remaining on the semiconductor element substrate is removed using a solvent (step 4). The solvent used here may be any solvent as long as it can dissolve the remaining resist layer without dissolving the cured resin layer that seals the circuit portion, and specifically, methanol, isopropyl alcohol, acetone. Etc. are used.
[0026]
After removing the resist layer, it is preferable to dry the semiconductor element substrate from the viewpoint of improving adhesive strength and improving cured properties. Drying conditions may be 80 to 200 ° C., particularly 100 to 180 ° C., and 30 minutes to 4 hours, particularly 30 minutes to 2 hours.
[0027]
As described above, for example, as shown in FIG. 14, a substrate 1 in which necessary portions are sealed with the organic resin sealing material 7 can be obtained.
[0028]
In the present invention, when a plurality of circuits and electrodes are installed and each circuit is resin-sealed as described above, the resin-encapsulated semiconductor element substrate thus obtained is cut, for example, a dicing tape A sealing device separated into individual pieces by affixing a resin-encapsulated semiconductor element substrate to a dicing saw, cutting a portion not sealed with an organic resin sealing material, and separating each circuit portion from each other Can be obtained.
[0029]
The sealing device obtained by the method of the present invention can be mounted on a package using a die bond agent. After mounting, the semiconductor device electrode and the package are connected with a gold wire, and in some cases, another resin is potted on the package, or a ceramic lid is attached to the package with an adhesive or the like. Can be obtained.
[0030]
In addition, when the semiconductor element is an optical device such as an LED, the package can be mounted by bonding a transparent glass lid with an adhesive, or potting with a resin such as a transparent silicone resin or epoxy resin. Can be completed.
[0031]
Further, when a sealing device having an LED or a light emitting element is mounted on a substrate by a flip chip method, a solder ball or the like may be used after the sealing device is cut into individual pieces or before being cut into pieces. A connection terminal is attached to an electrode on a semiconductor element or a semiconductor element substrate, and then the sealing device is connected to an organic substrate such as an optical / electronic composite substrate or a package via a solder ball, thereby sealing with a resin that transmits light. The stopped semiconductor element can be easily mounted.
[0032]
Thus, according to the present invention, an optical semiconductor device that can be mounted on an optical / electronic composite substrate can be easily sealed.
Moreover, according to this invention, in order to obtain white light, LED can be sealed using the organic resin composition containing fluorescent substance and a light-scattering material previously, and LED can be assembled easily.
[0033]
According to the present invention, by using an organic resin sealing material such as a silicone resin composition that is cured by heat or a condensation reaction, which has been impossible in the past, it is possible to seal and protect only the semiconductor element portion with high accuracy at the wafer level. It becomes possible.
[0034]
Hereinafter, an example is described more concretely based on a drawing. 1 to 7 show a sealing method of a semiconductor element of the present invention.
[0035]
First, FIG. 1 is a schematic sectional view showing an example of a semiconductor element substrate used in the present invention, in which a plurality of electrodes 2 and a circuit portion 3 are formed on a substrate 1.
[0036]
As shown in FIG. 2, a positive resist material (manufactured by SIPR-9271 Shin-Etsu Chemical Co., Ltd.) was applied to the surface of the semiconductor substrate 1 using a spin coater at a rotational speed of 2000 rpm, to form a resist layer 4 having a thickness of 20 μm.
[0037]
As shown in FIG. 3, the substrate 1 is irradiated with light 6 using a photomask 5 having a light shielding portion of 3 mm × 2 mm and a distance (light transmitting portion) between the light shielding portions of 0.5 mm. Only the part corresponding to the circuit part 3 was exposed. The light wavelength at this time is 365 nm, and the irradiation time is 30 seconds.
[0038]
The semiconductor element substrate used here has a connection pad part (electrode) for connecting a gold wire to the peripheral part of the circuit part, and the part sealed with the organic resin sealing material is the presence of this connection pad. For this reason, a photomask having this portion as a light transmission portion was used.
[0039]
After light irradiation, development was performed by a paddle method using a developer (2.4% tetramethylammonium hydroxide solution), and only the resist layer in the light irradiated portion was removed. As a result, a semiconductor element substrate (FIG. 4) in which only the portion where the organic resin sealing material was cast was developed and the resist layer was removed was produced.
[0040]
Next, as shown in FIG. 5, the semiconductor element substrate 1 was placed on a spin coater, and a thermosetting liquid silicone resin composition 7 was applied to a thickness of 20 μm while rotating at a rotational speed of 2000 rpm. The liquid silicone resin composition used here has the following formula:
Figure 0003897115
In 50 parts by mass of the polysiloxane represented by the formula, SiO 2 unit 50 mol%, (CH 3 ) 3 SiO 0.5 unit 42.5 mol% and (CH 2 ═CH) (CH 3 ) 2 SiO 0.5 unit 7.5 mol% 50 parts by mass of a resin-structured vinylmethylsiloxane (VMQ) consisting of the following formula:
Figure 0003897115
And 10 parts by weight of the organohydrogenpolysiloxane and 0.05 part by weight of a chloroplatinic acid octyl alcohol-modified solution, which were well stirred.
[0041]
After applying the liquid silicone resin composition, the silicone resin composition was cured by heating at 150 ° C. for 1 hour.
[0042]
After hardening, the remaining resist was dissolved by immersing the semiconductor element substrate 1 in an acetone solution (FIG. 6). After washing with acetone, the semiconductor element substrate 1 sealed with the organic resin sealing material 7 was dried at 150 ° C. for 1 hour.
[0043]
After the semiconductor element substrate is dried, the substrate is attached to a dicing tape, and a dicing saw is used to cut a portion that is not sealed with an organic resin. A sealed device 8 was obtained (FIG. 7).
[0044]
The individually stripped sealing device 8 obtained here was mounted on an organic substrate (package) 10 using an epoxy die bond agent 9 (FIG. 8).
[0045]
After mounting, the sealing device 8 and the organic substrate 10 were connected by the gold wire 11 (FIG. 9). Then, as shown in FIG. 10, the transparent glass lid 12 was adhered with an adhesive to complete the package. Alternatively, after connection, the package was completed by potting with silicone resin as shown in FIG.
[0046]
Further, after individually sealing the sealing device including the LED and the light emitting element (laser, etc.), the solder ball 14 is attached to the electrode on the semiconductor element substrate 1 (FIG. 12), and then the sealing device 8 is attached. When connected to the optical / electronic composite substrate 15 via solder balls, it was possible to easily mount a semiconductor element sealed with a resin that transmits light 6 (FIG. 13). In FIG. 13, 16 is an optical waveguide.
[0047]
【The invention's effect】
According to the sealing method of the present invention, an organic resin sealing material excellent in heat resistance, transparency and adhesiveness such as a silicone resin composition that is cured by heat or condensation reaction, which has been impossible in the past, is used at the wafer level. Only the circuit portion can be sealed and protected with high accuracy.
[0048]
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a semiconductor element substrate used in an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view of a semiconductor element substrate on which a resist layer is formed in an example of the present invention.
FIG. 3 is a schematic cross-sectional view showing a light irradiation step in an embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view of a semiconductor element substrate with a resist removed by light irradiation in an example of the present invention.
FIG. 5 is a schematic cross-sectional view of a semiconductor element substrate on which an organic resin sealing material is formed in an example of the present invention.
FIG. 6 is a schematic cross-sectional view of a semiconductor element substrate with a resist layer removed in an example of the present invention.
FIG. 7 is a schematic cross-sectional view of a sealed device that has been cut into individual pieces by cutting in an example of the present invention.
FIG. 8 is a schematic cross-sectional view showing an example in which the sealing device obtained by the present invention is die-bonded to a package.
FIG. 9 is a schematic sectional view showing an example in which the sealing device of the present invention is wire-bonded to a substrate.
FIG. 10 is a schematic cross-sectional view showing an example in which the sealing device is sealed with a glass lid.
FIG. 11 is a schematic cross-sectional view showing an example of potting the sealing device with a resin.
FIG. 12 is a schematic sectional view showing an example in which bumps are formed on the sealing device obtained in the present invention.
FIG. 13 is a schematic cross-sectional view showing an example in which a bump forming sealing device is mounted on a substrate.
14A and 14B are a plan view and a cross-sectional view showing an example of a semiconductor element substrate sealed with an organic resin sealing material.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Electrode 3 Circuit part 4 Positive resist layer 5 Photomask 6 Light 7 Organic resin sealing material 8 Sealing device 9 Die-bonding agent 10 Package 11 Gold wire 12 Glass lid 13 Transparent resin 14 Bump 15 Optical / electronic composite substrate 16 Optical waveguide

Claims (6)

基板表面に１又は複数の回路と電極とを形成してなる半導体素子の上記回路部分を樹脂封止する方法において、
（１）上記回路及び電極が設置された基板表面にポジ型レジスト材料を５〜１００μｍの厚みで塗布し、レジスト層を形成する工程、
（２）樹脂封止すべき回路部分のレジスト層のみ露光して、回路部分が現像液で除去されるようにレジスト層を選択的に露光し、次いで現像を行う工程、
（３）レジスト層が選択的に現像、除去されて露呈した樹脂封止すべき回路部分に付加反応硬化型もしくは室温硬化型シリコーン樹脂組成物又はエポキシ樹脂組成物からなる樹脂封止材をレジスト層と同じ膜厚になるように塗布し、この封止材を硬化させる工程、
（４）上記回路部分を封止する硬化樹脂層を溶解させず、残存レジスト層を溶解可能な溶剤を用いて残存レジスト層を除去する工程
を備えたことを特徴とする半導体素子の封止方法。In the method of resin-sealing the circuit portion of the semiconductor element formed by forming one or more circuits and electrodes on the substrate surface,
(1) A step of applying a positive resist material to a thickness of 5 to 100 μm on the substrate surface on which the circuit and electrodes are installed, and forming a resist layer;
(2) a step of exposing only the resist layer of the circuit portion to be resin-sealed, selectively exposing the resist layer so that the circuit portion is removed with a developer, and then developing;
(3) Resin sealing layer made of addition reaction curable type or room temperature curable type silicone resin composition or epoxy resin composition is applied to the circuit portion to be encapsulated, which is exposed by selectively developing and removing the resist layer. The process of applying the same film thickness as this and curing this encapsulant,
(4) A method for sealing a semiconductor element, comprising: a step of removing the remaining resist layer using a solvent capable of dissolving the remaining resist layer without dissolving the cured resin layer for sealing the circuit portion. . 基板表面に１又は複数の回路と電極とを形成してなる半導体素子の上記回路部分を樹脂封止する方法において、
（１）上記回路及び電極が設置された基板表面にネガ型レジスト材料を５〜１００μｍの厚みで塗布し、レジスト層を形成する工程、
（２）樹脂封止すべき回路部分のレジスト層のみ露光せずに、回路部分が現像液で除去されるようにレジスト層を選択的に露光し、次いで現像を行う工程、
（３）レジスト層が選択的に現像、除去されて露呈した樹脂封止すべき回路部分に付加反応硬化型もしくは室温硬化型シリコーン樹脂組成物又はエポキシ樹脂組成物からなる樹脂封止材をレジスト層と同じ膜厚になるように塗布し、この封止材を硬化させる工程、
（４）上記回路部分を封止する硬化樹脂層を溶解させず、残存レジスト層を溶解可能な溶剤を用いて残存レジスト層を除去する工程
を備えたことを特徴とする半導体素子の封止方法。In the method of resin-sealing the circuit portion of the semiconductor element formed by forming one or more circuits and electrodes on the substrate surface,
(1) A step of applying a negative resist material to a thickness of 5 to 100 μm on the surface of the substrate on which the circuit and electrodes are installed to form a resist layer;
(2) a step of selectively exposing the resist layer so that the circuit portion is removed with a developer without exposing only the resist layer of the circuit portion to be resin-sealed, and then developing;
(3) Resin sealing layer made of addition reaction curable type or room temperature curable type silicone resin composition or epoxy resin composition is applied to the circuit portion to be encapsulated, which is exposed by selectively developing and removing the resist layer. The process of applying the same film thickness as this and curing this encapsulant,
(4) A method for sealing a semiconductor element, comprising: a step of removing the remaining resist layer using a solvent capable of dissolving the remaining resist layer without dissolving the cured resin layer for sealing the circuit portion. . 半導体素子が複数の回路と電極とが形成されたものであり、上記工程（４）を行った後、樹脂封止した各回路部分を個別細片化するように基板を切断することを特徴とする請求項１又は２記載の半導体素子の封止方法。The semiconductor element is formed with a plurality of circuits and electrodes, and after performing the above step (4), the substrate is cut so that each resin-sealed circuit portion is individually cut into pieces. The method for sealing a semiconductor element according to claim 1 or 2 . 樹脂封止材が、無機蛍光体及び／又は光散乱剤を含有することを特徴とする請求項１乃至３のいずれか１項記載の半導体素子の封止方法。The method for sealing a semiconductor element according to any one of claims 1 to 3 , wherein the resin sealing material contains an inorganic phosphor and / or a light scattering agent. 樹脂封止材が、透明であることを特徴とする請求項１乃至４のいずれか１項記載の半導体素子の封止方法。Resin sealing material, the sealing method of a semiconductor device of any one of claims 1 to 4, characterized in that it is transparent. 半導体素子がＬＥＤ光デバイスであることを特徴とする請求項１乃至５のいずれか１項記載の半導体素子の封止方法。 The semiconductor element sealing method according to claim 1, wherein the semiconductor element is an LED optical device .
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Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7417220B2 (en) * 2004-09-09 2008-08-26 Toyoda Gosei Co., Ltd. Solid state device and light-emitting element
JP4676735B2 (en) * 2004-09-22 2011-04-27 東レ・ダウコーニング株式会社 Optical semiconductor device manufacturing method and optical semiconductor device
FR2880029B1 (en) * 2004-12-23 2007-02-16 Rhodia Chimie Sa NON-YELLOWING SILICONE COMPOSITION
EP1710847B1 (en) * 2005-04-08 2014-09-17 Nichia Corporation Light emitting device with silicone resin layer formed by screen printing
JP4954499B2 (en) * 2005-05-20 2012-06-13 信越化学工業株式会社 Silicone resin lens for LED and manufacturing method thereof
US8044412B2 (en) 2006-01-20 2011-10-25 Taiwan Semiconductor Manufacturing Company, Ltd Package for a light emitting element
US20090260740A1 (en) * 2006-01-25 2009-10-22 Paul Teel Drywall tape and mud dispenser
JP2007207921A (en) * 2006-01-31 2007-08-16 Stanley Electric Co Ltd Method for manufacturing surface-mounting optical semiconductor device
JP5268082B2 (en) * 2006-02-22 2013-08-21 シチズン電子株式会社 Optical semiconductor device
EP2041478B1 (en) * 2006-03-07 2014-08-06 QD Vision, Inc. An article including semiconductor nanocrystals
JP4745138B2 (en) * 2006-06-06 2011-08-10 電気化学工業株式会社 Method for producing silica powder
JP2008060542A (en) * 2006-08-03 2008-03-13 Toyoda Gosei Co Ltd Light-emitting device, method of manufacturing same, and light source device provided with the same
US8502364B2 (en) * 2006-08-22 2013-08-06 Mitsubishi Chemical Corporation Semiconductor device member, production method of semiconductor-device-member formation liquid and semiconductor device member, and semiconductor-device-member formation liquid, phosphor composition, semiconductor light-emitting device, lighting system and image display system using the same
JP2008218610A (en) * 2007-03-02 2008-09-18 Citizen Electronics Co Ltd Light-emitting diode
JP5321498B2 (en) * 2010-02-23 2013-10-23 信越化学工業株式会社 Method for forming encapsulant pattern
US20120068218A1 (en) * 2010-09-17 2012-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally efficient packaging for a photonic device
US9633883B2 (en) 2015-03-20 2017-04-25 Rohinni, LLC Apparatus for transfer of semiconductor devices
JP2016183225A (en) * 2015-03-25 2016-10-20 京セラ株式会社 Liquid transparent resin composition for sealing, wafer level chip size package, and semiconductor device
JP6637674B2 (en) * 2015-04-30 2020-01-29 信越化学工業株式会社 Printed wiring board, method for manufacturing printed wiring board, and semiconductor device
WO2018061722A1 (en) * 2016-09-30 2018-04-05 株式会社村田製作所 Module with built-in antenna and communication device
US10141215B2 (en) 2016-11-03 2018-11-27 Rohinni, LLC Compliant needle for direct transfer of semiconductor devices
US10504767B2 (en) 2016-11-23 2019-12-10 Rohinni, LLC Direct transfer apparatus for a pattern array of semiconductor device die
US10297478B2 (en) 2016-11-23 2019-05-21 Rohinni, LLC Method and apparatus for embedding semiconductor devices
US10471545B2 (en) 2016-11-23 2019-11-12 Rohinni, LLC Top-side laser for direct transfer of semiconductor devices
US10062588B2 (en) 2017-01-18 2018-08-28 Rohinni, LLC Flexible support substrate for transfer of semiconductor devices
US11171249B2 (en) * 2017-07-25 2021-11-09 Ams Sensors Singapore Pte. Ltd. Wafer-level methods for manufacturing uniform layers of material on optoelectronic modules
US10410905B1 (en) 2018-05-12 2019-09-10 Rohinni, LLC Method and apparatus for direct transfer of multiple semiconductor devices
US11094571B2 (en) 2018-09-28 2021-08-17 Rohinni, LLC Apparatus to increase transferspeed of semiconductor devices with micro-adjustment
US20220137230A1 (en) * 2020-10-30 2022-05-05 Waymo Llc Light Detection and Ranging (Lidar) Devices Having Vertical-Cavity Surface-Emitting Laser (VCSEL) Emitters

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976912A (en) * 1994-03-18 1999-11-02 Hitachi Chemical Company, Ltd. Fabrication process of semiconductor package and semiconductor package
US7137687B2 (en) * 2002-04-10 2006-11-21 Sony Corporation Liquid discharge head, liquid discharge apparatus, and method for forming liquid discharge head

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