JP3881441B2 - Time information evaluation apparatus and evaluation method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention separates time management information contained in a bitstream in which a plurality of types of encoded packets are multiplexed and a time base reference value used for decoding processing from the bit stream, and obtains the obtained time base reference value. The present invention relates to a time information evaluation apparatus that evaluates time by comparing synchronization information that is a time reference and time management information as a reference, and outputs a time adjustment signal for synchronization in the decoding process. In particular, for example, a video signal and an audio It is suitable for use in an MPEG system or the like, which is one of transmission systems that multiplex / separate packets obtained by encoding these signals while ensuring signal synchronization.
[0002]
[Prior art]
Various types of information such as text, audio, still images, and moving images are handled at the same time to express such information, and to meet the requirements for multimedia processing information and recording, MPEG (Moving Picture) Experts Group) system standards were considered. This system standard is ISO / IEC 13818-1. According to this system standard, a bit stream obtained by encoding and compressing images, sounds, and the like is multiplexed into one bit stream. This system standard stipulates packet multiplexing in which video data and audio data are divided into bit streams called packets, and additional information such as a header is attached to each packet for transmission. Further, in order to perform decoding and reproduction from the middle of the bitstream, the MPEG system uses a structural unit called a pack in which a plurality of packets are bundled. In this system, the bit stream structure is hierarchized into a hierarchical structure of an upper layer and a lower layer. In this hierarchy, information called a time stamp is embedded in the lower layer in order to synchronize the multiplexed video / audio data.
[0003]
Here, the time stamp is time information that defines when to perform decoding, display, output, etc., and is multiplexed in the top packet header of the compressed data packetized on the encoding side. In the system standard, presentation time stamps (Presentation Time Stamp: hereinafter referred to as PTS) that specify the time of playback output to ensure the accuracy of timing between compressed packet data, for example, simultaneous playback of video data and audio data A decoding time stamp (Decoding Time Stamp: hereinafter referred to as DTS) that specifies the decoding start time of the data is specified.
[0004]
The system standard defines a system time reference reference value (System Clock Reference: hereinafter referred to as SCR) and a program time reference reference value (hereinafter referred to as PCR). SCR and PCR are the settings for reproducing the time relationship set on the encoder side on the decoder side. calibration To do Used . Such settings and calibration A system time clock (hereinafter referred to as STC) is set as a reference time when performing the above. In order to stably operate the PLL (Phase Locked Loop) circuit that generates the STC of the decoder, the encoder sends the SCR and PCR transmission intervals at 700 ms or less and 100 ms or less, respectively.
[0005]
In the MPEG system, PTS and DTS are added to the bit stream on the encoder side with an accuracy of 1/90 kHz so as not to cause a timing shift during data reproduction from the viewpoint of synchronization accuracy. According to such a system standard, the decoder adjusts the difference between the time when the last byte of SCR or PCR arrives and the STC when using SCR or PCR. In the time adjustment, the counter that outputs the STC of the decoder at the moment of arrival sets the value indicated by SCR or PCR to ensure the synchronization relationship.
[0006]
By adopting such a system standard, the decoder separates audio data and video data encoded and compressed from the multiplexed bit stream, and also separates the PTS of both data. In the decoder, in order to fill in the difference between the PTSs obtained by this separation, for example, the data on either side is delayed and adjusted, thereby synchronizing the audio data and the video data in the data transmission. And audio playback is done.
[0007]
[Problems to be solved by the invention]
By the way, when considering the case of displaying NTSC (National Television System Committee) video data, the standard for displaying 30 frame images per second is 1/30 [ s] (= 33 ms). For example, when PTS and STC are compared when trying to decode an access unit indicating a frame unit, if the PTS value is greater than the STC value (STC <PTS), it is determined that the playback output time has not yet been reached. The playback screen is not output by the packet having the PTS value, and the screen that is played back with the packet data supplied at the previous playback output time is displayed on the screen. Therefore, the same screen continues to be displayed until the STC value reaches the next playback output time PTS, and the screen is frozen (freeze processing).
[0008]
The decoder also sets the PTS value of the arriving access unit to the STC value at the previous time adjustment, that is, the STC (STC before 1/30 [s]. _-1/30 ) The size is determined by the value (skip determination). At this time, the decoder performs adjustment processing for skipping one access unit so that the value of PTS becomes larger than the value of STC in the next determination (skip processing). As a result, the PTS value is obtained 1/30 [s] earlier from the access unit from the next time. In this case, at least one screen is skipped and displayed.
[0009]
In this way, the decoder adjusts the screen display time by freeze / skip processing so as to satisfy the system standard.
[0010]
However, since the DTS and PTS bit lengths are specified as 33 bits in the MPEG system, simply compare PTS between audio packets and video packets, or simply compare PTS and STC in these packets. When one value exceeds 33 bits, the value may return to zero. Due to this comparison, an error occurs in the time adjustment determination, and the display screen freezes or skips.
[0011]
It is an object of the present invention to provide a time information evaluation apparatus and an evaluation method therefor that eliminate such drawbacks of the prior art and prevent erroneous time adjustment that occurs when comparing PTS and STC.
[0012]
[Means for Solving the Problems]
In order to solve the above-described problem, the time information evaluation apparatus of the present invention holds first reference time signal output means for outputting a first reference time signal and a second reference time signal input from the outside. A time information evaluation apparatus comprising: a second reference time signal holding unit; and a comparison unit that compares the order of the first reference time signal and the second reference time signal and outputs a comparison result. When comparing the reference time signal of 1 and the second reference time signal, it has condition detection means for detecting that a condition for erroneously evaluating the comparison result is satisfied, and the detection result of the condition detection means The time information is evaluated based on the information.
[0013]
Here, the condition detection means outputs a detection signal for detecting that the condition for erroneously evaluating the comparison result is satisfied by detecting that the first reference time signal exceeds a predetermined number of bits. It is advantageous if the second reference time signal is a means for stopping the output of this detection signal by detecting that the predetermined number of bits has been exceeded.
[0014]
The condition detecting means is a first detecting means for detecting that the first reference time signal has exceeded a predetermined number of bits, and a second for detecting that the second reference time signal has exceeded a predetermined number of bits. It is desirable to have the detection means.
[0015]
The condition detecting means outputs a detection signal for detecting that the condition for erroneously evaluating the comparison result is established by detecting that the second reference time signal has reached the first predetermined value. More preferably, the second reference time signal is a means for stopping the output of the detection signal by detecting that the second reference time signal has reached the second predetermined value.
[0016]
In addition to this, the condition detecting means advantageously has a difference output means for taking a difference between the first reference time signal and the second reference time signal and outputting difference data of a predetermined number of bits according to the difference. It is.
[0017]
The condition detection means includes a first carry-up detection means for detecting a change from the full count state of the first reference time signal, and a first carry-up detection for detecting a change from the full count state of the second reference time signal. And state detection means for detecting that the outputs of both the first carry-up detection means and the second carry-up detection means are in the same state, and the state detection means is configured to detect when an overflow condition is detected. It is preferable to clear the values of the first and second carry-up detection means.
[0018]
The time information evaluation apparatus according to the present invention avoids the processing performed in association with the error by detecting an error in the comparison result between the first reference time signal and the second reference time signal by the condition detecting means. This prevents malfunctions.
[0019]
Further, the time information evaluation method of the present invention is a time information evaluation method for comparing the first reference time signal and the second reference time signal input from the outside, and the first reference time signal. A condition detection step of detecting that a condition for erroneously evaluating the comparison result with the second reference time signal is satisfied, and outputting a detection signal in accordance with the detection, and a first reference time based on the detection signal And a step of masking based on a comparison of the context of the signal and the second reference time signal.
[0020]
Here, the condition detecting step outputs a detection signal for detecting that the condition for erroneously evaluating the comparison result is established by detecting that the first reference time signal exceeds a predetermined number of bits. Preferably, this is a step of stopping the output of the detection signal by detecting that the second reference time signal exceeds a predetermined number of bits.
[0021]
The condition detection step outputs a detection signal for detecting that the condition for erroneously evaluating the comparison result is satisfied by detecting that the second reference time signal has reached the first predetermined value. More preferably, this is a step of stopping the output of the detection signal by detecting that the second reference time signal has reached the second predetermined value.
[0022]
In the time information evaluation method of the present invention, an error in the comparison result between the first reference time signal and the second reference time signal is detected in the condition detection step, and when this detection signal is generated, the first reference time is detected. By performing the process in the step of masking the context of the signal and the second reference time signal, the process performed in association with this error is avoided and the malfunction is prevented.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of a time information evaluation apparatus according to the present invention will be described in detail with reference to the accompanying drawings.
[0024]
The time information evaluation apparatus of the present invention is an MPEG which is one of transmission systems for transmitting information by multiplexing and demultiplexing packets encoded with these signals while ensuring synchronization of video signals and audio signals. The present invention is applied to, for example, a time stamp evaluation circuit such as a system, and will be described with reference to FIGS. The time stamp evaluation circuit is used for the reception system (or demodulation side) in the transmission / reception system, and the time relationship of the processing performed on the transmission system (or encoding side) with respect to the supplied bit stream is accurately received by the reception system. This is a circuit for evaluating the synchronous reproduction reproduced in the above. The present invention has a feature of preventing freeze and stop phenomenon caused by malfunction of a time stamp evaluation circuit in an MPEG system.
[0025]
FIG. 1 shows a first embodiment of a time stamp evaluation circuit 10 to which the present invention is applied. The time stamp evaluation circuit 10 basically includes an STC counter 11, a PTS register 12, a condition detection unit 13, a comparison unit 14, an evaluation storage unit 15, and a timing adjustment unit 16. Here, the time stamp evaluation circuit 10 is supplied with a plurality of types of encoded packets included in the multiplexed bitstream, for example, PTS and decoding processing, for example, SCR separated from the bitstream, respectively. ing.
[0026]
The STC counter 11 is a counter that operates with a 90 kHz clock CLK90 set in order to set the counter with the supplied SCR and maintain synchronization with the television signal. The STC counter 11 outputs a system time clock (hereinafter referred to as STC). That is, STC (synchronization information) that is a time reference is output based on the supplied SCR. The STC counter 11 is specified to represent a value measured with a 90 kHz clock in 33-bit length in order to ensure the accuracy of PTS. A load signal CRLOADN is supplied from the outside to the counter set. The STC counter 11 takes in the SCR when the load signal CRLOADN is at the level “L” with negative logic.
[0027]
The PTS register 12 is a storage unit that stores the supplied PTS. As described above, since the PTS is represented by a 33-bit length, the register has a 33-bit width. The PTS register 12 also operates with the clock CLK90. The PTS register 12 captures PTS as data in the register when the supplied load signal TSLOADN is at the level “L” and the clock CLK90 rises.
[0028]
The condition detection unit 13 detects whether a condition for erroneous evaluation that occurs when using PTS and STC is satisfied. Along with this detection, the condition detection unit 13 adjusts PTS and STC or avoids the establishment of the condition. In this embodiment, the condition detection unit 13 supplies a signal indicating that the condition is satisfied to the comparison unit 14. As will be described later, the comparison unit 14 determines whether to determine the supplied data as it is based on whether a bit indicating that the condition is satisfied is set.
[0029]
The condition detection unit 13 is disposed in front of the comparison unit 14. In this embodiment, the condition detection unit 13 detects a change occurring in the value of the 34th bit exceeding the 33-bit length defined in the outputs of the STC counter 11 and the PTS register 12. In other words, the condition detection unit 13 detects whether any of the STC counter 11 and the PTS register 12 is in a state where it exceeds 33 bits and returns to zero (boundary with a discontinuous value) based on an overflow state.
[0030]
As an example of a configuration for detecting overflow, the condition detector 13 is a carry-up detector 13a that detects a change in the count output of the STC counter 11 from the full count state, and this PTS based on the PTS value output from the PTS register 12. A carry-up detection unit 13b that detects a change in the most significant bit from the full-count state, and a state detection unit 13c that detects that both the carry-up detection units 13a and 13b are in the carry signal detection state. When a carry signal is supplied, the carry-up detection units 13a and 13b immediately change the output level to “H” and supply it to the comparison unit 14 as the 34th bit. The state detection unit 13c uses an AND circuit, and the state detection unit 13c carries out a clear signal CLEAR to the carry-up detection units 13a and 13b when both the carry-up detection units 13a and 13b carry up and an overflow state is detected. Supply. The carry-up detection units 13a and 13b clear both stored values. The carry-up detection unit 13a may be configured using, for example, a counter or an arithmetic operation register, and the carry-up detection unit 13b may be configured using, for example, an arithmetic operation register. The carry-up detection unit 13b compares the value stored in the PTS register 12 and the data supplied via the input port C in order to detect the presence or absence of an overflow condition.
[0031]
The comparison unit 14 compares the supplied STC and PTS to determine the synchronization shift. In this case, the synchronization loss means that when the PTS supplied to the STC is large, the PTS is supplied early, and when the PTS supplied to the STC is small, the PTS is supplied late. . Signals PTSBIG and STCBIG corresponding to this comparison are output to the evaluation storage unit 15. However, STC _-1/30 When ≦ PTS ≦ STC, the signals PTSBIG and STCBIG are output at the level “L” so as not to adjust the time. Further, in order to eliminate the comparison result due to the reset of the counter, the comparison unit 14 performs a size comparison in a state where the bit exceeds 33 bits and returns to zero, by adding the 34th bit of STC and PTS. The comparison unit 14 is configured to be able to compare 34 bits in length.
[0032]
The evaluation storage unit 15 stores the comparison result supplied from the comparison unit 14 as evaluation information. The evaluation storage unit 15 includes registers 15a and 15b for storing two obtained comparison results, respectively. The registers 15a and 15b operate with the clock CLK90. The evaluation storage unit 15 outputs output signals PTSFAST and PTSSLOW from the registers 15a and 15b, respectively.
[0033]
The timing adjustment unit 16 is a register that stores and outputs a signal supplied by the clock CLK90. The timing adjustment unit 16 functions as a delay element by temporarily storing the supplied load signal TSLOADN in the timing adjustment unit 16 at the rising timing of the clock CLK90 and outputting the data stored at the next rising of the clock CLK90 as a signal. Have. The load signal TSLOADN becomes a timing signal delayed by one clock of the clock CLK90 and is output to the evaluation storage unit 15 as the load signal TSLOAD1DN.
[0034]
Next, the operation of the time stamp evaluation circuit 10 will be described with reference to the timing charts of FIGS. Here, FIG. 2 shows an arrangement of timing charts divided at timing T4. The signals and output signals used in the time stamp evaluation circuit 10 will be briefly described. For example, SCR is supplied to the time stamp evaluation circuit 10 from the input port A on the input side as a clock reference to the STC counter 11 (see FIG. 3B). Here, the value of the supplied SCR is represented by CR [32: 0]. The load signal CRLOADN supplied from the input port B is a timing signal when CR [32: 0] is taken into the STC counter 11 (see FIG. 3 (c)). For the time stamp supplied from the input port C, for example, PTS is used and is represented by TS [32: 0] for convenience (see FIG. 3 (d)). The load signal TSLOADN supplied from the input port D is a timing signal when TS [32: 0] is taken into the PTS register 12 (see FIG. 3 (e)). From the input port E, a clock CLK90 is input as a basic clock for operating the time stamp evaluation device 10 (see FIG. 3 (a)). The symbol [32: 0] indicates that CR [32: 0] and TS [32: 0] supplied from the input ports A and C are 33 bits long from 0 to 32 bits. Using this notation, the signals STC [33] and PTS [33] indicate the 34th bit.
[0035]
The STC counter 11 sets CR [32: 0] = 0x1fffffffc to the STC counter 11 at the timing T1 when the load signal CRLOADN is at the level “L” and the clock CLK90 rises. As a result, the STC counter 11 changes the output after timing T1, that is, the value of STC [32: 0], from 0x1fffffff8 to 0x1fffffffc (see FIG. 3 (f)).
[0036]
Next, PTS [32: 0] = 0x1fffffffb is set in the PTS register 12 at the timing T2 when the load signal TSLOADN is at the level “L” and the clock CLK90 rises. As a result, the PTS register 12 has an output PTS [32: 0] of 0x1fffffffb from timing T2 until the next data load to the PTS register 12 is enabled (see Fig. 3 (h)). ).
[0037]
At timing T2, the data set in the STC counter 11 and the PTS register 12 are supplied to the comparator 14 via the condition detector 13. In this case, since the condition is not satisfied, the condition detection unit 13 supplies the outputs of the STC counter 11 and the PTS register 12 to the comparison unit 14 as they are. The comparison unit 14 performs size comparison based on the respective values obtained at the timing T2. When comparing the STC and PTS values, the STC value is larger. However, the comparison unit 14 _-1/30 When ≦ PTS ≦ STC, the level “L” is set to be output during this period so as not to adjust the time. Therefore, output signals PTSBIG and STCBIG are output at the level “L” as a comparison result from the comparison unit 14 (see FIG. 3 (l) and FIG. 3 (n)).
[0038]
In the registers 15a and 15b of the evaluation storage unit 15, the timing signal TSLOAD1DN obtained by delaying the load signal TSLOADN by one clock in the timing adjustment unit 16 becomes the level “L” (see FIG. 3 (k)), and the clock CLK90 The output signal PTSBIG is captured at the timing T3 at the rising edge. The registers 15a and 15b output the evaluation signals PTSFAST and PTSSLOW at the level “L” at the next rising edge of the clock CLK90 (ie, timing T4), respectively.
[0039]
By the way, at the timing T4 when the time corresponding to 4 clocks has elapsed from the timing T1, the STC counter 11 changes from the state in which all 33-bit length bits are set to zero as shown in FIG. 4 (f). The comparison unit 14 compares STC [32: 0] = 0x000000000 and PTS [32: 0] = 0x1fffffffb when comparing only the 33-bit STC and PTS values supplied after timing T4. A normal comparison is performed because it is out of the rules for the time domain for which comparison is prohibited. The comparison unit 14 outputs a comparison result when the value of PTS is larger (see the hatched portion in FIG. 4 (l)). The comparison judgment is performed during such a comparison prohibition period, and the output becomes the level “H” because the relationship between the values of PTS and STC is PTS <STC (ie, data PTS [32: 0] Will be taken into PTS register 12 as 0x000000001). This output is output from the register 15a when the load signal TSLOAD1DN of FIG. 4 (k) is at the level “L” and the clock CLK90 rises (timing T6). This level output continues until timing T8 when the load signal TSLOAD1DN becomes the next level "L". Originally, the time stamp evaluation circuit must output the level “L” while prohibiting comparison during the period from the timing T4 to T7.
[0040]
Here, in the time stamp evaluation circuit 10 to which the present invention is applied, the STC counter 11 generates the carry signal STC [33] at the timing T4 (see FIG. 4 (g)). The carry signal STC [33] is supplied to the carry-up detection unit 13a of the condition detection unit 13. The carry-up detection unit 13a outputs the 34th bit data to the state detection unit 13c and the comparison unit 14 almost simultaneously when the carry signal STC [33] is supplied. The carry-up detection unit 13a keeps the carry state for a certain period of time when the count value changes to zero, which is likely to make a comparison error, and releases the carry state when normal operation is ensured. Release will be described later.
[0041]
The PTS register 12 takes in the value of PTS when the supplied load signal TSLOADN is enabled (see FIG. 4E) and the clock CLK90 rises at timing T5. At this time, the value of PTS read into the PTS register 12 is a value advanced by 4 clocks from the timing T1, that is, 0x1fffffffe (see FIG. 4 (h)). Since the value of the PTS register 12 is not updated until the timing T7 when the load signal TSLOADN in FIG. 4 (e) becomes the level “L” (see FIG. 4 (h)), the data PTS shown in FIG. Even if [32: 0] reaches 0x000000001 at timing T6, the carry-up signal PTS [33] is not output from the carry-up detection unit 13b because this value is not captured (see FIG. 4 (i)). The carry-up detection unit 13b compares the 33rd bit PTS [32] of the PTS register 12 with the 33rd bit of the data TS [32: 0] supplied from the input port C, that is, TS [33], and carries the carry signal PTS. [33] is going to occur. When the carry signal PTS [33] is generated, it is supplied to the comparator 14 as the 34th bit data almost simultaneously, and is also output to one end of the state detector 13c.
[0042]
Here, since the state detection unit 13 detects that both the STC and PTS values exceed the discontinuous boundary at timing T7, the state detection unit 13 determines that the range causing the malfunction has passed and determines the carry-up detection units 15a and 15b. Each clear signal is supplied (see Fig. 4 (J)). As a result, the carry-up detection units 15a and 15b are both released from the detection state.
[0043]
On the other hand, the comparison unit 14 is out of the protection time region when compared with 33 bits as in the conventional case, but STC [33] and STC [32: 0] are combined as in the present embodiment. By comparing the value represented by the bit with the value of PTS, the comparison unit 14 determines that the value of PTS is smaller (PTS <STC). Further, at this time, the comparison unit 14 performs the protection time region (STC _-1/30 ≦ PTS ≦ STC), the function of not adjusting the time is exhibited and the output signals PTSBIG and STCBIG are output at the level “L”. Therefore, the evaluation storage registers 15a and 15b output the output signals PTSFAST and PTSSLOW at the level “L”.
[0044]
Further, the time stamp evaluation at timing T7 will be described. The PTS register 12 takes in a value. Here, at timing T7, STC [33] is level “H” and STC [32: 0] = 0x000000004 of the STC counter 11, so the value STC [33: 0] supplied to the comparison unit 14 is 0x200000004. . The carry-up detector 13b generates a carry signal PTS [33] at timing T6. Therefore, the value PTS [33: 0] supplied to the comparison unit 14 is 0x200000001. When the value STC [33: 0] is compared with the value PTS [33: 0], the comparison unit 14 has a relationship of PTS <STC and outputs a level “L” as a protection time region. The comparison unit 14 can operate normally without causing an error STC> PTS near the discontinuous boundary.
[0045]
By operating in this way, it is possible to avoid an error that occurs near the boundary where the count becomes discontinuous by resetting the counter. By accurately evaluating the time relationship used by the time stamp evaluation circuit 10 for reproduction synchronization, unnecessary freezes and skips appear and it is possible to avoid display that is difficult to see.
[0046]
Next, a second embodiment of the time stamp evaluation circuit 10 to which the present invention is applied will be described. The basic configuration is the same as that of the first embodiment. For this reason, the same reference numerals are given to the common parts.
[0047]
As shown in FIG. 5, the condition detection unit 13 includes a determination prohibition detection unit 13d that detects a period during which a wrong evaluation condition is satisfied, and outputs of the determination prohibition detection unit 13d and the timing adjustment unit 16. And a mask part 13e for taking a logical sum.
[0048]
Here, reproduction in the MPEG standard is performed in units of access units. An access unit unit means a frame unit in a video signal. Therefore, when the NTSC television system is used, the transmission system has a time adjustment of 1/30 [s], that is, every 33 [ms]. Done, STC and PTS values are within 1/30 [s]. During this time, the STC counter 11 counts 3000 (0xbb8). In other words, in the case of video, the count value indicates that there is a PTS value before the discontinuity boundary and within 1/30 [s] (range 0x1fffff448 ≤PTS ≤0x1ffffffff) and STC When the value of is set to zero, the comparison unit 14 _-1/30 ≤PTS ≤STC is out of the period. Since the comparison unit 14 performs a normal size comparison, the signals PTSBIG and STCBIG make an inaccurate determination without outputting the level “L” so as not to adjust the time.
[0049]
The determination prohibition detection unit 13d is supplied with the output PTS [32: 0] from the PTS register 12. The determination prohibition detection unit 13d determines the upper 21 bits out of the 33-bit length. If these upper 21 bits are all level “H”, it means that the period has been reached within 1/30 [s]. When the judgment prohibition detection unit 13d detects a time region within the period of 1/30 [s], the comparison result transmission prohibition signal MASK is sent to the mask unit 13e at the level “H”, otherwise Level “L” is transmitted in the time domain.
[0050]
The mask unit 13e is a two-input OR circuit. The output TSLOAD1DN from the timing adjustment unit 16 is supplied to one end side of the OR circuit, and the output (prohibition signal MASK) from the determination prohibition detection unit 13d is supplied to the other end side. The mask unit 13e outputs a load signal ENABLEN that enables the data storage operation to each register of the evaluation storage unit 15. However, the load signal ENABLEN is a timing signal for disabling operation during the above-described condition establishment period.
[0051]
The operation of the time stamp evaluation circuit 10 will be described with reference to the timing charts of FIGS. FIG. 6 shows a layout when the timing charts of FIGS. 7 and 8 are divided before the timing T13. In the timing charts of FIGS. 7 and 8, in addition to the signals used in FIGS. 3 and 4, a prohibition signal MASK for temporarily prohibiting the evaluation of the time stamp evaluation circuit 10 and a signal ENABLEN indicating the enable state of the evaluation storage unit 15 Is used.
[0052]
CR [32: 0] = 0x1ffffeffe supplied via the input port A to the STC counter 11 at the timing T10 of the rising edge of the clock CLK90 and the load signal CRLOADN supplied via the input port B becomes level “L”. Is set. Further, at the timing T11 when the load signal TSLOADN becomes level “L” and the clock CLK90 rises, the PTS register 12 stores TS [32: 0] = 0x1ffffeffc supplied via the input port C. The load signal TSLOADN is delayed by one clock in the timing adjustment unit 16 (see the load signal TSLOAD1DN in FIG. 3 (i)). Data having a 21-bit width higher than the 13th bit output from the PTS register 12 is supplied to the determination prohibition detection unit 13d. At timing T11, the determination prohibition detection unit 13d determines that the supplied data is not yet reached within the period within 1/30 [s] of prohibition of determination because the supplied data is smaller than 0x1ffffc and 0x1fffff. By this determination, the determination prohibition detection unit 13d outputs a signal of level “L” to the mask unit 13e (see FIG. 7 (h)). The mask unit 13e calculates the logical sum of the load signal TSLOAD1DN and the output from the determination prohibition detection unit 13d and outputs the load signal ENABLEN to the evaluation storage unit 15.
[0053]
On the other hand, the comparison unit 14 compares the values of the data STC [32: 0] and PTS [32: 0] supplied at the timing T11. At this time, the comparison unit 14 determines that the value of the data STC [32: 0] is larger than the value of PTS [32: 0] _-1/30 Since ≦ PTS ≦ STC, the output signal PTSBIG and the output signal STCBIG are output at the level “L” (see FIG. 7 (k) and FIG. 7 (m)). This signal is stored in the registers 15a and 15b at timing T12. As a result, after one more clock, the registers 15a and 15b output the output signal PTSFAST in FIG. 7 (l) and the output signal PTSSLOW in FIG. 7 (n).
[0054]
When the time further elapses and, for example, the load signal TSLOADN becomes level “L” at timing T13 shown in the timing chart of FIG. 7, 0x1fffffffe is set in the PTS register 12. At this time, the STC counter 11 outputs a count value based on, for example, a value set after the timing T10. The comparison unit 14 compares the supplied data STC [32: 0] = 0x000000000 with the data PTS [32: 0] = 0x1fffffffe. Since the value of the data PTS [32: 0] is larger, the comparison unit 14 sets the output signal PTSBIG to the level “H”. This level “H” continues until timing T16 when the next PTS [32: 0] is set. When the load signal TSLOADN becomes level “L” at timing T13, the data PTS [32: 0] = 0x1fffffffe is set in the PTS register 12 at timing T14.
[0055]
The upper 21 bits of the data supplied to the PTS register 12 are supplied to the determination prohibition detection unit 13d. The judgment prohibition detection unit 13d determines that the bit supplied at timing T14 is all “1”, and therefore immediately determines that it has entered a dangerous time region that would cause an error in judgment. Set to “H” (see FIG. 8 (g)). This mask signal is output to one end side of the mask portion 13e.
[0056]
Regardless of the output from the timing adjustment unit 16 (the signal TSLOAD1DN shown in FIG. 8 (i)), the mask unit 13e immediately takes the logical sum with the signal corresponding to the output of the determination prohibition detection unit 13d and outputs it. The signal ENABLEN is output at the level “H” as before (see FIG. 8 (j)). The load signal ENABLEN is supplied to the evaluation storage unit 15.
[0057]
When the comparison is performed by the comparison unit 14 as in the conventional case, the output from the comparison unit 14 at timing T15 is the evaluation storage unit as indicated by the broken line because the signal PTSBIG in FIG. Fifteen registers 15a are loaded. The output at this level is because the data STC [32: 0] supplied to the comparison unit 14 after the timing T13 is reset as described above. _-1/30 When ≦ PTS ≦ STC, it is no other than the condition that the time adjustment is not performed. The comparator 14 outputs another output signal STCBIG at the level “L” (see FIG. 8 (m)). If the signal level stored at the timing T16 is output from the evaluation storage unit 15 after the output from the comparison unit 14 is stored in the evaluation storage unit 15, the time stamp evaluation circuit 10 erroneously performs time information evaluation. Therefore, in the time stamp evaluation circuit 10, a time information evaluation error occurs during a period in which the level “L” is supplied as shown by the load signal TSLOAD1N in FIG. 8 (i), that is, a period from timing T15 to T17.
[0058]
Here, as in this embodiment, if the load signal ENABLEN supplied to the evaluation storage unit 15 at this time is at the level “H” due to the prohibition of determination, the register 14 is output even though the comparison unit 14 is output. It is not stored in 15a and 15b, and after the timing T15, it is determined as the determination prohibition period, and the level “L” is still output. Therefore, an error in time information evaluation that occurs during this period can be avoided.
[0059]
Next, at timing T16, the PTS register 12 captures and sets the data (0x000000001) of FIG. 8 (g). The data (0x000000001) stored from the PTS register 12 is supplied to the determination prohibition detection unit 13d. The determination prohibition detection unit 13d determines from this data that the determination prohibition period has been exceeded, and immediately sets the level of the mask signal MASK in FIG. 8 (h) to the level “L”. When the comparison unit 14 compares the data (0x000000004) from the STC counter 11 and the data (0x000000001) from the PTS register 12 at timing T16, the data relationship (STC _-1/30 Since ≦) PTS ≦ STC, both the output signal PTSBIG and the output signal STCBIG are output at the level “L” without performing time adjustment.
[0060]
Further, a third embodiment to which the present invention is applied will be described. The STC counter 11, the PTS register 12, the comparison unit 14, the evaluation storage unit 15, and the timing adjustment unit 16 are exactly the same as those described in the first embodiment. In the present embodiment, as shown in FIG. 9, the condition detector 13 uses a differentiator 13f. The subtractor 13f is the lower order of the data obtained from the difference (STC [32: 0]-PTS [32: 0]) of the 33-bit data of the supplied PTS [32: 0] and STC [32: 0] The 13 bits are output to the comparison unit 14. However, the 13th bit is a sign flag. The output from the differentiator 13f is the output signal SUB [12: 0]. Since the output signal SUB [12: 0] represents a period of 1/30 [s], the value of the thirteenth bit means whether or not the discontinuity boundary has been exceeded.
[0061]
The comparator 14 outputs the output signals PTSBUG and STCBIG depending on whether the output signal SUB [12: 0] is a positive or negative value. That is, when the output signal SUB [12: 0] is a negative value, the output signal PTSBIG outputs the level “H”. When the output signal SUB [12: 0] is a positive value, the output signal STCBIG outputs a level “H”. Further, the comparison unit 14 performs the STC in the same manner as in the first and second embodiments described above. _-1/30 When ≦ PTS ≦ STC, the output signals PTSBUG and STCBIG are set to “L” level and output so as not to adjust the time.
[0062]
Next, the operation in the configuration of the present embodiment will be briefly described with reference to the timing charts of FIGS. Here, FIG. 10 shows a layout when the timing chart shown in FIGS. 11 and 12 is divided at timing T24. Since the load signal CRLOADN in FIG. 11 (c) is at the level “L” at the rise of the clock CLK90 in FIG. 11 (a), the data 0x1fffffffc at the time of loading in FIG. 11 (b) is set in the STC counter 11 ( (See timing T21 in FIG. 11 (f)). At timing T22, the load signal TSLOADN becomes level “L”. Thereby, the data TS [32: 0] = 0x1fffffffb supplied from the input port C is stored in the PTS register 12. At this time, the differentiator 13f outputs STC [32: 0] -PTS [32: 0] = 0x0003.
[0063]
The comparison unit 14 is supplied with a positive value because the 13th bit (= SUB [12]) is zero in the output of the differentiator 13f, and outputs the output signal PTSBIG at the level “L”. (See Figure 11 (j)). In addition, since the supplied difference data SUB [12: 0] is smaller than the value of 0xbb8 indicating the time domain of 1/30 [s], STC _-1/30 The output signal STCBIG is determined to be within the range of ≦ PTS ≦ STC and output at the level “L” (see FIG. 11 (l)). Since the load signal TSLOAD1DN is at the level “L” at timing T23, the registers 15a and 15b of the evaluation storage unit 15 store the output signals PTSBIG and STCBIG, respectively. The signal levels stored in the registers 15a and 15b are output from the output ports F and G as the time evaluation of the time stamp.
[0064]
Next, the timing T24 is at the position of the discontinuous boundary from the state in which all 33 bits of the STC counter 11 are set (0x1ffffffff) to the reset state (0x000000000). At this time, the load signal TSLOADN is at the level “L” between timing T24 and timing T25 (see FIG. 12 (e)). Therefore, data TS [32: 0] = 0x1fffffffe is stored in the PTS register 12 at timing T25. The subtractor 13f has a negative operation result because STC [32: 0] is zero. However, since the differentiator 13f outputs only the lower 13 bits (= SUB [12: 0]), the comparison unit 14 determines that the value is a positive value (0x0005). The new load signal TSLOADN becomes level “L” at timing T25, but SUB [12: 0] = 0x0003 is output from the differentiator 13f to the comparator 14 (see FIG. 12 (h)). The comparison unit 14 outputs the output signals PTSBIG and STCBIG to the registers 15a and 15b from the supplied data at the level “L” (see FIGS. 12 (j) and (l)). Also in this case, the level “L” is output from the output ports F and G (see FIGS. 12 (k) and 12 (m)). When data is stored in the PTS and register 12 at timing T26 in FIG. 12 and the comparison result is fetched at timing T28, the data is supplied in the same way as described above so that the comparison result is not erroneous. Can be prevented.
[0065]
The time stamp evaluation apparatus 10 can make an accurate determination without performing complicated control for erroneous determination that occurs in the vicinity of a discontinuous boundary. In the present embodiment, the present invention has been described with a specific circuit configuration. First, the PTS value is taken in accordance with the enable state of the load signal TSLOADN, and the difference from the current STC value is taken. Thus, it is possible to make a positive / negative determination with only the lower 13 bits and finally evaluate the time stamp without error in consideration of the rules of the time domain. Because of this simple algorithm, the evaluation can be performed without error with a small number of program steps, and can be easily realized by software.
[0066]
By configuring in this way, the time stamp evaluation apparatus 10 can avoid malfunctions near the discontinuity boundary. Therefore, when data transmitted using this evaluation result is reproduced, unnecessary errors due to malfunctions that have sometimes occurred in the past are unnecessary. Occurrence of a freeze state or a skip state can be suppressed.
[0067]
The embodiment according to the present invention has been described with respect to a system to which the MPEG standard is applied. However, the present invention is not limited to this embodiment. For example, data of a finite length such as a video PTS and an audio PTS are compared with each other. It can be applied to a circuit or the like. In the second embodiment, the input bits to the determination prohibition detection means are limited to only the upper bits of the PTS. However, all the bits may be used, or the detailed calculation may be performed using the output value of the STC counter. Good. In the third embodiment, the output of the differentiator 13f is limited to the lower 13 bits. However, an arbitrary number of bits may be used.
[0068]
【The invention's effect】
As described above, according to the time information evaluation apparatus of the present invention, an error in the comparison result between the first reference time signal and the second reference time signal is detected by the condition detection means, and the error is performed along with this error. By avoiding the processing and preventing the malfunction, unnecessary occurrence of, for example, image freezing or skipping within a predetermined protection time region can be completely eliminated.
[0069]
Further, according to the time information evaluation method of the present invention, an error in the comparison result between the first reference time signal and the second reference time signal is detected in the condition detection step, and when this detection signal is generated, By processing in the step of masking the context of the first reference time signal and the second reference time signal, and avoiding the processing that has been performed in accordance with this error to prevent malfunction, it is possible to keep within a predetermined protection time region. For example, it is possible to provide an easy-to-view image without completely generating, for example, image freeze or skip.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a block configuration of a first embodiment in which a time evaluation apparatus of the present invention is applied to a time stamp evaluation circuit.
FIG. 2 is a timing chart layout diagram for explaining the operation of the time stamp evaluation circuit shown in FIG. 1;
FIG. 3 is a timing chart for explaining the operation of the time stamp evaluation circuit shown in FIG. 1;
4 is a timing chart for explaining the continuation of the operation of the time stamp evaluation circuit shown in FIG. 3. FIG.
FIG. 5 is a block diagram showing a block configuration of a second embodiment in which the time evaluation apparatus of the present invention is applied to a time stamp evaluation circuit.
6 is a layout diagram of a timing chart for explaining the operation of the time stamp evaluation circuit shown in FIG. 5. FIG.
7 is a timing chart for explaining the operation of the time stamp evaluation circuit shown in FIG. 5;
8 is a timing chart for explaining the continuation of the operation of the time stamp evaluation circuit shown in FIG.
FIG. 9 is a block diagram showing a block configuration of a third embodiment in which the time evaluation apparatus of the present invention is applied to a time stamp evaluation circuit.
FIG. 10 is a timing chart layout diagram for explaining the operation of the time stamp evaluation circuit shown in FIG. 9;
11 is a timing chart for explaining the operation of the time stamp evaluation circuit shown in FIG. 9;
12 is a timing chart for explaining the continuation of the operation of the time stamp evaluation circuit shown in FIG.
[Explanation of symbols]
10 Time stamp evaluation circuit
11 STC counter
12 PTS register
13 Condition detector
14 Comparison part
15 Evaluation storage
16 Timing adjustment section

Claims (9)

First reference time signal output means for outputting a first reference time signal generated internally ;
Second reference time signal holding means for holding a second reference time signal input from the outside;
A time information evaluation apparatus comprising: a comparison unit that compares the first and second reference time signals with each other and compares the first and second reference time signals and outputs the comparison result;
When comparing the first reference time signal and the second reference time signal, it has condition detection means for detecting that a condition for erroneously evaluating the comparison result is satisfied,
A time information evaluation apparatus for evaluating time information based on a detection result of the condition detection means. 2. The apparatus according to claim 1, wherein the condition detection unit detects that the first reference time signal exceeds a predetermined number of bits, thereby satisfying a condition for erroneously evaluating the comparison result. A time signal for detecting that the second reference time signal has exceeded a predetermined number of bits, and outputting the detection signal to stop the output of the detection signal. Evaluation device. 3. The apparatus according to claim 1, wherein the condition detection unit detects the first reference time signal exceeding a predetermined number of bits, and
And a second detection means for detecting that the second reference time signal exceeds a predetermined number of bits. The apparatus according to claim 1, wherein the condition detection unit detects that the second reference time signal has reached a first predetermined value, thereby satisfying a condition for erroneously evaluating the comparison result. A time signal which is a means for outputting a detection signal for detecting that the second reference time signal has reached a second predetermined value and stopping the output of the detection signal. Information evaluation device. 2. The apparatus according to claim 1, wherein the condition detecting unit takes a difference between the first reference time signal and the second reference time signal and outputs difference data having a predetermined number of bits according to the difference. A time information evaluation apparatus having a difference output means. 2. The apparatus according to claim 1, wherein the condition detection unit includes a first carry-up detection unit that detects a change from a full count state of the first reference time signal;
Second carry-up detection means for detecting a change from a full count state of the second reference time signal;
State detecting means for detecting that the outputs of the first carry-up detecting means and the second carry-up detecting means are both in the same state, and the state detecting means is configured to detect when an overflow condition is detected. A time information evaluation apparatus characterized by clearing the values of the first and second carry-up detection means. In the time information evaluation method for comparing the context of the first reference time signal generated internally and the second reference time signal input from the outside, the method includes:
A condition detection step of detecting that a condition for erroneously evaluating a comparison result between the first reference time signal and the second reference time signal is satisfied, and outputting a detection signal along with the detection; and
A time information evaluation method comprising: a step of masking based on a comparison of front and back relations between the first reference time signal and the second reference time signal based on the detection signal. 8. The method according to claim 7, wherein the condition detection step detects that the first reference time signal has exceeded a predetermined number of bits, thereby satisfying a condition for erroneously evaluating the comparison result. Output of a detection signal for detecting whether the second reference time signal exceeds a predetermined number of bits, and stopping the output of the detection signal by detecting that the second reference time signal has exceeded a predetermined number of bits Evaluation methods. 8. The method according to claim 7, wherein the condition detecting step detects that the comparison result is erroneously detected by detecting that the second reference time signal has reached a first predetermined value. Outputting a detection signal for detecting that the second reference time signal has reached a second predetermined value, and stopping the output of the detection signal by detecting that the second reference time signal has reached a second predetermined value Information evaluation method.

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