JP3847419B2 - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

Info

Publication number
JP3847419B2
JP3847419B2 JP17737997A JP17737997A JP3847419B2 JP 3847419 B2 JP3847419 B2 JP 3847419B2 JP 17737997 A JP17737997 A JP 17737997A JP 17737997 A JP17737997 A JP 17737997A JP 3847419 B2 JP3847419 B2 JP 3847419B2
Authority
JP
Japan
Prior art keywords
pixel electrode
liquid crystal
wiring
counter electrode
crystal display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP17737997A
Other languages
Japanese (ja)
Other versions
JPH1124095A (en
Inventor
雄三 大土井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17737997A priority Critical patent/JP3847419B2/en
Publication of JPH1124095A publication Critical patent/JPH1124095A/en
Application granted granted Critical
Publication of JP3847419B2 publication Critical patent/JP3847419B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、TV、モニタ、ノート型パーソナルコンピュータ、携帯端末等に用いられる液晶表示装置に関するものである。
【0002】
【従来の技術】
近年、直視型の液晶表示装置として、高画質が得られるという点から、画素毎にアモルファスSi(以下a−Siと記す)または多結晶Si(以下Poly−Siと記す)からなる薄膜トランジスタ(以下TFTと称す)を設け、このスイッチング動作により画素電極に電圧を印加し、液晶を駆動するアクティブマトリクス型の液晶表示装置が多く使用されるようになった。
アクティブマトリクス型の液晶表示装置としては、液晶に印加する電界の方向を基板面に垂直な方向とするTN(Twisted Nematic)表示方式が主に採用されている。近年、広視野角を実現する技術として、液晶に印加する電界の方向を基板面にほぼ平行な方向とするIPS(In-Plane Switching )方式の液晶表示装置が開発された。
【0003】
図4は、特開平7−36058号公報に示されたIPS方式の液晶表示装置のTFTアレイ平面図である。図において、1はAl、Cr、Ta、Mo、W、Ti、Zr、Cuおよびその合金等の導体からなるゲート配線、2はゲート配線1と同時形成された対向電極、3は対向電極2と接続した共通配線、4はスイッチング素子を形成するためのa−Si、poly−Si等からなるTFT部分、5はAl、Cr、Ta、Mo、W、Ti、Zr、Cuおよびその合金等の導体からなるソース配線、6はソース配線5と同時形成された画素電極、7は共通配線3と画素電極6の間に絶縁層を挟んで形成された液晶駆動電圧保持用の保持容量部分、8は液晶分子をそれぞれ示す。
【0004】
IPS方式では、画素電極6と対向電極2が同じ基板上に形成されており、液晶8に印加される電界は基板面にほぼ平行な方向となり、液晶分子は面内回転する。画素電極6、対向電極2上では、液晶分子に水平方向の電界がかからないため、液晶分子は回転しない。すなわち、IPS方式では原理的に、画素電極6、対向電極2が透明である必要はない。従って、本従来例では、製造工程を簡略化するために、対向電極2はゲート配線1、共通配線3と、画素電極6はソース配線5とそれぞれ同一部材で同時形成している。従来のTN方式では、ゲート配線、ソース配線とは別に、ITO(In、Snの酸化物)等の透明な導電性酸化膜からなる画素電極、カラーフィルタ基板の対向電極形成が必要であったが、IPS方式では、透明な画素電極、対向電極形成の2工程を省略でき、製造工程が大幅に削減できる利点がある。
【0005】
【発明が解決しようとする課題】
IPS方式の液晶表示装置では、画素電極6および対向電極2は透明である必要はないため、従来のTN方式で使用されているITO等の透明な導電性酸化膜は必要としない。よって、液晶表示パネルと駆動回路を接続する液晶パネル周辺に設けられた接続端子はゲート配線1、ソース配線5および共通配線3の構成部材からなっていた。ところが、一般に、液晶表示パネルと駆動回路ICの搭載されたTCP(Tape Carrier Package)との接続には、熱圧着性の異方性導電フィルムが使用されており、この接続信頼性に関しては、従来のTN方式の接続端子で使用されているITO等の透明導電性酸化膜との接続信頼性が最も確立されている。ITO等の導電性酸化膜より構成される接続端子は、もともとが酸化膜であるため、Al、Cr、Cu等の金属膜端子と異なり、表面酸化による腐食、導電性低下、密着力低下等の心配が少ないという利点がある。従って、接続端子がゲート配線1、ソース配線5および共通配線3等の部材からなり、ITO等の導電性酸化膜以外の場合は、新たな接続条件出し、信頼性等を確立しなければならないという問題があった。
【0006】
また、接続端子を、ゲート配線1、ソース配線5および共通配線3の構成部材とは別に、ITO等の導電性酸化膜で形成する場合には、接続端子形成だけのために導電性酸化膜の形成、写真製版、エッチング等の製造工程が増加するという問題があった。
さらに、ゲート配線1、ソース配線5および共通配線3のいずれかをITO等の透明な導電性酸化膜で形成した場合、接続端子をこれと同じ導電性酸化膜で形成すれば、信頼性に問題はなく、製造工程の増加もないが、ITO等の導電性酸化膜は一般に電気抵抗が大きいため配線抵抗が大きくなり、信号遅延等の問題が生じるため、例えば10型以上の大型パネルには使用できないという問題があった。
【0007】
本発明は、上記のような問題点を解消するためになされたもので、液晶表示パネルと駆動回路との接続信頼性が従来のTN方式のパネルと同様に高く、かつ製造工程の増加が少なく、大型パネルまで対応可能なIPS方式の液晶表示装置を提供することを目的とする。
【0008】
【課題を解決するための手段】
この発明に係わる液晶表示装置は、基板上に配置された複数本のゲート配線とソース配線の各交点に設けられた薄膜トランジスタに接続された画素電極と、画素電極との間に絶縁膜を挟んで保持容量を形成する共通配線と、画素電極と平行に配置され、共通配線に接続された対向電極と、基板周辺部に配置され、ゲート配線、ソース配線および共通配線と各々の駆動回路を接続する接続端子と、これらを形成した基板と対向基板との間に配向膜を介して挟持された液晶を備え、画素電極と対向電極との間に電圧を印加し、基板面にほぼ平行に電界を発生させ、液晶を面内応答させる液晶表示装置であって、画素電極および対向電極は、ゲート配線、ソース配線および共通配線とは異なる層に形成され、少なくとも画素電極および対向電極のいずれかは導電性酸化膜を含む積層膜で構成され、かつ、接続端子は、上記積層膜で形成され、接続端子表面を導電性酸化膜とするものである。
【0009】
また、画素電極および対向電極は、ゲート配線および共通配線よりも上層に形成されるものである。
【0010】
【発明の実施の形態】
参考例1.
以下、この発明の参考例1を図について説明する。図1は、本発明の参考例1である液晶表示装置のTFTアレイ平面図である。図において、1はAl、Cr、Ta、Mo、W、Ti、Zr、Cuおよびその合金等の導体からなるゲート配線、2はゲート配線1と同時形成され、後述の画素電極61と平行に配置された対向電極、3は対向電極2と接続され、後述の画素電極61との間に絶縁膜を挟んで保持容量を形成する共通配線、4はゲート配線1と後述のソース配線51との各交点に設けられ、スイッチング素子を形成するa−Si、poly−Si等からなるTFT部、51はCr、Ta、Mo、W、Ti、Zr、Cu、Pt、またはこれらの組み合わせからなる合金あるいはAlにこれらを添加したAl合金等の金属膜上にITO等の導電性酸化膜を積層した構成からなるソース配線、61はTFT部4に接続され、ソース配線51と同時形成された画素電極である。
【0011】
さらに、100、300、500は基板周辺部に配置され、ソース配線51および画素電極61と同時形成された接続端子であり、それぞれゲート配線1、共通配線3およびソース配線51と各々の駆動回路を接続する。101、301は接続端子100、300をそれぞれゲート配線1、共通配線3と接続するためのコンタクトホールである。接続端子100、300、500表面は、すべてが導電性酸化膜になっている。
参考例による液晶表示装置は、図1に示すTFTアレイ基板と対向基板との間に配向膜を介して液晶を挟持し、画素電極61と対向電極2との間に電圧を印加し、基板面にほぼ平行に電界を発生させ、液晶を面内応答させるものであり、製造工程削減のため、ソース配線51、画素電極61および接続端子100、300、500が同一材料で形成されていることを特徴とする。
【0012】
本参考例によるTFTアレイの製造方法を以下に説明する。
本参考例において、ソース配線51、画素電極61、接続端子100、300、500となる積層膜形成は、電気抵抗の低い金属膜上に導電性酸化膜を連続形成する。例えば、Mo4000Å上に、代表的導電性酸化膜であるITOを500〜1000Å程度、連続してスパッタ形成すればよい。写真製版工程は従来と変わりないが、注意すべき事として、露光後のフォトレジストのアルカリ現像時に、例えばITOと金属膜を積層した膜構成の場合、アルカリ現像液中の金属膜の電位がITOの電位よりも低いと、ITOに電気的腐食が発生することがある。例えば、純Alの上にITOを積層した構成の場合、アルカリ現像液中のITOの電位は、−1.3〜−1.4Vであり、純Alは−1.9Vであるため、ITOが電気的に腐食して溶けてしまう。従って、導電性酸化膜がITOの場合、アルカリ現像液中のITOの電位よりも高い電位の金属膜を選択する必要がある。例えば、Crは−0.3V、Cuは−0.2V、Moは−0.6V、Taは−0.85V、Wは−0.7Vであるので、使用可能である。また、純Alではなく、Alに電位の高い前記金属を添加したAl合金、例えばAl−W、Al−Mo、Al−Pt等も使用可能である。
【0013】
次に、写真製版工程で形成したフォトレジストマスクを用いて、上記の積層膜を導電性酸化膜、金属膜の順に連続的にウェットエッチング、ドライエッチングすればよい。
参考例では、従来の製造工程におけるソース配線51、画素電極61の形成工程に薄い導電性酸化膜を連続形成する工程と、エッチングする工程を追加するだけでよい。写真製版のマスクパターンは、ソース配線51、画素電極61に加え、接続端子100、300、500を含むパターン形状に設計すればよい。このように、本参考例によれば、少しの製造工程の増加で、液晶表示装置の接続端子の信頼性が従来パネルと同等に確保できる効果がある。また、ソース配線51は導電性酸化膜を含む積層膜で構成されているので、低抵抗な金属と積層することにより配線抵抗を低くでき、大型パネルにも対応可能である。
【0014】
参考例2.
図2は、本発明の参考例2である液晶表示装置のTFTアレイ平面図である。図において、5はAl、Cr、Ta、Mo、W、Ti、Zr、Cuおよびその合金等の導体からなるソース配線、6はソース配線5と同時形成された画素電極、11はCr、Ta、Mo、W、Ti、Zr、Cu、Pt、またはこれらの組み合わせからなる合金あるいはAlにこれらを添加したAl合金等の金属膜上にITO等の導電性酸化膜を積層した構成からなるゲート配線、21、31はゲート配線11と同時形成された対向電極および共通配線である。102、302、502は、ゲート配線11、対向電極21および共通配線31と同時形成された接続端子である。501は接続端子502とソース配線5を接続するためのコンタクトホールである。103、303、503は接続端子上の絶縁膜を除去して導電性酸化膜表面を露出するための接続端子穴である。この接続端子穴103、303および503により、接続端子102、302、502表面は導電性酸化膜になっている。本参考例では、製造工程削減のため、ゲート配線11、対向電極21、共通配線31、接続端子102、302、502が同一材料で同時形成されている。なお、図中、同一、相当部分には同一符号を付し、説明を省略する。
【0015】
参考例では、従来の製造工程におけるゲート配線11、対向電極21および共通配線31の形成工程に薄い導電性酸化膜を連続形成する工程と、エッチングする工程を追加するだけでよい。写真製版のマスクパターンは、ゲート配線11、対向電極21および共通配線31に加え、接続端子102、302、502を含むパターン形状に設計すればよく、上記参考例1と同様の効果が得られる。
【0016】
実施の形態1.
図3は、本発明の実施の形態である液晶表示装置のTFTアレイ平面図である。図において、22、62はITO等の導電性酸化膜、またはCr、Ta、Mo、W、Ti、Zr、Cu、Pt、またはこれらの組み合わせからなる合金あるいはAlにこれらを添加したAl合金等の金属膜上にITO等の導電性酸化膜を積層した構成からなる対向電極、画素電極である。対向電極22、画素電極62は同一材料で同時形成されている。104、304、504は画素電極62および対向電極22と同時形成された接続端子である。23は対向電極22と共通配線3を接続するコンタクトホール、105、305、505は接続端子104、304、504とゲート配線1、共通配線3、ソース配線5を接続するためのコンタクトホールである。接続端子104、304、504表面は、すべてが導電性酸化膜になっている。なお、図中、同一、相当部分には同一符号を付し、説明を省略する。
本実施の形態において、画素電極62、対向電極22がITO等の導電性酸化膜の場合は、写真製版のマスクパターンで、画素電極62、対向電極22に加えて接続端子104、304、504を含むパターン形状に設計を変更するだけでよい。また、画素電極62、対向電極22がITO等の導電性酸化膜を含む積層膜の場合は、従来の製造工程における画素電極62、対向電極22の形成工程に薄い導電性酸化膜を連続形成する工程と、エッチングする工程を追加するだけでよい。写真製版のマスクパターンは、画素電極62、対向電極22に加え、接続端子104、304、504を含むパターン形状に設計すればよい。
【0017】
本実施の形態では、画素電極62および対向電極22は、ゲート配線1、ソース配線5および共通配線3とは別の膜で構成されている。ゲート配線1、ソース配線5および共通配線3は電気抵抗を低減するために膜厚は厚い方が望ましいが、一方、画素電極62、対向電極22は配向膜ラビングによる液晶配向特性を良好にするために、電極による段差が少なくなるように膜厚が薄い方が望ましい。画素電極62および対向電極22の長さは1画素内で短いため、電気抵抗はあまり問題にならない。従って、例えばゲート配線1、ソース配線5の膜厚2000〜4000Åに対して、画素電極62、対向電極22の膜厚は、電極の段差が少なくなるように1000Å以下の薄い膜厚とすることが可能である。
【0018】
以上のように、本実施の形態によれば、少しの製造工程の増加で、液晶表示装置の接続端子の信頼性が従来パネルと同等に確保できる効果がある。また、ゲート配線1、ソース配線5、共通配線3は金属膜で構成されているので、配線抵抗を低くでき、大型パネルにも対応できる。さらに、画素電極62、対向電極22は段差が少ない薄い膜で形成できるので、液晶配向特性を良好にすることが可能である。
【0019】
なお、上記実施の形態では、スイッチング素子としてTFTを用いた場合について説明したが、Si基板を用い単結晶SiからなるMOSトランジスタの場合にも同様に本発明は有効である。
【0020】
【発明の効果】
以上のように、この発明によれば、画素電極および対向電極をゲート配線、ソース配線および共通配線とは異なる層に形成し、少なくとも画素電極および対向電極のいずれかを導電性酸化膜を含む積層膜で形成し、かつ、接続端子を上記積層膜で形成し、接続端子表面を導電性酸化膜で構成したので、少ない製造工程の増加で、高い接続端子の信頼性が得られ、さらに、配線抵抗が低く大型パネルにも対応可能な液晶表示装置が得られる効果がある。
【図面の簡単な説明】
【図1】 この発明の参考例1である液晶表示装置のTFTアレイを示す平面図である。
【図2】 この発明の参考例2である液晶表示装置のTFTアレイを示す平面図である。
【図3】 この発明の実施の形態である液晶表示装置のTFTアレイを示す平面図である。
【図4】 従来の液晶表示装置のTFTアレイを示す平面図である。
【符号の説明】
1、11 ゲート配線、2、21、22 対向電極、3、31 共通配線、4 TFT部、5、51 ソース配線、6、61、62 画素電極、7 蓄積容量部分、8 液晶分子、100、102、104、300、302、304、500、502、504 接続端子、23、101、105、301、305、501、505 コンタクトホール、
103、303、503 接続端子穴。
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device used for a TV, a monitor, a notebook personal computer, a portable terminal, and the like.
[0002]
[Prior art]
In recent years, a thin film transistor (hereinafter referred to as a TFT) made of amorphous Si (hereinafter referred to as a-Si) or polycrystalline Si (hereinafter referred to as Poly-Si) for each pixel in view of obtaining high image quality as a direct-view type liquid crystal display device. The active matrix type liquid crystal display device which drives the liquid crystal by applying a voltage to the pixel electrode by this switching operation has come to be used in many cases.
As an active matrix liquid crystal display device, a TN (Twisted Nematic) display method in which the direction of the electric field applied to the liquid crystal is perpendicular to the substrate surface is mainly employed. In recent years, an IPS (In-Plane Switching) type liquid crystal display device in which the direction of the electric field applied to the liquid crystal is substantially parallel to the substrate surface has been developed as a technique for realizing a wide viewing angle.
[0003]
FIG. 4 is a plan view of a TFT array of the IPS liquid crystal display device disclosed in Japanese Patent Application Laid-Open No. 7-36058. In the figure, 1 is a gate wiring made of a conductor such as Al, Cr, Ta, Mo, W, Ti, Zr, Cu and alloys thereof, 2 is a counter electrode formed simultaneously with the gate wiring 1, and 3 is a counter electrode 2. Connected common wiring, 4 is a TFT portion made of a-Si, poly-Si or the like for forming a switching element, 5 is a conductor such as Al, Cr, Ta, Mo, W, Ti, Zr, Cu and alloys thereof 6 is a pixel electrode formed at the same time as the source wiring 5, 7 is a storage capacitor portion for holding a liquid crystal driving voltage formed by sandwiching an insulating layer between the common wiring 3 and the pixel electrode 6, and 8 is Each liquid crystal molecule is shown.
[0004]
In the IPS system, the pixel electrode 6 and the counter electrode 2 are formed on the same substrate, the electric field applied to the liquid crystal 8 is in a direction substantially parallel to the substrate surface, and the liquid crystal molecules rotate in the plane. On the pixel electrode 6 and the counter electrode 2, the liquid crystal molecules do not rotate because no electric field is applied in the horizontal direction to the liquid crystal molecules. That is, in the IPS method, the pixel electrode 6 and the counter electrode 2 do not need to be transparent in principle. Therefore, in this conventional example, in order to simplify the manufacturing process, the counter electrode 2 is formed simultaneously with the gate wiring 1, the common wiring 3, and the pixel electrode 6 with the source wiring 5 by the same member. In the conventional TN method, apart from the gate wiring and the source wiring, it is necessary to form a pixel electrode made of a transparent conductive oxide film such as ITO (In and Sn oxide) and a counter electrode of the color filter substrate. The IPS method has the advantage that the two steps of forming the transparent pixel electrode and the counter electrode can be omitted, and the manufacturing process can be greatly reduced.
[0005]
[Problems to be solved by the invention]
In the IPS liquid crystal display device, the pixel electrode 6 and the counter electrode 2 do not need to be transparent, so that a transparent conductive oxide film such as ITO used in the conventional TN method is not required. Therefore, the connection terminals provided around the liquid crystal panel for connecting the liquid crystal display panel and the drive circuit are composed of the constituent members of the gate wiring 1, the source wiring 5 and the common wiring 3. However, in general, a thermo-compression anisotropic conductive film is used for connection between a liquid crystal display panel and a TCP (Tape Carrier Package) on which a drive circuit IC is mounted. The connection reliability with a transparent conductive oxide film such as ITO used in the TN connection terminals is most established. Since the connection terminal composed of a conductive oxide film such as ITO is originally an oxide film, unlike metal film terminals such as Al, Cr, Cu, etc., corrosion due to surface oxidation, decrease in conductivity, decrease in adhesion, etc. There is an advantage that there is less worry. Therefore, when the connection terminal is made of a member such as the gate wiring 1, the source wiring 5, and the common wiring 3, and other than the conductive oxide film such as ITO, a new connection condition must be established and reliability must be established. There was a problem.
[0006]
Further, when the connection terminal is formed of a conductive oxide film such as ITO separately from the constituent members of the gate wiring 1, the source wiring 5, and the common wiring 3, the conductive oxide film is formed only for the formation of the connection terminal. There has been a problem that manufacturing processes such as formation, photoengraving and etching increase.
Further, when any one of the gate wiring 1, the source wiring 5 and the common wiring 3 is formed of a transparent conductive oxide film such as ITO, there is a problem in reliability if the connection terminal is formed of the same conductive oxide film. Although there is no increase in the number of manufacturing steps, conductive oxide films such as ITO generally have high electrical resistance, which increases wiring resistance and causes problems such as signal delay. There was a problem that I could not.
[0007]
The present invention has been made to solve the above-described problems. The connection reliability between the liquid crystal display panel and the drive circuit is as high as that of the conventional TN panel, and the number of manufacturing steps is small. An object of the present invention is to provide an IPS liquid crystal display device that can handle large panels.
[0008]
[Means for Solving the Problems]
The liquid crystal display device according to the present invention includes a pixel electrode connected to a thin film transistor provided at each intersection of a plurality of gate lines and source lines arranged on a substrate, and an insulating film sandwiched between the pixel electrodes. A common wiring that forms a storage capacitor, a counter electrode that is arranged in parallel with the pixel electrode and connected to the common wiring, and is arranged on the periphery of the substrate, and connects the gate wiring, the source wiring, and the common wiring to each drive circuit. A liquid crystal device is provided with a connection terminal and a liquid crystal sandwiched between the substrate on which these are formed and an opposing substrate via an alignment film. A voltage is applied between the pixel electrode and the opposing electrode, and an electric field is applied substantially parallel to the substrate surface. A liquid crystal display device in which liquid crystal is generated and makes a liquid crystal respond in-plane, wherein the pixel electrode and the counter electrode are formed in a layer different from the gate wiring, the source wiring, and the common wiring, and at least the pixel electrode and the counter electrode Re or is constituted by laminated films including a conductive oxide film, and the connecting terminals are made form the above stacked film, a connection terminal surface intended to be conductive oxide film.
[0009]
The pixel electrode and the counter electrode are formed in an upper layer than the gate wiring and the common wiring.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Reference Example 1
Reference Example 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a TFT array of a liquid crystal display device which is Reference Example 1 of the present invention. In the figure, 1 is a gate wiring made of a conductor such as Al, Cr, Ta, Mo, W, Ti, Zr, Cu and alloys thereof, and 2 is formed simultaneously with the gate wiring 1 and arranged in parallel with a pixel electrode 61 described later. The common electrode 3, which is connected to the counter electrode 2 and forms a storage capacitor with an insulating film sandwiched between the pixel electrode 61 (described later), and 4, each of the gate wiring 1 and the source wiring 51 (described later). TFT section made of a-Si, poly-Si or the like provided at the intersection and forming a switching element, 51 is an alloy made of Cr, Ta, Mo, W, Ti, Zr, Cu, Pt, or a combination thereof, or Al A source wiring 61 having a structure in which a conductive oxide film such as ITO is laminated on a metal film such as an Al alloy to which these are added, and a pixel electrode 61 connected to the TFT portion 4 and formed simultaneously with the source wiring 51 A.
[0011]
Further, reference numerals 100, 300, and 500 are connection terminals that are disposed at the periphery of the substrate and are formed simultaneously with the source wiring 51 and the pixel electrode 61. The gate wiring 1, the common wiring 3, the source wiring 51, and the respective driving circuits are respectively connected. Connecting. Reference numerals 101 and 301 denote contact holes for connecting the connection terminals 100 and 300 to the gate wiring 1 and the common wiring 3, respectively. The surfaces of the connection terminals 100, 300, 500 are all conductive oxide films.
The liquid crystal display device according to this reference example has a liquid crystal sandwiched between the TFT array substrate and the counter substrate shown in FIG. 1 via an alignment film, and a voltage is applied between the pixel electrode 61 and the counter electrode 2. An electric field is generated substantially parallel to the surface to cause the liquid crystal to respond in-plane, and the source wiring 51, the pixel electrode 61, and the connection terminals 100, 300, and 500 are formed of the same material in order to reduce the manufacturing process. It is characterized by.
[0012]
A manufacturing method of the TFT array according to this reference example will be described below.
In this reference example, in the formation of the laminated film that becomes the source wiring 51, the pixel electrode 61, and the connection terminals 100, 300, and 500, a conductive oxide film is continuously formed on a metal film having a low electrical resistance. For example, ITO, which is a representative conductive oxide film, may be continuously sputtered on Mo4000? Although the photoengraving process is the same as before, it should be noted that when the photoresist is exposed to alkali, the potential of the metal film in the alkali developer is, for example, in the case of a film configuration in which ITO and a metal film are laminated. If the potential is lower than that, electrical corrosion may occur in the ITO. For example, in the case of a configuration in which ITO is laminated on pure Al, the potential of ITO in the alkaline developer is -1.3 to -1.4V, and pure Al is -1.9V. Electrically corrodes and melts. Therefore, when the conductive oxide film is ITO, it is necessary to select a metal film having a higher potential than that of ITO in the alkaline developer. For example, Cr is -0.3V, Cu is -0.2V, Mo is -0.6V, Ta is -0.85V, and W is -0.7V, and can be used. Further, instead of pure Al, an Al alloy in which the above-described metal having a high potential is added to Al, such as Al—W, Al—Mo, Al—Pt, or the like, can also be used.
[0013]
Next, using the photoresist mask formed in the photoengraving process, the laminated film may be successively wet etched and dry etched in the order of the conductive oxide film and the metal film.
In this reference example , a process of continuously forming a thin conductive oxide film and a process of etching need only be added to the process of forming the source wiring 51 and the pixel electrode 61 in the conventional manufacturing process. The photoengraving mask pattern may be designed in a pattern shape including the connection terminals 100, 300, and 500 in addition to the source wiring 51 and the pixel electrode 61. Thus, according to this reference example , there is an effect that the reliability of the connection terminal of the liquid crystal display device can be ensured to be equal to that of the conventional panel with a slight increase in manufacturing steps. Further, since the source wiring 51 is composed of a laminated film including a conductive oxide film, the wiring resistance can be lowered by laminating with a low resistance metal, and it can be applied to a large panel.
[0014]
Reference Example 2
FIG. 2 is a plan view of a TFT array of a liquid crystal display device which is Reference Example 2 of the present invention. In the figure, 5 is a source wiring made of a conductor such as Al, Cr, Ta, Mo, W, Ti, Zr, Cu and alloys thereof, 6 is a pixel electrode formed simultaneously with the source wiring 5, 11 is Cr, Ta, A gate wiring comprising a structure in which a conductive oxide film such as ITO is laminated on a metal film such as an alloy made of Mo, W, Ti, Zr, Cu, Pt, or a combination thereof, or an Al alloy obtained by adding these to Al; Reference numerals 21 and 31 are a counter electrode and a common wiring formed simultaneously with the gate wiring 11. Reference numerals 102, 302, and 502 are connection terminals formed simultaneously with the gate wiring 11, the counter electrode 21, and the common wiring 31. Reference numeral 501 denotes a contact hole for connecting the connection terminal 502 and the source wiring 5. Reference numerals 103, 303, and 503 denote connection terminal holes for removing the insulating film on the connection terminals and exposing the surface of the conductive oxide film. By the connection terminal holes 103, 303, and 503, the surfaces of the connection terminals 102, 302, and 502 are conductive oxide films. In this reference example , the gate wiring 11, the counter electrode 21, the common wiring 31, and the connection terminals 102, 302, and 502 are simultaneously formed of the same material in order to reduce the manufacturing process. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof is omitted.
[0015]
In this reference example , a process of continuously forming a thin conductive oxide film and a process of etching need only be added to the process of forming the gate wiring 11, the counter electrode 21 and the common wiring 31 in the conventional manufacturing process. The photoengraving mask pattern may be designed to have a pattern shape including the connection terminals 102, 302, and 502 in addition to the gate wiring 11, the counter electrode 21, and the common wiring 31, and the same effect as in the first reference example can be obtained.
[0016]
Embodiment 1 FIG .
FIG. 3 is a plan view of the TFT array of the liquid crystal display device according to the first embodiment of the present invention. In the figure, reference numerals 22 and 62 denote a conductive oxide film such as ITO, an alloy composed of Cr, Ta, Mo, W, Ti, Zr, Cu, Pt, or a combination thereof, or an Al alloy obtained by adding these to Al. It is a counter electrode and a pixel electrode having a configuration in which a conductive oxide film such as ITO is laminated on a metal film. The counter electrode 22 and the pixel electrode 62 are simultaneously formed of the same material. Reference numerals 104, 304, and 504 denote connection terminals formed simultaneously with the pixel electrode 62 and the counter electrode 22. Reference numeral 23 is a contact hole for connecting the counter electrode 22 and the common wiring 3, and 105, 305 and 505 are contact holes for connecting the connection terminals 104, 304 and 504 to the gate wiring 1, the common wiring 3 and the source wiring 5. The surfaces of the connection terminals 104, 304, and 504 are all conductive oxide films. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof is omitted.
In the present embodiment, when the pixel electrode 62 and the counter electrode 22 are conductive oxide films such as ITO, the connection terminals 104, 304, and 504 are connected to the pixel electrode 62 and the counter electrode 22 in addition to the pixel electrode 62 and the counter electrode 22 with a photolithography mask pattern. It is only necessary to change the design to include the pattern shape. In the case where the pixel electrode 62 and the counter electrode 22 are laminated films including a conductive oxide film such as ITO, a thin conductive oxide film is continuously formed in the formation process of the pixel electrode 62 and the counter electrode 22 in the conventional manufacturing process. It is only necessary to add a process and an etching process. The mask pattern for photolithography may be designed in a pattern shape including the connection terminals 104, 304, and 504 in addition to the pixel electrode 62 and the counter electrode 22.
[0017]
In the present embodiment, the pixel electrode 62 and the counter electrode 22 are formed of a film different from the gate wiring 1, the source wiring 5, and the common wiring 3. The gate wiring 1, the source wiring 5 and the common wiring 3 are preferably thicker in order to reduce electrical resistance, while the pixel electrode 62 and the counter electrode 22 are for improving the liquid crystal alignment characteristics by the alignment film rubbing. In addition, it is desirable that the film thickness is small so that the level difference due to the electrode is reduced. Since the length of the pixel electrode 62 and the counter electrode 22 is short in one pixel, the electrical resistance is not a problem. Therefore, for example, the film thickness of the pixel electrode 62 and the counter electrode 22 is set to a thin film thickness of 1000 mm or less so that the step difference between the electrodes is reduced with respect to the film thickness of 2000 to 4000 mm of the gate wiring 1 and the source wiring 5. Is possible.
[0018]
As described above, according to the present embodiment, there is an effect that the reliability of the connection terminal of the liquid crystal display device can be ensured to be equal to that of the conventional panel with a slight increase in manufacturing steps. In addition, since the gate wiring 1, the source wiring 5, and the common wiring 3 are made of a metal film, the wiring resistance can be lowered, and it can be applied to a large panel. Further, since the pixel electrode 62 and the counter electrode 22 can be formed of thin films with few steps, the liquid crystal alignment characteristics can be improved.
[0019]
In the first embodiment, the case where a TFT is used as the switching element has been described. However, the present invention is also effective in the case of a MOS transistor made of single crystal Si using a Si substrate.
[0020]
【The invention's effect】
As described above, according to the present invention, the pixel electrode and the counter electrode are formed in a layer different from the gate wiring, the source wiring, and the common wiring, and at least one of the pixel electrode and the counter electrode includes the conductive oxide film. forming a film, and the connection terminals form the shape in the laminated film, since it is configured to connect terminal surface with a conductive oxide film, an increase of less manufacturing steps, the reliability of high connection terminals can be obtained, furthermore, There is an effect that a liquid crystal display device having low wiring resistance and compatible with a large panel can be obtained.
[Brief description of the drawings]
FIG. 1 is a plan view showing a TFT array of a liquid crystal display device which is Reference Example 1 of the present invention.
FIG. 2 is a plan view showing a TFT array of a liquid crystal display device which is Reference Example 2 of the present invention.
FIG. 3 is a plan view showing a TFT array of the liquid crystal display device according to the first embodiment of the present invention.
FIG. 4 is a plan view showing a TFT array of a conventional liquid crystal display device.
[Explanation of symbols]
1, 11 Gate wiring, 2, 21, 22 Counter electrode, 3, 31 Common wiring, 4 TFT section, 5, 51 Source wiring, 6, 61, 62 Pixel electrode, 7 Storage capacitance portion, 8 Liquid crystal molecule, 100, 102 104, 300, 302, 304, 500, 502, 504 Connecting terminal, 23, 101, 105, 301, 305, 501, 505 Contact hole,
103, 303, 503 Connection terminal holes.

Claims (2)

基板上に配置された複数本のゲート配線とソース配線の各交点に設けられた薄膜トランジスタに接続された画素電極、
上記画素電極との間に絶縁膜を挟んで保持容量を形成する共通配線、
上記画素電極と平行に配置され、上記共通配線に接続された対向電極、
上記基板周辺部に配置され、上記ゲート配線、上記ソース配線および上記共通配線と各々の駆動回路を接続する接続端子、
上記基板と対向基板との間に配向膜を介して挟持された液晶を備え、上記画素電極と上記対向電極との間に電圧を印加し、基板面にほぼ平行に電界を発生させ、上記液晶を面内応答させる液晶表示装置であって、
上記画素電極および上記対向電極は、上記ゲート配線、上記ソース配線および上記共通配線とは異なる層に形成され、少なくとも上記画素電極および上記対向電極のいずれかは導電性酸化膜を含む積層膜で構成され、かつ、上記接続端子は、上記積層膜で形成され、上記接続端子表面が導電性酸化膜であることを特徴とする液晶表示装置。
A pixel electrode connected to a thin film transistor provided at each intersection of a plurality of gate wirings and source wirings disposed on the substrate;
A common wiring that forms a storage capacitor with an insulating film interposed between the pixel electrode and the pixel electrode;
A counter electrode disposed in parallel with the pixel electrode and connected to the common wiring;
A connection terminal that is disposed in the periphery of the substrate and connects the gate wiring, the source wiring, and the common wiring to each drive circuit;
A liquid crystal sandwiched between the substrate and the counter substrate with an alignment film interposed between them; a voltage is applied between the pixel electrode and the counter electrode to generate an electric field substantially parallel to the substrate surface; A liquid crystal display device that responds in-plane,
The pixel electrode and the counter electrode, the gate wire, and the source wiring and the common wiring are formed in different layers, a laminated film comprising any conductive oxide film of at least the pixel electrode and the counter electrode it is configured, and the connection terminals are made form the above stacked film, a liquid crystal display device, wherein said connection terminal surface is electrically conductive oxide layer.
上記画素電極および上記対向電極は、上記ゲート配線および上記共通配線よりも上層に形成されることを特徴とする請求項1に記載の液晶表示装置。 2. The liquid crystal display device according to claim 1, wherein the pixel electrode and the counter electrode are formed in an upper layer than the gate line and the common line.
JP17737997A 1997-07-02 1997-07-02 Liquid crystal display Expired - Fee Related JP3847419B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17737997A JP3847419B2 (en) 1997-07-02 1997-07-02 Liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17737997A JP3847419B2 (en) 1997-07-02 1997-07-02 Liquid crystal display

Publications (2)

Publication Number Publication Date
JPH1124095A JPH1124095A (en) 1999-01-29
JP3847419B2 true JP3847419B2 (en) 2006-11-22

Family

ID=16029921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17737997A Expired - Fee Related JP3847419B2 (en) 1997-07-02 1997-07-02 Liquid crystal display

Country Status (1)

Country Link
JP (1) JP3847419B2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7411211B1 (en) * 1999-07-22 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Contact structure and semiconductor device
JP2001092379A (en) * 1999-09-27 2001-04-06 Nec Corp Active matrix substrate and its manufacturing method
JP2001257350A (en) 2000-03-08 2001-09-21 Semiconductor Energy Lab Co Ltd Semiconductor device and its preparation method
JP2002040484A (en) * 2000-07-26 2002-02-06 Hitachi Ltd Active matrix type liquid crystal display device
TW525216B (en) 2000-12-11 2003-03-21 Semiconductor Energy Lab Semiconductor device, and manufacturing method thereof
SG111923A1 (en) 2000-12-21 2005-06-29 Semiconductor Energy Lab Light emitting device and method of manufacturing the same
US8218120B2 (en) 2005-03-31 2012-07-10 Lg Display Co., Ltd. Array substrate for in-plane switching liquid crystal display device and method of fabricating the same
KR20060104708A (en) * 2005-03-31 2006-10-09 엘지.필립스 엘시디 주식회사 An array substrate for in-plane switching mode lcd and method of fabricating of the same
KR101225440B1 (en) 2005-06-30 2013-01-25 엘지디스플레이 주식회사 Liquid crystal display and fabricating method thereof
KR101264789B1 (en) * 2006-06-30 2013-05-15 엘지디스플레이 주식회사 An array substrate for in plan switching LCD and method of fabricating of the same
JP5553513B2 (en) * 2009-02-09 2014-07-16 株式会社ジャパンディスプレイ Liquid crystal display device and manufacturing method thereof
JP5732552B2 (en) * 2014-01-27 2015-06-10 株式会社半導体エネルギー研究所 Display device

Also Published As

Publication number Publication date
JPH1124095A (en) 1999-01-29

Similar Documents

Publication Publication Date Title
US7553708B2 (en) Fabricating method for a liquid crystal display of horizontal electric field applying type
JP2780543B2 (en) Liquid crystal display substrate and liquid crystal display device
JP2000258799A (en) Manufacture of liquid crystal display device
JP3847419B2 (en) Liquid crystal display
JP2985124B2 (en) Liquid crystal display
US20030112382A1 (en) Liquid crystal display device
JP3258768B2 (en) Matrix display device
JP2001281693A (en) Liquid crystal display panel and its production method
JP3235540B2 (en) Thin film transistor array for liquid crystal display device and method of manufacturing the same
JP2000214481A (en) Liquid crystal display device and its production
JP2001142092A (en) Liquid crystal display device and method of producing the same
JP2702294B2 (en) Active matrix substrate
JPH07113728B2 (en) Active matrix substrate
JP2957901B2 (en) Active matrix array substrate and manufacturing method thereof
JP3076483B2 (en) Method for manufacturing metal wiring board and method for manufacturing thin film diode array
JP2000250065A (en) Liquid crystal image display device and production of semiconductor device for image display device
JPH0566410A (en) Liquid crystal display device
JPH11212120A (en) Liquid crystal display device and production thereof
JP2870016B2 (en) Liquid crystal device
JPH11258627A (en) Thin-film device
JPH095767A (en) Input edge structure for liquid crystal panel
JPH04338728A (en) Active matrix substrate
JP3658260B2 (en) Liquid crystal display
JP2687967B2 (en) Liquid crystal display
JP2924402B2 (en) Thin film transistor array, method for manufacturing the same, and method for manufacturing liquid crystal display device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20031215

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20031215

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20051228

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060110

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060310

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060516

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060714

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060808

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060823

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090901

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100901

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110901

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110901

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120901

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130901

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees