JP3823658B2 - Electro-optical device driving circuit, driving method, electro-optical device, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving circuit, a driving method, an electro-optical device, and an electronic apparatus for an electro-optical device that performs gradation display by modulation on a time axis.
[0002]
[Prior art]
In general, a flat display such as a liquid crystal display, a light emitting diode, a plasma display, and an EL (electroluminescence) display has a plurality of pixels at each intersection of a plurality of data lines and a plurality of scanning lines, and controls an applied voltage. Thus, an optical change is generated in each pixel, and an image is displayed using this. In such an electro-optical device, there is a time axis modulation method as one of drive methods for performing gradation display. A time axis modulation method (or a pulse width modulation method, a multiplex gradation driving method, a time-division gradation driving method, or the like) converts one field (or one frame) into a plurality of subfields (or subframes). By dividing and assigning an ON time corresponding to the gradation to each subfield, and by applying binary control to the applied voltage of each pixel in an ON or OFF state in units of subfields, cumulative in one field (or one frame) The on-time width is controlled according to the gradation. An example of such a time-axis modulation method is described in Japanese Patent Application Laid-Open No. 10-49097, “Display Device, Driving Circuit, and Gradation Display Method”, Japanese Patent Application Laid-Open No. 11-38928, “Display Device”, and the like.
[0003]
In the time axis modulation method as described above, the voltage applied to the data line is controlled to be a binary value in an on or off state regardless of the gradation value. Therefore, there is an advantage that the configuration of the driving circuit can be simplified as compared with the active matrix driving method in which a voltage having a magnitude corresponding to the gradation value of each pixel is applied to the data line.
[0004]
[Problems to be solved by the invention]
In the time axis modulation method, the on / off state of each pixel is controlled for each subfield. A drive circuit that drives and controls the data lines and the scan lines repeatedly scans each scan line in each subfield unit, and controls on / off of the voltage applied to each data line for each scan so that each pixel on each scan line is controlled. Set the on / off state for. In a conventional time-axis modulation type driving circuit, information indicating the on / off state of each pixel on each scanning line is input from the outside as serial data for each scanning line, and the input serial data is a shift register or the like. After being converted into parallel data corresponding to the data line group by the conversion circuit using, the data is applied to the data line group in synchronization with scanning of the scanning line. In this case, on-off data transfer according to the number of subfield divisions, the number of scanning lines, and the number of data lines is performed in one field period. The number of data transfers in one field period increases in proportion to the number of subfield divisions. Therefore, it is conceivable that the data transfer frequency further increases when the number of gradations is increased.
[0005]
As described above, the drive circuit using the conventional time-axis modulation method has an effect of simplifying the configuration, but has a tendency to increase the transfer frequency of the gradation data input from the external circuit. There has been a problem that noise and power consumption increase due to the frequency increase. These problems have become a prominent problem in electro-optical devices and electronic devices that have high demands for low noise and low power consumption in addition to demands for an increase in the number of gradations and the number of pixels.
[0006]
Therefore, the present invention lowers the transfer frequency of information indicating the on / off state of each pixel input from the outside to the drive circuit that drives and controls the applied voltage of each pixel by the time-axis modulation method, as compared with the prior art. An object of the present invention is to provide an electro-optical device driving circuit, a driving method, an electro-optical device, and an electronic apparatus.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention provides an ON state in units of a plurality of subfields obtained by dividing one field for each pixel arranged corresponding to each intersection of a plurality of data lines and a plurality of scanning lines. Driving an electro-optical device that controls gradation and off-state, and performs weight display by weighting the time in which each pixel is in the on-state in each subfield according to the gradation of the pixel. In the circuit, a storage means comprising a plurality of memory cells for storing data indicating the on state or the off state of the pixel in each subfield in a storage area provided corresponding to each pixel; The scanning line side driving means for sequentially selecting the scanning lines on the basis of the selection timing indicated by the clock signal for each subfield, and the scanning line side driving means Read out the data to be given to the plurality of pixels corresponding to the scanning line to be read from the memory cell in the storage unit, and based on the data read out by the readout unit, through the plurality of data lines Data line side driving means for supplying a voltage for bringing each pixel into the on state or the off state, and the reading means is supplied to the plurality of pixels corresponding to the scanning line selected in each subfield. A selection circuit for selecting a memory cell for storing data, the selection circuit being on-level corresponding to a pulse signal that is the same as the clock signal and a time during which each pixel is turned on in each subfield; The same pulse signal as the clock signal included in a period in which the predetermined signal is supplied and the predetermined signal is on level. By supplying the memory cell, the memory cell is selected. On the other hand, the pulse signal identical to the clock signal is not supplied to the memory cell while the predetermined signal is off level. The drive circuit of the electro-optical device is characterized in that the selected memory cell outputs the data based on the same pulse signal as the supplied clock signal without performing selection.
[0008]
According to this invention, since the data indicating the on / off state of each pixel is stored in the storage means in the transfer circuit, the data can be rewritten only when the data corresponding to any pixel changes. It is often possible to reduce the transfer frequency (transfer rate) when transferring data to the drive circuit and reduce the power consumption.
[0009]
In a preferred aspect of the present invention, there is further provided writing means for writing data corresponding to each subfield in a storage area corresponding to a pixel arbitrarily selected from the plurality of storage areas in the storage means.
[0010]
In this case, the reading means selects a plurality of storage areas of the storage means by the first selection means and reads data, and the writing means is a second selection means independent of the first selection means. Thus, data may be written by selecting a storage area corresponding to an arbitrary pixel in the storage means.
[0011]
Further, the storage means stores binary signals of the number of (pixels) × (number of subfields), and each binary signal indicates the on state and the off state of the pixels. It suffices to require a number of binary signal memory cells.
[0012]
Also, the present invention controls each pixel arranged corresponding to each intersection of a plurality of data lines and a plurality of scanning lines in an on state and an off state in units of a plurality of subfields obtained by dividing one field. In addition, in the driving method of the electro-optical device in which the gradation display is performed by weighting the time in which each pixel is turned on in each subfield according to the gradation of the pixel, Data indicating the on-state or the off-state of a pixel is stored in each of a plurality of memory cells in a storage area corresponding to each pixel in a storage means, and the plurality of scanning lines are stored for each subfield. The pixels are sequentially selected based on the selection timing indicated by the clock signal, and each pixel is turned on in the same pulse signal and each subfield as the clock signal. By using a predetermined signal that is on level corresponding to a certain time, and supplying the same pulse signal as the clock signal included in the period during which the predetermined signal is on level, to the memory cell, On the other hand, when the predetermined signal is in the off level, the same pulse signal is not selected by not supplying the same pulse signal as the clock signal to the memory cell. Based on the read data, data to be applied to a plurality of pixels corresponding to the selected scanning line is read out, and the plurality of pixels are turned on via the plurality of data lines based on the read data. When a voltage for turning on or off is supplied and a change occurs in gradation data corresponding to one of the pixels, each pixel stored in the storage means There is provided a method of driving an electro-optical device characterized by rewriting the data corresponding to the pixel of the data.
[0013]
Further, the present invention can be implemented as an electro-optical device that is driven and controlled by these drive circuits in addition to the drive circuits as described above.
[0014]
Furthermore, the present invention can be implemented as an electronic apparatus including these electro-optical devices as display devices.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a driving circuit 100 according to the present invention and its peripheral circuits. The driving circuit 100 is connected to a liquid crystal panel 300 based on a control signal such as gradation data DI input from a controller 200. The N data lines X1 to XN and the M scanning lines Y1 to YM are driven and controlled to perform gradation control of the liquid crystal panel 300 by the time axis modulation method. In the present embodiment, description will be made based on a liquid crystal panel in a liquid crystal display device as an example of an electro-optical device. The drive circuit 100 applies a data line side drive circuit (hereinafter referred to as an X driver) 110 that controls a voltage applied to the N data lines X1 to XN of the liquid crystal panel 300, and applies to the M data lines Y1 to YN. It is composed of a scanning line side drive circuit (hereinafter referred to as Y driver) 120 that controls the voltage. The X driver 110 selects (scans) a frame memory 111 that stores display data for one frame (one screen scanning period, that is, one vertical scanning period) to be displayed on the liquid crystal panel 300, and scanning lines Y1 to YM of the liquid crystal panel 300. And a selection circuit 112 that selects display data corresponding to a plurality of pixels on each scanning line at a timing synchronized with the other. The Y driver 120 includes a shift register and a plurality of latch circuits. The Y driver 120 scans the shift register based on the clock signal CLY input from the controller 200, and sequentially selects the scanning lines Y1 to YM according to the output corresponding thereto. Then, a predetermined selection voltage is sequentially applied to the scanning line.
[0016]
The controller 200 includes a microprocessor, a memory, a clock signal generation circuit, and the like. The controller 200 generates a plurality of control signals according to a predetermined program or a signal supplied from an external device and supplies the control signal to the drive circuit 100. To do. In FIG. 1, as a main signal supplied from the controller 200 to the drive circuit 100, a clock signal CLY for instructing the selection timing of the scanning lines Y1 to YM, and an alternating drive signal that is a signal that repeats level inversion for each frame. FR, signal SF corresponding to the frame number of each subfield dividing one field, address signal AD indicating the memory address of the access destination of the frame memory 111, and data signal to be written to the memory address of the access destination specified by the address signal AD DI is illustrated. Here, the address signal AD and the data signal DI are signals composed of a plurality of bits, and are transferred by a plurality of signal line buses.
[0017]
In the present embodiment, one field is divided into eight subfields having different on-time widths, and the on / off state of each pixel is controlled in units of each subfield.
[0018]
As will be described later, the liquid crystal panel 300 has a liquid crystal sandwiched between an element substrate and a counter substrate. As shown in FIG. 2, N data lines X1 to XN and M are displayed on a display area 301a on the element substrate. The scanning lines Y1 to YM are formed and configured to be orthogonal to each other. Then, the pixels P11 to PN1 are located at the intersections of the scanning line Y1 and the data lines X1 to XN, the pixels P12 to PN2 are located at the intersections of the scanning line Y2 and the data lines X1 to XN, and the scanning line YM. Pixels P1M to PNM are provided at each intersection of the data lines X1 to XN, and a total of N × M pixels P11 to PNM are provided corresponding to each intersection.
[0019]
For example, as shown in FIG. 3, each of the pixels P11 to PNM has a gate on the scanning line Yk (k is an integer from 1 to M) and a data line Xj (j is an integer from 1 to N). A transistor P101 having a source connected to the pixel and a drain connected to the pixel electrode P103. A liquid crystal P104, which is an electro-optic material, is sandwiched and held between the pixel electrode P103 and the counter electrode P105, which is a transparent electrode, so as to form a liquid crystal layer. A storage capacitor P102 is formed between the pixel electrode P103 and the common potential LCcom. The storage capacitor P102 is a capacitor provided to hold the applied voltage substantially constant for a necessary time after a voltage is applied to the pixel electrode P103 via the transistor P101. Note that the storage capacitor P102 only needs to hold the voltage written in the pixel, and may be provided between another potential of the common potential LCcom and the pixel electrode P103. The transistor P101 may be a transmission gate structure of a complementary transistor instead of a single N-channel transistor. In this case, however, it is necessary to apply a pair of complementary signals to the complementary transistors and simultaneously perform on / off control.
[0020]
The common potential LCcom is a potential common to the pixels P11 to PNM. The common potential LCcom is applied so that an AC voltage is applied to each pixel in units of frames by a voltage control circuit (not shown) in the drive circuit 100 in FIG. 1 based on the AC drive signal FR supplied from the controller 200. The potential is controlled to be different for each frame. That is, based on the alternating drive signal FR, the potential LCcom of the common electrode is alternately switched at two voltage levels according to frame switching, for example, 0V, 5V, 0V,. In the frame with the potential LCcom = 0V, 5V is applied to each pixel as the on voltage and 0V as the off voltage. In the frame with LCcom = 5V, 0V is applied as the on voltage and 5V is applied as the off voltage. Thereby, AC driving of the applied voltage of each pixel is performed. The on / off voltage of each pixel is switched by using an exclusive OR (negative logic) XNOR gates OG1 to OGN (FIG. 4) in the X driver 110, which will be described later, when the AC drive signal FR is' 1 'or' 0. This is done by switching whether to invert the output values to the data lines X1 to XN.
[0021]
Next, a configuration example of the X driver 110 shown in FIG. 1 will be described with reference to FIG. In the example shown in FIG. 4, the frame memory 111 is provided with N × M memory cell blocks B <b> 11 to BNM as storage areas corresponding to N × M pixels of the liquid crystal panel 300. In this case, the memory cell blocks B11, B21,..., BNM respectively correspond to the pixels P11, P21,. Each of the memory cell blocks B11, B21, ..., BN1, B12, B22, ..., BN2, ..., B1M, B2M, ..., BNM is an 8-bit memory cell C111 to C118, C211 to C218, ..., CN11 to CN18, respectively. , ..., C121 to C128, C221 to C228, ..., CN21 to CN28, ..., C1M1 to C1M8, C2M1 to C2M8, ..., CNM1 to CNM8. In each of the eight memory cells Cjk1 to 8 constituting the memory cell block Bjk (j is an integer of 1 to N, k is an integer of 1 to M), each pixel in each subfield 1 to 8 Binary data indicating the on (“1”) or off (“0”) state of Pjk is stored. In addition, an 8-bit data signal DI is written to each of the memory cells Cjk1 to 8 through 8 signal lines DI1 to DI8. In this case, signals of the least significant bit to the most significant bit of the data signal DI are transmitted on the signal lines DI1 to DI8, respectively.
[0022]
The signal lines DI1 to DI8 are inverted by inverters IG1 to IG8, respectively, so that each becomes a pair of signal lines of positive logic and negative logic, and each of 16 signal lines is connected to M XI gate blocks XG1 to XGM. Each is entered. Any one of the XI gates XG1 to XGM is selected in accordance with signals on the address lines XI1 to XIM supplied from the memory XI decoder 1111 so that the selected gate is turned on. That is, when the address signal XIk (k = 1 to M) becomes “1” level, the XI gate XGk is selected, and each of the 16 transfer gates configured in the XI gate XGk is turned on. Then, 16 signals from the output ends of the signal lines DI1 to 8 and the inverters IG1 to IG8 are connected to eight sets of bit line groups BIk1 to BIk8 each consisting of a pair of signal lines. For example, when the address signal XI1 becomes “1”, the XI gate 1 is turned on, and the signal line groups BI11 to BI18 are connected to the signal lines DI1 to 8 and the outputs of the inverters IG1 to IG8.
[0023]
For example, the bit line group BI11 has N memory cells C111, C211,..., CN11, the bit line group BI18 has N memory cells C118, C218,..., CN18, and the bit line group BI28 has N pieces. The bit signal line group BIkm (k = 1 to M, m = 1 to 8 (m corresponds to the bit position)) is connected to the memory cells C128, C228,..., CN28. Are commonly connected to N memory cells C1km to CNkm respectively corresponding to the pixels P1k to PNk on the same scanning line Yk. On the other hand, the memory XI decoder decodes the address signal AD supplied from the controller 200 and performs signal processing to set one of the address signal lines XI1 to XIM to the “1” level (active). .
[0024]
The address signal AD is a signal for arbitrarily selecting any one of the N × M memory cell blocks B11 to BNM. Based on the address signal AD, the memory XI decoder 1111 selects any one of the address lines XI1 to XIM. Since one is selected and any one of the XI gates XG1 to XGM is turned on, any one of the M sets of bit line groups BI1m to BIMm (m = 1 to 8), BIkm (BIk1) ~ BIk8) will be selected. At the same time, on the basis of the address signal AD, the memory YI decoder 1112 selects any one of the address lines YI1 to YIM (an integer from j = 1 to M), and M memory cell blocks Bj1 to Bj1 are selected. BjM is selected. Each address line YIj (j = 1 to M) controlled by the memory YI decoder 1112 is connected to all the memory cells C111,..., C118 to C1M1,..., C1M8 of the memory cells B11 to B1M, for example. 2, all the grayscale data corresponding to the pixels Pj1 to PjM on the same data line Xj in the liquid crystal panel 300 of FIG. 2, that is, M × 8 (8 is the number of bits) memory cells Cj1m to CjMm (m = 1 to 8).
[0025]
Therefore, the controller 200 in FIG. 1 selects any one of the memory cell blocks B11 to BNM by the address signal AD, and the on / off state of the pixel Pjk in each subfield is set in each bit of the data signal DI. Is set, each memory cell Cjkm can store the on / off state in each subfield m of the pixel Pjk. FIG. 5 is a circuit diagram showing a configuration of the memory cell Cjkm.
[0026]
The memory cell Cjkm (j = 1 to N, k = 1 to M, m = 1 to 8) shown in FIG. 5 shows an example of a configuration in which the memory cell is a 2-port CMOS static memory. The memory cell Cjkm includes two inverters 501 and 502 whose outputs are connected to the other input, transistors (transfer gates) 503 and 504 whose sources are connected to the input of the inverter 501 or the input of the inverter 502, respectively, The transistor 506 has a drain connected to the output of 501. The drain of the transistor 503 and the drain of the transistor 504 are connected to a positive logic bit line BIT (a signal line having the same level as the data line DIm) and a negative logic bit line (an inverted signal of BIT) of the bit line group BIkm, respectively. At the same time, the gates of the transistors 503 and 504 are both connected to an address line YIj that functions as a word line (WORD1). The bit line group BIkm is connected to the data line DIm and the inverter IGm via transistors (transfer gates) 510 and 511 in the XI gate XGk. Accordingly, the address lines XIk are set to “1” level to turn on the transistors 510 and 511, and the address line YIj is set to “1” level to turn on the transistors 503 and 504. A signal on the line group BIkm, that is, a signal level on the data line DIm can be written.
[0027]
On the other hand, the transistor 506 has a gate connected to the address line YOkm supplied from the memory YO decoder 112 of FIG. 4 and a source connected to the data line DOj. Transistor 506 constitutes an output port for data line DOj, whereas transistors 503 and 504 constitute a data input / output port for data line DIm (in this embodiment, only the input operation is performed). That is, when the address line YOkm that functions as the second word line (WORD2) becomes “1” level, the transistor 506 is turned on, so that the signal level held in the memory circuit including the inverters 501 and 502 ( However, the output of the inverter 501 is negative logic) is output on the data line DOj. Here, the data line DOj is connected to one input of an exclusive OR gate OGj having a negative logic output. Since the alternating drive signal FR is input to the other input of the exclusive OR gate OGj having the negative logic output, the output line Xj that is the output of the exclusive OR gate OGj is connected to the inverter of the memory cell Cjkm. The data stored in the storage circuit 501 and 502 is repeatedly inverted and output in units of frames.
[0028]
On the other hand, as shown in FIG. 4, the address signals YO11 to YO18, YO21 to YO28,..., YOM1 to YOM8, which are the outputs of the memory YO decoder 112, are N memory cells (for example, C111, C211,. , CN18 and the N memory cells C118, C218,..., CN18 are connected to be a common address signal (WORD2 in FIG. 5), that is, the address signal YOkm. (K = 1 to M, m = 1 to 8) are connected in common to each of the N memory cells C1km to CNkm, where N memory cells C1km to CNkm are one of the liquid crystal panels 300 of FIG. This is a storage area for holding on / off data corresponding to one subfield m of N pixels P1k to PNk on the scanning line Yk. Therefore, by selecting each address signal YOkm by the memory YO decoder 112, on-off data (N) corresponding to the N pixels P1k to PNk on the scanning line Yk in units of subfield m for each scanning line Yk. Negative logic data) is output from the memory cells C1km to CNkm to the data lines DO1 to DON, and is output to the data lines X1 to XN of the liquid crystal panel 300 via exclusive OR gates OG1 to OGN having negative logic outputs. Will be applied.
[0029]
FIG. 6 is a functional block diagram for explaining the configuration of the memory YO decoder 112 of FIG. In synchronization with the clock signal CLY, which is a signal for instructing the selection timing of the scanning line Yk, M outputs 1 of outputs k equal to the position (or scanning line number) k of the scanning line at that time of the scanning line Yk. 1 to M, which are sequentially selected from .about.M, and an output having a number equal to the subfield number at that time in synchronism with the change of the subfield signal SF, that is, switching of the subfield period. Are composed of M selection circuits SB1 to SBM which are 1: 8 selectors which are sequentially selected from .about.8. The M selection circuits SB1 to SBM are respectively connected to the outputs 1 to M of the selection circuit SA, and the eight outputs of each selection circuit SB1, SB2,..., SBM are address lines YO18 to YO11, YO28 to YO21,..., YOM8 to YOM1 are connected. In the example shown in this figure, since the input of the selection circuit SA is the clock signal CLY, the same pulse signal as the clock signal CLY is output to each of the address lines YO18 to YO11, YO28 to YO21, ..., YOM8 to YOM1. The
[0030]
The configuration of the memory YO decoder 112 shown in FIG. 6 is for explaining the function of the memory YO decoder 112, and each of the selection circuits SA and SB1 to SBM has 1 as shown in FIG. : Not limited to those composed of M or 1: 8 switches, each of the selection circuits SA, SB1 to SBM, a shift circuit that performs a shift operation in synchronization with the clock signal CLY or signal SF, a counter circuit, etc., and a transfer gate Or a combination of a plurality of gate circuits.
[0031]
Next, an operation example of the memory YO decoder 112 described with reference to FIGS. 4 and 6 will be described with reference to FIG. In the example shown in FIG. 7, when one field is divided into eight subfields, the time width of each subfield is made different so as to correspond to the weight according to the gradation. That is, the subfields 1, 2, 3,..., 8 have a period of 2 (SF−) in each subfield by setting the periods Tsf1, Tsf1 to 2 times, Tsf1 to 4 times,. 1) A time width corresponding to the power is assigned. In this case, gradation control of 2 8 (= 256) gradations is possible in each field unit. For example, as shown at the bottom of FIG. 7, the applied voltage of the pixel is controlled so that all the subfields 1 to 8 are turned on when the gradation G = 255, and the subfield when the gradation G = 130. 2 and 8 (time width: (2 + 128) × Tsf1 = 130Tsf) are controlled so that the applied voltage of the pixel is controlled. When the gradation G = 5, subfields 1 and 3 (time width: (1 + 4) ) × Tsf1 = 5Tsf), the applied voltage of the pixel is controlled.
[0032]
The scanning of each scanning line Y1 to YM is repeatedly performed for each subfield. Therefore, the clock signal CLY instructing scanning of the scanning lines Y1 to YM includes Y pulse signals PY1 to PYM corresponding to the number of scanning lines within the time width T0 which is equal to or shorter than the time width Tsf1 of the shortest subfield 1. Thus, it is generated in the controller 200. In this example, the pulse signals PY1 to PYM are set so as to be sequentially output within the time T0 from the switching time of each subfield. When the clock signal CLY and the subfield signal SF are input, the memory YO decoder 112 sets the selection output of each of the selection circuits SB1 to SBM to the first output 1 and the selection circuit in the subfield 1. The output of SA is sequentially switched according to the clock signal CLY and output to the selection circuits SB1 to SBM. That is, as shown in FIG. 7, from the address lines YO11, YO12,..., YOM1, one pulse signal in which the clock signal CLY is selected for any one of the address lines is sequentially output. Become. In FIG. 7, the description order of the address lines YO11, YO12,..., YOM1, etc. is matched with the output order of the pulses, and is different from the description order (upper and lower relations) in the block diagrams shown in FIGS. Yes. As described above, the address lines YO11, YO12,..., YOM1 collectively select the memory cells C111 to CN11, C121 to CN21,. The memory cells C111 to CN11, C121 to CN21,..., C1M1 to CNM1 include sub-pixels of N pixels P11 to PN1, P12 to PN2,. Since the ON / OFF data of field 1 is stored, N pixels on the same scanning lines Y1, Y2,..., YM are stored in the data lines X1 to XN at the selection timing of the address lines YO11, YO12,. On / off data corresponding to subfield 1 of P11 to PN1, P11 to PN1,..., P11 to PN1 are all output.
[0033]
Next, when the subfield is switched from 1 to 2, the selection circuits SB1 to SBM select the address lines YO12, YO22,..., YOM2 by connecting the second output 2 to the inputs, respectively. Therefore, one pulse signal as shown in FIG. 7 is sequentially output from each address line YO12, YO22,..., YOM2. Thereby, the memory cells C112 to CN12 in which the ON / OFF data of the subfield 2 of each of the N pixels P11 to PN1, P12 to PN2,..., P1M to PNM on the same scanning line Y1, Y2,. , C122 to CN22,..., C1M2 to CNM2 are output to the data lines X1 to XN at the selection timing of the address lines YO12, YO22,.
[0034]
When the subfield is switched from 7 to 8, the selection circuits SB1 to SBM select the address lines YO18, YO28,..., YOM8 by connecting the eighth output 8 to the inputs, respectively. Therefore, one pulse signal as shown in FIG. 7 is sequentially output from each address line YO18, YO28,..., YOM8. Thereby, the memory cells C118 to CN18 in which the ON / OFF data of the subfield 8 of each of the N pixels P11 to PN1, P12 to PN2,..., P1M to PNM on the same scanning line Y1, Y2,. , C128 to CN28,..., C1M8 to CNM8 are output to the data lines X1 to XN at the selection timing of the address lines YO12, YO22,. Thereafter, the operations in the subfields 1 to 8 are repeated as described above.
[0035]
Note that the time widths of the subfields 1 to 8 in the above description are not changed according to a multiplier of 2, but are characteristics of effective voltage and transmittance (or reflectance) applied to the liquid crystal of each pixel in one field. It is preferable to adjust the time width of each subfield so that the non-linear characteristic of the curve is compensated and the transmittance changes linearly according to the change of the gradation data. Further, the order of the subfields 1 to 8 is not limited to this embodiment, and any order may be used. Further, at the beginning of one frame, a subfield for writing the data to be in a pixel off state to all the pixels to make the contrast uniform may be added.
[0036]
As described above, according to the present embodiment, on-off information in units of subfields for each pixel can be written into a plurality of predetermined memory cells in the frame memory 111 at the same time. Data to be output to all the data lines X1 to XN can be selected in a lump for each line and each subfield. At that time, at the time of writing, the gradation data corresponding to all subfields is written to the memory cell corresponding to the selected pixel regardless of the arrangement of each pixel on the scanning line at the time of writing. By using an address line different from the used address line (word line), the memory cell selection method is changed, and a special conversion circuit such as a parallel-serial conversion circuit is not used. It can be rearranged into on-off data.
[0037]
Note that the writing of the gradation data DI to the frame memory 111 can be performed on an arbitrary pixel and at an arbitrary timing regardless of the arrangement of the pixels. Therefore, rewriting of the gradation data of each pixel is performed at an arbitrary timing as necessary, or even when rewriting at the earliest cycle, it is possible to perform frame unit by corresponding to or synchronizing with the frame cycle. It is possible to perform gradation control. In addition, it is not necessary to change the gradation data of all the pixels for each frame period, and only the gradation data corresponding to the pixels in the area where the display gradation needs to be changed may be rewritten. That is, according to the present embodiment, when the gradation data DI is supplied from the controller 200 to the drive circuit 100, the total data for each pixel is compared with the conventional method using serial data and subfield units. Since the gradation data corresponding to the subfield is transferred as parallel data, the transfer frequency can be reduced. Furthermore, in the present embodiment, by using a frame memory configured by a random access memory provided in the drive circuit 100, random writing can be performed regardless of the pixel or frame period, so that transfer data can be rewritten. In combination with control such as limiting to pixels in a part of the region that requires a large transfer frequency, a significant transfer frequency reduction effect can be obtained.
[0038]
In the above embodiment, the time axis modulation control by 8 subfields is performed using all the 8-bit memory cells provided corresponding to each pixel. For example, 7 to 5 bits are used. In addition, the memory YO decoder 112 selects 7 to 5 outputs of the selection circuits SB1 to SBM so that the number of subfields differs from the number of bits of the memory. It is also possible to perform adjustment control.
[0039]
Note that the configuration of the memory cell shown in FIG. 5 is an example of a basic circuit configuration of the 2-port memory cell, and the configuration of the memory cell is changed or the selection circuit of the memory cell is changed. Thus, it is possible to appropriately change the provision of a circuit such as preventing simultaneous access to two ports. For example, as shown in FIG. 4, when the clock signal CLY is input to the memory YI decoder 1112, for example, when the clock signal CLY is at “1” level in the memory YI decoder 1112, the address line YI 1 A circuit that does not select .about.YIN can be provided, and a circuit that does not simultaneously write and read data to each memory cell can be added.
[0040]
Next, referring to FIGS. 8 and 9, as a modification of the above embodiment, the time width of each subfield is made the same, and the on-time within the period of each subfield is set to a weight corresponding to the gradation. A description will be given of a configuration example in the case where gradation control is performed by making different. In this case, as shown in FIG. 8, for example, one field period is divided into eight subfields 1 to 8 having the same time width Tsf, and the on time of each subfield is set to T1 time in subfield 1, The subfield 2 is set to T1 × 2 hours, the subfield 3 is set to T1 × 4 hours,..., And the subfield 8 is set to T1 × 128 hours. In this case, the ON time T1 × 128 in the subfield 8 is a value that does not exceed the time width Tsf of the subfield period. In this embodiment, since the scanning of the scanning lines for turning on and off the pixels is required within one subfield period, the controller 200 receives two times of on time and off time for each subfield. Are supplied with clock signals CLY (M pulse signals YP1 to YPM, respectively). The M pulse signals YP1 to YPM are generated at the start of the on-time and at the start of the off-time, but all the pulse signals YP1 to YPM have the shortest on-time T1 and the shortest off-time (subfield 8). Is set to be generated within time T2, which is shorter than the off time (Tsf−T1 × 128)).
[0041]
Note that the time widths of the subfields 1 to 8 in the above description are not changed according to a multiplier of 2, but are characteristics of effective voltage and transmittance (or reflectance) applied to the liquid crystal of each pixel in one field. It is preferable to adjust the time width of each subfield so that the non-linear characteristic of the curve is compensated and the transmittance changes linearly according to the change of the gradation data. Further, the order of the subfields 1 to 8 is not limited to this embodiment, and any order may be used. Further, at the beginning of one frame, a subfield for writing the data to be in a pixel off state to all the pixels to make the contrast uniform may be added.
[0042]
As shown in FIG. 9, in the present embodiment, a conversion circuit 801 for converting a subfield signal SF into a signal SFP whose level changes in accordance with on-time and off-time in the memory YO decoder 112a; As an input of the selection circuit SA, an AND gate 802 for supplying a logical product of the clock signal CLY and the signal SFP is provided. As a result, a clock pulse corresponding to two scans is supplied as the clock signal CLY in each subfield period, but from the memory YO decoder 112a, the signal SFP is in a period corresponding to the “1” level. The clock signal CLY for one scan is valid as an input signal, and a selection signal is output from each of the address signal lines YO11 to YOM8. Therefore, when the signal SFP is “1” level, the data of the memory cells C111 to CNM8 selected by the address signal lines YO11 to YOM8 in the frame memory 111 are output from the data lines X1 to XN, but the signal SFP Since the memory cells C111 to CNM8 are not selected when the signal is at the “0” level, only the signals for turning off the respective pixels are output from the data lines X1 to XN.
[0043]
In the above embodiment, a liquid crystal display device is used as the electro-optical device. For example, an electroluminescence (EL) display, a field emission display (FED), a digital mirror device (DMD), a plasma display (PDP) It is possible to apply the present invention to an electro-optical device that performs gradation display using other pixels that perform binary display of ON or OFF. However, for example, when an organic EL display or the like is used, changes such as not performing AC driving are appropriately performed.
[0044]
Next, the structure of the electro-optical device (liquid crystal panel) 300 in the above-described embodiment will be described with reference to FIGS. Here, FIG. 10 is a plan view showing the configuration of the electro-optical device 300, and FIG. 11 is a cross-sectional view taken along the line AA 'in FIG. As shown in these drawings, the electro-optical device 300 includes an element substrate 301 on which a pixel electrode P103 and the like are formed, and a counter substrate 302 on which the counter electrode P105 and the like are formed with a certain gap between each other by a sealant 304. And a liquid crystal P104 as an electro-optical material is sandwiched between the gaps. Actually, the sealing material 304 has a cut-out portion, and after the liquid crystal P104 is sealed through this, the sealing material 304 is sealed with a sealing material, but is omitted in these drawings. Here, since the element substrate 301 is a semiconductor substrate as described above, it is opaque. For this reason, the pixel electrode P103 is formed of a reflective metal such as aluminum, and the electro-optical device 300 is used as a reflective type. On the other hand, since the counter substrate 302 is made of glass or the like, it is transparent. Now, in the element substrate 301, a light shielding film 306 is provided on the inner side of the sealant 304 and on the outer side of the display region 301a. In the region where the light shielding film 306 is formed, the Y driver 120 is formed in the region 330a, and the X driver 110 is formed in the region 340a. As described above, the X driver 110 includes (number of pixels) × (number of subfields) memory cells. That is, the light shielding film 306 prevents light from entering the drive circuit formed in this region. An AC voltage (LCcom) based on the level of the AC drive signal FR is applied to the light shielding film 306 along with the counter electrode P105. For this reason, in the region where the light-shielding film 306 is formed, the voltage applied to the liquid crystal layer becomes almost zero, so that the display state is the same as the voltage non-application state of the pixel electrode P103. In the element substrate 301, a plurality of connection terminals are formed in a region 307 outside the region 340 a where the X driver 110 is formed and separated from the sealant 304, so that an external control signal, a power source, and the like are supplied. It is configured to input. In the electro-optical device 300, the transistors of each pixel and the transistors of the drive circuits of the Y driver 120 and the X driver 110 can be operated by a single power supply voltage supplied from the power input terminal of the electro-optical device. Therefore, it is not necessary to generate a large number of voltage levels, so that power consumption is reduced, level shift is not required, and the circuit configuration is simplified. The liquid crystal P104 includes a TN (Twisted Nematic) type, STN (Supper Twisted Nematic) type, polymer dispersion type, ferroelectric type, bistable TN (Bi-stable Twisted Nematic) type, vertical alignment type, and no twist. Various types of liquid crystal such as a horizontal alignment type can be used.
[0045]
On the other hand, the counter electrode P105 of the counter substrate 302 is electrically connected to the light shielding film 306 and the connection terminal in the element substrate 301 by a conductive material (not shown) provided in at least one of the four corners of the substrate bonding portion. Conduction is achieved. That is, the voltage LCcom based on the AC drive signal FR is applied to the light shielding film 306 via the connection terminal provided on the element substrate 301 and further to the counter electrode P105 via the conductive material. ing. In addition, the counter substrate 302 is first provided with a color filter arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the electro-optical device 300, for example, if it is a direct view type. Second, a light shielding film (black matrix) made of, for example, a metal material or resin is provided. In the case of use of color light modulation, for example, when used as a light valve of a projector described later, no color filter is formed. In the case of the direct view type, the electro-optical device 300 is provided with a front light that emits light from the counter substrate 302 side as necessary. In addition, the electrode formation surfaces of the element substrate 301 and the counter substrate 302 are each provided with an alignment film (not shown) that is rubbed in a predetermined direction to define the alignment direction of the liquid crystal molecules when no voltage is applied. On the other hand, a polarizer (not shown) corresponding to the orientation direction is provided on the counter substrate 301 side. However, if a polymer-dispersed liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal P104, the above-described alignment film, polarizer, and the like are not required. As a result, the light utilization efficiency is increased. This is advantageous in terms of reducing power consumption.
[0046]
In the above embodiment, the element substrate 301 constituting the electro-optical device is a semiconductor substrate, and the transistor P106 connected to the pixel electrode P103, the constituent elements of the drive circuit, and the like are formed of MOS type FETs. However, the present invention is not limited to this. For example, the element substrate 301 may be an amorphous substrate such as glass or quartz, or a plastic substrate, and a semiconductor thin film may be deposited thereon to form a TFT. When TFTs are used in this way, a transparent substrate can be used as the element substrate 301. In this case, the transistors constituting all or part of the peripheral circuits such as the transistors of each pixel and the X driver and Y driver are formed of TFTs on the transparent substrate.
[0047]
Here, when the element substrate is a substrate made of glass, quartz, plastic, or the like, it may be difficult to make the circuit of the X driver 110 incorporating the frame memory 111 on the element substrate by TFT. In such a case, the frame memory or the like in the X driver is constituted by a semiconductor integrated circuit, the output circuit portion to the data line is constituted by a TFT on the element substrate, and the semiconductor integrated circuit is formed on the element substrate by a COG (Chip On Glass) method.
[0048]
Furthermore, as an electro-optic material, in addition to liquid crystal, an electroluminescence element (EL) or the like can be used for an apparatus that performs display by the electro-optic effect. In the case of liquid crystal, it is necessary to periodically drive alternating current, but in the case of organic EL, it is not necessary to periodically drive alternating current. In other words, the present invention can be applied to any electro-optical device having a configuration similar to the above-described configuration, particularly to any electro-optical device that performs gradation display using pixels that perform binary display that is on or off. It is.
[0049]
Next, some examples in which the above-described liquid crystal device is used in a specific electronic device will be described. First, a projector using the electro-optical device according to the embodiment as a light valve will be described. FIG. 12 is a plan view showing the configuration of the projector. As shown in this figure, in the projector 1100, a polarization illumination device 1110 is arranged along the system optical axis PL. In this polarization illumination device 1110, the light emitted from the lamp 1112 becomes a substantially parallel light beam as reflected by the reflector 1114, and enters the first integrator lens 1120. Thereby, the emitted light from the lamp 1112 is divided into a plurality of intermediate light beams. The divided intermediate light beam is converted into a single type of polarized light beam (s-polarized light beam) having substantially the same polarization direction by a polarization conversion element 1130 having a second integrator lens on the light incident side, and the polarized illumination device 1110 It will be emitted from.
[0050]
Now, the s-polarized light beam emitted from the polarization illumination device 1110 is reflected by the s-polarized light beam reflecting surface 1141 of the polarization beam splitter 1140. Of this reflected light beam, the blue light (B) light beam is reflected by the blue light reflecting layer of the dichroic mirror 1151 and modulated by the reflective electro-optical device 300B. Of the light beams that have passed through the blue light reflection layer of the dichroic mirror 1151, the red light (R) light beam is reflected by the red light reflection layer of the dichroic mirror 1152, and is modulated by the reflective liquid electro-optical device 300R. The On the other hand, among the light beams transmitted through the blue light reflection layer of the dichroic mirror 1151, the green light (G) light beam is transmitted through the red light reflection layer of the dichroic mirror 1152 and modulated by the reflective electro-optical device 300G. .
[0051]
In this way, the red, green, and blue lights that have been color-light modulated by the electro-optical devices 300R, 300G, and 300B are sequentially synthesized by the dichroic mirrors 1152 and 1151, and the polarization beam splitter 1140, and then are projected by the projection optical system 1160. Is projected on the screen 1170. In addition, since the luminous flux corresponding to each primary color of R, G, and B is incident on the electro-optical devices 300R, 300B, and 300G by the dichroic mirrors 1151, 1152, a color filter is not necessary.
[0052]
Next, an example in which the electro-optical device is applied to a mobile personal computer will be described. FIG. 13 is a perspective view showing the configuration of the personal computer. In the figure, a computer 1200 includes a main body 1204 having a keyboard 1202 and a display unit 1206. The display unit 1206 is configured by adding a front light to the front surface of the electro-optical device 300 described above.
[0053]
In this configuration, since the electro-optical device 300 is used as a reflection direct view type, it is desirable that the pixel electrode P103 has irregularities so that the reflected light is scattered in various directions.
[0054]
Further, an example in which the electro-optical device is applied to a mobile phone will be described. FIG. 14 is a perspective view showing the configuration of this mobile phone. In the figure, a mobile phone 1300 includes an electro-optical device 300 in addition to a plurality of operation buttons 1302, as well as an earpiece 1304 and a mouthpiece 1306. The electro-optical device 300 is also provided with a front light on the front surface as necessary. Also in this configuration, since the electro-optical device 300 is used as a reflection direct view type, it is desirable that the pixel electrode P103 has irregularities.
[0055]
In addition to the electronic devices described with reference to FIGS. 12 to 14, liquid crystal televisions, viewfinder type, monitor direct-view type video tape recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors , Workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the electro-optical device according to the embodiment or the modification can be applied to these various electronic devices.
[0056]
【The invention's effect】
According to the present invention, a storage means having a plurality of storage areas for storing on-off data of each subfield for each pixel and a plurality of storage areas of the storage means corresponding to each scanning line are selected for each subfield. Corresponding selection means for collectively selecting information is provided, so that information indicating the on / off state of each pixel input from the outside to the drive circuit that drives and controls the applied voltage of each pixel by the time-axis modulation method is provided. The transfer frequency can be reduced compared to the conventional case.
[0057]
Further, by simply addressing (number of pixels) × (number of subfields) data stored in the storage means, pixel on / off data for one line can be read line-sequentially. The circuit configuration is simplified.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a drive circuit and its peripheral circuits of an electro-optical device according to the present invention.
FIG. 2 is a block diagram showing a configuration of the liquid crystal panel 300 of FIG.
3 is a block diagram showing a configuration example of pixels P11 to PNM in FIG. 2;
4 is a block diagram showing a configuration example of an X driver 110 in FIG. 1. FIG.
FIG. 5 is a block diagram illustrating a configuration example of a memory cell Cjkm in FIG. 4;
6 is a block diagram showing a configuration example of a memory YO decoder (selection circuit) 112 in FIG. 4;
7 is a timing chart for explaining an operation example of the memory YO decoder 112 in FIG. 6;
8 is a timing chart for explaining the operation of a modified example of the memory YO decoder 112 of FIG. 6;
9 is a block diagram showing a configuration of a modified example of the memory YO decoder 112 in FIG. 6;
10 is a plan view showing the structure of the electro-optical device (liquid crystal panel) 300 according to the present invention shown in FIG.
11 is a cross-sectional view showing the structure of the electro-optical device 300 of FIG.
12 is a cross-sectional view illustrating a configuration of a projector that is an example of an electronic apparatus to which the electro-optical device 300 of FIG. 10 is applied.
13 is a perspective view illustrating a configuration of a personal computer which is an example of an electronic apparatus to which the electro-optical device 300 in FIG. 10 is applied.
14 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the electro-optical device 300 in FIG. 10 is applied.
[Explanation of symbols]
100 …… Drive circuit
110 …… X driver
111 …… Frame memory
112 ... Selection circuit (memory YO decoder)
120 …… Y driver
200 …… Controller
300 …… Liquid crystal display

Claims (7)

For each pixel arranged corresponding to each intersection of a plurality of data lines and a plurality of scanning lines, an on state and an off state are controlled in units of a plurality of subfields obtained by dividing one field, In the drive circuit of the electro-optical device that performs gradation display by weighting the time in which each pixel is turned on in the subfield according to the gradation of the pixel,
Storage means comprising a plurality of memory cells for storing data indicating the on state or the off state of the pixel in each subfield in a storage area provided corresponding to each pixel;
Scanning line side driving means for sequentially selecting the plurality of scanning lines for each subfield based on a selection timing indicated by a clock signal;
Reading means for reading out the data to be given to a plurality of pixels corresponding to the scanning line selected by the scanning line side driving means from the memory cell in the storage means;
Data line side driving means for supplying a voltage for setting each pixel to the on state or the off state via the plurality of data lines based on the data read by the reading means;
The readout means includes a selection circuit for selecting a memory cell that stores the data supplied to a plurality of pixels corresponding to a scanning line selected in each subfield,
The selection circuit is supplied with a pulse signal that is the same as the clock signal and a predetermined signal that is turned on in response to the time that each pixel is turned on in each subfield,
The memory cell is selected by supplying the same pulse signal as the clock signal included in the period in which the predetermined signal is on level to the memory cell, while the predetermined signal is in the period in which the predetermined signal is off level. The memory cell is not selected by not supplying the same pulse signal as the clock signal to the memory cell,
The drive circuit of the electro-optical device, wherein the selected memory cell outputs the data based on the same pulse signal as the supplied clock signal.   2. The electro-optical device according to claim 1, further comprising writing means for writing data corresponding to each subfield into a storage area corresponding to a pixel arbitrarily selected from the plurality of storage areas in the storage means. Driving circuit.   The reading means selects a plurality of storage areas of the storage means by a first selection means and reads data, and the writing means is selected by a second selection means independent of the first selection means. 3. The drive circuit for an electro-optical device according to claim 2, wherein data is written by selecting a storage area corresponding to an arbitrary pixel.   4. The storage means stores (number of pixels) × (number of subfields) binary signals, and each binary signal indicates an on state and an off state of a pixel. The drive circuit for the electro-optical device according to any one of the above. Each pixel arranged corresponding to each intersection of a plurality of data lines and a plurality of scanning lines is controlled in an on state and an off state in units of a plurality of subfields obtained by dividing one field, and In the driving method of the electro-optical device in which gradation display is performed by weighting the time during which each pixel is turned on in the field according to the gradation of the pixel,
Data indicating the on state or the off state of each pixel in each subfield is stored in each of a plurality of memory cells in a storage area provided corresponding to each pixel in the storage means,
The plurality of scanning lines are sequentially selected based on a selection timing indicated by a clock signal for each subfield,
Using the same pulse signal as the clock signal and a predetermined signal that is on level corresponding to the time that each pixel is turned on in each subfield,
The memory cell is selected by supplying the same pulse signal as the clock signal included in the period in which the predetermined signal is in the on level to the memory cell, while the predetermined signal is in the period in which the predetermined signal is in the off level. By not supplying the same pulse signal as the clock signal to the memory cell, the memory cell is not selected, so that the memory cell can be selected from the memory cell based on the same pulse signal. Read data to be given to multiple pixels,
Based on the read data, supply a voltage for turning on or off the plurality of pixels via the plurality of data lines,
An electro-optical device characterized by rewriting data corresponding to a pixel among data corresponding to each pixel stored in the storage means when a change occurs in gradation data corresponding to any pixel. Driving method. An electro-optical device having a plurality of pixels arranged corresponding to each intersection of a plurality of data lines and a plurality of scanning lines,
5. An electro-optical device that is driven and controlled by the drive circuit for the electro-optical device according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 6 as a display device.

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