JP3798760B2 - Method for forming semiconductor wafer - Google Patents

Method for forming semiconductor wafer Download PDF

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JP3798760B2
JP3798760B2 JP2003115507A JP2003115507A JP3798760B2 JP 3798760 B2 JP3798760 B2 JP 3798760B2 JP 2003115507 A JP2003115507 A JP 2003115507A JP 2003115507 A JP2003115507 A JP 2003115507A JP 3798760 B2 JP3798760 B2 JP 3798760B2
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Prior art keywords
semiconductor wafer
forming
wafer
protective member
bump
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JP2003115507A
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JP2004327464A (en
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浩志 松坂
孝志 佐藤
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株式會社塩山製作所
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Description

【0001】
【発明の属する技術分野】
本発明は、半導体ウェハを形成する方法であって、特に、電気的接点となるバンプ電極を半導体ウェハの回路形成面に形成するための形成方法に関する。
【0002】
【従来の技術】
近年、ICカード、携帯電話、PDA等の携帯型電子機器の高性能化や小型薄型化に伴い、各種電子部品を基板の表面に実装することができる表面実装方式が多く採用されている。このような表面実装方式の電子デバイスを製造する場合は、ウェハプロセスの過程で電極用のバンプを形成するための工程が設けられている。
【0003】
図4及び図5は、従来のバンプ電極の形成を中心とした半導体ウェハの製造工程を示したものである。ここで、図4はバンプ形成工程で、図5はバックグラインド工程を示す。図4に示したバンプ形成工程では、所定厚みにスライスされた半導体ウェハ(ウェハ1)の回路形成面2に、UMB(アンダー・メタル・バンプ)スパッタリングを用いて金蒸着膜3を形成する(工程a,b)。そして、前記金蒸着膜3にレジスト膜4を形成し(工程c)、このレジスト膜4の上にバンプの形成パターンが描かれたフォトレジスト膜5を被着する(工程d)。次に、前記フォトレジスト膜5の上からレーザ光あるいは紫外線を照射して露光処理(工程e)を行った後、前記フォトレジスト膜5でマスクした以外の部分をエッチングによって除去することで、所定のバンプ電極7がウェハ1の回路形成面2上に形成される(工程f)。
【0004】
前記バンプ電極7が形成されたウェハ1は、図5に示されるように、バンプ電極7の形成面をバックグラインド処理用の作業台8に載置し、前記バンプ電極7の形成面と反対側の裏面9をバックグラインダ10を回転させながら押圧していき、所定の厚みになるまで研削して薄型化している(工程g,h)。
【0005】
【発明が解決しようとする課題】
しかしながら、上記ウェハ1にバンプ電極7を形成した後、バックグラインド工程に移行してウェハ1全体を薄く研削する方法では、バックグラインド処理中にバンプ形成面が作業台8に擦られて、先に形成されたバンプ電極7の形状が潰れてしまうといった問題がある。
【0006】
また、ある一定の厚み(500μm以下)に薄型化されたウェハにあっては、バックグラインド工程やバンプ形成工程における負荷に耐えきれずにウェハが反ったり、歪んだりしてしまうおそれがある。このようなことも原因となって、先に形成されたバンプ電極の形状が歪んでしまったり、潰れてしまったりする場合がある。
【0007】
以上のような問題が発生すると、ウェハ1自体が損傷すると共に、バンプ電極7の形成に関しても加工精度が悪くなるなどの悪影響を及ぼすこととなる。
【0008】
そこで、本発明の目的は、半導体ウェハの薄型化に伴う反りや湾曲を抑えることによって、形状の一定した電極用のバンプを高精度且つ迅速に形成する半導体ウェハの形成方法を提供することにある。
【0009】
【課題を解決するための手段】
上記課題を解決するために、本発明に係る半導体ウェハの形成方法は、研磨加工する作業台の上に半導体ウェハの回路形成面を有する表面側が接するように半導体ウェハを載置した後、半導体ウェハの裏面を研磨加工して厚みを薄くし、この薄く加工された半導体ウェハの裏面に石英ガラス、金属又はシリコンからなる保護部材を貼着した後、前記半導体ウェハの回路形成面にバンプ電極部を形成し、このバンプ電極部の形成後に前記保護部材を半導体ウェハの裏面から剥離することによって、前記半導体ウェハの裏面を露出させたことを特徴とする。
【0010】
この発明によれば、研磨加工において半導体ウェハを所定の厚みに薄型化した後、前記半導体ウェハの裏面に一定の厚み及び強度を備えた保護部材を貼着することで、この後に実施するバンプ形成工程における半導体ウェハの反りや湾曲を防止することができる。このため、バンプ形成工程において、半導体ウェハに機械的な負荷が掛かったり、温度変動等が発生しても、精度よくバンプ電極を形成することができる。また、バンプ形成工程を研磨加工のような半導体ウェハに大きな負荷が掛かる工程の後に実施することによって、先に形成されたバンプ電極が潰れるといったような不具合も発生しなくなる。
【0011】
また、前記半導体ウェハに貼着する保護部材に石英ガラスを使用することで、衝撃や温度変化に対する耐性が高まるので、半導体ウェハのさらなる薄型化が図られる。
【0012】
【発明の実施の形態】
以下、添付図面に基づいて本発明の半導体ウェハの形成方法について説明する。図1乃至図3は、半導体ウェハのバックグラインド処理からバンプ電極を形成するまでの流れを示す工程図である。
【0013】
本実施形態における半導体ウェハの形成方法は、半導体ウェハ(以下、単にウェハという)の数あるプロセスの中にあって、バンプ電極の形成に関わる工程を中心としたものである。この一連の工程は、ウェハを一定厚みに研磨加工するバックグラインド工程、前記ウェハに補強用の保護部材を貼着する保護部材貼着工程、前記ウェハ面に電極用のバンプを形成するバンプ形成工程及び保護部材剥離工程とからなっている。なお、前記一連の工程における作業は、加工中のウェハに埃が付いたり、温度や湿度変化によって変形しないように、温度・湿度が管理された一定の減圧条件の下で行われる。
【0014】
前記バックグラインド工程では、図示しない前処理工程で回路形成面が形成されたウェハの裏面を研磨して薄く平坦化する作業が行われる。ここでは、図1(工程a,b)に示すように、前記ウェハ21の回路形成面22に保護シート(図示せず)を被せ、この回路形成面22を下にして作業台28に置き、ウェハ21の裏面29にバックグラインダ10を回転させながら押圧していき、前記ウェハ21を所定の厚みになるように均一に研磨加工する。このバックグラインド工程によって、前記ウェハ21は、通常500μm程度の厚みから250μm程度の厚みに研磨されるが、薄型化に対応した製品に使用される場合は、30μm程度にまで研磨することが可能である。
【0015】
次の保護部材貼着工程では、前記バックグラインド工程において薄型化されたウェハ21の裏面29に保護部材であるガラス基板が貼着される。このガラス基板の貼着にあたって、最初に前記薄型化されたウェハ21の裏面29にレジスト膜31を形成する(工程c)。そして、前記レジスト膜31が形成された面に粘着剤であるワックス32を均一に塗布する(工程d)。このワックス32は、樹脂とアルコールを混合した材料からなる液状体で、固化した後は200℃程度の高温に対しても一定の粘着力を保持できるようになっている。続いて、前記ワックス32が塗布された面にガラス基板33を載置し、押圧してウェハ21と接合する(工程e)。前記ガラス基板33は、貼着されるウェハ21と同径か、それよりも一回り大きい板体に形成されたもので、厚みが1000μm程度の石英ガラスが使用される。このような石英ガラスは、外部からの衝撃やウェハプロセス中に掛かる温度変動に対して、変形や腐蝕等の発生が抑えられる。なお、前記ガラス基板33との粘着性を高めるために、前記ウェハ21を100〜130℃に加熱してワックス32を軟化させた上で、接合面に気泡が入らないように、均等な圧力を掛けながら行う。
【0016】
図2に示すバンプ形成工程では、前記貼着したガラス基板33を下にしたウェハ21を作業台に載置し(工程f)、上面に露出した回路形成面22にUMBスパッタリングによって、金蒸着膜23を形成する(工程g)。この金蒸着膜23は、バンプ電極の下地部材であって、良質な導電性を備えている。次に、前記金蒸着膜23の上にレジスト膜24を形成し(工程h)、その上にバンプ電極パターンが形成されたフォトレジスト膜25を被着する(工程i)。そして、前記フォトレジスト膜25の上からレーザ光あるいは紫外線を照射して露光(工程j)することで、バンプ電極パターン以外の部分のレジスト膜24及びフォトレジスト膜25を除去する。続いて、前記レジスト膜24及びフォトレジスト膜25でマスクされた箇所を残してエッチングを行う。最後に前記バンプ電極27上に残ったレジスト膜24及びフォトレジスト膜25をきれいに除去して、バンプ電極27を上面に露出させる(工程k)。
【0017】
図3に示す保護部材剥離工程では、前記バンプ形成工程でバンプ電極27が形成されたウェハ21からガラス基板33を剥離する(工程l)。この剥離作業では、ガラス基板33との間に介在しているワックス32を溶融した上で、前記ウェハ21面に傷が付かないように静かに引き剥がす。最後に、ウェハ21の洗浄工程に移行して、前記ガラス基板33を剥離した後に残ったワックス32や微小な埃を洗い流す(工程m)。このような一連の工程を経たウェハ21は、ダイシング工程や組立工程等の後処理工程に移行して個別の半導体チップが形成される。
【0018】
以上説明したように、バックグラインド工程からバンプ形成工程に移行する間に保護部材貼着工程を設けたことで、薄く研削加工されたウェハ21を補強することができ、後のバンプ形成処理が容易となった。従来の形成方法では、ウェハの厚みが250μm以下になると、バンプ電極の形成不良率が多くなるため、薄型化が制限されていたが、本発明の形成方法によれば、バックグラインド工程で可能な30μm程度の薄さに対してもバンプ電極を精度よく形成することができる。また、前記バンプ形成工程をバックグラインド工程の後に実施することで、形成したバンプの形状がばらついたり、形が崩れるといったバンプ形成不良を低減させることができる。
【0019】
上記実施形態ではウェハを構成する原料がシリコンであったが、このようなシリコン以外にもセレン、ゲルマニウムなどの酸化物で構成されたウェハ等にも応用可能であり、ウェハのサイズについても限定されない。
【0020】
なお、本実施形態では、ウェハに貼着する保護部材に石英ガラスを用いたが、このような石英ガラスでなくとも同様な強度や厚みを備えた材料であれば、金属やシリコンでも問題なく使用することができる。
【0021】
【発明の効果】
以上説明したように、本発明に係る半導体ウェハの形成方法によれば、半導体ウェハに対してバックグラインド処理やバンプ電極形成処理を行う際に、前記半導体ウェハに補強用の支持部材を貼着して行うので、前記バックグラインド作業やバンプ形成作業中における衝撃や温度変化による撓み変形が発生しない。このため、薄型でありながら、品質の安定した半導体チップの大量生産が可能となる。
【図面の簡単な説明】
【図1】本発明に係る半導体ウェハの形成方法におけるバックグラインド工程及び保護部材貼着工程を示す説明図である。
【図2】上記半導体ウェハの形成方法におけるバンプ形成工程を示す説明図である。
【図3】上記半導体ウェハの形成方法における保護部材剥離工程を示す説明図である。
【図4】従来の半導体ウェハの形成方法におけるバンプ形成工程を示す説明図である。
【図5】上記従来の半導体ウェハの形成方法におけるバックグラインド工程を示す説明図である。
【符号の説明】
21 ウェハ
22 回路形成面
23 金蒸着膜
24 レジスト膜
25 フォトレジスト膜
27 バンプ電極
32 ワックス
33 ガラス基板(保護部材)
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a semiconductor wafer, and more particularly to a forming method for forming bump electrodes serving as electrical contacts on a circuit forming surface of a semiconductor wafer.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the improvement in performance and size and thickness of portable electronic devices such as IC cards, mobile phones, and PDAs, many surface mounting methods that can mount various electronic components on the surface of a substrate have been adopted. In the case of manufacturing such a surface mounting type electronic device, a step for forming bumps for electrodes is provided in the course of a wafer process.
[0003]
4 and 5 show a semiconductor wafer manufacturing process centering on the formation of a conventional bump electrode. Here, FIG. 4 shows a bump forming process, and FIG. 5 shows a back grinding process. In the bump formation step shown in FIG. 4, a gold vapor deposition film 3 is formed on the circuit formation surface 2 of a semiconductor wafer (wafer 1) sliced to a predetermined thickness using UMB (under metal bump) sputtering (step). a, b). Then, a resist film 4 is formed on the gold vapor deposition film 3 (step c), and a photoresist film 5 on which a bump formation pattern is drawn is deposited on the resist film 4 (step d). Next, an exposure process (step e) is performed by irradiating the photoresist film 5 with laser light or ultraviolet rays, and then a portion other than the masked with the photoresist film 5 is removed by etching. The bump electrode 7 is formed on the circuit forming surface 2 of the wafer 1 (step f).
[0004]
As shown in FIG. 5, the wafer 1 on which the bump electrode 7 is formed has the bump electrode 7 forming surface placed on a work table 8 for back grinding, and is opposite to the bump electrode 7 forming surface. The back surface 9 is pressed while rotating the back grinder 10, and is ground to a predetermined thickness to reduce the thickness (steps g and h).
[0005]
[Problems to be solved by the invention]
However, in the method in which the bump electrode 7 is formed on the wafer 1 and then the process proceeds to the back grinding process and the entire wafer 1 is ground thinly, the bump forming surface is rubbed against the work table 8 during the back grinding process. There is a problem that the shape of the formed bump electrode 7 is crushed.
[0006]
In addition, in a wafer thinned to a certain thickness (500 μm or less), the wafer may be warped or distorted without being able to withstand the load in the back grinding process or the bump forming process. For this reason, the shape of the bump electrode formed previously may be distorted or crushed.
[0007]
When the above problems occur, the wafer 1 itself is damaged, and the formation of the bump electrode 7 is also adversely affected such that the processing accuracy is deteriorated.
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a semiconductor wafer in which bumps for electrodes having a constant shape are formed with high accuracy and speed by suppressing warpage and curvature associated with thinning of the semiconductor wafer. .
[0009]
[Means for Solving the Problems]
In order to solve the above-described problems, a method for forming a semiconductor wafer according to the present invention includes : placing a semiconductor wafer on a work table to be polished so that a surface side having a circuit forming surface of the semiconductor wafer is in contact; The back surface of the semiconductor wafer is polished to reduce the thickness, and a protective member made of quartz glass, metal or silicon is attached to the back surface of the thinly processed semiconductor wafer, and then the bump electrode portion is formed on the circuit forming surface of the semiconductor wafer. The back surface of the semiconductor wafer is exposed by peeling the protective member from the back surface of the semiconductor wafer after forming the bump electrode portion .
[0010]
According to the present invention, after the semiconductor wafer is thinned to a predetermined thickness in the polishing process, a protective member having a certain thickness and strength is adhered to the back surface of the semiconductor wafer, so that bump formation is performed thereafter. It is possible to prevent warping or bending of the semiconductor wafer in the process. For this reason, in the bump forming process, even if a mechanical load is applied to the semiconductor wafer or a temperature variation occurs, the bump electrode can be formed with high accuracy. Further, when the bump forming process is performed after a process in which a large load is applied to the semiconductor wafer, such as polishing, a problem such as a collapse of the previously formed bump electrode does not occur.
[0011]
In addition, since quartz glass is used as the protective member to be attached to the semiconductor wafer, resistance to impact and temperature change is increased, so that the semiconductor wafer can be further reduced in thickness.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a method for forming a semiconductor wafer according to the present invention will be described with reference to the accompanying drawings. 1 to 3 are process diagrams showing the flow from the back grinding process of a semiconductor wafer to the formation of bump electrodes.
[0013]
The method for forming a semiconductor wafer in the present embodiment is a process in which there are a number of semiconductor wafers (hereinafter simply referred to as wafers), and is centered on processes related to the formation of bump electrodes. This series of processes includes a back grinding process for polishing a wafer to a constant thickness, a protective member attaching process for attaching a reinforcing protective member to the wafer, and a bump forming process for forming electrode bumps on the wafer surface. And a protective member peeling step. The operations in the series of steps are performed under a certain decompression condition in which the temperature and humidity are controlled so that the wafer being processed does not become dusty or deforms due to changes in temperature or humidity.
[0014]
In the back grinding process, an operation of polishing and flattening the back surface of the wafer on which the circuit forming surface is formed in a pre-processing process (not shown) is performed. Here, as shown in FIG. 1 (steps a and b), the circuit forming surface 22 of the wafer 21 is covered with a protective sheet (not shown) and placed on the work table 28 with the circuit forming surface 22 facing down. The back grinder 10 is pressed against the back surface 29 of the wafer 21 while rotating, and the wafer 21 is uniformly polished to a predetermined thickness. By this back grinding process, the wafer 21 is usually polished from a thickness of about 500 μm to a thickness of about 250 μm. However, when used for a product corresponding to a reduction in thickness, it can be polished to about 30 μm. is there.
[0015]
In the next protective member attaching step, a glass substrate as a protective member is attached to the back surface 29 of the wafer 21 that has been thinned in the back grinding step. In attaching the glass substrate, first, a resist film 31 is formed on the back surface 29 of the thinned wafer 21 (step c). Then, a wax 32 as an adhesive is uniformly applied to the surface on which the resist film 31 is formed (step d). The wax 32 is a liquid material made of a material in which a resin and alcohol are mixed, and can maintain a certain adhesive force even at a high temperature of about 200 ° C. after solidification. Subsequently, the glass substrate 33 is placed on the surface coated with the wax 32 and pressed to join the wafer 21 (step e). The glass substrate 33 is formed in a plate body having the same diameter as the wafer 21 to be adhered or a size larger than that, and quartz glass having a thickness of about 1000 μm is used. Such quartz glass can suppress the occurrence of deformation, corrosion and the like against external impacts and temperature fluctuations applied during the wafer process. In order to increase the adhesion to the glass substrate 33, the wafer 21 is heated to 100 to 130 ° C. to soften the wax 32, and an equal pressure is applied so that bubbles do not enter the bonding surface. Do it while hanging.
[0016]
In the bump forming step shown in FIG. 2, the wafer 21 with the adhered glass substrate 33 is placed on a work table (step f), and a gold deposited film is formed on the circuit forming surface 22 exposed on the upper surface by UMB sputtering. 23 is formed (step g). The gold vapor deposition film 23 is a base member for the bump electrode and has good conductivity. Next, a resist film 24 is formed on the gold vapor deposition film 23 (step h), and a photoresist film 25 having a bump electrode pattern formed thereon is deposited thereon (step i). Then, the photoresist film 25 and the photoresist film 25 other than the bump electrode pattern are removed by irradiating the photoresist film 25 with laser light or ultraviolet light and performing exposure (step j). Subsequently, etching is performed leaving a portion masked by the resist film 24 and the photoresist film 25. Finally, the resist film 24 and the photoresist film 25 remaining on the bump electrode 27 are removed cleanly to expose the bump electrode 27 on the upper surface (step k).
[0017]
In the protective member peeling step shown in FIG. 3, the glass substrate 33 is peeled from the wafer 21 on which the bump electrodes 27 are formed in the bump forming step (step l). In this peeling operation, the wax 32 present between the glass substrate 33 is melted and then gently peeled off so as not to damage the surface of the wafer 21. Finally, the process moves to the cleaning process of the wafer 21, and the wax 32 and minute dust remaining after the glass substrate 33 is peeled off are washed away (process m). The wafer 21 that has undergone such a series of steps shifts to a post-processing step such as a dicing step or an assembly step, and individual semiconductor chips are formed.
[0018]
As described above, by providing the protective member attaching step during the transition from the back grinding step to the bump forming step, the thinly ground wafer 21 can be reinforced, and subsequent bump forming processing is easy. It became. In the conventional forming method, when the wafer thickness is 250 μm or less, the defective formation rate of the bump electrode is increased, so that the thinning is limited. However, according to the forming method of the present invention, it is possible in the back grinding process. The bump electrode can be formed with high accuracy even for a thickness of about 30 μm. In addition, by performing the bump forming process after the back grinding process, it is possible to reduce bump formation defects such as variations in the shape of the formed bumps or deformation.
[0019]
In the above embodiment, the raw material constituting the wafer is silicon. However, the present invention can be applied to wafers made of oxides such as selenium and germanium in addition to silicon, and the size of the wafer is not limited. .
[0020]
In this embodiment, quartz glass is used for the protective member to be attached to the wafer, but metal or silicon can be used without any problem as long as the material has the same strength and thickness without using such quartz glass. can do.
[0021]
【The invention's effect】
As described above, according to the method for forming a semiconductor wafer according to the present invention, when a back grinding process or a bump electrode forming process is performed on the semiconductor wafer, a reinforcing support member is attached to the semiconductor wafer. Therefore, there is no deformation due to impact or temperature change during the back grinding operation or bump forming operation. For this reason, it is possible to mass-produce semiconductor chips having a stable quality while being thin.
[Brief description of the drawings]
FIG. 1 is an explanatory view showing a back grinding process and a protective member attaching process in a method for forming a semiconductor wafer according to the present invention.
FIG. 2 is an explanatory view showing a bump forming step in the semiconductor wafer forming method.
FIG. 3 is an explanatory view showing a protective member peeling step in the method for forming a semiconductor wafer.
FIG. 4 is an explanatory view showing a bump forming step in a conventional method for forming a semiconductor wafer.
FIG. 5 is an explanatory view showing a back grinding process in the conventional method for forming a semiconductor wafer.
[Explanation of symbols]
21 Wafer 22 Circuit formation surface 23 Gold vapor deposition film 24 Resist film 25 Photoresist film 27 Bump electrode 32 Wax 33 Glass substrate (protective member)

Claims (3)

研磨加工する作業台の上に半導体ウェハの回路形成面を有する表面側が接するように半導体ウェハを載置した後、半導体ウェハの裏面を研磨加工して厚みを薄くし、この薄く加工された半導体ウェハの裏面に石英ガラス、金属又はシリコンからなる保護部材を貼着した後、前記半導体ウェハの回路形成面にバンプ電極部を形成し、このバンプ電極部の形成後に前記保護部材を半導体ウェハの裏面から剥離することによって、前記半導体ウェハの裏面を露出させたことを特徴とする半導体ウェハの形成方法。 After placing the semiconductor wafer on the workbench to be polished so that the surface side having the circuit forming surface of the semiconductor wafer is in contact, the back surface of the semiconductor wafer is polished to reduce the thickness, and this thinly processed semiconductor wafer After attaching a protective member made of quartz glass, metal or silicon on the back surface of the semiconductor wafer, a bump electrode portion is formed on the circuit forming surface of the semiconductor wafer, and after forming the bump electrode portion, the protective member is applied from the back surface of the semiconductor wafer. A method of forming a semiconductor wafer , wherein the back surface of the semiconductor wafer is exposed by peeling . 研磨加工する作業台の上に半導体ウェハの回路形成面を有する表面側が接するように半導体ウェハを載置した後、半導体ウェハの裏面を研磨加工して厚みを薄くするバックグラインド工程と、前記裏面に石英ガラス、金属又はシリコンからなる保護部材を貼着する保護部材貼着工程と、前記半導体ウェハの表面側から金メッキを形成するスパッタリング工程と、前記金メッキ上に電極パターンを形成するフォトレジスト工程と、前記電極パターン上にバンプ電極を形成するバンプ形成工程と、前記バンプ電極が形成された後、前記保護部材を剥離する保護部材剥離工程とを備えた半導体ウェハの形成方法。 After the semiconductor wafer is placed so that the surface side having the circuit forming surface of the semiconductor wafer is in contact with the work table to be polished, a back grinding process for polishing the back surface of the semiconductor wafer to reduce the thickness, A protective member attaching step for attaching a protective member made of quartz glass, metal or silicon ; a sputtering step for forming gold plating from the surface side of the semiconductor wafer; and a photoresist step for forming an electrode pattern on the gold plating; A method for forming a semiconductor wafer , comprising: a bump forming step for forming a bump electrode on the electrode pattern; and a protective member peeling step for peeling the protective member after the bump electrode is formed . 前記保護部材は、薄く加工された前記半導体ウェハの裏面に形成されるレジスト膜と、このレジスト膜上に塗布された粘着剤を介して貼着される請求項1又は2記載の半導体ウェハの形成方法。 3. The semiconductor wafer formation according to claim 1, wherein the protective member is attached via a resist film formed on a back surface of the thinly processed semiconductor wafer and an adhesive applied on the resist film. Method.
JP2003115507A 2003-04-21 2003-04-21 Method for forming semiconductor wafer Expired - Fee Related JP3798760B2 (en)

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Cited By (1)

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US9227295B2 (en) 2011-05-27 2016-01-05 Corning Incorporated Non-polished glass wafer, thinning system and method for using the non-polished glass wafer to thin a semiconductor wafer

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KR20060085848A (en) 2005-01-25 2006-07-28 삼성전자주식회사 Method of fabricating semiconductor wafer having bump forming process after back grinding
JP4829161B2 (en) * 2007-03-30 2011-12-07 Okiセミコンダクタ株式会社 Manufacturing method of semiconductor device
KR101537420B1 (en) * 2009-05-15 2015-07-16 엘지전자 주식회사 Cooker and manufacturing method thereof
CN105103272B (en) * 2013-09-27 2018-10-09 富士电机株式会社 The manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9227295B2 (en) 2011-05-27 2016-01-05 Corning Incorporated Non-polished glass wafer, thinning system and method for using the non-polished glass wafer to thin a semiconductor wafer
US9573835B2 (en) 2011-05-27 2017-02-21 Corning Incorporated Non-polished glass wafer, thinning system and method for using the non-polished glass wafer to thin a semiconductor wafer

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