JP2005303214A - Grinding method for semiconductor wafer - Google Patents

Grinding method for semiconductor wafer Download PDF

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JP2005303214A
JP2005303214A JP2004120954A JP2004120954A JP2005303214A JP 2005303214 A JP2005303214 A JP 2005303214A JP 2004120954 A JP2004120954 A JP 2004120954A JP 2004120954 A JP2004120954 A JP 2004120954A JP 2005303214 A JP2005303214 A JP 2005303214A
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semiconductor wafer
grinding
protective film
semiconductor
integrated circuit
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Yoshihiro Matsushima
芳宏 松島
Katsuki Uchiumi
勝喜 内海
Takahiro Kumakawa
隆博 隈川
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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<P>PROBLEM TO BE SOLVED: To provide a grinding method that can decrease thickness variations of a semiconductor wafer. <P>SOLUTION: When the backside of a semiconductor wafer 2, on whose surface an integrated circuit layer 1 composed of multiple semiconductor elements is formed, is ground to make its thickness uniform, the steps are carried out of forming a protective film 11 from a liquid resinous material that protects the integrated circuit and metal bump composing the semiconductor elements by covering the surface of the semiconductor wafer 2, grinding and leveling off the surface of the protective film 11, grinding the backside of the semiconductor wafer 2 using a grinding stone while keeping the leveled-off surface of the protective film 11 in contact with the top of the chuck table 4. Through such an easy method as protects the semiconductor elements on the surface of the semiconductor wafer 2 not by sticking a conventional protective tape on it but by forming the protective film 11 with a liquid resinous material and gets the surface of the protective film 11 ground and leveled off prior to grinding the backside of the semiconductor wafer 2, uniformity of the semiconductor wafer 2's thickness can be significantly improved. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、複数の半導体素子が表面に形成された半導体ウェーハの裏面を研削して前記半導体ウェーハの厚みを均一にする半導体ウェーハの研削方法に関し、特に、半導体ウェーハの厚み精度が向上する研削方法に関するものである。   The present invention relates to a method for grinding a semiconductor wafer in which the thickness of the semiconductor wafer is made uniform by grinding the back surface of a semiconductor wafer having a plurality of semiconductor elements formed on the surface, and in particular, a grinding method that improves the thickness accuracy of the semiconductor wafer. It is about.

半導体チップをパッケージングして実装する際やCOG(Chip on Glass)実装する際などは、半導体チップに高度な厚み精度が要求される。そのために、IC、LSI等の集積回路が形成された半導体ウェーハの裏面研削が実施されている。   When packaging and mounting a semiconductor chip or COG (Chip on Glass) mounting, the semiconductor chip is required to have high thickness accuracy. For this purpose, backside grinding of semiconductor wafers on which integrated circuits such as IC and LSI are formed is performed.

一般には、図7に示すように、IC、LSI等の集積回路が複数形成された集積回路層1を持った半導体ウェーハ2(図7(a))に、回路保護用の保護テープ3をローラ3aにて表面に貼着し(図7(b))、保護テープ3を半導体ウェーハ2の外形に沿って切り抜いた後(図7(c))、半導体ウェーハ2を、裏面研削装置のチャックテーブル4に保護テープ3を下にして真空吸着にて保持し(図7(d))、上向きとなった裏面に回転する研削砥石5を接触させて押圧力を加えることにより所定の厚さまで研削し(図7(e))、研削終了後に保護テープ3を剥がしている(図7(f)(g))。   In general, as shown in FIG. 7, a protective tape 3 for circuit protection is rolled onto a semiconductor wafer 2 (FIG. 7 (a)) having an integrated circuit layer 1 on which a plurality of integrated circuits such as IC and LSI are formed. 3a is attached to the surface (FIG. 7 (b)), the protective tape 3 is cut out along the outer shape of the semiconductor wafer 2 (FIG. 7 (c)), and the semiconductor wafer 2 is then chucked on the back grinding apparatus. 4 is held by vacuum suction with the protective tape 3 facing down (FIG. 7 (d)), and a grinding wheel 5 that rotates is brought into contact with the back surface that faces upward, and is pressed to a predetermined thickness by applying a pressing force. (FIG. 7 (e)), the protective tape 3 is peeled off after the grinding (FIG. 7 (f) (g)).

図8に示すように、集積回路層1の各集積回路を外部に電気接続するための金属バンプ6が表面に形成された半導体ウェーハ2については(図8(a))、金属バンプ6が埋まるほどに糊層3bが厚い保護テープ3を貼着したうえで(図8(b))、同様の手順を行うことにより(図8(c)(d)(e)(f)(g))、研削時の押圧力によって金属バンプ6に生じる応力を緩和し、応力の集中による金属バンプ6の変形や半導体ウェーハ2の割れの発生を防止している。   As shown in FIG. 8, for the semiconductor wafer 2 on which metal bumps 6 for electrically connecting the integrated circuits of the integrated circuit layer 1 to the outside are formed (FIG. 8A), the metal bumps 6 are buried. After applying the protective tape 3 having a thick adhesive layer 3b (FIG. 8 (b)), the same procedure is performed (FIG. 8 (c) (d) (e) (f) (g)) The stress generated in the metal bump 6 due to the pressing force at the time of grinding is relieved, and deformation of the metal bump 6 and cracking of the semiconductor wafer 2 due to the concentration of stress are prevented.

しかし保護テープ3を用いる裏面研削方法には様々な問題がある。
第1の問題は保護テープ3の厚みばらつきである。裏面研削用の保護テープ3は、一定の厚みのフィルムの表面にアクリル系接着剤を塗布して製造されているのであるが、接着剤の塗布むらなどが生じることがあり、その場合に保護テープ3としての厚みが3〜10μm程度ばらつく。このような保護テープ3の厚みばらつきの影響で、裏面研削装置の厚み加工精度は1〜2μm程度であるのに関わらず、保護テープ3を貼着して裏面研削される半導体ウェーハ2の厚みばらつきは大きくなり、4〜12μm程度のばらつきとなる。
However, the back grinding method using the protective tape 3 has various problems.
The first problem is the thickness variation of the protective tape 3. The protective tape 3 for backside grinding is manufactured by applying an acrylic adhesive to the surface of a film having a certain thickness, and uneven application of the adhesive may occur. The thickness of 3 varies by about 3 to 10 μm. Due to the influence of the thickness variation of the protective tape 3, the thickness variation of the semiconductor wafer 2 to which the protective tape 3 is attached and the back surface grinding is performed regardless of the thickness processing accuracy of the back grinding apparatus being about 1 to 2 μm Becomes larger and has a variation of about 4 to 12 μm.

第2の問題は、保護テープ3の貼着時に半導体ウェーハ2の表面との間に気泡が挟み込まれることがあり、裏面研削時に気泡部分で半導体ウェーハ2の厚みが局部的に薄くなったり、半導体ウェーハ2に割れやクラックを生じることがある。   The second problem is that air bubbles may be sandwiched between the surface of the semiconductor wafer 2 when the protective tape 3 is stuck, and the thickness of the semiconductor wafer 2 is locally reduced at the air bubbles when grinding the back surface. The wafer 2 may be cracked or cracked.

第3の問題は、保護テープ3による保護では金属バンプ6の応力を充分に取り除くことはできず、金属バンプ6の変形や半導体ウェーハ2の割れを完全には防止できないことである。   The third problem is that the protection by the protective tape 3 cannot sufficiently remove the stress of the metal bump 6, and the deformation of the metal bump 6 and the cracking of the semiconductor wafer 2 cannot be completely prevented.

このため、半導体ウェーハ2に保護テープ3を貼着するのでなく、レジスト膜などを形成して、裏面研削する方法が提案されている。たとえば、図9に示すように、集積回路層1が表面に形成された半導体ウェーハ2(図9(a))に、集積回路層1を覆うようにレジスト膜7を形成し(図9(b))、集積回路層1の各集積回路に対応して金属バンプを形成すべき領域のレジスト膜7を光源8,フォトマスク9を用いて露光し(図9(c))、現像することにより複数の細孔10を形成し(図9(d))、各細孔10内にめっきを施して金属バンプ6を形成した後(図9(e))、半導体ウェーハ2を、レジスト膜7をチャックテーブル4に対面させて保持して所定の厚さまで裏面研削し(図9(f))、レジスト膜7を除去して(図9(g))、金属バンプ6を備えた半導体ウェーハ2を得る(図9(h))方法が開示されている(たとえば特許文献1)。
特開2003−51473号公報(第4頁、第8図)
For this reason, a method of forming a resist film or the like and grinding the back surface instead of attaching the protective tape 3 to the semiconductor wafer 2 has been proposed. For example, as shown in FIG. 9, a resist film 7 is formed so as to cover the integrated circuit layer 1 on the semiconductor wafer 2 (FIG. 9A) on which the integrated circuit layer 1 is formed (FIG. 9B). )), The resist film 7 in the region where the metal bumps are to be formed corresponding to each integrated circuit of the integrated circuit layer 1 is exposed using the light source 8 and the photomask 9 (FIG. 9C) and developed. After forming a plurality of pores 10 (FIG. 9 (d)) and plating each pore 10 to form metal bumps 6 (FIG. 9 (e)), the semiconductor wafer 2 is coated with the resist film 7. The semiconductor wafer 2 provided with the metal bumps 6 is obtained by holding the chuck table 4 so as to face and grinding the back surface to a predetermined thickness (FIG. 9 (f)), removing the resist film 7 (FIG. 9 (g)). A method of obtaining (FIG. 9 (h)) is disclosed (for example, Patent Document 1).
JP 2003-51473 A (page 4, FIG. 8)

上記したレジスト膜7を用いる裏面研削方法では、それまでの方法で問題となっていた保護テープ3の貼着時の気泡混入による厚みばらつきや、気泡ないし応力による半導体ウェーハ2の割れや金属バンプ6の変形などは回避できる。   In the back surface grinding method using the resist film 7 described above, the thickness variation due to bubble mixing when the protective tape 3 is stuck, which has been a problem with the conventional methods, cracks in the semiconductor wafer 2 due to bubbles or stress, and metal bumps 6 The deformation of can be avoided.

しかしその一方で、レジスト膜7などの保護膜は、半導体ウェーハ2の表面に滴下したレジストなどの液状樹脂材料を半導体ウェーハ2の回転によって塗り広げた後、ホットプレートなどで硬化させて形成するため、半導体ウェーハ2の中央部から外周方向に向かう膜厚ばらつきが生じたり、半導体ウェーハ2の外周縁部に樹脂材料の盛り上がりが生じることがある。したがってこの場合も、厚みばらつきの大きい膜を保護膜として裏面研削することになり、裏面研削後の半導体ウェーハ2の厚みばらつきを十分に改善することはできない。   However, on the other hand, the protective film such as the resist film 7 is formed by spreading a liquid resin material such as a resist dropped on the surface of the semiconductor wafer 2 by rotating the semiconductor wafer 2 and then curing it with a hot plate or the like. The film thickness variation from the central part of the semiconductor wafer 2 toward the outer peripheral direction may occur, or the resin material may rise at the outer peripheral edge of the semiconductor wafer 2. Therefore, also in this case, the back surface grinding is performed using a film having a large thickness variation as a protective film, and the thickness variation of the semiconductor wafer 2 after the back surface grinding cannot be sufficiently improved.

本発明は上記問題を解決するもので、厚みばらつきを低減できる半導体ウェーハの研削方法を提供することを目的とする。   The present invention solves the above problems, and an object thereof is to provide a semiconductor wafer grinding method capable of reducing thickness variation.

上記課題を解決するために本発明は、半導体ウェーハの表面の半導体素子を保護テープで保護するのでなく、液状の樹脂材料で保護膜を形成して保護し、この保護膜の表面を半導体ウェーハの裏面研削に先立って研削して平坦化しておくもので、これにより裏面研削後の半導体ウェーハの厚み均一性を容易に著しく向上させることができる。   In order to solve the above problems, the present invention does not protect the semiconductor elements on the surface of the semiconductor wafer with a protective tape, but protects the surface of the semiconductor wafer by forming a protective film with a liquid resin material. Prior to the back surface grinding, the surface is ground and flattened, whereby the thickness uniformity of the semiconductor wafer after the back surface grinding can be easily remarkably improved.

第1の発明の半導体ウェーハの研削方法は、複数の半導体素子が表面に形成された半導体ウェーハの裏面を研削して前記半導体ウェーハの厚みを均一にする際に、前記半導体ウェーハの表面を覆って前記半導体素子を構成している集積回路や金属バンプを保護する保護膜を液状の樹脂材料により形成する工程と、前記保護膜の表面を研削して平坦化する工程と、前記平坦化された保護膜の表面をステージ上に接触保持して前記半導体ウェーハの裏面を研削し、研削終了後に保護膜を除去する工程とを行うことを特徴とする。   According to a first aspect of the present invention, there is provided a method for grinding a semiconductor wafer, wherein when the back surface of the semiconductor wafer having a plurality of semiconductor elements formed on the surface is ground to make the thickness of the semiconductor wafer uniform, the surface of the semiconductor wafer is covered. Forming a protective film for protecting an integrated circuit and metal bumps constituting the semiconductor element with a liquid resin material, grinding and planarizing a surface of the protective film, and the planarized protection And a step of grinding the back surface of the semiconductor wafer by holding the surface of the film in contact with a stage and removing the protective film after the grinding.

第2の発明の半導体ウェーハの研削方法は、複数の半導体素子が表面に形成された半導体ウェーハの裏面を研削して前記半導体ウェーハの厚みを均一にする半導体ウェーハの研削方法であって、前記半導体ウェーハの表面を覆って前記半導体素子を構成している集積回路を保護する保護膜をフォトレジスト材料により形成する工程と、前記半導体ウェーハの裏面をステージ上に接触保持して前記保護膜の表面を研削し平坦化する工程と、前記平坦化された保護膜に前記複数の半導体素子の外部端子を露出させる開口部をフォトリソグラフィ法により形成し、各開口部内に前記外部端子に接続する金属バンプをめっき法により形成する工程と、前記金属バンプを開口部内に有した保護膜の表面をステージ上に接触保持して前記半導体ウェーハの裏面を研削し、研削終了後に保護膜を除去する工程とを行うことを特徴とする。   A semiconductor wafer grinding method according to a second aspect of the present invention is a semiconductor wafer grinding method for grinding the back surface of a semiconductor wafer having a plurality of semiconductor elements formed on the surface thereof to make the thickness of the semiconductor wafer uniform. A step of forming a protective film covering the surface of the wafer and protecting the integrated circuit constituting the semiconductor element with a photoresist material; and holding the back surface of the semiconductor wafer on the stage so that the surface of the protective film is A step of grinding and flattening, and an opening for exposing the external terminals of the plurality of semiconductor elements are formed in the flattened protective film by photolithography, and metal bumps connected to the external terminals are formed in the openings. The step of forming by plating and the surface of the protective film having the metal bumps in the opening are held in contact on the stage to Grinding the surface, and performing the step of removing the protective film after the grinding completion.

第3の発明の半導体ウェーハの研削方法は、複数の半導体素子が表面に形成された半導体ウェーハの裏面を研削して前記半導体ウェーハの厚みを均一にする半導体ウェーハの研削方法であって、前記半導体ウェーハの表面を覆って前記半導体素子を構成している集積回路を保護する保護膜をフォトレジスト材料により形成する工程と、前記保護膜に前記複数の半導体素子の外部端子を露出させる開口部をフォトリソグラフィ法により形成し、各開口部内に前記外部端子に接続する金属バンプをめっき法により形成する工程と、前記金属バンプを有した半導体ウェーハの裏面をステージ上に接触保持して前記保護膜の表面を研削し平坦化する工程と、前記平坦化された保護膜の表面をステージ上に接触保持して前記半導体ウェーハの裏面を研削し、研削終了後に保護膜を除去する工程とを行うことを特徴とする。   According to a third aspect of the present invention, there is provided a semiconductor wafer grinding method for grinding a back surface of a semiconductor wafer having a plurality of semiconductor elements formed on the surface thereof to make the thickness of the semiconductor wafer uniform. Forming a protective film covering the surface of the wafer and protecting the integrated circuit constituting the semiconductor element with a photoresist material; and exposing openings for exposing the external terminals of the plurality of semiconductor elements to the protective film. A step of forming a metal bump connected to the external terminal in each opening by a plating method, and a surface of the protective film by holding the back surface of the semiconductor wafer having the metal bump on the stage in contact with each other Grinding the surface of the semiconductor wafer and grinding the back surface of the semiconductor wafer by holding the surface of the flattened protective film in contact with the stage. , And performs the step of removing the protective film after the grinding completion.

上記した半導体ウェーハの研削方法において、保護膜は、半導体素子の集積回路や金属バンプによって半導体ウェーハの表面に形成される段差よりも厚く形成し、前記金属バンプの高さよりも厚く残留するように研削することができる。   In the semiconductor wafer grinding method described above, the protective film is formed thicker than the step formed on the surface of the semiconductor wafer by the integrated circuit of the semiconductor element or the metal bump, and is ground so as to remain thicker than the height of the metal bump. can do.

また、上記した半導体ウェーハの研削方法において、保護膜は、半導体素子の集積回路や金属バンプによって半導体ウェーハの表面に形成される段差よりも厚く形成し、この保護膜を研削する際に金属バンプの頂部も研削することができる。   In the semiconductor wafer grinding method described above, the protective film is formed thicker than the step formed on the surface of the semiconductor wafer by the integrated circuit of the semiconductor element or the metal bump, and when the protective film is ground, The top can also be ground.

本発明の半導体ウェーハの研削方法によれば、従来の保護テープに代えて液状樹脂により保護膜を形成し、この保護膜を半導体ウェーハの裏面研削に先立って研削して平坦化するという容易な手法で、半導体ウェーハの厚みばらつきを回避できる。   According to the method for grinding a semiconductor wafer of the present invention, an easy method of forming a protective film with a liquid resin instead of the conventional protective tape, and grinding and planarizing the protective film prior to the back surface grinding of the semiconductor wafer. Thus, variation in the thickness of the semiconductor wafer can be avoided.

また剛性の高い樹脂を保護膜材料として選択することにより、裏面研削時に金属バンプにかかる応力を十分に軽減することができ、前記応力による金属バンプの変形や半導体ウェーハの割れを防止できる。   Further, by selecting a highly rigid resin as the protective film material, it is possible to sufficiently reduce the stress applied to the metal bumps during back surface grinding, and to prevent deformation of the metal bumps and cracking of the semiconductor wafer due to the stress.

従来の保護テープに起因する不都合、すなわち、保護テープの厚みばらつきによる半導体ウェーハの厚みばらつきや、保護テープと半導体ウェーハ表面との間に気泡が挟み込まれることによる半導体ウェーハの局部的薄化や割れやクラックを解消できる方法である。   Disadvantages caused by conventional protective tape, that is, semiconductor wafer thickness variation due to protective tape thickness variation, local thinning or cracking of semiconductor wafer due to air bubbles being sandwiched between the protective tape and the semiconductor wafer surface, This is a method that can eliminate cracks.

以下、本発明の半導体ウェーハの研削方法を、図面を参照しながら説明する。
(第1の実施形態)
図1は、本発明の第1の実施形態における半導体ウェーハの研削方法を説明する工程断面図である。
Hereinafter, a semiconductor wafer grinding method of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a process cross-sectional view illustrating a semiconductor wafer grinding method according to a first embodiment of the present invention.

図1(a)は研削対象の半導体ウェーハ2を示し、IC、LSI等の集積回路が複数形成された集積回路層1を表面に有している。
この半導体ウェーハ2の集積回路層1の上に、図1(b)に示すように、レジストやポリイミドなどの液状の樹脂材料を用いて塗布法などで保護膜11を形成する。この保護膜11は、集積回路層1の凹凸よりも厚くなるように形成する。塗布法としては、スピンコート法、ロールコート法、スリットコート法などを使用可能である。
FIG. 1A shows a semiconductor wafer 2 to be ground, and has an integrated circuit layer 1 on which a plurality of integrated circuits such as IC and LSI are formed on the surface.
As shown in FIG. 1B, a protective film 11 is formed on the integrated circuit layer 1 of the semiconductor wafer 2 by a coating method or the like using a liquid resin material such as resist or polyimide. The protective film 11 is formed to be thicker than the unevenness of the integrated circuit layer 1. As a coating method, a spin coating method, a roll coating method, a slit coating method, or the like can be used.

次に、図1(c)に示すように、半導体ウェーハ2をその裏面を下にして研削装置のチャックテーブル4上に載せ、真空吸着にて保持した状態で、上向きとなった保護膜11を研削砥石5を回転させて研削する。このときには、研削後の保護膜11の膜厚(t1)が研削前の保護膜11の最小膜厚(t2)よりも小さくなるように研削量を設定する。   Next, as shown in FIG. 1 (c), the semiconductor film 2 is placed on the chuck table 4 of the grinding apparatus with the back side down, and the protective film 11 facing upward is held by vacuum suction. The grinding wheel 5 is rotated for grinding. At this time, the grinding amount is set so that the film thickness (t1) of the protective film 11 after grinding is smaller than the minimum film thickness (t2) of the protective film 11 before grinding.

次に、図1(d)に示すように、半導体ウェーハ2をその保護膜11を下にしてチャックテーブル4上に載せ、真空吸着にて保持した状態で、図1(e)に示すように、上向きとなった半導体ウェーハ2の裏面を研削砥石5で研削する。このときには、半導体ウェーハ2の研削後厚みが所望の厚みとなるように研削量を設定する。この研削の後に、チップ破壊強度向上のために、必要に応じてポリッシングやエッチングなどを行ってもよい。   Next, as shown in FIG. 1 (d), as shown in FIG. 1 (e), the semiconductor wafer 2 is placed on the chuck table 4 with its protective film 11 down and held by vacuum suction. Then, the back surface of the semiconductor wafer 2 facing upward is ground with a grinding wheel 5. At this time, the grinding amount is set so that the thickness of the semiconductor wafer 2 after grinding becomes a desired thickness. After this grinding, polishing or etching may be performed as necessary to improve the chip breaking strength.

次に、図1(f)に示すように、半導体ウェーハ2をチャックテーブル4から取り外し、保護膜11を有機溶剤などの剥離液や現像液などにて溶解させて除去して、図1(g)に示すような、集積回路層1を表面に有した所望厚み(t3)の半導体ウェーハ2を得る。   Next, as shown in FIG. 1 (f), the semiconductor wafer 2 is removed from the chuck table 4, and the protective film 11 is removed by dissolving with a stripping solution such as an organic solvent or a developing solution. The semiconductor wafer 2 having a desired thickness (t3) having the integrated circuit layer 1 on the surface as shown in FIG.

以上のような研削方法によれば、保護膜11を含めた半導体ウェーハ2の研削後の仕上げ厚み精度は、保護膜11の表面を研削加工した後に半導体ウェーハ2の裏面を研削加工するため研削装置の厚み加工精度の2倍となり、研削装置(チャックテーブル4,研削砥石5)の厚み加工精度は1〜2μm程度であることから、1〜4μm程度となる。従来の保護テープを用いた研削方法での厚み加工精度は前述の通り4〜12μmなので、それに比べて大きく向上する。   According to the grinding method as described above, the finishing thickness accuracy after grinding of the semiconductor wafer 2 including the protective film 11 is obtained by grinding the back surface of the semiconductor wafer 2 after grinding the surface of the protective film 11. The thickness processing accuracy of the grinding device (chuck table 4, grinding wheel 5) is about 1 to 2 μm, and is about 1 to 4 μm. Since the thickness processing accuracy in the conventional grinding method using the protective tape is 4 to 12 μm as described above, the accuracy is greatly improved.

なお保護膜11の厚みは、研削前の厚みを5μm〜数百μmとし、研削後の厚みを1μm〜数百μmとすればよい。
(第2の実施形態)
図2は、本発明の第2の実施形態における半導体ウェーハの研削方法を説明する工程断面図である。
The thickness of the protective film 11 may be 5 μm to several hundred μm before grinding and 1 μm to several hundred μm after grinding.
(Second Embodiment)
FIG. 2 is a process cross-sectional view illustrating a semiconductor wafer grinding method according to the second embodiment of the present invention.

図2(a)は研削対象の半導体ウェーハ2を示し、IC、LSI等の集積回路が複数形成された集積回路層1と、この集積回路層1の各集積回路を外部に電気接続するための複数の金属バンプ6とを表面に有している。金属バンプ6は、金、半田、銅などにて、無電解めっき法、電解めっき法、印刷法などで形成されていてよい。   FIG. 2 (a) shows a semiconductor wafer 2 to be ground. An integrated circuit layer 1 on which a plurality of integrated circuits such as IC and LSI are formed, and each integrated circuit of the integrated circuit layer 1 is electrically connected to the outside. A plurality of metal bumps 6 are provided on the surface. The metal bump 6 may be formed of gold, solder, copper or the like by an electroless plating method, an electrolytic plating method, a printing method, or the like.

この半導体ウェーハ2の集積回路層1の上に、図2(b)に示すように、レジストやポリイミドなどの液状の樹脂材料を用いて塗布法などで保護膜11を形成する。この保護膜11は、金属バンプ6の高さよりも厚くなるように形成する。   As shown in FIG. 2B, a protective film 11 is formed on the integrated circuit layer 1 of the semiconductor wafer 2 by a coating method or the like using a liquid resin material such as resist or polyimide. The protective film 11 is formed to be thicker than the height of the metal bump 6.

次に、図2(c)に示すように、半導体ウェーハ2をその裏面を下にして研削装置のチャックテーブル4上に載せ、真空吸着にて保持した状態で、上向きとなった保護膜11を研削砥石5を回転させて研削する。このときには、研削後の保護膜11の膜厚(t1)が研削前の保護膜11の最小膜厚(t2)よりも小さく、かつ金属バンプ6の最大高さ(t4)よりも大きくなるように研削量を設定する。   Next, as shown in FIG. 2 (c), the semiconductor wafer 2 is placed on the chuck table 4 of the grinding apparatus with the back side down, and the protective film 11 facing upward is held in a vacuum suction state. The grinding wheel 5 is rotated for grinding. At this time, the film thickness (t1) of the protective film 11 after grinding is smaller than the minimum film thickness (t2) of the protective film 11 before grinding and larger than the maximum height (t4) of the metal bump 6. Set the grinding amount.

次に、図2(d)に示すように、半導体ウェーハ2をその保護膜11を下にしてチャックテーブル4上に載せ、真空吸着にて保持した状態で、図2(e)に示すように、上向きとなった半導体ウェーハ2の裏面を研削砥石5で研削する。このときには、半導体ウェーハ2の研削後厚みが所望の厚みとなるように研削量を設定する。この研削の後に、必要に応じてポリッシングやエッチングなどを行ってもよい。   Next, as shown in FIG. 2D, the semiconductor wafer 2 is placed on the chuck table 4 with the protective film 11 facing down and held by vacuum suction as shown in FIG. Then, the back surface of the semiconductor wafer 2 facing upward is ground with a grinding wheel 5. At this time, the grinding amount is set so that the thickness of the semiconductor wafer 2 after grinding becomes a desired thickness. After this grinding, polishing or etching may be performed as necessary.

次に、図2(f)に示すように、半導体ウェーハ2をチャックテーブル4から取り外し、保護膜11を剥離液や現像液などにて溶解させて除去して、図2(g)に示すような、金属バンプ6,集積回路層1を表面に有した所望厚み(t3)の半導体ウェーハ2を得る。   Next, as shown in FIG. 2 (f), the semiconductor wafer 2 is removed from the chuck table 4, and the protective film 11 is dissolved and removed with a stripping solution or a developing solution, as shown in FIG. 2 (g). A semiconductor wafer 2 having a desired thickness (t3) having the metal bumps 6 and the integrated circuit layer 1 on the surface is obtained.

以上のようにすることで、第1の実施形態と同様に、保護膜11を含めた半導体ウェーハ2の研削後の仕上げ厚み精度が従来の保護テープを用いた研削方法に比べて大きく向上する。   As described above, as in the first embodiment, the finishing thickness accuracy after grinding of the semiconductor wafer 2 including the protective film 11 is greatly improved as compared with the grinding method using the conventional protective tape.

さらに、従来の保護テープやレジスト膜を用いた研削方法では、裏面研削時の金属バンプ6への応力を充分に取り除くことができず、金属バンプ6の変形や半導体ウェーハ2の割れを完全に防止できなかったのに対し、この第2の実施形態の研削方法では、剛性の高い樹脂材料を保護膜11用途に選択することで、金属バンプ6への応力を十分に取り除くことができ、金属バンプ6の変形や半導体ウェーハ2の割れを防止することができる。   Furthermore, the conventional grinding method using a protective tape or a resist film cannot sufficiently remove the stress on the metal bump 6 during back grinding, and completely prevents deformation of the metal bump 6 and cracking of the semiconductor wafer 2. On the other hand, in the grinding method of the second embodiment, by selecting a resin material having high rigidity for the protective film 11, the stress on the metal bump 6 can be sufficiently removed, and the metal bump can be removed. 6 deformation and cracking of the semiconductor wafer 2 can be prevented.

なお、保護膜11は研削前の厚みを数10μm〜数百μmとし、研削後の厚みを数μm〜数百μmとすればよい。また金属バンプ6は径が数μm〜数百μm、高さが数μm〜数百μmの範囲で、上記した条件を満たすように形成、研削すればよい。以下の各実施形態でも同様である。
(第3の実施形態)
図3は、本発明の第3の実施形態における半導体ウェーハの研削方法を説明する工程断面図である。
The protective film 11 may have a thickness before grinding of several tens of μm to several hundreds of μm, and a thickness after grinding of several μm to several hundreds of μm. Further, the metal bump 6 may be formed and ground so as to satisfy the above-mentioned conditions in the range of several μm to several hundred μm in diameter and several μm to several hundred μm in height. The same applies to the following embodiments.
(Third embodiment)
FIG. 3 is a process cross-sectional view illustrating a semiconductor wafer grinding method according to a third embodiment of the present invention.

上記した第2の実施形態と同様に、図3(a)に示すような、IC、LSI等の集積回路が複数形成された集積回路層1と複数の金属バンプ6とを表面に有した半導体ウェーハ2を研削対象として、図3(b)に示すように、集積回路層1の上に塗布法などを用いてレジストやポリイミドなどの液状の樹脂材料を用いて塗布法などで保護膜11を形成する。保護膜11の厚みは金属バンプ6の高さよりも厚い。   Similar to the second embodiment described above, a semiconductor having an integrated circuit layer 1 having a plurality of integrated circuits such as IC and LSI and a plurality of metal bumps 6 on its surface as shown in FIG. As shown in FIG. 3B, the protective film 11 is applied on the integrated circuit layer 1 by a coating method using a liquid resin material such as a resist or polyimide on the integrated circuit layer 1 as shown in FIG. Form. The protective film 11 is thicker than the metal bump 6.

次に、図3(c)に示すように、半導体ウェーハ2をその裏面を下にして研削装置のチャックテーブル4上に載せ、真空吸着にて保持した状態で、上向きとなった保護膜11の表面を研削砥石5で研削するのであるが、このときに、研削後の保護膜11の膜厚(t1)が金属バンプ6の最小高さ(t5)よりも薄くなるように研削量を設定して、金属バンプ6の頂部も同時に研削し、金属バンプ6の高さを平準化する。   Next, as shown in FIG. 3 (c), the semiconductor wafer 2 is placed on the chuck table 4 of the grinding apparatus with the back side down, and the protective film 11 facing upward is held by vacuum suction. The surface is ground with the grinding wheel 5. At this time, the grinding amount is set so that the film thickness (t 1) of the protective film 11 after grinding becomes thinner than the minimum height (t 5) of the metal bump 6. Then, the top of the metal bump 6 is also ground at the same time, and the height of the metal bump 6 is leveled.

その後は再び第2の実施形態と同様に、図3(d)に示すように、半導体ウェーハ2をその保護膜11を下にしてチャックテーブル4上に載せ、真空吸着にて保持した状態で、図3(e)に示すように、上向きとなった半導体ウェーハ2の裏面を研削砥石5で研削する。このときには、半導体ウェーハ2の研削後厚みが所望の厚みとなるように研削量を設定する。この研削の後に、必要に応じてポリッシングやエッチングなどを行ってもよい。   Thereafter, as in the second embodiment, as shown in FIG. 3 (d), the semiconductor wafer 2 is placed on the chuck table 4 with the protective film 11 facing down and held by vacuum suction. As shown in FIG. 3 (e), the back surface of the semiconductor wafer 2 facing upward is ground with a grinding wheel 5. At this time, the grinding amount is set so that the thickness of the semiconductor wafer 2 after grinding becomes a desired thickness. After this grinding, polishing or etching may be performed as necessary.

そして、図3(f)に示すように、半導体ウェーハ2をチャックテーブル4から取り外し、保護膜11を剥離液や現像液などにて溶解させて除去して、図3(g)に示すような、金属バンプ6,集積回路層1を表面に有した所望厚み(t3)の半導体ウェーハ2を得る。   Then, as shown in FIG. 3 (f), the semiconductor wafer 2 is removed from the chuck table 4 and the protective film 11 is dissolved and removed with a stripping solution or a developing solution, as shown in FIG. 3 (g). Then, a semiconductor wafer 2 having a desired thickness (t3) having the metal bumps 6 and the integrated circuit layer 1 on the surface is obtained.

この第3の実施形態の研削方法でも、保護膜11を含めた半導体ウェーハ2の研削後の仕上げ厚み精度が従来の保護テープを用いた研削方法に比べて大きく向上する。また、従来の保護テープやレジスト膜を用いた研削方法に比べて、金属バンプ6への応力を十分に取り除くことができ、金属バンプ6の変形や半導体ウェーハ2の割れを容易に防止できる。
(第4の実施形態)
図4は、本発明の第4の実施形態における半導体ウェーハの研削方法を説明する工程断面図である。
Even in the grinding method of the third embodiment, the finished thickness accuracy of the semiconductor wafer 2 including the protective film 11 after grinding is greatly improved as compared with the grinding method using the conventional protective tape. Moreover, compared with the grinding method using the conventional protective tape and resist film, the stress to the metal bump 6 can be removed sufficiently, and the deformation of the metal bump 6 and the crack of the semiconductor wafer 2 can be easily prevented.
(Fourth embodiment)
FIG. 4 is a process cross-sectional view illustrating a semiconductor wafer grinding method according to the fourth embodiment of the present invention.

図4(a)は研削対象の半導体ウェーハ2を示し、IC、LSI等の集積回路が複数形成された集積回路層1を表面に有している。
この半導体ウェーハの集積回路層1の上に、図4(b)に示すように、塗布法などを用いてフォトレジスト材料からなる保護膜11を形成する。この保護膜11は、集積回路層1の凹凸よりも厚くなるように形成する。
FIG. 4A shows a semiconductor wafer 2 to be ground, and has an integrated circuit layer 1 on the surface on which a plurality of integrated circuits such as IC and LSI are formed.
On the integrated circuit layer 1 of the semiconductor wafer, as shown in FIG. 4B, a protective film 11 made of a photoresist material is formed using a coating method or the like. The protective film 11 is formed to be thicker than the unevenness of the integrated circuit layer 1.

次に、図4(c)に示すように、半導体ウェーハ2をその裏面を下にして研削装置のチャックテーブル4上に載せ、真空吸着にて保持した状態で、上向きとなった保護膜11を研削砥石5を回転させて研削する。このときには、研削後の保護膜11の膜厚(t1)が研削前の保護膜11の最小膜厚(t2)よりも小さくなるように研削量を設定する。   Next, as shown in FIG. 4 (c), the semiconductor wafer 2 is placed on the chuck table 4 of the grinding apparatus with the back side down, and the protective film 11 facing upward is held by vacuum suction. The grinding wheel 5 is rotated for grinding. At this time, the grinding amount is set so that the film thickness (t1) of the protective film 11 after grinding is smaller than the minimum film thickness (t2) of the protective film 11 before grinding.

次に、図4(d)に示すように、プロジェクションアライナーやステッパ露光機などの露光装置において、フォトマスク9のパターンと半導体ウェーハ2の集積回路層1の各集積回路との位置合わせを行った後、光源8により、各集積回路上で金属バンプが形成されるべき部分の保護膜11(フォトレジスト材料によっては金属バンプが形成されるべきでない部分)を選択的に露光処理する。   Next, as shown in FIG. 4D, alignment of the pattern of the photomask 9 and each integrated circuit of the integrated circuit layer 1 of the semiconductor wafer 2 was performed in an exposure apparatus such as a projection aligner or a stepper exposure machine. Thereafter, the light source 8 selectively exposes a portion of the protective film 11 where metal bumps are to be formed on each integrated circuit (a portion where metal bumps should not be formed depending on the photoresist material).

次に、図4(e)に示すように、保護膜11を現像して、選択的に露光された部分(あるいは露光されなかった部分)に細孔10を形成する。
次に、図4(f)に示すように、細孔10の内部に無電解めっき法や電解めっき法などによりめっきを施して、金、半田、銅などの金属バンプ6を形成する。このとき、金属バンプ6の高さは、研削後の保護膜11の膜厚(t1)よりも低くなるように設定する。
Next, as shown in FIG. 4E, the protective film 11 is developed to form pores 10 in selectively exposed portions (or unexposed portions).
Next, as shown in FIG. 4 (f), the inside of the pores 10 is plated by an electroless plating method, an electrolytic plating method or the like to form metal bumps 6 such as gold, solder, and copper. At this time, the height of the metal bump 6 is set to be lower than the film thickness (t1) of the protective film 11 after grinding.

次に、図4(g)に示すように、半導体ウェーハ2をその保護膜11を下にしてチャックテーブル4上に載せ、真空吸着にて保持した後、上向きとなった半導体ウェーハ2の裏面を研削砥石5で研削する。このときには、半導体ウェーハ2の研削後厚みが所望の厚みとなるように研削量を設定する。この研削の後に、必要に応じてポリッシングやエッチングなどを行ってもよい。   Next, as shown in FIG. 4 (g), the semiconductor wafer 2 is placed on the chuck table 4 with the protective film 11 down and held by vacuum suction, and then the back surface of the semiconductor wafer 2 facing upward is placed. Grind with a grinding wheel 5. At this time, the grinding amount is set so that the thickness of the semiconductor wafer 2 after grinding becomes a desired thickness. After this grinding, polishing or etching may be performed as necessary.

次に、図4(h)に示すように、半導体ウェーハ2をチャックテーブル4から取り外し、保護膜11を剥離液や現像液などにて溶解させて除去して、図4(i)に示すような、金属バンプ6,集積回路層1を表面に有した所望厚み(t3)の半導体ウェーハ2を得る。   Next, as shown in FIG. 4 (h), the semiconductor wafer 2 is removed from the chuck table 4, and the protective film 11 is dissolved and removed with a stripping solution or a developing solution, as shown in FIG. 4 (i). A semiconductor wafer 2 having a desired thickness (t3) having the metal bumps 6 and the integrated circuit layer 1 on the surface is obtained.

この第4の実施形態の研削方法でも、保護膜11を含めた半導体ウェーハ2の研削後の仕上げ厚み精度が従来の保護テープを用いた研削方法に比べて大きく向上する。また、従来の保護テープやレジスト膜を用いた研削方法に比べて、金属バンプ6への応力を十分に取り除くことができ、金属バンプ6の変形や半導体ウェーハ2の割れを容易に防止できる。
(第5の実施形態)
図5は、本発明の第5の実施形態における半導体ウェーハの研削方法を説明する工程断面図である。
Also in the grinding method of the fourth embodiment, the finished thickness accuracy of the semiconductor wafer 2 including the protective film 11 after grinding is greatly improved as compared with the grinding method using the conventional protective tape. Moreover, compared with the grinding method using the conventional protective tape and resist film, the stress to the metal bump 6 can be removed sufficiently, and the deformation of the metal bump 6 and the crack of the semiconductor wafer 2 can be easily prevented.
(Fifth embodiment)
FIG. 5 is a process cross-sectional view illustrating a semiconductor wafer grinding method according to a fifth embodiment of the present invention.

図5(a)は研削対象の半導体ウェーハ2を示し、IC、LSI等の集積回路が複数形成された集積回路層1を表面に有している。
この半導体ウェーハの集積回路層1の上に、図5(b)に示すように、塗布法などを用いてフォトレジスト材料からなる保護膜11を形成する。この保護膜11は、集積回路層1の凹凸よりも厚くなるように形成する。
FIG. 5A shows a semiconductor wafer 2 to be ground, and has an integrated circuit layer 1 on the surface on which a plurality of integrated circuits such as IC and LSI are formed.
On the integrated circuit layer 1 of this semiconductor wafer, as shown in FIG. 5B, a protective film 11 made of a photoresist material is formed using a coating method or the like. The protective film 11 is formed to be thicker than the unevenness of the integrated circuit layer 1.

次に、図5(c)に示すように、プロジェクションアライナーやステッパ露光機などの露光装置において、フォトマスク9のパターンと半導体ウェーハ2の集積回路層1の各集積回路との位置合わせを行った後、光源8により、各集積回路上で金属バンプが形成されるべき部分の保護膜11(フォトレジスト材料によっては金属バンプが形成されるべきでない部分)を選択的に露光処理する。   Next, as shown in FIG. 5C, the alignment of the pattern of the photomask 9 and each integrated circuit of the integrated circuit layer 1 of the semiconductor wafer 2 was performed in an exposure apparatus such as a projection aligner or a stepper exposure machine. Thereafter, the light source 8 selectively exposes a portion of the protective film 11 where metal bumps are to be formed on each integrated circuit (a portion where metal bumps should not be formed depending on the photoresist material).

次に、図5(d)に示すように、保護膜11を現像して、選択的に露光された部分(あるいは露光されなかった部分)に細孔10を形成する。
次に、図5(e)に示すように、細孔10の内部に無電解めっき法や電解めっき法などによりめっきを施して、金、半田、銅などの金属バンプ6を形成する。このとき、金属バンプ6の高さは、保護膜11の膜厚よりも十分に低くなるように設定する。
Next, as shown in FIG. 5D, the protective film 11 is developed to form pores 10 in selectively exposed portions (or unexposed portions).
Next, as shown in FIG. 5 (e), the inside of the pores 10 is plated by an electroless plating method, an electrolytic plating method or the like to form metal bumps 6 such as gold, solder, and copper. At this time, the height of the metal bump 6 is set to be sufficiently lower than the film thickness of the protective film 11.

次に、図5(f)に示すように、半導体ウェーハ2をその裏面を下にしてチャックテーブル4上に載せ、真空吸着にて保持した後、上向きとなった保護膜11を研削砥石5で研削する。このときには、研削後の保護膜11の膜厚(t1)が、研削前の保護膜11の最小膜厚(t2)よりも薄く、かつ金属バンプ6の最大高さ(t4)よりも厚くなるように研削量を設定する。   Next, as shown in FIG. 5 (f), the semiconductor wafer 2 is placed on the chuck table 4 with its back side down and held by vacuum suction, and then the protective film 11 facing upward is removed with a grinding wheel 5. Grind. At this time, the film thickness (t1) of the protective film 11 after grinding is smaller than the minimum film thickness (t2) of the protective film 11 before grinding and larger than the maximum height (t4) of the metal bump 6. Set the grinding amount to.

次に、図5(g)に示すように、半導体ウェーハ2をその保護膜11を下にしてチャックテーブル4上に載せ、真空吸着にて保持した後、図5(h)に示すように、上向きとなった半導体ウェーハ2の裏面を研削砥石5で研削する。このときには、半導体ウェーハ2の研削後厚みが所望の厚みとなるように研削量を設定する。この研削の後に、必要に応じてポリッシングやエッチングなどを行ってもよい。   Next, as shown in FIG. 5 (g), the semiconductor wafer 2 is placed on the chuck table 4 with its protective film 11 facing down and held by vacuum suction, and then as shown in FIG. 5 (h). The back surface of the semiconductor wafer 2 facing upward is ground with a grinding wheel 5. At this time, the grinding amount is set so that the thickness of the semiconductor wafer 2 after grinding becomes a desired thickness. After this grinding, polishing or etching may be performed as necessary.

次に、図5(i)に示すように、半導体ウェーハ2をチャックテーブル4から取り外し、保護膜11を剥離液や現像液などにて溶解させて除去して、図5(j)に示すような、金属バンプ6,集積回路層1を表面に有した所望厚み(t3)の半導体ウェーハ2を得る。   Next, as shown in FIG. 5 (i), the semiconductor wafer 2 is removed from the chuck table 4, and the protective film 11 is dissolved and removed with a stripping solution or a developing solution, as shown in FIG. 5 (j). A semiconductor wafer 2 having a desired thickness (t3) having the metal bumps 6 and the integrated circuit layer 1 on the surface is obtained.

この第5の実施形態の研削方法でも、保護膜11を含めた半導体ウェーハ2の研削後の仕上げ厚み精度が従来の保護テープを用いた研削方法に比べて大きく向上する。また、従来の保護テープやレジスト膜を用いた研削方法に比べて、金属バンプ6への応力を十分に取り除くことができ、金属バンプ6の変形や半導体ウェーハ2の割れを容易に防止できる。
(第6の実施形態)
図6は、本発明の第6の実施形態における半導体ウェーハの研削方法を説明する工程断面図である。
Also in the grinding method of the fifth embodiment, the finished thickness accuracy after grinding of the semiconductor wafer 2 including the protective film 11 is greatly improved as compared with the grinding method using the conventional protective tape. Moreover, compared with the grinding method using the conventional protective tape and resist film, the stress to the metal bump 6 can be removed sufficiently, and the deformation of the metal bump 6 and the crack of the semiconductor wafer 2 can be easily prevented.
(Sixth embodiment)
FIG. 6 is a process cross-sectional view illustrating a semiconductor wafer grinding method according to a sixth embodiment of the present invention.

上記した第5の実施形態と同様に、図6(a)に示すような、IC、LSI等の集積回路が複数形成された集積回路層1とを表面に有した半導体ウェーハ2を研削対象として、図6(b)に示すように、集積回路層1の上に塗布法などを用いてフォトレジスト材料からなる保護膜11を形成する。この保護膜11は、集積回路層1の凹凸よりも厚くなるように形成する。   Similar to the fifth embodiment described above, a semiconductor wafer 2 having an integrated circuit layer 1 having a plurality of integrated circuits such as IC and LSI formed thereon as shown in FIG. As shown in FIG. 6B, a protective film 11 made of a photoresist material is formed on the integrated circuit layer 1 using a coating method or the like. The protective film 11 is formed to be thicker than the unevenness of the integrated circuit layer 1.

そして、図6(c)に示すように、プロジェクションアライナーやステッパ露光機などの露光装置において、フォトマスク9のパターンと半導体ウェーハ2の集積回路層1の各集積回路との位置合わせを行った後、光源8により、各集積回路上で金属バンプが形成されるべき部分の保護膜11(フォトレジスト材料によっては金属バンプが形成されるべきでない部分)を選択的に露光処理する。   Then, after aligning the pattern of the photomask 9 and each integrated circuit of the integrated circuit layer 1 of the semiconductor wafer 2 in an exposure apparatus such as a projection aligner or a stepper exposure machine, as shown in FIG. The light source 8 selectively exposes a portion of the protective film 11 where a metal bump is to be formed on each integrated circuit (a portion where a metal bump should not be formed depending on the photoresist material).

そして、図6(d)に示すように、樹脂膜7を現像して、選択的に露光された部分(あるいは露光されなかった部分)に細孔10を形成し、図6(e)に示すように、細孔10の内部に無電解めっき法や電解めっき法などによりめっきを施して、金、半田、銅などの金属バンプ6を形成する。   Then, as shown in FIG. 6 (d), the resin film 7 is developed to form pores 10 in selectively exposed portions (or unexposed portions), as shown in FIG. 6 (e). As described above, the inside of the pores 10 is plated by an electroless plating method, an electrolytic plating method, or the like to form metal bumps 6 such as gold, solder, and copper.

次に、図6(f)に示すように、半導体ウェーハ2をその裏面を下にしてチャックテーブル4上に載せ、真空吸着にて保持した後、上向きとなった保護膜11を研削砥石5で研削するのであるが、ここでは第5の実施形態と異なって、研削後の保護膜11の膜厚(t1)が、金属バンプの最小高さ(t5)よりも薄くなるように研削量を設定して、金属バンプ6の頂部も同時に研削し、金属バンプ6の高さを平準化する。   Next, as shown in FIG. 6 (f), the semiconductor wafer 2 is placed on the chuck table 4 with its back side down and held by vacuum suction, and then the protective film 11 facing upward is removed with a grinding wheel 5. Grinding is performed, but here, unlike the fifth embodiment, the grinding amount is set so that the film thickness (t1) of the protective film 11 after grinding is thinner than the minimum height (t5) of the metal bump. Then, the top of the metal bump 6 is also ground at the same time, and the height of the metal bump 6 is leveled.

その後は再び第5の実施形態と同様に、図6(g)に示すように、半導体ウェーハ2をその保護膜11を下にしてチャックテーブル4上に載せ、真空吸着にて保持した後、図6(h)に示すように、上向きとなった半導体ウェーハ2の裏面を研削砥石5で研削する。このときには、半導体ウェーハ2の研削後厚みが所望の厚みとなるように研削量を設定する。   Thereafter, as in the fifth embodiment, as shown in FIG. 6G, the semiconductor wafer 2 is placed on the chuck table 4 with the protective film 11 facing down and held by vacuum suction. As shown in 6 (h), the back surface of the semiconductor wafer 2 facing upward is ground with a grinding wheel 5. At this time, the grinding amount is set so that the thickness of the semiconductor wafer 2 after grinding becomes a desired thickness.

そして、図6(i)に示すように、半導体ウェーハ2をチャックテーブル4から取り外し、保護膜11を剥離液や現像液などにて溶解させて除去して、図6(j)に示すような、金属バンプ6,集積回路層1を表面に有した所望厚み(t3)の半導体ウェーハ2を得る。   Then, as shown in FIG. 6 (i), the semiconductor wafer 2 is removed from the chuck table 4, and the protective film 11 is dissolved and removed with a stripping solution, a developing solution or the like, as shown in FIG. 6 (j). Then, a semiconductor wafer 2 having a desired thickness (t3) having the metal bumps 6 and the integrated circuit layer 1 on the surface is obtained.

この第6の実施形態の研削方法でも、保護膜11を含めた半導体ウェーハ2の研削後の仕上げ厚み精度が従来の保護テープを用いた研削方法に比べて大きく向上する。また、従来の保護テープやレジスト膜を用いた研削方法に比べて、金属バンプ6への応力を十分に取り除くことができ、金属バンプ6の変形や半導体ウェーハ2の割れを容易に防止できる。   Even in the grinding method of the sixth embodiment, the finishing thickness accuracy after grinding of the semiconductor wafer 2 including the protective film 11 is greatly improved as compared with the grinding method using the conventional protective tape. Moreover, compared with the grinding method using the conventional protective tape and resist film, the stress to the metal bump 6 can be removed sufficiently, and the deformation of the metal bump 6 and the crack of the semiconductor wafer 2 can be easily prevented.

本発明の半導体ウェーハの研削方法は、保護テープを用いる従来の研削方法に代えて使用して厚み精度を向上させることができ、高度な厚み精度が要求されるパッケージ・実装に用いる半導体チップの製造に有用である。   The semiconductor wafer grinding method of the present invention can be used in place of the conventional grinding method using a protective tape to improve the thickness accuracy, and manufacture of semiconductor chips for use in packages and packaging that require high thickness accuracy. Useful for.

半導体ウェーハ上に金バンプを形成する場合も同等の厚み加工精度を実現でき、金属バンプ高さの平準化を同時に図ることも可能なので、特に高度なチップ厚み精度が要求されるCOG(Chip on Glass)などの実装に使用される半導体チップの製造にも非常に有効である。   Even when gold bumps are formed on a semiconductor wafer, equivalent thickness processing accuracy can be achieved, and metal bump heights can be leveled at the same time, so COG (Chip on Glass) that requires particularly high chip thickness accuracy. It is also very effective in the manufacture of semiconductor chips used for mounting.

本発明の第1の実施形態における半導体ウェーハの研削方法を説明する工程断面図Process sectional drawing explaining the grinding method of the semiconductor wafer in the 1st Embodiment of this invention 本発明の第2の実施形態における半導体ウェーハの研削方法を説明する工程断面図Process sectional drawing explaining the grinding method of the semiconductor wafer in the 2nd Embodiment of this invention 本発明の第3の実施形態における半導体ウェーハの研削方法を説明する工程断面図Process sectional drawing explaining the grinding method of the semiconductor wafer in the 3rd Embodiment of this invention 本発明の第4の実施形態における半導体ウェーハの研削方法を説明する工程断面図Process sectional drawing explaining the grinding method of the semiconductor wafer in the 4th Embodiment of this invention 本発明の第5の実施形態における半導体ウェーハの研削方法を説明する工程断面図Process sectional drawing explaining the grinding method of the semiconductor wafer in the 5th Embodiment of this invention 本発明の第6の実施形態における半導体ウェーハの研削方法を説明する工程断面図Process sectional drawing explaining the grinding method of the semiconductor wafer in the 6th Embodiment of this invention 従来の半導体ウェーハの研削方法を説明する工程断面図Process sectional drawing explaining the conventional grinding method of a semiconductor wafer 従来の別の半導体ウェーハの研削方法を説明する工程断面図Process sectional view explaining another conventional grinding method for semiconductor wafers 従来のさらに別の半導体ウェーハの研削方法を説明する工程断面図Process sectional drawing explaining the conventional grinding method of another semiconductor wafer

符号の説明Explanation of symbols

1 集積回路層
2 半導体ウェーハ
4 チャックテーブル
5 研削砥石
6 金属バンプ
8 光源
9 フォトマスク
10 細孔(開口部)
11 保護膜
DESCRIPTION OF SYMBOLS 1 Integrated circuit layer 2 Semiconductor wafer 4 Chuck table 5 Grinding wheel 6 Metal bump 8 Light source 9 Photomask 10 Fine pore (opening)
11 Protective film

Claims (5)

複数の半導体素子が表面に形成された半導体ウェーハの裏面を研削して前記半導体ウェーハの厚みを均一にする半導体ウェーハの研削方法であって、
前記半導体ウェーハの表面を覆って前記半導体素子を構成している集積回路や金属バンプを保護する保護膜を液状の樹脂材料により形成する工程と、
前記保護膜の表面を研削して平坦化する工程と、
前記平坦化された保護膜の表面をステージ上に接触保持して前記半導体ウェーハの裏面を研削し、研削終了後に保護膜を除去する工程と
を行う半導体ウェーハの研削方法。
A method for grinding a semiconductor wafer in which the back surface of a semiconductor wafer having a plurality of semiconductor elements formed on the front surface is ground to make the thickness of the semiconductor wafer uniform,
Forming a protective film that covers the surface of the semiconductor wafer and protects the integrated circuit and metal bumps constituting the semiconductor element with a liquid resin material;
Grinding and planarizing the surface of the protective film;
A method of grinding a semiconductor wafer, comprising: holding a surface of the planarized protective film in contact with a stage to grind the back surface of the semiconductor wafer; and removing the protective film after the grinding is completed.
複数の半導体素子が表面に形成された半導体ウェーハの裏面を研削して前記半導体ウェーハの厚みを均一にする半導体ウェーハの研削方法であって、
前記半導体ウェーハの表面を覆って前記半導体素子を構成している集積回路を保護する保護膜をフォトレジスト材料により形成する工程と、
前記半導体ウェーハの裏面をステージ上に接触保持して前記保護膜の表面を研削し平坦化する工程と、
前記平坦化された保護膜に前記複数の半導体素子の外部端子を露出させる開口部をフォトリソグラフィ法により形成し、各開口部内に前記外部端子に接続する金属バンプをめっき法により形成する工程と、
前記金属バンプを開口部内に有した保護膜の表面をステージ上に接触保持して前記半導体ウェーハの裏面を研削し、研削終了後に保護膜を除去する工程と
を行う半導体ウェーハの研削方法。
A method for grinding a semiconductor wafer in which the back surface of a semiconductor wafer having a plurality of semiconductor elements formed on the front surface is ground to make the thickness of the semiconductor wafer uniform,
Forming a protective film that covers the surface of the semiconductor wafer and protecting the integrated circuit constituting the semiconductor element with a photoresist material;
A step of holding the back surface of the semiconductor wafer in contact with a stage and grinding and flattening the surface of the protective film;
Forming an opening exposing the external terminals of the plurality of semiconductor elements in the planarized protective film by a photolithography method, and forming a metal bump connected to the external terminal in each opening by a plating method;
A method for grinding a semiconductor wafer, comprising: holding a surface of a protective film having the metal bumps in an opening in contact with a stage, grinding a back surface of the semiconductor wafer, and removing the protective film after the grinding is completed.
複数の半導体素子が表面に形成された半導体ウェーハの裏面を研削して前記半導体ウェーハの厚みを均一にする半導体ウェーハの研削方法であって、
前記半導体ウェーハの表面を覆って前記半導体素子を構成している集積回路を保護する保護膜をフォトレジスト材料により形成する工程と、
前記保護膜に前記複数の半導体素子の外部端子を露出させる開口部をフォトリソグラフィ法により形成し、各開口部内に前記外部端子に接続する金属バンプをめっき法により形成する工程と、
前記金属バンプを有した半導体ウェーハの裏面をステージ上に接触保持して前記保護膜の表面を研削し平坦化する工程と、
前記平坦化された保護膜の表面をステージ上に接触保持して前記半導体ウェーハの裏面を研削し、研削終了後に保護膜を除去する工程と
を行う半導体ウェーハの研削方法。
A method for grinding a semiconductor wafer in which the back surface of a semiconductor wafer having a plurality of semiconductor elements formed on the front surface is ground to make the thickness of the semiconductor wafer uniform,
Forming a protective film that covers the surface of the semiconductor wafer and protecting the integrated circuit constituting the semiconductor element with a photoresist material;
Forming an opening exposing the external terminals of the plurality of semiconductor elements in the protective film by a photolithography method, and forming a metal bump connected to the external terminal in each opening by a plating method;
The process of grinding and flattening the surface of the protective film by holding the back surface of the semiconductor wafer having the metal bumps in contact with the stage,
A method of grinding a semiconductor wafer, comprising: holding a surface of the planarized protective film in contact with a stage to grind the back surface of the semiconductor wafer; and removing the protective film after the grinding is completed.
保護膜は、半導体素子の集積回路や金属バンプによって半導体ウェーハの表面に形成される段差よりも厚く形成し、前記金属バンプの高さよりも厚く残留するように研削する請求項1から請求項3のいずれかに記載の半導体ウェーハの研削方法。   The protective film is formed thicker than a step formed on the surface of the semiconductor wafer by an integrated circuit of a semiconductor element or a metal bump, and is ground so as to remain thicker than the height of the metal bump. The semiconductor wafer grinding method according to any one of the above. 保護膜は、半導体素子の集積回路や金属バンプによって半導体ウェーハの表面に形成される段差よりも厚く形成し、この保護膜を研削する際に金属バンプの頂部も研削する請求項3記載の半導体ウェーハの研削方法。   4. The semiconductor wafer according to claim 3, wherein the protective film is formed thicker than the step formed on the surface of the semiconductor wafer by the integrated circuit of the semiconductor element or the metal bump, and the top of the metal bump is ground when the protective film is ground. Grinding method.
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