JP3705985B2 - Shift register and image display device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a shift register that can be suitably used for, for example, a drive circuit of an image display device and can shift an input pulse even when the amplitude of a clock signal is lower than a drive voltage, and an image display device using the shift register. Is.
[0002]
[Prior art]
For example, in a data signal line driving circuit or a scanning signal line driving circuit of an image display device, in order to take a timing when sampling each data signal from a video signal, or to create a scanning signal to be given to each scanning signal line Shift registers are widely used.
[0003]
On the other hand, the power consumption of the electronic circuit increases in proportion to the frequency, the load capacity, and the square of the voltage. Therefore, for example, in a circuit connected to the image display device such as a circuit for generating a video signal to the image display device, or in the image display device, the drive voltage tends to be set lower and lower in order to reduce power consumption. is there.
[0004]
For example, in a circuit in which a polycrystalline silicon thin film transistor is used to secure a wide display area, such as a pixel, a data signal line driving circuit, or a scanning signal line driving circuit, the circuit may be used between substrates or within the same substrate. The difference in threshold voltage may reach, for example, about several [V], so that it is difficult to say that the drive voltage has been sufficiently reduced. For example, as in the video signal generation circuit, In a circuit using a crystalline silicon transistor, the drive voltage is often set to a value of, for example, 5 [V], 3.3 [V], or less. Therefore, when a clock signal lower than the drive voltage of the shift register is applied, the shift register is provided with a level shifter that boosts the clock signal.
[0005]
Specifically, for example, as shown in FIG. 39, when a clock signal CK having an amplitude of about 5 [V] is supplied to the conventional shift register 101, the level shifter 103 causes the drive voltage of the shift register 101 to The clock signal CK is boosted up to (15 [V]). The boosted clock signal CK is applied to each of the flip-flops F1 to Fn, and the shift register unit 102 shifts the start signal SP in synchronization with the clock signal CK.
[0006]
[Problems to be solved by the invention]
However, in the conventional shift register 101, since the clock signal CK is level-shifted and then transmitted to the flip-flops F1 to Fn, the transmission distance increases as the distance between both ends of the flip-flops F1 to Fn increases. This causes a problem that power consumption increases.
[0007]
Specifically, as the transmission distance becomes longer, the capacity of the signal line for transmission becomes larger, so that the level shifter 103 needs a larger driving capability and power consumption increases. Further, when the driving capability of the level shifter 103 is not sufficient as in the case where the driving circuit including the level shifter 103 is formed using a polycrystalline silicon thin film transistor, a waveform without distortion is transmitted in the figure. As indicated by the broken line, since it is necessary to provide the buffer 104 between the level shifter 103 and each of the flip-flops F1 to Fn, more power consumption is required.
[0008]
In recent years, there has been a demand for an image display device with a wider display screen and higher resolution, and therefore the number of stages of the shift register unit 102 tends to increase more and more. Therefore, there is a strong demand for a shift register and an image display device that consume less power even when the distance between both ends of the flip-flops F1 to Fn increases.
[0009]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a shift register that operates normally even when the amplitude of the clock signal is lower than the drive voltage and consumes less power, and the shift register. An object of the present invention is to realize an image display device using the.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, a shift register according to the present invention providesA multi-stage flip-flop;A level shifter that boosts a clock signal having a smaller amplitude than the driving voltage of the flip-flop and applies the clock signal to each flip-flop, and receives an input pulse in synchronization with the clock signal.Sequentially in each flip-flop aboveThe shift register for transmission is characterized by the following measures.
[0011]
  That is, each flip-flopIs complexThe level shifter is provided for each block, and corresponds to a block that does not require the input of the clock signal to transmit the input pulse at that time among the plurality of level shifters. At least one of the level shifters to stop is stopped.
[0012]
Note that whether or not each block requires a clock signal for transmission of an input pulse is determined by a flip-flop constituting the shift register. For example, when a set / reset flip-flop set according to a clock signal is used as the flip-flop, the block is input from the pulse to the block until the final flip-flop is set. When the flip-flop is a D flip-flop, the clock signal is required after the pulse is input to the block until the final flip-flop finishes outputting the pulse. . In any case, each block may include one flip-flop, and each flip-flop may be provided with a level shifter, or each flip-flop may be provided with a level shifter. Good.
[0013]
In the above configuration, the clock signal is boosted by one of a plurality of level shifters and then applied to the flip-flop in the block corresponding to the level shifter, and the input pulse is sequentially transmitted in synchronization with the boosted clock signal. Is done. In addition, at least one of the level shifters that do not need to output a clock signal among the level shifters stops operating.
[0014]
Here, an example of a block that does not require a clock signal is a block that does not transmit an input pulse. Even in the case of a block transmitting an input pulse, for example, in the case of a set / reset flip-flop in which a flip-flop is set according to a clock signal and reset according to an output of a later flip-flop. Does not require a clock signal during the period after the final flip-flop is set.
[0015]
In the above configuration, since the shift register is provided with a plurality of level shifters, the distance from the level shifter to the flip-flop can be shortened as compared with the case where the only level shifter applies the clock signal after the level shift to all the flip-flops. . As a result, since the transmission distance of the clock signal after the level shift can be shortened, the load capacity of the level shifter can be reduced, and the driving capability required for the level shifter can be suppressed. This makes it unnecessary to provide a buffer between the level shifter and the flip-flop, for example, even when the drive capability of the level shifter is small and the distance between both ends of the flip-flop is long, thereby reducing the power consumption of the shift register. Can be reduced. In addition, since at least one of the plurality of level shifters has stopped operating, the power consumption of the shift register can be reduced as compared with the case where all the level shifters operate simultaneously. As a result, it is possible to realize a shift register which can operate with a low voltage clock signal input and which has low power consumption.
[0016]
Furthermore, the present invention is not limited to the case where a set / reset / flip-flop is included as a flip-flop.The boosted clock signal is input to the clock terminal.The present invention can also be applied to a case including a D flip-flop. in this case,A circuit for outputting whether or not the specific block is in a predetermined period for performing the transmission based on a signal input to the specific block and each output signal of the flip-flop of the specific block;The specific level shifter corresponding to the specific block isBased on the output of the circuit,The operation starts when the pulse input to the specific block is started, and the operation stops after the flip-flop at the final stage of the specific block ends the pulse output.The
[0017]
Alternatively, in the shift register, the specific block includes the D flip-flop, and the specific block transmits the signal based on a signal input to the specific block and an output signal of the flip-flop at the final stage of the specific block. The specific level shifter corresponding to the specific block includes a latch circuit that indicates that the predetermined period has been started by performing an output to store and hold the start of the predetermined period until the end of the predetermined period. Based on the output of the circuit, the operation is performed at least from the time when the pulse input to the specific block is started to the time when the flip-flop at the final stage of the specific block ends the pulse output.
[0018]
According to this configuration, since the specific block includes the D flip-flop as the flip-flop, unlike the case of the set / reset flip-flop, the specific block has a case where the pulse width (number of clocks) of the input pulse changes. However, the input pulse can be transmitted without any problem. Further, according to the above configuration, the specific level shifter supplies the clock signal after the level shift during a period necessary when the D flip-flop of the specific block operates, and it is not necessary to input the clock signal to the D flip-flop. If so, stop the operation. As a result, it is possible to realize a shift register that can transmit input pulses having different pulse widths and consumes less power.
[0019]
In addition, the period from when a pulse is input to a specific block until the final stage flip-flop outputs a pulse is, for example, the logical sum of the pulse signal input to the specific block and the output signal of each stage flip-flop. Or by latching a trigger signal. Therefore, in this case, the circuit configuration of the shift register can be simplified as compared with the case where the operation period is calculated separately from the input / output of the flip-flop.
[0020]
Further, in the shift register having the above configuration, in the block including a plurality of the flip-flops, the boosted clock signal is supplied only to the flip-flops that need to input the clock signal at that time. Also good.
[0021]
In the shift register having the above configuration, all the flip-flops may be the D flip-flops.
[0022]
Furthermore, in the shift register configured as described above,The level shifter may include a current drive type level shift unit including an input switching element. For example,The level shifter may include a current driven level shift unit in which an input switching element to which the clock signal is applied is always turned on during operation.
[0023]
According to this configuration, while the level shifter is operating, the input switching element of the level shifter is always conducting. Therefore, unlike a voltage-driven type level shifter that turns on / off the input switching element according to the level of the clock signal, there is no problem even if the amplitude of the clock signal is lower than the threshold voltage of the input switching element, The clock signal can be level shifted.
[0024]
Furthermore, the current-driven level shifter consumes more power than the voltage-driven level shifter because the input switching element is conductive during operation, but at least one of the plurality of level shifters has stopped operating. . This makes it possible to realize a shift register that can be level-shifted even when the amplitude of the clock signal is lower than the threshold voltage of the input switching element, and that consumes less power than when all level shifters operate simultaneously.
[0025]
Further, in the shift register having the above configuration, an input signal control unit that stops the level shifter by giving a signal at a level that is cut off by the input switching element as an input signal to the level shift unit.For example, in the above level shifterIt may be provided.
[0026]
According to this configuration, the case where the input switching element is a MOS transistor will be described as an example. For example, when the input signal is applied to the gate, the input signal at a level at which the drain-source is cut off is applied. When applied to the gate, the input switching element is blocked. When an input signal is applied to the source, the input switching element is shut off by, for example, applying substantially the same input signal as that of the drain.
[0027]
In any configuration, when the input signal control unit controls the level of the input signal and shuts off the input switching element, the current drive type level shifter stops its operation. As a result, the input signal control unit can stop the level shifter and can reduce power consumption by the amount of current that flows to the input switching element during operation.
[0028]
On the other hand, the shift register having each configuration described above may include a power supply control unit that stops power supply to the level shift unit and stops the level shifter.
[0029]
According to the said structure, an electric power supply control part stops the electric power supply to each level shift part, and stops the said level shifter. Thereby, the power supply control unit can stop the level shifter, and can reduce power consumption by the amount of power consumed by the level shifter during operation while the operation is stopped.
[0030]
By the way, if the output voltage of the level shifter becomes unstable while the level shifter is not operating, the operation of the flip-flop connected to the level shifter may become unstable.
[0031]
Therefore, in the shift register having each configuration described above, it is preferable that the level shifter includes an output stabilizing means for maintaining the output voltage at a predetermined value when stopped.
[0032]
According to this configuration, while the level shifter is stopped, the output voltage of the level shifter is maintained at a predetermined value by the output stabilizing means. As a result, a malfunction of the flip-flop caused by an indefinite output voltage can be prevented, and a more stable shift register can be realized.
[0033]
Further, the shift register having each configuration described above is provided with a switch that is disposed between the clock signal line through which the clock signal is transmitted and the level shift unit, and is opened while the level shifter is stopped. Is preferable. The switch can be realized as a part of the input signal control unit.
[0034]
In the above configuration, unlike the case where all the level shifters are always connected to the clock signal line and the input switching element of all the level shift units is a load of the clock signal line, the input switching element connected to the clock signal line operates. Limited to medium level shifters. Further, even when the switch is opened during stop and the level shifter input becomes indefinite, the output stabilizing means maintains the output of the level shifter at a predetermined value, so that the flip-flop does not malfunction. As a result, the load capacity of the clock signal line can be reduced, and the power consumption of the circuit that drives the clock signal line can be reduced.
[0035]
On the other hand, in order to solve the above problems, an image display device according to the present invention includes a plurality of pixels arranged in a matrix, a plurality of data signal lines arranged in each row of each pixel, and a plurality of data signal lines. A plurality of scanning signal lines arranged in each column, and a scanning signal line driving circuit that sequentially applies scanning signals of different timings to the scanning signal lines in synchronization with a first clock signal having a predetermined period; A data signal is sequentially applied in synchronization with a second clock signal having a predetermined period and a video signal indicating the display state of each pixel is supplied to each pixel of the scanning signal line to which the scanning signal is applied. In the image display device having the data signal line driving circuit that extracts and outputs to each data signal line, at least one of the data signal line driving circuit and the scanning signal line driving circuit is the first or the second The clock signal is characterized in that it comprises a shift register of any of the above-described configuration according to the clock signal.
[0036]
Here, in the image display device, as the number of data signal lines or the number of scanning signal lines increases, the number of flip-flops for generating the timing for each signal line increases, and between the ends of the flip-flops. The distance becomes longer. However, the shift register having the above-described configuration can reduce the number of buffers and reduce power consumption even when the level shifter has a small driving capability and the distance between both ends of the flip-flop is long.
[0037]
Therefore, an image display device with low power consumption can be realized by providing at least one of the data signal line driving circuit and the scanning signal line driving circuit with the shift register having the above-described configuration.
[0038]
Further, in the image display device having the above configuration, it is desirable that the data signal line driving circuit, the scanning signal line driving circuit, and each pixel are formed on the same substrate.
[0039]
According to this configuration, the data signal line driving circuit, the scanning signal line driving circuit, and each pixel are formed on the same substrate, the wiring between the data signal line driving circuit and each pixel, and scanning The wiring between the signal line driver circuit and each pixel is arranged on the substrate and does not need to be exposed outside the substrate. As a result, even when the number of data signal lines and the number of scanning signal lines increase, the number of signal lines to be taken out of the substrate does not change, and the time and labor during assembly can be reduced. Further, since it is not necessary to provide a terminal for connecting each signal line to the outside of the substrate, it is possible to prevent an undesired increase in the capacity of each signal line and to prevent a decrease in the degree of integration.
[0040]
By the way, the polycrystalline silicon thin film has a larger substrate area than the single crystalline silicon, while the polycrystalline silicon transistor has a transistor characteristic such as mobility and threshold value which is larger than that of the single crystalline silicon transistor. Is inferior. Therefore, when each circuit is manufactured using a single crystal silicon transistor, it is difficult to expand the display area. When each circuit is manufactured using a polycrystalline silicon thin film transistor, the driving ability of each circuit is lowered. In addition, when both drive circuits and pixels are formed on different substrates, it is necessary to connect the two substrates with each signal line, which takes time during manufacturing and increases the capacity of each signal line. .
[0041]
Therefore, in the image display device having each configuration described above, it is preferable that the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element made of a polycrystalline silicon thin film transistor.
[0042]
In this configuration, since the data signal line driving circuit, the scanning signal line driving circuit, and each pixel all include a switching element made of a polycrystalline silicon thin film transistor, the display area can be easily expanded. Furthermore, since it can be easily formed on the same substrate, it is possible to reduce the labor during manufacture and the capacity of each signal line. In addition, since the shift registers having the above-described configurations are used, the level-shifted clock signal can be applied to each flip-flop without any trouble even when the level shifter has a low driving capability. As a result, an image display device with low power consumption and a wide display area can be realized.
[0043]
In addition, in the image display device having each configuration described above, it is preferable that the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element manufactured at a process temperature of 600 degrees or less.
[0044]
According to this configuration, since the process temperature of the switching element is set to 600 ° C. or less, even if an ordinary glass substrate (a glass substrate having a strain point of 600 ° C. or less) is used as the substrate of each switching element, No warping or warping caused by processes above that point. As a result, it is possible to realize an image display device that is easier to mount and has a larger display area.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
(First reference form)
Of the present inventionFirst reference form of embodiment1 will be described with reference to FIGS. 1 to 7 as follows. Note that the present invention can be widely applied to shift registers in which the amplitude of the input clock signal is smaller than the drive voltage. Hereinafter, a case where the present invention is applied to an image display device will be described as a preferable example.
[0046]
That is, as shown in FIG.This reference formThe image display apparatus 1 includes a display unit 2 having pixels PIX arranged in a matrix, a data signal line driving circuit 3 and a scanning signal line driving circuit 4 for driving each pixel PIX, and a control circuit. When 5 generates a video signal DAT indicating the display state of each pixel PIX, an image can be displayed based on the video signal DAT.
[0047]
The display unit 2 and the drive circuits 3 and 4 are provided on the same substrate in order to reduce manufacturing labor and wiring capacity. In order to integrate more pixels PIX and expand the display area, each of the circuits 2 to 4 is composed of a polycrystalline silicon thin film transistor formed on a glass substrate. Furthermore, even if a normal glass substrate (a glass substrate having a strain point of 600 degrees or less) is used, the polycrystalline thin film silicon transistor has a temperature of 600 degrees or less so that warpage or warping caused by a process at or above the strain point does not occur. Manufactured at a process temperature of
[0048]
Here, the display unit 2 has 1 (L: hereinafter, capital letter L is used for convenience of reference) data signal lines SL1 to SLL and m data signal lines SL1 to SLL. Scanning signal lines GL1 to GLm. If any positive integer less than or equal to L is i and any positive integer less than or equal to m is j, a pixel PIX (i, j) is provided for each combination of the data signal line SLi and the scanning signal line GLj. Each pixel PIX (i, j) is arranged in a portion surrounded by two adjacent data signal lines SLi · SLi + 1 and two adjacent scanning signal lines GLj · GLj + 1.
[0049]
On the other hand, the pixel PIX (i, j) includes, for example, a field effect transistor (switching element) SW having a gate connected to the scanning signal line GLj and a drain connected to the data signal line SLi, as shown in FIG. The field effect transistor SW is provided with a pixel capacitor CP to which one electrode is connected at the source. The other end of the pixel capacitor CP is connected to a common electrode line common to all the pixels PIX. The pixel capacitor CP is composed of a liquid crystal capacitor CL and an auxiliary capacitor CS added if necessary.
[0050]
When the scanning signal line GLj is selected in the pixel PIX (i, j), the field effect transistor SW is turned on, and the voltage applied to the data signal line SLi is applied to the pixel capacitor CP. On the other hand, while the selection period of the scanning signal line GLj ends and the field effect transistor SW is cut off, the pixel capacitor CP continues to hold the voltage at the cut off. Here, the transmittance or reflectance of the liquid crystal varies depending on the voltage applied to the liquid crystal capacitor CL. Therefore, if the scanning signal line GLj is selected and a voltage corresponding to the video data is applied to the data signal line SLi, the display state of the pixel PIX (i, j) can be changed together with the video data.
[0051]
In the image display device 1 shown in FIG. 2, the scanning signal line drive circuit 4 selects the scanning signal line GL, and the video data to the pixel PIX corresponding to the combination of the scanning signal line GL and the data signal line SL being selected is displayed. The data signal line driving circuit 3 outputs the data signal line SL. As a result, the respective video data is written to the pixels PIX... Connected to the scanning signal line GL. Further, the scanning signal line driving circuit 4 sequentially selects the scanning signal lines GL, and the data signal line driving circuit 3 outputs video data to each data signal line SL. As a result, each video data is written in all the pixels PIX of the display unit 2.
[0052]
Here, between the control circuit 5 and the data signal line drive circuit 3, video data to each pixel PIX is transmitted in a time division manner as a video signal DAT, and the data signal line drive circuit 3 receives the timing signal. Each video data is extracted from the video signal DAT at a timing based on the clock signal CKS and the start signal SPS having a predetermined cycle.
[0053]
Specifically, the data signal line driving circuit 3 shifts the start signal SPS sequentially in synchronization with the clock signal CKS, thereby generating output signals S1 to SL having different timings by a predetermined interval. And a sampling unit 3b that samples the video signal DAT at timings indicated by the output signals S1 to SL and extracts the video data output to the data signal lines SL1 to SLL from the video signal DAT. Similarly, the scanning signal line driving circuit 4 sequentially outputs the scanning signals having different timings to the scanning signal lines GL1 to GLm by sequentially shifting the start signal SPG in synchronization with the clock signal CKG. A shift register 4a is provided.
[0054]
here,This reference formIn the image display apparatus 1 according to the above, the display unit 2 and the drive circuits 3 and 4 are formed of polycrystalline silicon thin film transistors, and the drive voltage VCC of these circuits 2 to 4 is set to about 15 [V], for example. Has been. On the other hand, the control circuit 5 is formed of a single crystal silicon transistor on a substrate different from those of the circuits 2 to 4, and the driving voltage is, for example, a voltage of 5 [V] or less. It is set to a value lower than the voltage VCC. In addition, although each said circuits 2-4 and the control circuit 5 are formed in the mutually different board | substrate, the number of signals transmitted between both is larger than the number of signals between each said circuits 2-4. For example, it is about the video signal DAT, each start signal SPS (SPG), or the clock signal CKS (CKG). Further, since the control circuit 5 is formed of a single crystal silicon transistor, it is easy to ensure a sufficient driving capability. Therefore, even if they are formed on different substrates, the labor, wiring capacity, and power consumption at the time of manufacture are suppressed to a level that does not cause a problem.
[0055]
here,This reference formThe shift register 11 shown in FIG. 1 is used as at least one of the shift registers 3a and 4a. In the following description, each of the start signals SPS (SPG) is referred to as SP, the number of stages L (m) of the shift register 1 is referred to by n, and the output signal is S1 so that it can be used as any shift register. ~ Sn.
[0056]
Specifically, the shift register 11 includes n-stage set / reset flip-flops (SR flip-flops) F1 (1)..., And operates with the drive voltage VCC, and the control circuit. 5 includes a level shifter 13 (1)... That boosts the clock signal CK having a smaller amplitude than the drive voltage VCC and applies it to each SR flip-flop F1 (1).
[0057]
This reference formIn this case, each level shifter 13 (1)... Is provided in a one-to-one correspondence with each SR flip-flop F1 (1)..., And as will be described later, the amplitude of the clock signal CK is greater than that of the drive voltage VCC. Even if the voltage is small, it is configured as a current driven type level shifter so that the voltage can be boosted without any trouble. Further, when an integer equal to or greater than 1 and equal to or less than 1 is assumed to be i, each level shifter 13 (i) responds based on the clock signal CK and its inverted signal CK bar while the control signal ENAi instructs the operation. The boosted clock signal CKi can be applied to the SR flip-flop F1 (i). Further, while the control signal ENA instructs to stop the operation, the operation can be stopped to prevent the application of the clock signal CKi to the corresponding SR flip-flop F1 (i). By shutting off the element, the power consumption of the level shifter 13 (i) due to the through current can be reduced.
[0058]
On the other hand, the flip-flop unit 12 is configured to be able to transmit the start signal SP having one clock cycle width to the next stage at each edge (rising edge and falling edge) of the clock signal CK. Specifically, the output of each level shifter 13 (i) is applied to the SR flip-flop F1 (i) through the inverter I1 (i) as a negative logic set signal S bar. The output Q of each SR flip-flop F1 (i) is output as the output Si of the shift register 11, and is applied as a control signal ENAi + 1 to the next level shifter 13 (i + 1). Note that the start signal SP from the control circuit 5 shown in FIG. 1 is boosted and applied as the control signal ENA1 to the level shifter 13 (1) in the foremost stage. Furthermore, a signal delayed by the pulse width of the pulse to be transmitted among the set signals to the subsequent SR flip-flop F1 is applied to each SR flip-flop F1 (i) as the reset signal R.This reference formIn this case, since a pulse having a width of one clock cycle is transmitted, a signal delayed by one clock cycle, that is, a clock signal CK (i + 2) to the SR flip-flop F1 (i + 2) after two stages is positive logic. Applied as a reset signal.
[0059]
Further, the odd level SR flip-flops F1 (1), F1 (3)... Are set at the rising edge of the clock signal CK so that the odd level shifters 13 (1). The inverted signal CK bar of the clock signal is applied to the inverted input terminal. In contrast, the even level shifters 13 (2), 13 (4)... Are set so that the even number SR flip-flops F1 (2)... Are set at the falling edge of the clock signal CK. CK is applied to the inverting input terminal, and the inverted signal CK bar is applied to the non-inverting input terminal.
[0060]
According to the above configuration, as shown in FIG. 4, while the start signal SP is being pulsed, the level shifter 13 (1) in the forefront stage operates and the boosted clock signal CK1 is converted into the SR flip-flop F1 ( Apply to 1). As a result, the SR flip-flop F1 (1) is set when the clock signal CK first rises after the pulse input start time, and changes the output S1 to the high level.
[0061]
The output S1 is applied as the control signal ENA2 to the second level shifter 13 (2). As a result, the level shifter 13 (2) outputs the clock signal CK2 while the SR flip-flop F1 (1) outputs a pulse (while the control signal ENA2 = S1 is at the high level). However, since the clock signal CK is applied to the inverting input terminal to the level shifter 13 (2), the level shifter 13 (2) outputs the boosted signal as the clock signal CK2 having the opposite polarity to the clock signal CK. To do. Thereby, the SR flip-flop F1 (2) is set when the clock signal CK first falls after the output S1 of the previous stage becomes high level, and changes the output S2 to high level.
[0062]
Each output signal Si is applied as a control signal ENAi + 1 to the level shifter 13 (i + 1) at the next stage, so that the SR flip-flop F1 (2). Output S2... Is output with a delay of ½ period of the clock signal CK.
[0063]
On the other hand, the output C Ki + 2 of the level shifter 13 (i + 2) after the second stage is applied as the reset signal R to the level shifter 13 (i) of each stage. Therefore, each output Si changes to a low level after having become a high level for one clock cycle. As a result, the flip-flop unit 12 can transmit the start signal SP having one clock cycle width to the next stage at each edge (rising edge and falling edge) of the clock signal CK.
[0064]
Here, since each level shifter 13 (i) is provided for each SR flip-flop F1 (i), even if the number of stages of the SR flip-flop F1 (i) is large, the clock signal CK is the only level shifter. After the voltage is boosted, the distance between the level shifter and the flip-flop corresponding to each other can be shortened as compared with the case where the voltage is applied to all flip-flops. Therefore, the transmission distance of the clock signal CKi after boosting can be shortened, and the load capacity of each level shifter 13 (i) can be reduced. Further, since the load capacity is small, for example, it is difficult to sufficiently secure the driving capability of the level shifter 13 (i) as in the case where the level shifter 13 (i) is composed of a polycrystalline silicon thin film transistor. However, it is not necessary to provide a buffer. As a result, the power consumption of the shift register 11 can be reduced.
[0065]
Further, when each SR flip-flop F1 (i) does not require the input of the clock signal CKi, such as when the start signal SP or the output Si-1 of the previous stage is at the low level, the level shifter 13 (i) operates. It has stopped. In this state, since the clock signal CKi is not driven, power consumption necessary for driving does not occur. Furthermore, as will be described later, the power supply itself to the level shifter 13a provided in each level shifter 13 (i) is stopped, the input switching element is shut off, and no through current flows. Therefore, power is consumed only by the level shifter 13 (i) in operation, although a large number (n) of current-driven level shifters are provided. As a result, the power consumption of the shift register 11 can be greatly reduced.
[0066]
in addition,This reference formThe level shifter 13 (i) of the SR flip-flop F1 (i) requires the SR flip-flop F1 (i), that is, from the time when the start signal SP or the output Si-1 of the previous stage starts pulse output. The period until i) is set is determined based only on the start signal SP or the output Si-1 in the previous stage. As a result, the operation / stop of each level shifter 13 (i) can be controlled simply by directly applying the start signal SP or the output Si-1 of the previous stage, compared with the case where a circuit for creating a new control signal is provided. The circuit configuration of the shift register 11 can be simplified.
[0067]
further,This reference formThen, while each level shifter 13 (i) is stopped, clock input to each SR flip-flop F1 (i) is blocked. Therefore, the start signal SP can be correctly transmitted without providing a switch that is turned on according to the necessity of clock input separately from the level shifter 13 (i).
[0068]
Here, in each SR flip-flop F1, as shown in FIG. 5, for example, a P-type MOS transistor P1, N-type MOS transistors N2 and N3 are connected in series between the drive voltage VCC and the ground level. A negative logic set signal S bar is applied to the gates of the transistors P1 and N3. A positive logic reset signal R is applied to the gate of the transistor N2. Further, the drain potentials of the two transistors P1 and N2 connected to each other are inverted by the inverters INV1 and INV2, respectively, and output as an output signal Q. On the other hand, P-type MOS transistors P4 and P5 and N-type MOS transistors N6 and N7 connected in series, respectively, are provided between the drive voltage VCC and the ground level. The drains of the transistors P5 and N6 are connected to the input of the inverter INV1, and the gates of the transistors P5 and N6 are connected to the output of the inverter INV1. Further, a reset signal R is applied to the transistor P4, and a set signal S bar is applied to the gate of the transistor N7.
[0069]
In the SR flip-flop F1, as shown in FIG. 6, when the set signal S bar changes to active (low level) while the reset signal R is inactive (low level), the transistor P1 becomes conductive, The input of the inverter INV1 is changed to high level. As a result, the output signal Q of the SR flip-flop F1 changes to a high level.
[0070]
In this state, the transistors P4 and P5 are turned on by the reset signal R and the output of the inverter INV1. Further, the transistors N2 and N6 are cut off by the reset signal R and the output of the inverter INV1. Thereby, even if the set signal S bar changes to inactive, the input of the inverter INV1 is maintained at a high level, and the output signal Q is maintained at a high level.
[0071]
Thereafter, when the reset signal R becomes active, the transistor P4 is cut off and the transistor N2 is turned on. Here, since the set signal S bar remains inactive, the transistor P1 is cut off and the transistor N3 becomes conductive. Therefore, the input of the inverter INV1 is driven to a low level, and the output signal Q changes to a low level.
[0072]
on the other hand,This reference formFor example, as shown in FIG. 7, the level shifter 13 related to the level shift unit 13 a that level-shifts the clock signal CK, and cuts off power supply to the level shift unit 13 a during a stop period in which the supply of the clock signal CK is unnecessary The power supply control unit 13b, the input control unit (switch) 13c for cutting off the level shift unit 13a and the signal line through which the clock signal CK is transmitted during the stop period, and the input of the level shift unit 13a during the stop period. An input switching element cutoff control unit (input signal control unit) 13d that shuts off the switching element, and an output stabilization unit (output stabilization means) 13e that maintains the output of the level shift unit 13a at a predetermined value during the stop period. Yes.
[0073]
The level shift unit 13a includes, as a differential input pair in the input stage, P-type MOS transistors P11 and P12 whose sources are connected to each other, and a constant current source Ic that supplies a predetermined current to the sources of both the transistors P11 and P12. And N-type MOS transistors N13 and N14 that constitute a current mirror circuit and serve as active loads of the transistors P11 and P12, and CMOS structure transistors P15 and N16 that amplify the output of the differential input pair. .
[0074]
The clock signal CK is input to the gate of the transistor P11 via a transistor N31 described later, and the inverted signal CK bar of the clock signal is input to the gate of the transistor P12 via a transistor N33 described later. The gates of the transistors N13 and N14 are connected to each other and further connected to the drains of the transistors P11 and N13. On the other hand, the drains of the transistors P12 and N14 connected to each other are connected to the gates of the transistors P15 and N16. The sources of the transistors N13 and N14 are grounded through an N-type MOS transistor N21 serving as the power supply control unit 13b.
[0075]
On the other hand, in the input controller 13c on the transistor P11 side, an N-type MOS transistor N31 is provided between the clock signal CK and the gate of the transistor P11. In the input switching element cutoff control unit 13d on the transistor P11 side, a P-type MOS transistor P32 is provided between the gate of the transistor P11 and the drive voltage VCC. Similarly, the inverted signal CK bar of the clock signal is applied to the gate of the transistor P12 through the transistor N33 as the input control unit 13c, and the drive voltage is supplied through the transistor P34 as the input switching element cutoff control unit 13d. VCC is given.
[0076]
The output stabilization unit 13e is configured to stabilize the output voltage OUT of the level shifter 13 during the stop period to the ground level, and a P-type MOS is provided between the drive voltage VCC and the gates of the transistors P15 and N16. A transistor P41 is provided.
[0077]
In addition,This reference formThe control signal ENA is set so as to indicate the operation of the level shifter 13 when it is at a high level. Therefore, the control signal ENA is applied to the gates of the transistors N21 to P41.
[0078]
In the level shifter 13 configured as described above, when the control signal ENA indicates an operation (when it is at a high level), the transistors N21, N31, and N33 are turned on, and the transistors P32, P34, and P41 are turned off. In this state, the current of the constant current source Ic flows through the transistors P11 and N13 or the transistors P12 and N14 and then through the transistor N21. The clock signal CK or the inverted signal CK bar of the clock signal is applied to the gates of the transistors P11 and P12. As a result, an amount of voltage corresponding to the ratio of the gate-source voltage flows through both transistors P11 and P12. On the other hand, since the transistors N13 and N14 function as active loads, the voltage at the connection point of the transistors P12 and N14 is a voltage corresponding to the difference in voltage level between the two CK and CK bars. The voltage becomes the gate voltage of the CMOS transistors P15 and N16, and after being amplified by both transistors P15 and N16, the voltage is output as the output voltage OUT.
[0079]
The level shifter 13 is configured to switch the conduction / cutoff of the transistors P11 and P12 in the input stage according to the clock signal CK. That is, unlike the voltage driving type, the current drive in which the transistors P11 and P12 in the input stage are always turned on during operation. The level of the clock signal CK is shifted by dividing the current of the constant current source Ic according to the ratio of the gate-source voltage of both transistors P11 and P12. Thereby, even when the amplitude of the clock signal CK is lower than the threshold value of the transistors P11 and P12 in the input stage, the level of the clock signal CK can be shifted without any trouble.
[0080]
As a result, as shown in FIG. 4, each level shifter 13 (i) has a peak value lower than the drive voltage VCC (for example, 5) as the clock signal CKi while the corresponding control signal ENAi is at a high level. The output voltage OUT having the same shape as that of the clock signal CK of about [V] and the peak value boosted to the drive voltage VCC (for example, about 15 [V]) can be output.
[0081]
On the contrary, when the control signal ENAi indicates the operation stop (when it is low level), the current flowing from the constant current source Ic via the transistors P11 and N13 or the transistors P12 and N14 is the transistor N21. Is blocked by. In this state, current supply from the constant current source Ic is blocked by the transistor N21, so that power consumption due to the current can be reduced. In this state, since no current is supplied to both transistors P11 and P12, both transistors P11 and P12 cannot operate as a differential input pair, and the output end, that is, the connection point of both transistors P12 and N14. Cannot be determined.
[0082]
Further, in this state, the transistors N31 and N33 of each input control unit 13c are cut off. As a result, the signal line for transmitting the clock signal CK (CK bar) is disconnected from the gates of the transistors P11 and P12 in the input stage, and the gate capacity serving as the load capacity of the signal line is reduced by the level shifter 13 in operation. Limited to things. As a result, despite the fact that a plurality of level shifters 13 (i) are connected to the signal line, the load capacity of the signal line can be reduced, and the clock signal CK (CK bar) is controlled as in the control circuit 5 shown in FIG. ) Can be reduced in power consumption.
[0083]
Further, since the transistors P32 and P34 of each input switching element cutoff control unit 13d are turned on during the stop, the gate voltages of both the transistors P11 and P12 are both the drive voltage VCC, and both the transistors P11 and P12 are cut off. The Thus, the current consumption can be reduced by the amount of current output from the constant current source Ic, as in the case where the transistor N21 is shut off. In this state, since both transistors P11 and P12 cannot operate as a differential input pair, the potential of the output terminal cannot be determined.
[0084]
In addition, when the control signal ENA indicates operation stop, the transistor P41 of the output stabilization unit 13e is further turned on. As a result, the gate potential of the output terminal, that is, the CMOS transistors P15 and N16 becomes the drive voltage VCC, and the output voltage OUT becomes the low level. As a result, as shown in FIG. 4, when the control signal ENAi indicates an operation stop, the output voltage OUT (CKi) of the level shifter 13 (i) is kept at a low level regardless of the clock signal CK. . As a result, unlike the case where the output voltage OUT is not fixed while the level shifter 13 (i) is stopped, the SR flip-flop F1 (i) can be prevented from malfunctioning, and the shift register 11 that can operate stably can be realized.
[0085]
(Second reference form)
This reference formThenFirst reference formUnlike FIG. 8, the case where the shift register is composed of a plurality of stages of D flip-flops will be described with reference to FIGS. The followingEach formFor convenience of explanation,First reference formMembers having the same functions as those in FIG.
[0086]
That is, as shown in FIG.This reference form1 is provided for each D flip-flop F2 (1) and the level shifter 13 (1)... Shown in FIG. Level shifters 23 (1)... Having the same configuration are provided.
[0087]
Each of the D flip-flops F2 (i) is a D flip-flop that changes the output Q according to the input D while the clock signal CKi is at a high level and maintains the output Q during the low level. The output Q of the flip-flop F2 (i) is output as an output Si and also input to the D flip-flop F2 (i + 1) at the next stage. Note that the start signal SP is input to the D flip-flop F2 (1) at the front stage.
[0088]
As in FIG. 1, the odd level shifters 23 (1)... Output the boosted clock signal CK as the clock signal CK1 during operation, and the even level shifters 23 (2). The signal CK2... Boosted with a polarity opposite to that of the clock signal CK is output. Regardless of whether the number is even or odd, the corresponding clock signal CKi and the inverted signal of the clock signal CKi generated by the inverter I2 (i) are applied to the D flip-flop F2 (i).
[0089]
Here, the output Si of the D flip-flop F2 (i) does not change until the clock signal CKi rises. Therefore, unlike the SR flip-flop F1 (i) shown in FIG. The clock signal CKi is also required at the time of falling. Therefore,This reference formIs provided with an OR circuit G1 (i) for calculating the logical sum of the input and output of each level shifter 23 (i), and outputs the calculation result as a control signal ENAi to the corresponding level shifter 23 (i). Yes.
[0090]
In the above configuration, as shown in FIG. 9, when the start signal SP is pulsed, the control signal ENA1 changes to high level and the boosted clock signal CK1 is input to the D flip-flop F2 (1). Is done. As a result, after the start signal SP is pulsed, the output S1 of the D flip-flop F2 (1) changes to a high level at the rising edge of the next clock signal CK1, while the clock signal CK1 is at a low level. Even if the start signal SP changes to the low level, it remains at the high level.
[0091]
After the start signal SP changes to low level, the output S1 of the D flip-flop F2 (1) changes to low level when the clock signal CK1 rises for the first time. Further, in this state, since both the start signal SP and the output S1 are at the low level, the OR circuit G1 (1) changes the control signal ENA1 to the low level and stops the level shifter 23 (1).
[0092]
Here, the output Si of each D flip-flop F2 (i) is input to the next-stage D flip-flop F2 (i + 1), and the adjacent D flip-flops F2 (i) and F2 (i + 1) The clock signals CKi and CK + 1 having opposite phases are input. As a result, the flip-flop unit 22 can transmit the start signal SP to the next stage for each edge (rising edge and falling edge) of the clock signal CK.
[0093]
In the above configuration, each level shifter 23 (i) is in a state where the corresponding D flip-flop F2 (i) needs to input the clock signal CKi, that is, after the pulse input to the D flip-flop F2 (i) is started. , The D flip-flop F2 (i) operates during the period until the pulse output is completed, and the operation can be stopped during the remaining period. As a result,First reference formSimilarly to the above, it is possible to realize the shift register 21 that can operate with a clock signal CK having an amplitude smaller than the drive voltage VCC and that consumes less power.
[0094]
further,This reference formThe flip-flop unit 22 according toFirst reference formUnlike the input D and the clock signal CK, it is composed of a D flip-flop that changes the output Q. Therefore, even if the pulse width (number of clocks) of the start signal SP changes, there is no problem. The start signal SP can be transmitted.
[0095]
For example, in the sampling unit 3b shown in FIG. 2, if the driving capability of the sampling transistor that samples the video signal DAT is low, a longer sampling period is required, and outputs S1... Sn with a longer pulse width (time) are required. And On the other hand, even with the same pulse width, the number of clocks increases as the frequency of the clock signal CK increases. Therefore, the optimum value of the pulse width of the start signal SP varies depending on the driving capability of the sampling transistor and the frequency of the clock signal CK. Therefore, as in the shift register 11 shown in FIG. 1, in the case where the connection destination of the reset signal R is set according to the pulse width (number of clocks) of the outputs S1,. It is necessary to design different circuits. In addition, when the same data signal line driving circuit 3 is driven with a clock signal CK having a different frequency, or when the data signal line driving circuit 3 is used for driving different display units 2, an optimal pulse width cannot be ensured and display quality may be deteriorated. There is.
[0096]
On the contrary,This reference formThe shift register 21 can output outputs S1,... With a desired pulse width only by changing the pulse width of the start signal SP. Therefore, it is possible to reduce the design effort and realize the image display device 1 in which the display quality does not deteriorate even in the above case.
[0097]
However, as shown in FIG. 5, the SR flip-flop F1 can be realized with fewer elements than the D flip-flop F2 shown in FIG. 10 to be described later, and can operate at a higher speed when the operating speed of the elements is the same. Furthermore, since the operation / stop of the level shifter 13 (i) at the next stage can be directly controlled by the output Si-1 at the previous stage, the OR circuit G1 (i) is unnecessary. As a result, when an optimum pulse width (number of clocks) can be determined in advance and a shift register having a high speed and a small circuit scale is required, it is preferable to use the SR flip-flop F1.
[0098]
Here, in each of the D flip-flops F2, for example, as shown in FIG. 10, P-type MOS transistors P51 and P52 and N-type MOS transistors N53 and N54 are provided between the drive voltage VCC and the ground level. Are connected in series with each other. An input signal D is applied to the gates of the transistors P52 and N53, and the drain potentials of the two transistors P52 and N53 connected to each other are inverted by the inverter INV51 and then output as the output Q. On the other hand, P-type MOS transistors P55 and P56 and N-type MOS transistors N57 and N58, which are connected in series, are provided between the drive voltage VCC and the ground level, respectively. The drains of both the transistors P56 and N57 are connected to the input of the inverter INV51, and the respective gates are connected to the output of the inverter INV51. Further, the inverted signal CK bar of the clock signal is applied to the gates of the transistors P51 and N58, and the clock signal CK is applied to the gates of the transistors N54 and P55.
[0099]
In the D flip-flop F2 configured as described above, the transistors P51 and N54 are turned on and the transistors P55 and N58 are cut off while the clock signal CK is at a high level. Thus, the input D is inverted by the transistors P52 and N53 and then inverted by the inverter INV51. As a result, the output Q changes to the same value as the input D. On the contrary, since the transistors P51 and N54 are cut off while the clock signal CK is at the low level, the transistors P52 and N53 cannot invert the input D. In this state, the transistors P55 and N58 are turned on, and the output of the inverter INV51 is fed back to the input. As a result, while the clock signal CK is at the low level, the output Q is maintained at the same value as the falling point of the clock signal CK even when the input D is at the high level. Therefore, as shown in FIG. 11, the output Q of the D flip-flop F2 changes following the input D when the clock signal CK first rises after the input D changes.
[0100]
On the other hand, for example, as shown in FIG. 12, each OR circuit G1 includes a series circuit composed of P-type MOS transistors P61 (1)... Corresponding to the inputs IN (1). ,... Corresponding to N-type MOS transistors N62 (1)... And a P-type MOS transistor P63 and an N-type MOS transistor N64 CMOS inverter. Since the OR circuit G1 is a two-input OR circuit, two transistors P61 and N62 are provided, and the input IN (1) is connected to the gates of the transistors P61 (1) and N62 (1). The input IN (2) is applied to the gates of the transistors P62 (2) and N62 (2). The series circuit and the parallel circuit are connected in series with each other and are arranged between the drive voltage VCC and the ground level. Further, the connection point between the series circuit and the parallel circuit is connected to the input terminal of the CMOS inverter, that is, the gates of the transistors P63 and N64. Thus, the OR circuit G1 can output the logical sum of the inputs IN (1) and IN (2) from the drains of the transistors P63 and N64 serving as the output terminals of the CMOS inverter.
[0101]
In FIG. 8, an OR circuit G1 (i) is provided for logically summing the inputs and outputs of each D flip-flop F2 (i) and instructing the level shifter 23 (i) to operate / stop. The OR circuit G1 (i) can be omitted if the input / output of the D flip-flop F2 (i) can be logically ORed to determine the operation / stop.
[0102]
Specifically, as shown in FIG. 13, in the shift register 21a according to this modification, instead of the level shifter 23 (i), a level shifter that operates when one of the control signals ENA1 and ENA2 is active (true). 24 (i) is provided. Accordingly, the OR circuit G1 (i) shown in FIG. 8 is omitted, and the input / output of the D flip-flop F2 (i) is directly input to the corresponding level shifters 24 (i) as control signals ENA1 and ENA2. .
[0103]
For example, as shown in FIG. 14, the level shifter 24 has substantially the same configuration as the level shifter 13 shown in FIG. 7. Unlike the level shifter 13, the level shifter 24 includes control signals in the power supply control unit 24 b to the output stabilization unit 24 e. Corresponding to ENA1 and ENA2, the same number (two in this case) of transistors N21 to P41 are provided. Specifically, in the power supply control unit 24b, the transistors N21 (1) and N21 (2) are connected in parallel to each other. Similarly, in the input control unit 24c corresponding to the transistor P11, the transistors N31 (1) and N31 (2) are respectively used, and in the input control unit 24c corresponding to the transistor P12, the transistors N33 (1) and N33 (2) are respectively provided. They are connected to each other in parallel. On the other hand, in the output stabilizing unit 24e, the transistors P41 (1) and P41 (2) are connected in series with each other, and each input switching element cutoff control unit 24d is connected with the transistors P32 (1) and P32 (2) connected in series with each other. Or transistors P34 (1) and P34 (2) connected in series with each other. Also,This reference formThen, since the shift register 21a transmits a high-level pulse signal, among the transistors N21 (1) to P41 (2), the gate corresponding to the control signal ENA1 (subscript (1)) is connected to the gate. The control signal ENA1 is applied, and the corresponding control signal ENA2 is applied to the gate corresponding to the control signal ENA2 (subscript (2)).
[0104]
According to the above configuration, when at least one of the control signals ENA1 and ENA2 is at a high level, one of the transistors N21 (1) and N21 (2), one of the transistors N31 (1) and N31 (2), and the transistor N33 (1) · N33 (2) is in conduction. Further, any one of the transistors P32 (1) and P32 (2), any one of the transistors P34 (1) and P34 (2), and any one of the transistors P41 (1) and P41 (2) are cut off. As a result, like the level shifter 13, the level shifter 24 operates. On the contrary, when both of the control signals ENA1 and ENA2 are at a low level, all of the N-type transistors N21 (1) to N34 (2) are cut off and the P-type transistors P31 (1) to P41 (2 ) Since everything is conductive, the level shifter 24 stops operating as in the level shifter 13 described above. As a result, like the level shifter 23 (i) shown in FIG. 8, the level shifter 24 (i) can be operated / stopped according to the input / output of the corresponding D flip-flop F2 (i), and the same effect can be obtained. Can do.
[0105]
(3rd reference form)
by the way,The first and second reference formsHowever, a level shifter is provided for each flip-flop.Each formAs shown, a level shifter may be provided for each of the plurality of flip-flops.Honsan Thought formA case where a level shifter is provided for each of the plurality of SR flip-flops will be described with reference to FIGS.
[0106]
That is,This reference formIn the shift register 11a according to FIG. 15, as shown in FIG. 15, the N SR flip-flops F1 are divided into K SR flip-flops F1 and divided into a plurality of blocks B1 to BP. Further, the level shifter 13 is provided for each block B. In the following, for convenience of explanation, if an integer greater than or equal to 1 is less than P and i is an integer greater than or equal to 1 and j is an integer greater than or equal to 1 and less than K, in the i-th block Bi, the j-th SR flip-flop F1 is F1 (i , j).
[0107]
further,This reference formIn each block Bi, an OR circuit G2 (i) for instructing the control signal ENAi to the level shifter 13 (i) is provided. The OR circuit G2 (i) receives the input signal to the block Bi and the output signals of the SR flip-flops F1 (i, 1)... F1i, (K-1) excluding the final stage in the block Bi. This is a K-input OR circuit that calculates a logical sum and outputs the logical sum to the level shifter 13 (i). Here, the input signal to the block Bi is the start signal SP in the frontmost block B1, and the output signal of the previous block Bi-1 in the second and subsequent blocks Bi. For example, as shown in FIG. 16, the OR circuit G2 increases the number of transistors P61 and the number of transistors N62 to the number of inputs (in this case, K) in the OR circuit G1 shown in FIG. It can be realized by a circuit.
[0108]
As a result, as shown in FIG. 17, the outputs Si, (K) of the SR flip-flop F1 (i, (K-1)) immediately before the last stage from the time when the pulse input to the block Bi is started. The control signal ENAi to the level shifter 13 (i) remains at the high level until the end of the pulse output of -1). As a result, the level shifter 13 (i) is at least as long as any of the SR flip-flops F1 (i, 1)... F1 (i, K) in the block Bi needs to input the clock signal CKi, that is, The clock signal CKi can be output and the SR flip-flop F1 (iK) is set from the time when the pulse input is started to the time when the final stage SR flip-flop F1 (i, K) is set. Thereafter, the operation can be stopped when the pulse output of the output Si, (K-1) of the SR flip-flop F1 (i, (K-1)) is completed.
[0109]
here,This reference formIn this case, the level shifter 13 (i) continues to output the clock signal CKi when any of the SR flip-flops F1 (i, j) of the block Bi requires a clock input, so that each SR flip-flop F1 ( When the clock signal CKi is supplied as is to i, j), the SR flip-flop F1 (i, j) is reset again after the SR flip-flop F1 (i, j) is reset as shown by the broken line in FIG. Is set, a plurality of pulses are generated from one pulse of the start signal SP. Therefore, as shown in FIG. 15, the shift register 11a is provided with a switch SWi, j between the level shifter 13 (i) and each SR flip-flop F1 (i, j). The clock signal CKi is applied to the SR flip-flop F1 (i, j) only while the flip-flop F1 (i, (j-1)) is outputting a pulse. Further, in order to prevent the set input to each SR flip-flop F1 (i, j) while the switch SWi, j is cut off, the negative logic set terminal of each SR flip-flop F1 (i, j) The drive voltage VCC is applied to the S bar via a P-type MOS transistor Pi, j. In the foremost stage of the shift register 11a, the start signal SP is applied to the gate of the transistor P1,1, and the previous stage SR flip-flop F1 (i, j-1) is applied to the gate of the remaining transistor Pi, j. The output Si, j-1 is applied. As a result, while the switch SWi, j is cut off, the transistor Pi, j becomes conductive, the set terminal S bar is fixed at a predetermined potential (in this case, the drive voltage VCC), and the set input is blocked. The As a result, the start signal SP is transmitted without any problem. For example, the SR flip-flop F1 to which the clock signal CKi is not supplied after being reset, such as the last stage SR flip-flop F1 (i, K), directly inputs the clock signal CKi without passing through the switch SW. May be.
[0110]
In the above configuration,First reference formAs shown in FIG. 4, the distance between the level shifter 13 and the SR flip-flop F1 is longer than when the level shifter 13 is provided for each SR flip-flop F1, but the clock signal CK is transmitted from a single level shifter to all SR flip-flops. Compared to the conventional technology that supplies, the distance between the two can be shortened and the buffer can be reduced,First reference formIn substantially the same manner, the shift register 11a with low power consumption can be realized.
[0111]
Here, if the number of SR flip-flops F1 included in the block B is increased, the number of level shifters 13 included in the shift register 11a can be reduced, so that the circuit configuration can be simplified. On the other hand, if the number of SR flip-flops F1 is increased too much, the drive capability of the level shifter 13 becomes insufficient and a buffer is required, so that power consumption increases. Therefore, when it is required to reduce the circuit scale without increasing the power consumption, the block B is not provided, and each block B is within the range in which the level shifter 13 (i) can supply the clock signal CK (i). It is desirable to set the number of the SR flip-flops F1.
[0112]
In addition,Reference form aboveThe case where the operation / stop of the level shifter 13 is controlled by the OR circuit G2 has been described as an example. However, like the level shifter 24 shown in FIG. 13, the level shifter 14 itself is connected to the OR circuit G2 as shown in FIG. The operation / stop may be determined based on the input signal. For example, as shown in FIG. 19, the level shifter 14 can be realized by a circuit in which the transistors N21 to P41 are provided in the level shifter 24 shown in FIG. 14 by the same number (K in this case) as the input.
[0113]
(First embodiment)
Hereinafter, a case where a level shifter is provided for each of a plurality of D flip-flops will be described with reference to FIGS. That is, as shown in FIG. 20, the shift register 21b according to the present embodiment is similar to the shift register 21 shown in FIG. 8, except that N D flip-flops F2 are provided for every K D flip-flops F2. Divided into a plurality of blocks B1 to BP. Further, the level shifter 23 is provided for each block B.
[0114]
Further, in the present embodiment, an OR circuit G3 (i) for instructing the control signal ENAi to the level shifter 23 (i) is provided for each block Bi. The OR circuit G3i is a (K + 1) -input OR circuit, and calculates the logical sum of the inputs and outputs of the D flip-flops F2 (i, 1)... F2 (i, K) in the block Bi. Output to the level shifter 23 (i). Here, the input signal to the D flip-flop F2 (i, 1) in the foremost stage is the start signal SP in the block B1 in the foremost stage, and in the block Bi in the second and subsequent stages, Output signal. For example, as shown in FIG. 21, the OR circuit G3 increases the number of transistors P61 and the number of transistors N62 to the number of inputs (in this case, K + 1) in the OR circuit G1 shown in FIG. It can be realized by a circuit.
[0115]
Thus, as shown in FIG. 22, while any of the D flip-flops F2 (i, 1)... F2 (i, K) in the block Bi requires input of the clock signal CKi, that is, the block The control signal ENAi to the level shifter 23 (i) is at a high level during the period from the start of pulse input to Bi to the end of D pulse flip-flop F2 (i, K) at the final stage, and the level shifter 23 (i) can output the clock signal CKi. Further, since the control signal ENAi is at a low level during the remaining period, the level shifter 23 (i) can stop the operation.
[0116]
In the above configuration,Second reference formCompared with the case where the level shifter 23 is provided for each D flip-flop F2 as in the shift register 21 shown in FIG. 1, the distance between the level shifter 23 and the D flip-flop F2 is longer, but all the D flip-flops from a single level shifter. Compared to the conventional technology that supplies the clock signal CK to the distance between the two, the distance between the two can be shortened and the buffer can be reduced.Second reference formIn substantially the same manner, a shift register 21b with low power consumption can be realized.
[0117]
further,Third reference formSimilarly to this, in the present embodiment, the number of level shifters 23 can be reduced as compared with the shift register 21. Furthermore, when it is required to reduce the circuit scale without increasing the power consumption, the D in each block Bi is within a range in which the level shifter 23 (i) can supply the clock signal CKi without providing a buffer. It is desirable to set the number of flip-flops F2.
[0118]
In FIG. 20, the operation / stop of the level shifter 23 is controlled by the OR circuit G3 as an example. However, like the shift register 11b shown in FIG. 18, the level shifter 21c shown in FIG. 25 itself may control the operation / stop based on each input signal to the OR circuit G3. For example, as shown in FIG. 24, the level shifter 25 can be realized by a circuit in which the transistors N21 to P41 are provided by the same number (in this case, K + 1) as the input in the level shifter 14 shown in FIG.
[0119]
(4th reference form)
by the way,The third reference embodiment and the first embodimentIn the above description, the case where the level shifter or the OR circuit ORs the K, (K + 1) signals to control the operation / stop of the level shifter has been described. On the contrary,This reference formNow, a case where the operation / stop of the level shifter is controlled using the latch circuit will be described with reference to FIGS.
[0120]
Specifically, as shown in FIG.This reference formIn the shift register 11c according to FIG. 15, a latch circuit 31 (i) is provided instead of the OR circuit G2 (i) of the shift register 11a shown in FIG. The latch circuit 31 changes the output with the pulse input to the first stage SR flip-flop F1 (i, 1) of the block Bi and the pulse output of the last stage SR flip-flop F1 (i, K) as triggers. The level shifter 13 (i) can be instructed to operate from the time when the pulse input is started to the time when the pulse output is started.
[0121]
For example, taking the first block B1 as an example, the latch circuit 31 is applied with the start signal SP inverted by the inverter 31a as a negative logic set signal S bar as shown in FIG. As a signal R, an SR flip-flop 31b to which the output S1, K of the SR flip-flop F1 (1, K) at the final stage is applied is provided. It should be noted that, in the block Bi after the next stage, the output of the previous block Bi-1 is applied instead of the start signal SP.
[0122]
In the above configuration, as shown in FIG. 27, the latch circuit 31 (i) has the output Si, K that has been high since the input to the first stage SR flip-flop F1 (i, 1) has changed to the high level. Until the level changes, the control signal ENAi is set to the high level. Thus, the level shifter 13 (i) can continue to supply the clock signal CKI during the period. When the output Si, K changes to the high level, the control signal ENAi becomes the low level, and the level shifter 13 (i) stops its operation. As a result,Third reference formSimilarly to the above, it is possible to realize the shift register 11c that consumes less power than the conventional one.
[0123]
further,This reference formThe latch circuit 31 (i) according toThird reference formUnlike the case of determining the operation / stop of the level shifters 13 (i) (14 (i)) based on the K signals as in the OR circuit G2 (i) (level shifter 14 (i)) of the block Bi, Regardless of the number of stages K of the SR flip-flop F1, the control signal ENAi is generated using two signals as a trigger. Therefore, the number of signal lines for transmitting signals necessary for determination can be reduced to two. Here, when the number of signal lines for determination increases, the number of intersections with the signal lines that transmit the outputs Si, j and the clock signals CK and CKi increases, and the capacity of each signal line may increase. However,This reference formThen, because the number of signal lines for determination is reduced to two,Third reference formAs a result, it is possible to suppress the increase in the wiring capacity caused by the determination signal line, and to realize the shift register 11c with low power consumption.
[0124]
In FIG. 26, the case where the latch circuit 31 (i) is composed of SR flip-flops has been described as an example, but the present invention is not limited to this. If the operation / stop of the level shifter 13 (i) can be controlled using two signals as triggers, the same effect can be obtained by using, for example, the latch circuit 32 shown in FIG. 28 instead of the latch circuit 31 (i). can get.
[0125]
The latch circuit 32 includes two D flip-flops 32a and 32b constituting a frequency divider, a NOR circuit 32c that calculates the negation of the logical sum of the start signal SP and the outputs S1 and K, and the output of the NOR circuit 32c. And an inverter 32d for inverting. The output Q of the D flip-flop 32a is input to the D flip-flop 32a via the D flip-flop 32b. The output LSET of the inverter 32d is applied as a clock to the D flip-flop 32a, and the output of the NOR circuit 32c is applied as a clock to the D flip-flop 32b. Further, the output LOUT of the D flip-flop 32a is output as the control signal ENA1. As a result, as shown in FIG. 29, the latch circuit 32 (i), like the latch circuit 31 (i), starts pulse input to the foremost stage SR flip-flop F1 (i, 1). Until the output Si, K rises, the high-level control signal ENAi is output to instruct the level shifter 13 (i) to operate.
[0126]
In addition,This reference formThen, as a trigger of the latch circuit (31, 32), start of pulse input to the first stage SR flip-flop F1 (i, 1) and start of pulse output of the last stage SR flip-flop F1 (i, K) However, this is not a limitation. The signal that can set the control signal ENAi to active at a timing before the period in which the SR flip-flop F1 in the block Bi requires the clock signal CKi, and the control signal ENAi to inactive at a timing after the period The same effect can be obtained by using a possible signal as a trigger.
[0127]
(Second Embodiment)
In the present embodiment, in a shift register using a D flip-flop, a configuration in which the operation / stop of the level shifter is controlled by a latch circuit will be described with reference to FIGS.
[0128]
That is, in the shift register 21d according to this embodiment, instead of the OR circuit G3 (i) of the shift register 21b shown in FIG. 20, the D flip-flop in the foremost stage is substantially the same as the latch circuit 31 (i) shown in FIG. A latch circuit 33 (i) is provided which uses a pulse input to F2 (i, 1) and a pulse output of the final stage D flip-flop F2 (i, K) as a trigger. However, as described above, in the case of the D flip-flop, the clock signal CKi is required until the final stage D flip-flop F2 (i, K) stops the pulse output, so the latch circuit 33 (i) Is configured to instruct the level shifter 23 (i) to operate from the time when the pulse input is started to the time when the pulse output is stopped.
[0129]
Specifically, taking the first block B1 as an example, the latch circuit 33, for example, as shown in FIG. 31, in addition to the latch circuit 31 shown in FIG. 26, the output signal LOUT and the output S1 of the final stage. , K and a NOR circuit 33c for calculating the negation of the logical sum and an inverter 33d for inverting the calculation result. It should be noted that, in the block Bi after the next stage, the output of the previous block Bi-1 is applied instead of the start signal SP.
[0130]
In the above configuration, as shown in FIG. 32, the latch circuit 33 (1) is configured such that the outputs S1, K are low after the input to the front D flip-flop F2 (1,1) changes to the high level. Until the level changes, the control signal ENA1 is set to the high level. As a result, the level shifter 23 (1) can continue to supply the clock signal CK1 during the period. Further, when the outputs S1, K change to the low level, the control signal ENA1 becomes the low level, and the level shifter 23 (1) stops its operation. As a result,First embodimentSimilarly to the above, it is possible to realize the shift register 21d that consumes less power than the conventional one.
[0131]
Furthermore, in this embodiment,Fourth reference formSimilarly to the above, the number of signal lines necessary for the determination of the operation / stop of the level shifter 23 can be reduced.First embodimentAs a result, it is possible to suppress the increase in the wiring capacitance caused by the determination signal line, and to realize the shift register 21d with low power consumption.
[0132]
In FIG. 31, the case where the latch circuit 33 is configured by an SR flip-flop has been described as an example, but the present invention is not limited to this. If the operation / stop of the level shifter 13 can be controlled by using two signals as triggers, the same effect can be obtained by using, for example, the latch circuit 34 shown in FIG. 33 instead of the latch circuit 31 (i).
[0133]
In the latch circuit 34, a NOR circuit 33c and an inverter 33d shown in FIG. 31 are added to the latch circuit 32 shown in FIG. As a result, as shown in FIG. 34, the latch circuit 34, as in the case of the latch circuit 33, starts from the start of pulse input to the D flip-flop F2 (i, 1) in the foremost stage of the block Bi. Until the D flip-flop F2 (i, K) completes the pulse output, the high-level control signal ENAi can be output to instruct the level shifter 23 (i) to operate.
[0134]
In the present embodiment, as a trigger for the latch circuits (33 to 34), the start of pulse input to the frontmost D flip-flop F2 (i, 1) and the last D flip-flop F2 (i, K) However, the present invention is not limited to this. A signal that allows the control signal ENAi to be set active at a timing before the period in which the D flip-flop F2 in the block Bi requires the clock signal CKi, and a control signal ENAi to be set inactive at a timing after the period The same effect can be obtained by using a possible signal as a trigger.
[0135]
(Third embodiment)
In the following, referring to FIG.First and second embodiments aboveSimilarly, the configuration in which the level shifter 23 (24, 25) can further reduce power consumption in the shift registers 21b to 21d that supply the clock signal CK to the plurality of D flip-flops F2 will be described.
[0136]
Specifically, the shift register according to the present embodiment has the same configuration as the shift registers 21b to 21d, but the clock signal control circuit 26 (i, j) is provided for each D flip-flop F2 (i, j). The level shifter 23 (i) (24 (i), 25 (i): represented by 23 (i) below) is a boosted clock only to the D flip-flop F2 that requires a clock input. The signal CK (i) is supplied.
[0137]
As shown in FIG. 35, the clock signal control circuit 26 (i, j) includes a switch SW1 (i, j) provided on a signal line to which the clock signal CKi is transmitted, and an inverted signal CKi bar of the clock signal CKi. Switch SW2 (i, j) provided on the transmission line. Both switches SW1 (i, j) and SW2 (i, j) are OR's that calculate the logical sum of the inputs and outputs of the D flip-flop F2 (i, j), similarly to the level shifter 23 (i, j) shown in FIG. It is controlled by the circuit G1 (i, j) and is turned on when the D flip-flop F2 (i, j) requires the clock signal CKi (CKi bar) and is cut off when no clock input is required. Further, the clock signal control circuit 26 (i, j) includes an N-type MOS transistor N71 (i, j) provided between the clock input terminal of the D flip-flop F2 (i, j) and the ground potential. A P-type MOS transistor P72 (i, j) provided between the inverted clock input terminal of the D flip-flop F2 (i, j) and the drive voltage VCC is provided. The output of the OR circuit G1 (i, j) is applied to the gate of the transistor N71 (i, j) after being inverted by the inverter INV71 (i, j), and the transistor P72 (i, j) The output of the OR circuit G1 (i, j) is applied to the gates.
[0138]
In the above-described configuration, the switch SW1 (i, j) (SW2 (i, j)) is turned on for a period during which the corresponding D flip-flop F2 (i, j) requires the boosted clock signal CKi (CKi bar). The clock signal CKi (CKi bar) is applied to the D flip-flop F2 (i, j). On the other hand, during the period when the clock input is not required, the switches SW1 (i, j) and SW2 (i, j) are cut off, and both switches SW1 (i, j) such as D flip-flop F2 (i, j), for example. ). The circuit after SW2 (i, j) is separated from the level shifter 23 (i). Further, during the period when the clock input is unnecessary, both the transistors N71 (i, j) and P72 (i, j) are turned on, and the clock input terminal and the inverting input terminal of the D flip-flop F2 (i, j) are connected. Since each is maintained at a predetermined value (low level and high level), unlike the case where both the input terminals are indefinite, malfunction of the D flip-flop F2 (i, j) can be suppressed.
[0139]
According to the above configuration, the circuit after both switches SW1 (i, j) and SW2 (i, j) and the level shifter 23 (i) are disconnected from the level shifter 23 (i) during the period when the clock input is unnecessary. Need only drive the D flip-flop F2 (i, j) that currently requires the clock signal CK (i). Therefore, the load capacity of the level shifter 23 (i) can be greatly reduced and the power consumption can be reduced as compared with the case where all the D flip-flops F2 (i, 1) to F2 (i, K) in the block Bi are driven. . As a result, a shift register with low power consumption can be realized.
[0140]
In the above description, the case where the clock signal control circuit 26 (i, j) is provided for each D flip-flop F2 (i, j) has been described as an example. However, the present invention is not limited to this. A clock signal control circuit 26 may be provided for each D flip-flop F2. In this case, both the switches SW1 and SW2 are in a state where the D flip-flop F2 connected to both the switches SW1 and SW2 requires a clock input, that is, after the pulse input to the D flip-flop F2 at the front stage is started. For example, the same as the OR circuit G3 shown in FIG. 20 or the latch circuit 33 (34) shown in FIG. 30 (FIG. 33) so that the D flip-flop F2 in the final stage can be turned on until the pulse output is completed. Controlled by the circuit. In this case, the load capacity of the level shifter 23 (24, 25) is larger than the configuration in which the clock signal control circuit 26 is provided for each D flip-flop F2, but the number of clock signal control circuits 26 can be reduced. The circuit configuration can be simplified.
[0141]
(5th reference form)
Incidentally, for example, in the data signal line driving circuit 3 and the scanning signal line driving circuit 4 shown in FIG.Each formIn some cases, the output of each stage of the shift registers (11, 11a to 11c, 21, 21a to 21d) is directly used as a signal indicating the timing. Sometimes used as a signal.
[0142]
Below,First, third and fourth reference formsIn the shift register using the SR flip-flop F1 as described above, a configuration suitable for performing a logical operation on outputs of a plurality of stages will be described with reference to FIGS. If the configuration uses the SR flip-flop F1, the otherFormBut can be applied to:First reference formThis will be described as an example.
[0143]
That is,This reference formIn addition to the configuration of the shift register 11 shown in FIG. 1, the shift register 11d according to the AND circuit G4 calculates a logical product of two adjacent outputs Si · Si + 1 and outputs the calculation result as a timing signal SMPi. (i) is provided. Further, an SR flip-flop F1 (0) is provided in the preceding stage of the SR flip-flop F1 (1) at the foremost stage, and a logical product of the output S0 of the SR flip-flop F1 (0) and the output S1 is calculated. And an AND circuit G4 (0) for output. Further, an inverted signal SP bar of the start signal SP is applied to the SR flip-flop F1 (0) as a negative logic set signal, and the output of the SR flip-flop F1 (0) is a level shifter which is the next stage. The control signal ENA1 is input to 13 (1). The SR flip-flop F1 (0), like the SR flip-flop F1 (i) at the other stage, is the level shifter 13 (2 stages) after the number of stages (in this case, two stages) corresponding to the pulse width of the pulse signal to be transmitted. The output CK2 of 2) is applied.
[0144]
Here, only the output S0 is connected to the single AND circuit G4 (0) among the outputs S0, S1,... Of each SR flip-flop F1 (0), F1 (1). Are connected to two AND circuits G4 (i-1) and G4 (i). As a result, the SR flip-flop F1 (0) and the remaining SR flip-flop F1 (i) have different output loads. Even if they are driven at the same timing, the output S0 and the remaining outputs S1. The delay times for the signal CK are different from each other. Therefore, when the frequency of the clock signal CK is high, the output signal of the AND circuit G4 (0) is a dummy signal DUMMY that is not used in the subsequent circuit in order to suppress timing variation due to delay in the delay time. Only the outputs SMP1... Of the remaining AND circuits G4 (1)... Are used for video signal extraction.
[0145]
In the above configuration, unlike the other stages, the inverted signal SP bar that is not synchronized with the clock signal CK is applied to the SR flip-flop F1 (0) as a negative logic set signal. The pulse width is different from the outputs S1 of the other SR flip-flops F1 (1). However, as described above, the output S0 is not used as a dummy signal DUMMY in a subsequent circuit. Therefore, even if the timing of the output S0 is different, the shift register 11d can output the timing signals SMP1... Having different timings by a predetermined time without any trouble.
[0146]
Further, in the above configuration, the inverted signal SP bar is applied to the SR flip-flop F1 (0), and the level shifter 13 is omitted. Therefore, the number of level shifters 13 can be reduced as compared with the case where the level shifters 13 are also provided in the SR flip-flop F1 (0).
[0147]
In addition,All the above formsIn the above description, the level shifter (13, 14, 23 to 25) is described as an example of the current drive type, but a voltage drive type level shifter 41 may be used as shown in FIG. The level shifter 41a of the level shifter 41 is turned on / off as an input switching element according to an N-type MOS transistor N81 that is turned on / off according to a clock signal CK and an inverted signal CK bar of the clock signal CK. And an N-type MOS transistor N82. A drive voltage VCC is applied to the drain of each transistor N81 (N82) via a P-type MOS transistor P83 (P84) serving as a load, and the sources of both transistors N81 and N82 are grounded. The potential at the connection point of the transistors N82 and P84 is output as the output OUT of the level shifter 41 and applied to the gate of the transistor P83. Similarly, the potential at the connection point of the transistors N81 and P83 is output as the inverted output OUT bar of the level shifter 41 and applied to the gate of the transistor P84.
[0148]
On the other hand, the level shifter 41 is provided with N-type MOS transistors N91 and N92 as an input opening switch section (switch) 41b. During the operation of the level shifter 41, the gate of the transistor N81 is connected via the transistor N91. The clock signal CK is applied, and the inverted signal CK bar of the clock signal CK is applied to the gate of the transistor N82 via the transistor N92.
[0149]
Further, the level shifter 41 is provided with an N-type MOS transistor N93 and a P-type MOS transistor P94 as the input stabilizing part 41c. Thus, when the level shifter 41 is stopped, the gate of the transistor N81 is grounded via the transistor N93, and the drive voltage VCC is applied to the gate of the transistor N82 via the transistor P94. The input stabilizing unit 41c is, OutCorresponding to the force stabilizing means, the input voltage to both the transistors N81 and N82 is controlled to stabilize the output. Here, the level shifter 41 is a voltage drive type and consumes power only when the output OUT is changed. Therefore, when the level shifter 41 is stopped, power consumption does not occur even if the output voltage is controlled by the input voltage.
[0150]
This formSince the operation of the level shifter 41 is shown when the control signal ENA is at a high level, the control signal ENA is applied to the gates of the transistors N91, N92, and P94, and the control signal ENA is applied to the transistor N93 as an inverter. Applied after being inverted by INV91.
[0151]
In the above configuration, when the control signal ENA is at a high level, the transistors N91 and N92 are turned on, and the transistors N81 and N82 are turned on / off according to the clock signal CK and its inverted signal CK bar. As a result, the output OUT is boosted to the level of the drive voltage VCC when the clock signal CK is at the high level, and at the ground level when the clock signal CK is at the low level.
[0152]
On the contrary, when the control signal ENA is at a low level, the transistors N93 and P94 are turned on, so that the transistor N81 is cut off and the transistor N82 is turned on. As a result, the output OUT is maintained at the ground level, and the inverted output OUT bar is maintained at the drive voltage VCC. In this state, since both transistors N91 and N92 are cut off, the gate of the transistor N81 (N82) as the input switching element is disconnected from the transmission line of the clock signal CK (CK bar). Thereby, for example, the load capacity and power consumption of the drive circuit for the clock signal CK (CK bar) such as the control circuit 5 shown in FIG. 2 can be reduced.
[0153]
In FIG. 38, as in the case of the level shifters 13 and 23, the case where the operation / stop is controlled by one control signal ENA has been described as an example. However, similarly to the level shifters 14, 24 and 25, the transistors N91 to P94. If the number of inverters INV91 is increased in accordance with the number of control signals ENA, the operation / stop can be controlled by a plurality of control signals ENA.
[0154]
Even when the level shifter 41 configured as described above is used, a plurality of level shifters 41 are provided, and at least one of the level shifters 41 that do not require clock output is stopped. Compared with the case of supplying a clock signal, the load capacity of each level shifter can be reduced, and the power consumption of the shift register can be reduced.
[0155]
However,All the above formsIn the current drive type level shifter 13 (14, 23 to 25: represented by the level shifter 13 below), a current always flows to the input switching elements (P11, P12) during operation. Even when the amplitude is lower than the threshold value of the input switching elements (transistors N81 and N82) and the level shifter 41 cannot operate, the clock signal CK can be boosted without any trouble. Further, since the level shifter 13 is stopped according to the necessity of the clock output, the power consumption increases even though there are a plurality of level shifters 13 that consume power even when the output is not changed. Can be suppressed. Therefore, it is desirable to use the current drive type level shifter 13.
[0156]
In addition,The first to third embodiments and the third and fourth reference embodimentsIn the above description, the case where the level shifters (13, 14, 23 to 25) are provided for each of the K flip-flops (F1 and F2) has been described as an example. Is provided, the same effect can be obtained even if the number of flip-flops included in each block is not the same.
[0157]
further,Each form aboveIn the above description, the image display device has been described as an example of application of the shift register. However, the shift register according to the present invention is widely applied to applications where a clock signal CK having an amplitude lower than the drive voltage of the shift register is applied. it can. However, the image display apparatus is strongly required to improve the resolution and enlarge the display area, so that the number of stages of the shift register is large and the driving ability of the level shifter cannot be sufficiently secured in many cases. Therefore, it is particularly effective when applied to a drive circuit of an image display device.
[0158]
【The invention's effect】
  As described above, the shift register according to the present invention is a flip-flop.IsA level shifter that boosts a clock signal having an amplitude smaller than the drive voltage is provided for each block, and among the plurality of level shifters, the level shifter is used for transmitting the input pulse at that time. At least one level shifter corresponding to a block that does not require input of a clock signal is configured to stop.
[0159]
In this configuration, since the shift register is provided with a plurality of level shifters, the distance from each level shifter to the flip-flop can be shortened. In addition, at least one of the plurality of level shifters has stopped operating. As a result, it is possible to realize a shift register that can be operated with a low voltage clock signal input and has low power consumption.
[0160]
The shift register according to the present invention has a specific block in the above configuration.The boosted clock signal is input to the clock terminal.Including D flip-flops,A circuit for outputting whether or not the specific block is in a predetermined period for performing the transmission based on a signal input to the specific block and each output signal of the flip-flop of the specific block;The specific level shifter isBased on the output of the circuit,The operation is started when the pulse input to the specific block is started, and the operation is stopped after the flip-flop at the final stage of the specific block ends the pulse output.
[0161]
Alternatively, in the shift register, the specific block includes the D flip-flop, and the specific block transmits the signal based on a signal input to the specific block and an output signal of the flip-flop at the final stage of the specific block. The specific level shifter corresponding to the specific block includes a latch circuit that indicates that the predetermined period has been started by performing an output to store and hold the start of the predetermined period until the end of the predetermined period. Based on the output of the circuit, the operation is performed from at least the time when the pulse input to the specific block is started to the time when the flip-flop at the final stage of the specific block ends the pulse output.
[0162]
According to this configuration, the specific level shifter supplies the clock signal after the level shift during a period required when the D flip-flop of the specific block operates, and the input of the clock signal to the D flip-flop is unnecessary. Since the operation is stopped, it is possible to realize a shift register that can transmit input pulses having different pulse widths and consumes less power..
[0163]
BookThe shift register according to the present invention has the above structure,The level shifter includes a current drive type level shift unit including an input switching element. The For example,The level shifter includes a current drive type level shift unit in which the input switching element to which the clock signal is applied is always turned on during operation.
[0164]
According to this configuration, at least one of the current-driven level shifters stops operating, so that the level can be shifted even when the amplitude of the clock signal is lower than the threshold voltage of the input switching element, and the power consumption There is an effect that a shift register with less can be realized.
[0165]
In the shift register according to the present invention, in the shift register having the above-described configuration, an input signal control unit that stops the level shifter by giving the level shift unit a signal at a level that is cut off by the input switching element.For example, in the above level shifterIt is the structure provided.
[0166]
According to this configuration, since the input signal control unit controls the level of the input signal and shuts off the input switching element, power consumption can be reduced by the amount of current flowing to the input switching element during operation. There is an effect.
[0167]
The shift register according to the present invention is configured so as to include a power supply control unit that stops the power supply to the level shift unit and stops the level shifter in the above configuration.
[0168]
According to this configuration, since the power supply to each level shift unit is stopped and the level shifter is stopped, the power consumption can be reduced by the amount of power consumed by the level shifter during operation..
[0169]
BookThe shift register according to the present invention is configured such that, in each of the above-described configurations, a switch that is opened while the level shifter is stopped is provided between the level shift unit and the transmission line of the clock signal.
[0170]
In this configuration, since the input switching element connected to the clock signal line is limited to the level shifter in operation, the load capacity of the clock signal line can be reduced and the power consumption of the circuit driving the clock signal line can be reduced. There is an effect that can be done.
[0171]
As described above, the image display device according to the present invention has a configuration in which at least one of the data signal line driving circuit and the scanning signal line driving circuit includes the shift register having any one of the above-described configurations.
[0172]
According to this configuration, since at least one of the data signal line driving circuit and the scanning signal line driving circuit includes the shift register having the above-described configurations, an image display device with low power consumption can be realized.
[0173]
The image display device according to the present invention has a configuration in which the data signal line driving circuit, the scanning signal line driving circuit, and each pixel are formed on the same substrate.
[0174]
According to this configuration, even if the number of data signal lines and the number of scanning signal lines increase, the number of signal lines going out of the substrate does not change, so that an undesired increase in capacitance of each signal line can be prevented. The effect of preventing a reduction in the degree of integration can be obtained.
[0175]
The image display device according to the present invention has a configuration in which the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element made of a polycrystalline silicon thin film transistor.
[0176]
In this configuration, since the data signal line driving circuit, the scanning signal line driving circuit, and each pixel all include a switching element made of a polycrystalline silicon thin film transistor, an image with low power consumption and a wide display area is obtained. There is an effect that a display device can be realized.
[0177]
The image display device according to the present invention has a configuration in which the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element manufactured at a process temperature of 600 ° C. or less.
[0178]
According to this configuration, even if an ordinary glass substrate (a glass substrate having a strain point of 600 degrees or less) is used, no warping or warping due to a process at or above the strain point is generated. There is an effect that an image display device having a wide display area can be realized.
[Brief description of the drawings]
FIG. 1 of the present inventionFirst reference form of embodimentFIG. 3 is a block diagram illustrating a main configuration of a shift register including a set / reset flip-flop.
FIG. 2 is a block diagram showing a main configuration of an image display apparatus using the shift register.
FIG. 3 is a circuit diagram illustrating a configuration example of a pixel in the image display device.
FIG. 4 is a timing chart showing the operation of the shift register.
FIG. 5 is a circuit diagram showing a configuration example of a set / reset flip-flop used in the shift register.
FIG. 6 is a timing chart showing the operation of the set / reset flip-flop.
FIG. 7 is a circuit diagram illustrating a configuration example of a level shifter in the shift register.
FIG. 8 shows the present invention.Second reference form of embodimentFIG. 2 is a block diagram illustrating a main configuration of a shift register including a D flip-flop.
FIG. 9 is a timing chart showing the operation of the shift register.
FIG. 10 is a circuit diagram showing a configuration example of the D flip-flop.
FIG. 11 is a timing chart showing the operation of the D flip-flop.
FIG. 12 is a circuit diagram illustrating a configuration example of an OR circuit used in the shift register.
FIG. 13 is a block diagram showing a modification of the shift register.
FIG. 14 is a circuit diagram showing a configuration example of a level shifter in the shift register.
FIG. 15 shows the present invention.Third reference form of embodimentFIG. 3 is a block diagram showing a shift register in which a level shifter is provided for each of a plurality of set / reset / flip-flops.
FIG. 16 is a circuit diagram illustrating a configuration example of an OR circuit used in the shift register.
FIG. 17 is a timing chart showing the operation of the shift register.
FIG. 18 is a block diagram showing a modification of the shift register.
FIG. 19 is a circuit diagram illustrating a configuration example of a level shifter in the shift register.
FIG. 20 shows the present invention.First embodimentFIG. 3 is a block diagram showing a shift register in which a level shifter is provided for each of a plurality of D flip-flops.
FIG. 21 is a circuit diagram illustrating a configuration example of an OR circuit used in the shift register.
FIG. 22 is a timing chart showing the operation of the shift register.
FIG. 23 is a block diagram showing a modification of the shift register.
FIG. 24 is a circuit diagram illustrating a configuration example of a level shifter in the shift register.
FIG. 25 shows the present invention.Fourth reference embodimentFIG. 2 is a block diagram showing a shift register including a latch circuit for controlling the operation of the level shifter and a set / reset flip-flop.
FIG. 26 is a block diagram illustrating a configuration example of the latch circuit.
FIG. 27 is a timing chart showing the operation of the shift register.
FIG. 28 is a block diagram showing another configuration example of the latch circuit.
FIG. 29 is a timing chart showing the operation of the latch circuit.
FIG. 30 shows the present invention.Second embodimentFIG. 2 is a block diagram showing a shift register including the latch circuit and a D flip-flop.
FIG. 31 is a block diagram illustrating a configuration example of the latch circuit.
FIG. 32 is a timing chart showing the operation of the shift register.
FIG. 33 is a block diagram showing another configuration example of the latch circuit.
FIG. 34 is a timing chart showing the operation of the latch circuit.
FIG. 35 shows the present invention.Third embodimentFIG. 2 is a circuit diagram showing a clock signal control circuit provided when a level shifter of each block selectively supplies a clock signal to a D flip-flop in the block.
FIG. 36 shows the present invention.5th reference form of embodimentFIG. 2 is a block diagram illustrating a main configuration of a shift register.
FIG. 37 is a timing chart showing the operation of the shift register.
FIG. 38 is a circuit diagram showing a voltage-driven type level shifter according to a modification of the present invention.
FIG. 39 shows a conventional example and is a block diagram showing a shift register including a level shifter.
[Explanation of symbols]
1 Image display device
3 Data signal line drive circuit
4 Scanning signal line drive circuit
11.11a-11d.21.21a-21c Shift register
13 ・ 14 ・ 23 ～ 25 ・ 41 Level shifter
13a / 14a / 23a-25a / 41a Level shift section
13b / 14b / 23b-25b Power supply control unit
13c, 14c, 23c to 25c Input control unit (switch)
13d / 14d input switching element cutoff controller (input signal controller)
13e, 14e, 23e to 25e Output stabilization part (output stabilization means)
23d to 25d Input switching element cutoff controller (input signal controller)
31-34 Latch circuit
41b Input release switch (switch)
41c Input stabilization part (output stabilization means)
B1 ... Block (specific block)
F1 (1) ... SR flip-flop (flip-flop)
F2 (1) ... D flip-flop (flip-flop)
G3 (1) ... OR circuit (circuit)
P11 / P12 transistor (input switching element)
PIX pixel

Claims (11)

A multi-stage flip-flop;
A shift register that boosts a clock signal having a smaller amplitude than the driving voltage of the flip-flop and applies the voltage to each flip-flop, and sequentially transmits an input pulse by the flip-flop in synchronization with the clock signal. In
Each flip-flop is divided into blocks of multiple,
The level shifter is provided for each block, and
Of the plurality of level shifters, at least one of the level shifters corresponding to the block that does not require the input of the clock signal to transmit the input pulse at that time is stopped.
A specific block of the blocks includes a plurality of the flip-flops, and includes a D flip-flop to which the clock signal boosted to a clock terminal is input as the flip-flop.
A circuit for outputting whether or not the specific block is in a predetermined period for performing the transmission based on a signal input to the specific block and an output signal of the flip-flop of the specific block;
The specific level shifter, which is the level shifter corresponding to the specific block, starts the operation when the pulse input to the specific block is started based on the output of the circuit, and the flip-flop at the final stage of the specific block After the pulse output ends, the operation stops ,
In the current drive type level shifter, the operation is started by flowing the current of the constant current source of the level shifter, and the operation is stopped by not flowing the current of the constant current source,
In the voltage-driven level shifter, the operation is started by inputting the clock signal to be boosted to the input switching element of the level shifter, and the input of the clock signal to be boosted to the input switching element is cut off. A shift register characterized by stopping the above operation . A multi-stage flip-flop;
A shift register that boosts a clock signal having a smaller amplitude than the driving voltage of the flip-flop and applies the voltage to each flip-flop, and sequentially transmits an input pulse by the flip-flop in synchronization with the clock signal. In
Each flip-flop is divided into blocks of multiple,
The level shifter is provided for each block, and
Of the plurality of level shifters, at least one of the level shifters corresponding to the block that does not require the input of the clock signal to transmit the input pulse at that time is stopped.
A specific block of the blocks includes a plurality of the flip-flops, and includes a D flip-flop to which the clock signal boosted to a clock terminal is input as the flip-flop.
Based on the signal input to the specific block and the output signal of the flip-flop at the final stage of the specific block, the predetermined period is started when the specific block is in the predetermined period for performing the transmission. A latch circuit shown by performing an output to be stored and held until the end of the predetermined period,
The specific level shifter, which is the level shifter corresponding to the specific block, outputs a pulse output from the flip-flop at the final stage of the specific block at least from the start of pulse input to the specific block based on the output of the latch circuit. There line operation until after you exit,
In the current-driven type level shifter, the above operation is performed by passing a current of a constant current source of the level shifter,
In the voltage-driven level shifter, the operation is performed by inputting the clock signal to be boosted to an input switching element of the level shifter . 3. The boosted clock signal is supplied only to the flip-flop that needs to input the clock signal at that time in the block including a plurality of the flip-flops. Shift register. 4. The shift register according to claim 1, wherein all the flip-flops are the D flip-flops. The level shifter is a current driven level shifter having an input switching element. The shift register according to claim 1, further comprising a shift portion. 6. The level shifter includes an input signal control unit that stops the level shifter by giving a signal at a level that is cut off by the input switching element as an input signal to the level shift unit. The shift register described. 6. The shift register according to claim 5, wherein the level shifter includes a power supply control unit that stops power supply to the level shift unit and stops the level shifter. A plurality of pixels arranged in a matrix;
A plurality of data signal lines arranged in each row of each pixel;
A plurality of scanning signal lines arranged in each column of the pixels;
A scanning signal line drive circuit that sequentially applies scanning signals of different timings to the scanning signal lines in synchronization with a first clock signal having a predetermined period;
A data signal is sequentially applied in synchronization with a second clock signal having a predetermined period and a video signal indicating the display state of each pixel is supplied to each pixel of the scanning signal line to which the scanning signal is applied. In an image display device having a data signal line drive circuit that extracts and outputs to each data signal line,
At least one of the data signal line drive circuit and the scanning signal line drive circuit, that the first or the second clock signal includes a shift register according to any one of claims 1 to 7, the clock signal A characteristic image display device. 9. The image display device according to claim 8, wherein the data signal line driving circuit, the scanning signal line driving circuit, and each pixel are formed on the same substrate. 10. The image display device according to claim 8, wherein each of the data signal line driving circuit, the scanning signal line driving circuit, and each pixel includes a switching element made of a polycrystalline silicon thin film transistor. The data signal line driving circuit, the scanning signal line drive circuit and each pixel, an image according to any one of claims 8 to 10, characterized in that it includes a switching element fabricated at 600 ° following process temperature Display device.

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