JP3685686B2 - Imaging area sensor and imaging apparatus - Google Patents

Description

フリッカーを生じないためには、電荷蓄積時間（図５のａ−ｂ間の時間およびｃ−ｄ間の時間）が、次式（２）を満たすことが必要である。
【数２】

式（２）を満たす電荷蓄積時間の値は、照明の交流点灯周期の倍数（交流点灯周期を含む）であり、従ってフリッカー周期（フリッカー周波数成分の周期）の倍数（フリッカー周期を含む）である。つまり、フリッカー周期（交流点灯周期）が１／１００［ｓ］のときには、フリッカーを生じない電荷蓄積時間は、１／１００［ｓ］，２／１００［ｓ］，３／１００［ｓ］，…である。また、フリッカー周期（交流点灯周期）が１／１２０［ｓ］のときには、フリッカーを生じない電荷蓄積時間は、１／１２０［ｓ］，２／１２０［ｓ］，３／１２０［ｓ］，…である。ただし、これらフリッカーを生じない電荷蓄積時間は、映像信号のフレーム周期以下である必要がある。例えば、電荷蓄積時間がフリッカー周期（交流点灯周期）に等しいとき、図６のように、それぞれの画素に照射される光量は等しくなり、フリッカーを生じない。
【００７２】
制御手段５ｂは、フリッカーを検知しなかったときは、エリアセンサ１の動作モードを撮像モードに切り換える。また、制御手段５ｂは、フリッカーを検知したときは、エリアセンサ１の電荷蓄積時間をフリッカーの生じないフリッカー周期の倍数に設定し、エリアセンサ１の動作モードを撮像モードに切り換える。例えば、制御手段５ｂは、１００［Ｈｚ］のフリッカー周波数成分を検知するフリッカー検知手段５ａによってフリッカーを検知したとき、エリアセンサ１の電荷蓄積時間を、フリッカー周期と同じ１／１００［ｓ］に設定し、エリアセンサ１の動作モードを撮像モードに切り換える。
【００７３】
撮像モードにおいては、信号レベル検知手段５ｉは、積算手段６による映像信号の積算値と、あらかじめ設定された基準値範囲とを比較し、上記の積算値が基準値範囲よりも大きいときは露出過多であるとし、上記の積算値が基準値範囲よりも小さいときは露出不足であるとし、比較結果を制御手段５ｂに送る。制御手段５ｂは、露出過不足のときには、上記の積算値が基準値範囲となるように（映像信号のレベルが一定になるように）、エリアセンサ１の電荷蓄積時間を調整し、必要に応じて利得調整手段３の信号利得を調整する。
【００７４】
フリッカーが検知されなかったあとの撮像モードにおいては、電荷蓄積時間を連続的に調整することができるため、映像信号レベルの調整は、エリアセンサ１の電荷蓄積時間を調整すれば足り、電荷蓄積時間によって調整できないときにのみ、利得調整手段３の利得を調整する。
【００７５】
しかし、フリッカーが検知されたあとの撮像モードにおいては、電荷蓄積時間はフリッカー周期の倍数に設定する必要があり、電荷蓄積時間は離散的な値でしか調整することができない。このため、分解能の荒い露出制御となってしまい、電荷蓄積時間が切り換えられたときの画像が不自然なものになってしまう。
【００７６】
そこで、制御手段５ｂは、フリッカーが検知されたあとの撮像モードにおいては、図７および図８のようにエリアセンサ１の電荷蓄積時間Ｔおよび利得制御手段３の信号利得Ｇを制御する。図７はフリッカー周波数成分が１００［Ｈｚ］となる照明（商用周波数５０［Ｈｚ］の照明）下での電荷蓄積時間Ｔおよび信号利得Ｇの制御を説明する図であり、（ａ）は被写体照度Ｌに対するエリアセンサ１の電荷蓄積時間Ｔの設定値、（ｂ）は被写体照度Ｌに対する利得調整手段３の信号利得Ｇの設定値である。また、図８はフリッカー周波数成分が１２０［Ｈｚ］となる照明（商用周波数６０［Ｈｚ］の照明）下での電荷蓄積時間Ｔおよび信号利得Ｇの制御を説明する図であり、（ａ）は被写体照度Ｌに対するエリアセンサ１の電荷蓄積時間Ｔの設定値、（ｂ）は被写体照度Ｌに対する利得調整手段３の信号利得Ｇの設定値である。
【００７７】
フリッカーを生じる照明下での撮像モードでは、図７（ａ）および図８（ａ）のように、被写体照度Ｌに対して電荷蓄積時間Ｔを不連続の値でしか制御できないため、同じ値の電荷蓄積時間Ｔが設定される被写体照度Ｌの範囲内において、図７（ｂ）および図８（ｂ）のように、信号利得Ｇの値を連続的に変化させることによって不連続な露出制御を補い、映像信号のレベルを一定に保持する。図７および図８のように電荷蓄積時間Ｔおよび信号利得Ｇを制御することによって、被写体の明るさがいかなるときでも不連続のない一定レベルの映像信号を得ることができる。
【００７８】
フリッカーを生じる照明下での電荷蓄積時間Ｔおよび信号利得Ｇの設定値の組合せの一覧は、ＬＵＴ５ｈとして演算手段５内にあらかじめ設けられている。図９はＬＵＴ５ｈの構造図であり、（ａ）は商用周波数５０［Ｈｚ］の照明下でのＬＵＴ５ｈの構成、（ｂ）は商用周波数６０［Ｈｚ］の照明下でのＬＵＴ５ｈの構成である。制御手段５ｂは、信号レベル検知手段５ｉからの映像信号の積算値（積算手段６による積算値）と基準値範囲との比較結果に従って、ＬＵＴ５ｈを参照し、ＬＵＴ５ｈに従って電荷蓄積時間Ｔおよび信号利得Ｇを設定する。
【００７９】
例えば、フリッカー検知手段５ａが１００［Ｈｚ］のフリッカー周波数成分を検知するものであるとき、ＬＵＴ５ｈの初期参照アドレスをｎ＝４とすると、制御手段５ｂは、フリッカーを検知すると、ＬＵＴ５ｈのアドレスｎ＝４を参照し、エリアセンサ１の電荷蓄積時間Ｔを１／１００［ｓ］に設定するとともに、利得調整手段３の信号利得Ｇを５（最大値）に設定する。この初期設定において、映像信号の積算値が基準値範囲よりも大きければ、制御手段５ｂは、参照アドレスｎをデクリメントし（ｎ＝３）、ＬＵＴ５ｈのアドレスｎ＝３を参照し、利得調整手段３の信号利得Ｇを４に変更する。この設定においても、上記映像信号の積算値が基準値範囲よりも大きければ、制御手段５ｂは、参照アドレスｎをさらにデクリメントし（ｎ＝２）、ＬＵＴ５ｈのアドレスｎ＝２を参照し、利得調整手段３の信号利得Ｇを３に変更する。また、上記の初期設定において、映像信号の積算値が基準値範囲よりも小さければ、制御手段５ｂは、参照アドレスｎをインクリメントし（ｎ＝５）、ＬＵＴ５ｈのアドレスｎ＝５を参照し、利得調整手段３の信号利得Ｇを２（最小値）に変更するとともに、エリアセンサ１の電荷蓄積時間Ｔを２／１００［ｓ］に変更する。このように、図７および図８の電荷蓄積時間Ｔおよび信号利得Ｇの設定値を、図９のようにＬＵＴ５ｈとして演算手段５内に設けておくことにより、露出制御および信号利得制御が容易になる。
【００８０】
このように実施の形態１によれば、同じラインの全てのＰＤの電荷蓄積を同時に開始させるとともにラインごとに順次電荷蓄積を開始させ、同じラインの全てのＰＤに蓄積された電荷を同時に加算して読み出すことにより、それぞれのラインの加算された撮像信号をエリアセンサ１から順次出力させ、ラインごとの加算された映像信号からフリッカーを検知し、フリッカーを検知した場合には、電荷蓄積時間をフリッカー周期の倍数（フリッカー周期）に設定することにより、電荷蓄積タイミングが画素ごとに異なる撮像エリアセンサにおいてフレーム内に生じるフリッカーを検知でき、このフリッカーを除去することができる。
【００８１】
なお、信号レベル検知手段５ｉによる映像信号レベルの検知結果に従って、ＬＵＴ５ｈの参照アドレスをインクリメントまたはデクリメントする方法は、映像信号レベルの制御方法の一例であり、他の方法によってＬＵＴ５ｈを参照することも可能である。また、上記実施の形態１では、フリッカー検知モードにおいて、同じラインの全てのＰＤの蓄積電荷を加算して読み出したが、同じラインのＰＤの内の所定の複数個のＰＤの蓄積電荷を加算して読み出すようにしても、フリッカーを検知できる。また、利得調整手段３または前置信号処理手段２から出力されたアナログの映像信号（ラインごとの加算された映像信号）をフリッカー検知手段５ａに入力する構成とすることも可能であり、特定周波数検出手段５ｃ、比較手段５ｄをアナログ回路によって実現することも可能である。これらの場合には、フリッカー検知手段５ａにＡ／Ｄコンバータを設ける必要がある。
【００８２】
実施の形態２．
実施の形態２の撮像装置は、上記実施の形態１の撮像装置において、演算手段５の構成を変更したものである。図１０は本発明の実施の形態２の撮像装置における演算手段５の構成図である。なお、図１０において、図１と同じものには同じ符号を付してある。
【００８３】
図１０のように、実施の形態２の演算手段５は、フリッカー検知手段５ｊと、制御手段５ｂと、ＬＵＴ５ｈと、信号レベル検知手段５ｉとを有する。フリッカー検知手段５ｊは、特定周波数検出手段５ｃ，５ｋと、比較手段５ｄとによって構成される。
【００８４】
特定周波数検出手段５ｃは、ラインごとの加算された映像信号からフリッカー周波数成分（１００［Ｈｚ］または１２０［Ｈｚ］の周波数成分）を検出し、特定周波数検出手段５ｋは、上記の映像信号から上記フリッカー周波数成分以外の周波数成分を検出する。特定周波数検出手段５ｋは、例えば特定周波数検出手段５ｃ（図３参照）と同じようにＢＰＦおよび積算手段によって実現できる。
【００８５】
比較器５ｄは、特定周波数検出手段５ｃによって検出されたフリッカー周波数成分（第１の周波数成分）の値と、特定周波数検出手段５ｋによって検出されたフリッカー周波数成分でない周波数成分（第２の周波数成分）の値とを比較し、第１の周波数成分が第２の周波数成分よりも所定値以上大きいとき、フリッカーを検知したものとする。
【００８６】
このように実施の形態２によれば、フリッカー周波数成分（第１の周波数成分）を検出する特定周波数検出手段５ｃの他に、フリッカー周波数成分でない周波数成分（第２の周波数成分）を検出する特定周波数検出手段５ｋを設け、比較器５ｄにおいてそれぞれの波数成分の値を比較し、第１の周波数成分が第２の周波数成分よりも所定値以上大きいときフリッカーを検知したものとすることにより、フリッカー検知手段を簡単な構成で実現できる。
【００８７】
実施の形態３．
実施の形態３の撮像装置は、上記実施の形態１の撮像装置において、演算手段５の構成を変更したものである。図１１は本発明の実施の形態３の撮像装置における演算手段５の構成図である。なお、図１１において、図１と同じものには同じ符号を付してある。
【００８８】
図１１のように、実施の形態３の演算手段５は、フリッカー検知手段５ｍと、制御手段５ｂと、ＬＵＴ５ｈと、信号レベル検知手段５ｉとを有する。フリッカー検知手段５ｍは、特定周波数検出手段５ｃ，５ｎと、比較手段５ｄ，５ｐと、基準値設定手段５ｅとによって構成される。
【００８９】
特定周波数検出手段５ｃは、ラインごとの加算された映像信号から１００［Ｈｚ］のフリッカー周波数成分を検出し、特定周波数検出手段５ｎは、上記の映像信号から１２０［Ｈｚ］の周波数成分を検出する。
【００９０】
比較手段５ｄは、特定周波数検出手段５ｃによって検出された１００［Ｈｚ］のフリッカー周波数成分（第１のフリッカー周波数成分）の値と、基準値設定手段５ｅの基準値とを比較し、第１のフリッカー周波数成分が基準値よりも大きいとき、商用周波数５０［Ｈｚ］の照明によるフリッカー周期１／１００［ｓ］のフリッカーを検知したものとする。また、比較手段５ｐは、特定周波数検出手段５ｎによって検出された１２０［Ｈｚ］のフリッカー周波数成分（第２のフリッカー周波数成分）の値と、基準値設定手段５ｅの基準値とを比較し、第１のフリッカー周波数成分が基準値よりも大きいとき、商用周波数６０［Ｈｚ］の照明によるフリッカー周期１／１２０［ｓ］のフリッカーを検知したものとする。
【００９１】
この実施の形態３では、ＬＵＴ５ｈには、図９（ａ）の商用周波数５０［Ｈｚ］用のテーブル、および図９（ｂ）の商用周波数６０［Ｈｚ］用のテーブルが設けられている。制御手段５ｂは、フリッカー周期１／１００［ｓ］のフリッカーが検知されたときには、ＬＵＴ５ｈの商用周波数５０［Ｈｚ］用のテーブルを参照してエリアセンサ１の電荷蓄積時間および利得制御手段３の信号利得を設定し、フリッカー周期１／１００［ｓ］のフリッカーが検知されたときには、ＬＵＴ５ｈの商用周波数５０［Ｈｚ］用のテーブルを参照してエリアセンサ１の電荷蓄積時間および利得制御手段３の信号利得を設定する。
【００９２】
このように実施の形態３によれば、１００［Ｈｚ］のフリッカー周波数成分（第１のフリッカー周波数成分）を検出する特定周波数検出手段５ｃと、１２０［Ｈｚ］のフリッカー周波数成分（第２のフリッカー周波数成分）を検出する特定周波数検出手段５ｎと、第１のフリッカー周波数成分を基準値と比較する比較器５ｄと、第２のフリッカー周波数成分を基準値と比較する比較器５ｐとを設け、、第１のフリッカー周波数成分が基準値より大きいとき、フリッカー周期１／１００［ｓ］のフリッカーを検知したものとし、第２のフリッカー周波数成分が基準値より大きいとき、フリッカー周期１／１２０［ｓ］のフリッカーを検知したものとすることにより、簡単な構成で、商用周波数５０［Ｈｚ］の照明下で生じるフリッカーおよび商用周波数６０［Ｈｚ］の照明下で生じるフリッカーの両方を検知できるとともに、いずれの商用周波数によるフリッカーが生じているかを判別することができる。
【００９３】
実施の形態４．
上記実施の形態１の演算手段５は、マイコンなど用いて実現することができる。以下に説明する実施の形態４の撮像装置は、上記実施の形態１の撮像装置において、演算手段５をマイコンを用いて実現したものである。図１２は本発明の実施の形態４の撮像装置における演算手段５の構成図である。
【００９４】
図１１のように、実施の形態４のマイコンによる演算手段５は、ＣＰＵ５ｑと、ＲＯＭ５ｒとを有する。ＣＰＵ５ｑは、図１のフリッカー検知手段５ａ（基準値設定手段５ｅを除く）、制御手段５ｂ、および信号レベル検知手段５ｉに相当する。ＲＯＭ５ｒには、基準値設定手段５ｅによる基準値、およびＬＵＴ５ｈのデータが記録されている。また、ＲＯＭ５ｒには、フリッカー検知手段５ａによるフリッカー検知手順、信号レベル検知手段５ｉによる信号レベル検知手順、および制御手段５ｂによる制御手順のプログラムが記憶されている。
【００９５】
このように実施の形態４によれば、演算手段５をマイコンによって実現することにより、演算手段５を簡単な構成で実現できる。
【００９６】
実施の形態５．
上記実施の形態１のエリアセンサ１はＣＭＯＳにて構成されているため、エリアセンサ１に、前置信号処理手段２、利得調整手段３、Ａ／Ｄコンバータ４などの回路を内蔵させることも技術的に可能である。実施の形態５の撮像装置は、上記実施の形態１の撮像装置において、エリアセンサ１に上記の回路を内蔵させたものである。図１３は本発明の実施の形態５の撮像装置の構成図である。また、図１４は図１３のエリアセンサ１１の構成図である。図１３および図１４において、図１または図２と同じものには、同じ符号を付してある。
【００９７】
図１３のように、実施の形態５の撮像装置は、エリアセンサ１１と、演算手段５と、積算手段６と、信号処理手段８とを備えている。また、図１４のように、エリアセンサ１１は、画素アレイ１１ａと、垂直シフトレジスタ１ｑと、水平シフトレジスタ１ｒと、駆動パルス発生手段１ｔと、前置信号処理手段２と、利得調整手段３と、Ａ／Ｄコンバータ４と、レジスタファイル１１ｈと、入力端子１１ｉと、レジスタ値入力端子１１ｊと、出力端子１１ｋとを有する。画素アレイ１１ａは、図２のエリアセンサ１のＰＤ（１ａ，１ｂ，１ｃ，１ｄ，…）、増幅器（１ｅ，１ｆ，１ｇ，１ｈ，…）、リセット回路（１ｕ，１ｖ，１ｗ，１ｘ，…）、画素選択トランジスタ（１ｉ，１ｊ，１ｋ，１ｍ，…）、および列選択トランジスタ（１ｎ，１ｐ，…）に相当する。
【００９８】
入力端子１１ｉは、演算手段５の制御手段５ｂ（図１参照）に接続されている。制御手段５ｂは、入力端子１１ｉに制御信号を送ることによって、エリアセンサ１１の動作モードを撮像モードまたはフリッカー検知モードに切り換えるとともに、電荷蓄積時間を設定する。
【００９９】
出力端子１１ｉは、積算手段６、信号処理手段演算手段８、および演算手段４のフリッカー検知手段５ａ（図１参照）に接続されている。画素アレイ１１ａから出力された撮像信号は、前置信号処理手段２においてノイズ除去され、利得調整手段３において増幅され、Ａ／Ｄコンバータ４においてディジタル信号に変換され、出力端子１１ｉから積算手段６、信号処理手段演算手段８、およびフリッカー検知手段５ａに入力される。
【０１００】
レジスタファイル１１ｈは、利得調整手段３の信号利得値を設定するとともに、Ａ／Ｄコンバータ４にリファレンス電圧値を供給する。レジスタファイル１１ｈのレジスタ設定は、レジスタ値入力端子１１ｊから入力され、レジスタ値入力端子１１ｊは、演算手段５に接続されている。演算手段５は、利得調整手段３の信号利得を変えたいときは、その信号利得値をレジスタ値入力端子１１ｊに出力し、レジスタファイル１１ｈによって信号利得値を変化させる。
【０１０１】
【発明の効果】
以上説明したように、本発明の撮像装置によれば、電荷蓄積タイミングが光電変換素子ごとに異なる撮像エリアセンサにおいてフレーム内に生じるフリッカーを容易に検知でき、このフリッカーを除去することができるという効果がある。
【０１０３】
また、本発明の請求項１または２に記載の撮像装置によれば、フリッカー検知手段を簡単な構成で実現できるという効果がある。
【０１０４】
また、本発明の請求項３記載の撮像装置によれば、簡単な構成で、商用周波数５０［Ｈｚ］によるフリッカーおよび商用周波数６０［Ｈｚ］によるフリッカーの両方を検知することができるとともに、いずれの商用周波数によるフリッカーが生じているかを判別できるという効果がある。
【０１０５】
また、本発明の請求項４記載の撮像装置によれば、特定周波数検出手段を簡単な構成で実現することができるという効果がある。
【０１０６】
また、本発明の請求項５記載の撮像装置によれば、フリッカーを除去でき、かつ映像信号レベルをスムーズに調整できるという効果がある。
【０１０７】
また、本発明の請求項６記載の撮像装置によれば、フリッカーの生じない電荷蓄積時間および信号の利得値をＬＵＴ化しておくことで、フリッカーを検知したあとの第１のモードでの電荷蓄積時間および信号利得の制御が容易になるという効果がある。
【０１０８】
また、本発明の請求項８記載の撮像装置によれば、フリッカーの生じない電荷蓄積時間および信号の利得値をＬＵＴ化しておくことで、フリッカーを検知したあとの第１のモードでの電荷蓄積時間および信号利得の制御が容易になるという効果がある。
【図面の簡単な説明】
【図１】 本発明の実施の形態１の撮像装置の構成図である。
【図２】 図１のエリアセンサの構成図である。
【図３】 図１の特定周波数検出手段の構成図である。
【図４】 図２のエリアセンサ内のある１列のＰＤによる撮像信号に含まれるフリッカー周波数成分の波形図である。
【図５】 フリッカーが生じるときの図２のエリアセンサの電荷蓄積時間を説明する図である。
【図６】 フリッカーを生じないときの図２のエリアセンサの電荷蓄積時間を説明する図である。
【図７】 図１の撮像装置においてフリッカー周波数成分が１００［Ｈｚ］となる照明（商用周波数５０［Ｈｚ］の照明）下での電荷蓄積時間および信号利得の制御を説明する図である。
【図８】 図１の撮像装置においてフリッカー周波数成分が１２０［Ｈｚ］となる照明（商用周波数６０［Ｈｚ］の照明）下での電荷蓄積時間および信号利得の制御を説明する図である。
【図９】 図１のＬＵＴの構造図である。
【図１０】 本発明の実施の形態２の撮像装置における演算手段の構成図である。
【図１１】 本発明の実施の形態３の撮像装置における演算手段の構成図である。
【図１２】 本発明の実施の形態４の撮像装置における演算手段の構成図である。
【図１３】 本発明の実施の形態５の撮像装置の構成図である。
【図１４】 図１３のエリアセンサの構成図である。
【図１５】 ＣＣＤエリアセンサを備えた従来の撮像装置の構成図である。
【図１６】 ＣＣＤエリアセンサの原理図である。
【図１７】 ＣＣＤエリアセンサにおいてフリッカーを生じる原理を説明する図である。
【図１８】 ＣＣＤエリアセンサにおけるフリッカーの抑圧方法を説明する図である。
【図１９】 従来のＣＭＯＳエリアセンサの構成図である。
【図２０】 図１９のエリアセンサの走査を説明する図である。
【図２１】 図１９のエリアセンサにおいてフリッカーを生じる原理を説明する図である。
【図２２】 図１９のエリアセンサでフリッカーを生じているときのラインごとの信号レベルを示す図である。
【図２３】 図１９のエリアセンサによるフリッカーを生じた画面を示す図である。
【符号の説明】
１ エリアセンサ、 １ａ，１ｂ，１ｃ，１ｄ 光電変換素子（フォトダイオード）、 １ｅ，１ｆ，１ｇ，１ｈ 増幅器、 １ｉ，１ｊ，１ｋ，１ｍ，１ｎ，１ｐ トランジスタ、 １ｑ 垂直シフトレジスタ、 １ｒ 水平シフトレジスタ、 １ｓ 出力端子、 １ｔ 駆動パルス発生手段、 １ｕ，１ｖ，１ｗ，１ｘ リセット回路、 ２ 前置信号処理手段、 ３ 利得調整手段、 ４ Ａ／Ｄコンバータ、 ５ 演算手段、 ５ａ，５ｉ，５ｍ フリッカー検知手段、５ｂ 制御手段、 ５ｃ，５ｋ，５ｎ 特定周波数検出手段、 ５ｄ，５ｐ 比較手段、 ５ｅ 基準値設定手段、 ５ｆ ＢＰＦ、 ５ｇ 積算手段、 ５ｈ ＬＵＴ、 ５ｑ ＣＰＵ、 ５ｒ ＲＯＭ、 ６ 積算手段、 ７ 出力端子、 ８ 信号処理手段、 １１ エリアセンサ、 １１ａ 画素アレイ、 １１ｈ レジスタファイル、 １１ｉ 入力端子、 １１ｊ レジスタ値入力端子、 １１ｋ 出力端子。[0001]
BACKGROUND OF THE INVENTION
In the present invention, the charge accumulation timing at the time of imaging differs for each photoelectric conversion element, such as a MOS (Metal Oxide Semiconductor Device) area sensor and a CMOS (Complimentary Metal Oxide Semiconductor Device) area sensor. When an object is imaged under illumination that is AC-lit with a commercial power supply (frequency 50 [Hz] or 60 [Hz]), the above charge is related to an imaging area sensor capable of adjusting the image area and an imaging apparatus including the imaging area sensor. An imaging area sensor for detecting flicker that occurs when the accumulation time is not synchronized with the AC lighting cycle (frequency 1/100 [s] or 1/120 [Hz]) and removing the flicker, and the imaging area The present invention relates to an imaging apparatus using a sensor.
[0002]
[Prior art]
FIG. 15 is a configuration diagram of a conventional imaging apparatus including a CCD (Charge Coupled Device) area sensor. In FIG. 15, 13 is a CCD imaging area sensor, 14 is a front signal processing means, 15 is a gain adjustment means, 16 is a signal processing means, 17 is a first integrating means, 18 is a second integrating means, and 19 is a first integrating means. 3 is an integrating means, 20 is an iris, 21 is an iris driver, 22 is a timing generator (TG), and 23 is a computing means.
[0003]
The operation of the conventional imaging apparatus in FIG. 15 will be described below. The iris 20 controls the amount of light collected on the CCD area sensor 13 (performs exposure control). The CCD area sensor 13 is operated by the driving pulse output from the TG 22, converts the incident light image into an electric signal, and outputs it to the pre-signal processing means 14 as an image pickup image signal.
[0004]
FIG. 16 is a principle diagram of the CCD area sensor 13. The CCD area sensor 13 includes a plurality of photoelectric conversion elements (PD: Photo Diode) 24 arranged two-dimensionally, a plurality of CCD vertical registers 25 provided for each column of the PD 24, and a CCD horizontal register 26. Yes.
[0005]
The PD 24 accumulates the charge generated according to the amount of incident light for a predetermined time, transfers it to the corresponding CCD vertical register 25, and then starts accumulating the charge again. All the PDs 24 start charge accumulation at the same time, and transfer the accumulated charge as a signal amount to the CCD vertical register 25 at the same time. Accordingly, in the CCD area sensor 13, the charge accumulation time and the charge accumulation timing of all the PDs 24 are the same.
[0006]
The charge transferred from the PD 24 to the CCD vertical register 25 is transferred in the vertical direction as indicated by the arrow in FIG. 16 by the CCD vertical register 25, reaches the CCD horizontal register 26, and is transferred in the horizontal direction by the CCD horizontal register 26 for imaging. Output as a signal. Since the CCD vertical register 25 and the CCD horizontal register 26 are completely shielded from light, in the CCD area sensor 13, the charge accumulation time and the charge accumulation timing of all the PDs 24 can be made the same.
[0007]
In this manner, the CCD area sensor 13 captures one frame (corresponding to one captured image) for each frame period by accumulating charges every charge accumulation time. In the CCD area sensor 13, the above-described charge accumulation time is the same as the frame period (time interval for imaging one frame), except for the case where an electronic shutter described later is caused to function. Note that the above-described frame corresponds to a captured image, and is different from a frame of an NTSC (National Television System Committee) video signal. The above frame corresponds to a field in an NTSC video signal. Therefore, the frame period is 1/60 [s] in the NTSC (National Television System Committee) system.
[0008]
In FIG. 15, the front signal processing means 14 removes noise from the image pickup signal of the CCD area sensor 13 by processing such as correlated double sampling and sends it to the gain control means 15 and the first integrating means 17 as a video signal. The first integrating means 17 integrates the video signal from the pre-signal processing means 14 every frame or every several frames, and sends a control signal to the iris driver 21 so that this integrated value becomes constant. Open and close.
[0009]
The gain adjusting means 15 amplifies the video signal from the front signal processing means 14 and sends it to the signal processing means 16, the second integrating means 18, and the third integrating means 19. The signal processing unit 16 performs signal processing such as image quality adjustment processing (for example, white balance adjustment, gamma correction, enhancement correction (contour correction)) and conversion processing on the video signal input from the gain adjustment unit 15, and Encode to get the required signal format. The second integrating means 18 integrates the video signal from the gain adjusting means 15 every one frame or every several frames, and adjusts the signal gain of the gain adjusting means 15 so that the integrated value becomes constant. Normally, the level of the video signal input to the gain adjusting unit 15 is adjusted to a certain level in advance by exposure control by the iris 20, so that the signal gain of the gain adjusting unit 15 is also constant, but the illuminance of the subject is low. Thus, when the necessary exposure amount is not obtained even when the iris 20 is fully opened, the video signal is amplified by the gain adjusting means 15 so that a video signal of a certain level can be obtained.
[0010]
The third integrating means 19 is provided for detecting flicker, integrates the video signal for each frame, and outputs the integrated value to the calculating means 23. The calculation means 23 detects whether or not flicker is generated based on the integrated value, and when flicker is detected, sends a control signal to the TG 22 to change the charge accumulation time of the CCD area sensor 13, Suppresses flicker.
[0011]
The flicker detection procedure will be described below. FIG. 17 is a diagram for explaining the principle of causing flicker in the CCD area sensor 13. The frequency of illumination such as a fluorescent lamp that is AC-lit with a commercial power supply is twice the commercial frequency as shown in FIG. That is, when the commercial frequency is 50 [Hz], the lighting frequency is 100 [Hz], and the AC lighting cycle (interval lighting interval time) is 1/100 [s]. When the commercial frequency is 60 [Hz], the lighting frequency is 120 [Hz], and the AC lighting cycle is 1/120 [s]. FIG. 17 shows a case where an image is captured with a charge accumulation time of 1/60 [s] under illumination with a commercial frequency of 50 [Hz]. In FIG. 17, the charge accumulation time is between ab and cd. At b, the accumulated charge is transferred, and charge accumulation for the next frame is started from c. At this time, the amount of illumination light between ab and cb (the area of the portion indicated by the hatched portion in FIG. 17) is different. Therefore, the brightness differs between the captured images between ab and cb. Therefore, it becomes an imaging signal having a different signal level for each frame, and flicker occurs. When imaging is performed with a charge accumulation time of 1/60 [s] under illumination with an alternating lighting frequency of 100 [Hz], flicker of 20 [Hz] occurs.
[0012]
The calculating means 23 determines that flicker has occurred when the frequency component of 20 [Hz] is detected from the integrated value for each frame of the video signal by the third integrating means 19.
[0013]
In the imaging apparatus of FIG. 15, the time constant of the feedback that controls the iris 20 from the first integrating means 17 and the feedback that controls the gain adjusting means 15 from the second integrating means 18 is used to prevent hunting (oscillation). , It is set sufficiently longer than the above 20 [Hz]. For this reason, it is difficult to sufficiently suppress flicker by the above feedback means. Therefore, in the imaging apparatus of FIG. 15, flicker is suppressed as follows.
[0014]
If it is determined that the flicker has occurred, the calculation means 23 sends a control signal to the TG 22 and changes the charge accumulation time of the CCD area sensor 13 by the TG 22. When the 20 [Hz] flicker is detected, the charge accumulation time is changed to 1/100 [s]. The CCD area sensor 13 has a function of an electronic shutter that changes the charge accumulation time by discharging the accumulated charges of all the PDs 24 once in the middle of charge accumulation and starting charge accumulation again after that. When the control signal is input from the calculation unit 23, the TG 22 causes the electronic shutter to function and outputs a drive pulse for setting the charge accumulation time to 1/100 [s] to the CCD area sensor 13. As a result, the charge accumulation time of the CCD area sensor 13 is changed to 1/100 [s] as shown in FIG. In the charge accumulation time of 1/100 [s], the amount of light between a and b and c and d in FIG. 18 is the same, so flicker does not occur.
[0015]
As described above, in an imaging apparatus using a CCD area sensor, flicker is detected from the integrated value of one frame of a video signal, and when flicker occurs, the charge accumulation time is set to the AC lighting cycle (1/100 [ s] or 1/120 [s]) to suppress flicker.
[0016]
However, in recent years, imaging devices for mobile applications (PDA: Personal Digital Assistants) aiming at low power consumption often use an imaging area sensor called a CMOS area sensor or a MOS area sensor instead of the CCD area sensor described above. . Unlike the CCD area sensor, the CMOS area sensor and the MOS area sensor have different charge accumulation timings for each photoelectric conversion element. Therefore, in the above-described CCD area sensor flicker detection method and suppression method, flicker detection and suppression are performed. I cannot suppress it.
[0017]
The principle of the CMOS area sensor will be described. The principle of the MOS area sensor is the same. FIG. 19 is a configuration diagram of a CMOS area sensor. In FIG. 19, 1a, 1b, 1c, and 1d are photoelectric conversion elements (PD), 1e, 1f, 1g, and 1h are amplifiers, 1i, 1j, 1k, and 1m are pixel selection transistors, 1n and 1p are column selection transistors, and 1q. Is a vertical shift register, 1y is a horizontal shift register, 1s is an output terminal for an imaging signal, 1z is a drive pulse generating means, 1u, 1v, 1w, and 1x are reset circuits, and 10 is a CMOS area sensor.
[0018]
The area sensor 10 in FIG. 19 includes M × N PDs (1a, 1b, 1c, 1d,...) And M × N amplifiers (1e, 1f, 1g,. 1h,...), M × N reset circuits (1u, 1v, 1w, 1x,...), M × N pixel selection transistors (1i, 1j, 1k, 1m,...), N Column selection transistors (1n, 1p,...), Drive pulse generating means 1z, vertical shift register 1q, horizontal shift register 1y, and output terminal 1s are provided. In the area sensor of FIG. 19, the PD 1a, the amplifier 1e, the reset circuit 1u, and the pixel selection transistor 1i constitute one pixel. The area sensor 10 is composed of M × N pixels configured as described above. The PDs 1a, 1b, 1c, 1d,... Generate charges corresponding to the amount of incident light. These charges are accumulated in the capacitance between the PDs 1a, 1b, 1c, 1d,... And the amplifiers 1e, 1f, 1g, 1h,. The vertical shift register 1q selects ON / OFF of the pixel selection transistors 1i, 1j, 1k, 1m,..., And the horizontal shift register 1y selects ON / OFF of the column selection transistors 1n, 1p,. The drive pulse generator 1z outputs drive pulses to the vertical shift register 1q and the horizontal shift register 1y, and controls the readout operation of the imaging signal by the charge accumulated in the PD and the reset operation of the PD.
[0019]
In the area sensor 10 configured as described above, PD1a, 1b,..., 1c, 1d,... Are sequentially selected in the order of the arrows in FIG. Are sequentially read out as imaging signals and output from the output terminal 1s. For example, by turning on the pixel selection transistors 1i, 1j,... Of the first line by the vertical shift register 1q and turning on the column selection transistor 1n of the first column by the horizontal shift register 1y, the first column of the first line is turned on. The charge of PD1a is read out through transistors 1i and 1n.
[0020]
Further, in the area sensor 10, as described above, the readout timing differs for each PD, but in order to make the charge accumulation time of all PDs the same, the horizontal shift register 1y and the vertical shift register 1q use the arrows in FIG. In this order, reset circuits 1u, 1v,..., 1w, 1x,... Are sequentially selected, and PDs 1a, 1b,..., 1c, 1d,. Start charge accumulation.
[0021]
In an imaging apparatus including an imaging area sensor having different charge accumulation timing for each PD, such as the CMOS area sensor 10 and the MOS area sensor described above, the CCD area sensor in which the charge accumulation timings of all PDs are the same. Unlikely, flicker occurs as follows.
[0022]
FIG. 21 is a diagram for explaining the principle of causing flicker in the area sensor 10. As described above, in the area sensor 10, the charge accumulation timing is different for each pixel. Therefore, the charge accumulation start timing and completion timing of each line (row) of the area sensor 10 are also different as shown in FIG. 21. . Therefore, the image signal has a signal level different for each line as shown in FIG. As a result, as shown in FIG. 23, the luminance becomes uneven in the vertical direction in the image of one frame, and flicker appears. In FIG. 23, a portion A is a low luminance portion, and a portion B is a high luminance portion.
[0023]
[Problems to be solved by the invention]
As described above, in a conventional imaging device including an imaging area sensor such as a CMOS area sensor or a MOS area sensor whose charge accumulation timing is different for each pixel, the AC lighting frequency of the illumination and the charge accumulation time of the imaging area sensor are synchronized. Otherwise, flicker occurs as luminance unevenness in the frame as shown in FIG.
[0024]
However, in an imaging device using an imaging area sensor with different charge accumulation timing for each pixel, flicker occurs as uneven luminance in the frame, and therefore, unlike an imaging device using a CCD area sensor, for each frame of the video signal. There has been a problem that the flicker cannot be detected from the integrated value.
[0025]
The present invention has been made to solve such a conventional problem. Flickers generated in a frame can be detected in an imaging area sensor having different charge accumulation timing for each pixel, and the flicker can be removed. An object is to provide an imaging area sensor and an imaging apparatus.
[0026]
[Means for Solving the Problems]
In order to achieve the above object, imaging according to claim 1 of the present invention apparatus Resets the photoelectric conversion elements individually, starts charge accumulation, reads out the charges accumulated in the photoelectric conversion elements individually and outputs them to the outside, and drives the reset means and the readout means Driving means for controlling the charge accumulation start timing and readout timing of each photoelectric conversion element; Possess , Image area sensor that can adjust the charge accumulation time of photoelectric conversion elements, because the charge accumulation timing at the time of imaging differs for each photoelectric conversion element And flicker detection means for detecting flicker from the video signal, and control means for controlling the drive means, When the driving means is in the first mode, it starts to sequentially accumulate charges for each photoelectric conversion element, sequentially reads the accumulated charges, sequentially outputs signals from the respective photoelectric conversion elements, Sometimes, charge accumulation of a plurality of photoelectric conversion elements on the same line (including all photoelectric conversion elements on the same line) is started at the same time, and charge accumulation is sequentially started for each line, and accumulated in the plurality of photoelectric conversion elements. The added charges are added and read at the same time, and the added signal of each line is sequentially output. When there are two drive modes and the control means operates the imaging area sensor in the second mode and flicker is detected, the charge accumulation time of the imaging area sensor is set to a multiple of the flicker period ( Including the flicker cycle), the imaging area sensor is operated in the first mode, and the flicker detection means detects the flicker frequency component from the video signal in the second mode; Comparing means for comparing the signal level of the flicker frequency component with a preset reference value is assumed, and flicker is detected when the flicker frequency component is greater than the reference value. It is characterized by that.
[0029]
Claims of the invention 2 In the imaging apparatus described above, the flicker detection unit is not a flicker frequency component from the first frequency detection unit that detects a first frequency component that is a flicker frequency component from the video signal in the second mode. A second frequency detecting means for detecting the second frequency component; and a comparing means for comparing the signal level of the first frequency component and the signal level of the second frequency component, wherein the first frequency component is The flicker is detected when it is larger than the second frequency component by a predetermined value or more.
[0030]
Claims of the invention 3 In the described imaging apparatus, the flicker detection unit detects a first flicker frequency component from the video signal in the second mode, and detects a second flicker frequency component from the video signal. Second frequency detecting means, first comparing means for comparing the signal level of the first flicker frequency component with a preset reference value, the signal level of the second frequency component and the reference value And a second comparison means for comparing the first and second flicker frequency components when the first flicker frequency component is greater than the reference value, and the second flicker frequency component is the reference frequency. When the value is larger than the value, flicker of the second frequency is detected.
[0031]
Claims of the invention 4 The described imaging apparatus is characterized in that the frequency detection means includes a band-pass filter that allows only a flicker frequency component to pass, and an integration means that integrates output signals of the band-pass filter.
[0032]
Claims of the invention 5 The imaging apparatus according to the present invention has a gain adjustment means for adjusting the gain of the video signal by the imaging area sensor, an integration means for integrating the gain-adjusted video signal, and an integrated value of the video signal within a predetermined range. Signal level determining means for determining whether or not the integrated value of the video signal is within the predetermined range in the imaging operation in the first mode when flicker is detected. Thus, the charge accumulation time and the signal gain of the gain adjusting means are controlled.
[0033]
Claims of the invention 6 The described imaging apparatus further includes a lookup table that lists combinations of charge accumulation times and signal gains that can be set in the imaging operation in the first mode when flicker is detected, and the control means includes: In the imaging operation in the first mode when flicker is detected, the charge accumulation time and the signal gain are controlled with reference to the lookup table.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a configuration diagram of an imaging apparatus according to Embodiment 1 of the present invention. In FIG. 1, 1 is an area sensor (imaging area sensor), 2 is a pre-signal processing means, 3 is a gain adjusting means, 4 is an A / D converter, 5 is an arithmetic means, 5a is a flicker detection means, and 5b is a control means. 5c is a specific frequency detecting means, 5d is a comparing means, 5e is a reference value setting means, 5h is an LUT (Look Up Table), 5i is a signal level detecting means, 6 is an integrating means, 7 is an output terminal, 8 is a signal processing Means.
[0035]
[Area sensor 1]
The area sensor 1 is a CMOS area sensor that captures an incident light image, converts it into an electrical signal, and outputs the captured image signal to the front signal processing means 2. FIG. 2 is a configuration diagram of the area sensor 1. 2, the same components as those in FIG. 19 are denoted by the same reference numerals, 1a, 1b, 1c, and 1d are photoelectric conversion elements (PD), 1e, 1f, 1g, and 1h are amplifiers, 1i, 1j, 1k, 1m is a pixel selection transistor, 1n and 1p are column selection transistors, 1q is a vertical shift register, 1r is a horizontal shift register, 1s is an output terminal of an imaging signal, 1t is a drive pulse generating means, 1u, 1v, 1w and 1x are reset Circuit.
[0036]
The area sensor 1 of the first embodiment of FIG. 2 is the same as the conventional CMOS area sensor of FIG. 19 except that the horizontal shift register 1y and the drive pulse generating means 1z are respectively the horizontal shift register 1r and the drive pulse generating means 1t. In addition to the imaging mode that sequentially reads out the individual charges, the charges of all PDs on the same line are added and read simultaneously, and the operation is performed in the flicker detection mode in which the added charges are sequentially read for each line. . In the imaging mode, the charge accumulation timing is different for each PD, but in the flicker detection mode, the charge accumulation timing of all PDs on the same line is the same, and the charge accumulation timing is different for each line.
[0037]
As shown in FIG. 2, the area sensor 1 according to the first embodiment includes M × N PDs (1a, 1b, 1c, 1d,...) And M × N (M, N are integers of 3 or more). An amplifier (1e, 1f, 1g, 1h,...), M × N reset circuits (1u, 1v, 1w, 1x,...), And M × N pixel selection transistors (1i, 1j, 1k, 1m). ,..., N column selection transistors (1n, 1p,...), Drive pulse generating means 1t, vertical shift register 1q, horizontal shift register 1r, and output terminal 1s.
[0038]
Each of the PDs 1a, 1b, 1c, 1d,... Accumulates charges corresponding to the amount of incident light during the charge accumulation time. The amplifiers 1e, 1f, 1g, 1h,... Amplify signals based on the accumulated charges of the PDs 1a, 1b, 1c, 1d,... (Convert the charges into voltage signals). The reset circuits 1u, 1v, 1w, 1x,... Reset the PDs 1a, 1b, 1c, 1d,... (Throw away the charges accumulated in the PDs) and start charge accumulation. The reset timing by the reset circuit is the charge accumulation start timing of the PD. The charge accumulation time of the PD is from the charge accumulation start timing (reset timing) to the charge read timing. The charge accumulation start timing differs for each PD in the imaging mode and varies for each line in the flicker detection mode, but the charge accumulation time is the same for all PDs.
[0039]
The horizontal shift register 1r sequentially selects the columns in the imaging mode in accordance with the drive pulse from the drive pulse generating means 1t, turns on the column selection transistor (1n or 1p) of the selected column, and in the flicker detection mode, selects all the columns. The column selection transistors (1n and 1p) are turned on simultaneously. The vertical shift register 1q sequentially selects one line in accordance with the drive pulse from the drive pulse generator 1t, and turns on all the pixel selection transistors (1i and 1j or 1g and 1h) on the selected line. Further, the horizontal shift register 1r and the vertical shift register 1q sequentially select one reset circuit in the imaging mode in accordance with the drive pulse from the drive pulse generating means 1t, sequentially reset the PD by the selected reset circuit, and flicker In the detection mode, all reset circuits on the same line are selected simultaneously and reset circuits on different lines are sequentially selected, and all the reset circuits on the selected line simultaneously reset the PD on that line.
[0040]
The drive pulse generator 1t supplies a drive pulse to the horizontal shift register 1r and the vertical shift register 1q in accordance with a control signal from the calculation unit 5 to operate the area sensor 1 in the imaging mode or flicker detection mode. The drive pulse generator 1t adjusts the charge accumulation time of the PD by adjusting the PD reset timing with respect to the read timing.
[0041]
As described above, in the area sensor 1 of the first embodiment, the charge accumulation timing at the time of imaging differs for each photoelectric conversion element, and in the CMOS imaging area sensor that can adjust the charge accumulation time of the photoelectric conversion element, it differs for each photoelectric conversion element. In addition to the imaging mode (first mode) in which charge accumulation starts sequentially at the timing, the charges accumulated in the respective photoelectric conversion elements are individually read out sequentially, and are sequentially output as imaging signals of the respective photoelectric conversion elements. The charge accumulation of all the photoelectric conversion elements in the line is started at the same time, and the charge accumulation is started at different timings for each line. The charges accumulated in the plurality of photoelectric conversion elements are simultaneously read and added, and the added charges are added. Operates in flicker detection mode (second mode) in which each line is sequentially output as an image pickup signal In which was to so that.
[0042]
[Pre-Signal Processing Unit 2, Gain Adjustment Unit 3, A / D Converter 4]
In FIG. 1, the front signal processing means 2 removes noise such as switching noise of transistors included in the imaging signal input from the area sensor 1, and sends it to the gain adjustment means 3. The gain control means 3 amplifies the video signal input from the pre-signal processing means 2 with a signal gain corresponding to the control signal from the calculation means 5 and sends it to the A / D converter 4. The A / D converter 4 converts the analog video signal input from the gain control means 3 into a digital signal, and sends it to the calculation means 5 (the flicker detection means 5a), the integration means 6, and the signal processing means 8.
[0043]
[Integrating means 6, signal processing means 8]
The integrating means 6 integrates the video signal every frame or every several frames, and sends the integrated value of this video signal to the computing means 5 (signal level detecting means 5i). The signal processing means 8 performs signal processing such as image quality adjustment processing and conversion processing on the video signal input from the A / D converter 4, encodes it into a video signal of a necessary format, and outputs it from the output terminal 7. For example, the white balance of the input video signal is adjusted, image quality adjustment such as gamma correction and enhancement correction (contour correction) is performed, the video signal is encoded into a required format, and output from the output terminal 7.
[0044]
[Calculation means 5]
The calculation means 5 includes flicker detection means 5a, control means 5b, LUT (Look Up Table) 5h, and signal level detection means 5i.
[0045]
[Flicker detection means 5a]
The flicker detection means 5a detects whether or not flicker occurs based on the video signal added for each line input from the A / D converter 4 of the signal processing means in the flicker detection mode. The detection result is sent to the control means 5b. For example, as shown in FIG. 1, the flicker detection means 5a includes a specific frequency detection means 5c, a comparison means 5d, and a reference value setting means 5e.
[0046]
[Specific frequency detection means 5c]
The specific frequency detection means 5c detects only the flicker frequency component (the frequency component included in the video signal when flicker occurs) from the video signal added for each line, and sends this flicker frequency component to the comparison means 5d. The flicker frequency component is a frequency component of 100 [Hz] under illumination at a commercial frequency of 50 [Hz], and a frequency component of 120 [Hz] under illumination at a commercial frequency of 60 [Hz].
[0047]
The specific frequency detecting means 5c can be realized by a BPF (Band Pass Filter) 5f and an integrating means 5g as shown in FIG. 3, for example. The BPF 5f passes only the flicker frequency component (frequency component of 100 [Hz] or 120 [Hz]) from the input video signal and sends it to the integrating means 5g. The integrating means 5g integrates the above flicker frequency component, for example, for one frame period, and sends the integrated value of this flicker frequency component to the comparing means 5d.
[0048]
[Reference value setting means 5e, comparison means 5d]
The reference value setting unit 5e supplies a preset reference value to the comparison unit 5d. The comparing means 5d compares the value of the flicker frequency component detected by the specific frequency detecting means 5c with the reference value, and if the flicker frequency component is larger than the reference value, it is assumed that the flicker is detected. If is less than the reference value, it is assumed that flicker has not been detected, and the detection result is sent to the control means 5b.
[0049]
[Signal level detection means 5i]
The signal level detection means 5i detects the level of the video signal by determining whether or not the integrated value of the video signal input from the integration means 6 is within a preset reference value range, and the detection result Is sent to the control means 5b.
[0050]
[Control means 5b]
The control means 5b controls the operation mode (imaging mode or flicker detection mode) and charge accumulation time of the area sensor 1 and the signal gain of the gain adjusting means 3. The control means 5b operates the area sensor 1 in the flicker detection mode, detects whether or not flicker is generated by the flicker detection means 5a, and then switches the area sensor 1 to the imaging mode. If flicker does not occur, in the imaging mode, the control means 5b continuously adjusts the charge accumulation time according to the detection result of the video signal level by the signal level detection means 5i, thereby setting the video signal level within a predetermined range. The signal level is adjusted by adjusting the signal gain of the gain adjusting means 3 only when the signal level cannot be adjusted by the charge accumulation time. In the imaging mode after detecting flicker, the control unit 5b sets the charge accumulation time of the area sensor 1 to a multiple (including the flicker period) of the flicker period (= AC lighting period by the commercial power source), The signal level is adjusted by adjusting the signal gain of the gain adjusting means 3.
[0051]
[LUT5h]
In the LUT 5h, combinations of the setting values of the charge accumulation time of the area sensor 1 and the setting value of the signal gain of the gain adjusting means 3 in the imaging mode after detecting flicker are tabulated in advance, and after detecting flicker In the imaging mode, the control means 5b refers to the LUT 5h, sets the charge accumulation time of the area sensor 1 and the signal gain of the gain adjustment means 3, and determines the charge accumulation time and signal according to the level of the detected video signal. Change the gain.
[0052]
[Operation in imaging mode of area sensor 1]
The operation of the area sensor 1 in the imaging mode will be described below with reference to FIG. The drive pulse generator 1t controls the horizontal shift register 1r and the vertical shift register 1q when a control signal for operating in the imaging mode is input from the controller 5b of the calculator 5, and the area sensor 1 is described below. To operate in the imaging mode.
[0053]
If the time (timing) is t, and the timing at which charge accumulation is started after the PD1a in the first column of the first line is reset is t = 0, the PD1b is reset at t = ΔT (> 0) in the imaging mode. Then, charge accumulation is started, and thereafter, at t = 2ΔT, 3ΔT,..., (N−1) ΔT, the PDs in the third and subsequent columns of the first line are sequentially reset, and the first column of the second line at t = NΔT. PD1c is reset, and PD1d is reset at t = (N + 1) ΔT. Hereinafter, t = (N + 2) ΔT, (N + 3) ΔT,..., (2N−1) ΔT, 2NΔT,. The PDs in the third column of the second line to the Nth column of the Mth line are sequentially reset. The PD1a in the first column of the first line is reset again after the PD in the Nth column of the Mth line is reset.
[0054]
Here, if the frame period of the video signal is Tf and the charge accumulation time in the imaging mode of the area sensor 1 (the same time for all PDs) is T,
M × N × ΔTa ≦ Tf
T ≦ Tf
It is.
[0055]
Along with the above reset operation, the following read operation is performed. First, when t = T, the pixel selection transistors 1i, 1j,... On the first line are turned on, and the column selection transistor 1n is turned on, and the charge accumulated in the PD 1a between t = 0 and t = T The imaging signal is read out and output from the output terminal 1s via the transistors 1i and 1n, and then the column selection transistor 1n is turned off. Next, when t = ΔT + T, the column selection transistor 1p is turned on, and an imaging signal based on the electric charge accumulated in the PD 1b between t = ΔT and t = ΔT + T is read and output through the transistors 1j and 1p. The column selection transistor 1p is turned off. Thereafter, in the same manner, at t = 2ΔT + T, 3ΔT + T,..., (N−1) ΔT + T, the imaging signals of the PDs in the third to Nth columns of the first line are sequentially read out, and the PD in the Nth column. Are read out, the pixel selection transistors 1i, 1j,... On the first line are turned off.
[0056]
Next, when t = NΔT + T, the pixel selection transistors 1k, 1m,... On the second line are turned on, and the column selection transistor 1n is turned on, and accumulated in PD1c between t = N × ΔT and t = NΔT + T. The imaging signal due to the charged charges is read, and the column selection transistor 1n is turned off. Next, when t = (N + 1) ΔT + T, the column selection transistor 1p is turned on, and the imaging signal based on the charge accumulated in the PD 1d is read out during the time t = (N + 1) ΔT to t = (N + 1) ΔT + T. The column selection transistor 1p is turned off. Hereinafter, in the same manner, in the case of t = (N + 2) ΔT + T, (N + 3) ΔT + T,..., (2N−1) ΔT + T, 2NΔT + T,. The imaging signals of the PD in the Nth column of the line are sequentially read out. The imaging signal of the PD1a in the first column of the first line is read again after the imaging signal of the PD in the Nth column of the Mth line is read out. As described above, in the imaging mode, M × N imaging signals of PD 1a, 1b, 1c, 1d,... Are sequentially read out and output for each frame period Tf.
[0057]
[Operation in Flicker Detection Mode of Area Sensor 1]
The operation of the area sensor 1 in the flicker detection mode will be described below with reference to FIG. The drive pulse generator 1t controls the horizontal shift register 1r and the vertical shift register 1q when a control signal for operating in the flicker detection mode is input from the controller 5b of the calculator 5 and the area sensor 1 is set as follows. Operate in imaging mode as described.
[0058]
If the time (timing) is t, and the timing at which the N PDs 1a, 1b,... On the first line are simultaneously reset and charge accumulation starts is t = 0, in the flicker detection mode, t = ΔU (> 0) , The N PDs 1c, 1d,... Of the second line are simultaneously reset to start charge accumulation, and thereafter the third line at t = 2ΔU, 3ΔU,..., (M−1) ΔU in the same manner. The N PDs on the Mth line are reset sequentially. The PDs 1a, 1b,... On the first line are reset again after the PD on the Mth line is reset.
[0059]
In addition to the above-described reset operation for simultaneously resetting all PDs on the same line, the following readout operation is performed in which the imaging signals of all PDs on the same line are added and output as imaging signals for each line. Let U be the charge accumulation time in the flicker detection mode of the area sensor 1 (the same time for all PDs). First, when t = U, the pixel selection transistors 1i, 1j,... On the first line are turned on, and all the column selection transistors 1n, 1p,. The image signals of the N PDs 1a, 1b,... In the first line due to the charged charges are simultaneously added and read out as indicated by the bold arrows in FIG. 2, and output from the output terminal 1s as the image signals of the first line. After that, the pixel selection transistors 1i, 1j,... And the column selection transistors 1n, 1p,.
[0060]
Next, when t = ΔU + U, the pixel selection transistors 1k, 1m,... On the second line are turned on and all the column selection transistors 1n, 1p,... Are turned on, and between t = ΔU to t = ΔU + U. The image signals of N PDs 1c, 1d,... In the second line due to the accumulated charges are simultaneously added and read out, and output from the output terminal 1s as the image signal of the second line, and then the pixel selection transistor 1k. , 1m,... And column selection transistors 1n, 1p,.
[0061]
Thereafter, in the same manner, at t = 2ΔU + U, 3ΔU + U,..., (M−1) ΔU + T, the N PD imaging signals of the third to Mth lines are simultaneously added and sequentially read out. The image signals are sequentially output from the output terminal 1s as image signals of the line to the Mth line.
[0062]
Here, the charge accumulation time U in the flicker detection mode is, for example, the same as the charge accumulation time T in the imaging mode. Further, ΔU is an output time interval of the added image pickup signal for each line, and ΔT = NΔT, for example, when ΔT is used as the output time interval of the image pickup signal for each PD in the image pickup mode. The charge accumulation time U in the flicker detection mode needs to be not a multiple of the AC lighting cycle (including the AC lighting cycle) by the commercial power source in order to detect flicker. That is, it is not necessary to be a multiple of AC lighting cycle 1/100 [s] under illumination at commercial frequency 50 [Hz], and AC lighting cycle 1/120 [s] under illumination at commercial frequency 60 [Hz]. It must be not a multiple. Further, for example, U = T / N and ΔU = ΔT, and the frame period Tf can be shortened to 1 / N in the imaging mode.
[0063]
[Operations of Pre-Signal Processing Unit 2, Gain Adjustment Unit 3, and A / D Converter 4]
The imaging signal output from the area sensor 1 in the imaging mode or the flicker detection mode is subjected to noise removal such as switching noise of the transistor of the area sensor 1 in the pre-signal processing means 2 and sent to the gain adjustment means 3 as a video signal. The gain adjustment means 3 amplifies the signal, sends it to the A / D converter 4, converts it to a digital signal in the A / D converter 4, and calculates the flicker detection means 5 a (in the flicker detection mode) of the calculation means 5, and the integration means 6. , And the signal processing means 8.
[0064]
[Operation of Signal Processing Unit 8 and Integration Unit 6]
The digital video signal is subjected to signal processing such as image quality adjustment processing (for example, white balance adjustment, gamma correction, enhancement correction, etc.) and conversion processing in the signal processing means 8, and is encoded into a video signal of a necessary format. , Output from the output terminal 7. The integrating means 6 integrates the video signal for one frame or several frames, and sends the integrated value to the calculating means 5.
[0065]
[Flicker detection operation]
First, the control means 5b sends a control signal for operating in the flicker detection mode to the drive pulse generating means 1t of the area sensor 1 to operate the area sensor 1 in the flicker detection mode. The imaging signal output from the area sensor 1 and added for each line is converted into a digital signal by the A / D converter 4 via the pre-signal processing means 2 and the gain adjustment means 3, and the flicker detection means 5a is specified. Input to the frequency detection means 5c.
[0066]
When flicker occurs in the area sensor 1, a component having the same frequency as the AC lighting frequency of illumination is included in the imaging signal. Hereinafter, this frequency component is referred to as a flicker frequency. In other words, since the AC lighting frequency of illumination with a commercial frequency of 50 [Hz] is 100 [Hz], when flicker occurs under this illumination, the imaging signal includes a flicker frequency component of 100 [Hz]. Further, since the AC lighting frequency of the commercial frequency 60 [Hz] illumination is 120 [Hz], when flicker occurs under this illumination, the imaging signal includes a 120 [Hz] flicker frequency component.
[0067]
The flicker detection means 5a detects the flicker frequency component from the video signal added for each input line, and determines whether or not flicker has occurred based on the magnitude of the flicker frequency component. In the flicker detection means 5a, the BPF 5f of the specific frequency detection means 5c passes only the flicker frequency component (100 [Hz] or 120 [Hz]) included in the video signal, and this flicker frequency component is passed to the integration means 5g. send. The integrating means 5g integrates the above flicker frequency component for each frame, and sends the integrated value of the flicker frequency component to the comparing means 5d. If flicker occurs, the integrated value of the flicker frequency component becomes large. The comparison means 5d compares the integrated value of the flicker frequency component with the reference value of the reference value setting means 5e, and detects the flicker if the integrated value is larger than the reference value. Is less than the reference value, it is assumed that flicker has not been detected, and the detection result is sent to the control means 1b.
[0068]
FIG. 4 is a waveform diagram of a flicker frequency component included in an image pickup signal by M PDs in one row in the area sensor 1. In FIG. 4, the column direction of the area sensor 1 is the Y direction, and the scanning line of the area sensor 1 is indicated by an arrow. Further, the Y axis in the waveform diagram of FIG. 4 is also the time axis. The flicker frequency component in FIG. 4 is a signal with a frequency of 100 [Hz] under illumination with a commercial frequency of 50 [Hz], and a signal with a frequency of 120 [Hz] under illumination with a commercial frequency of 60 [Hz]. .
[0069]
In the imaging mode, the charge accumulation timing is different for each column, so that the imaging signals from the PDs in different columns (for example, the imaging signals from the M PDs in the first column and the imaging signals from the M PDs in the center column). ), The phases of the flicker frequency components of FIG. 4 included in these video signals are different. For this reason, the video signal output from the area sensor 1 in the imaging mode or the video signal obtained by integrating the video signal for each line includes flicker frequency components having different phases, and the configuration of the specific frequency detecting unit 5c is complicated. become.
[0070]
However, in the flicker detection mode, the charge accumulation timings of all the PDs on the same line are the same, and therefore the charge accumulation timings of all the columns are the same. Therefore, the flicker frequency components included in the imaging signals of all the columns are It becomes the same phase. As a result, the image pickup signal added for each line in the flicker detection mode includes a flicker frequency component obtained by simply adding N flicker frequency components in FIG. 4 (for the number of columns). Therefore, since the video signal added for each line in the flicker detection mode includes a flicker frequency component having a large single phase level, the configuration of the specific frequency detecting means 5c can be simplified and the flicker frequency can be simplified. Components can be easily detected.
[0071]
FIG. 5 is a diagram for explaining the charge accumulation time of the area sensor 1 when flicker occurs. In FIG. 5, f (t) is a time function of illuminance. In the area sensor 1, the charge accumulation time of all the pixels is the same, but the charge accumulation timing is different for each pixel. For this reason, the amount of light irradiated in the charge accumulation time differs between a pixel having a charge accumulation time between a and b in FIG. 5 and a pixel having a charge accumulation time between cd. As a result, the amount of stored charge is different and flicker occurs. That is, when flicker occurs, the following equation (1) is obtained. In Equation (1), f (t) is a time function of illuminance (see FIG. 5).
[Expression 1]

In order not to cause flicker, the charge accumulation time (the time between a and b and the time between cd in FIG. 5) needs to satisfy the following formula (2).
[Expression 2]

The value of the charge accumulation time that satisfies the equation (2) is a multiple of the AC lighting cycle of the illumination (including the AC lighting cycle), and is therefore a multiple of the flicker cycle (cycle of the flicker frequency component) (including the flicker cycle). . That is, when the flicker cycle (AC lighting cycle) is 1/100 [s], the charge accumulation time during which no flicker occurs is 1/100 [s], 2/100 [s], 3/100 [s],. It is. When the flicker cycle (AC lighting cycle) is 1/120 [s], the charge accumulation time during which no flicker occurs is 1/120 [s], 2/120 [s], 3/120 [s],. It is. However, the charge accumulation time during which flicker does not occur needs to be shorter than the frame period of the video signal. For example, when the charge accumulation time is equal to the flicker cycle (AC lighting cycle), the amount of light applied to each pixel is equal as shown in FIG. 6, and flicker does not occur.
[0072]
When the flicker is not detected, the control means 5b switches the operation mode of the area sensor 1 to the imaging mode. Further, when detecting the flicker, the control unit 5b sets the charge accumulation time of the area sensor 1 to a multiple of the flicker cycle in which flicker does not occur, and switches the operation mode of the area sensor 1 to the imaging mode. For example, when the control unit 5b detects flicker by the flicker detection unit 5a that detects a flicker frequency component of 100 [Hz], the charge accumulation time of the area sensor 1 is set to 1/100 [s] which is the same as the flicker cycle. Then, the operation mode of the area sensor 1 is switched to the imaging mode.
[0073]
In the imaging mode, the signal level detecting means 5i compares the integrated value of the video signal by the integrating means 6 with a preset reference value range, and when the integrated value is larger than the reference value range, it is overexposed. When the integrated value is smaller than the reference value range, it is determined that the exposure is insufficient, and the comparison result is sent to the control means 5b. The control means 5b adjusts the charge accumulation time of the area sensor 1 so that the above integrated value falls within the reference value range (so that the level of the video signal becomes constant) when overexposed or insufficient, and if necessary, Thus, the signal gain of the gain adjusting means 3 is adjusted.
[0074]
In the imaging mode after flicker is not detected, the charge accumulation time can be continuously adjusted. Therefore, the adjustment of the video signal level is sufficient by adjusting the charge accumulation time of the area sensor 1, and the charge accumulation time. The gain of the gain adjusting means 3 is adjusted only when it cannot be adjusted by the above.
[0075]
However, in the imaging mode after flicker is detected, the charge accumulation time needs to be set to a multiple of the flicker cycle, and the charge accumulation time can be adjusted only by a discrete value. For this reason, exposure control with a rough resolution is performed, and an image when the charge accumulation time is switched becomes unnatural.
[0076]
Therefore, the control unit 5b controls the charge accumulation time T of the area sensor 1 and the signal gain G of the gain control unit 3 as shown in FIGS. 7 and 8 in the imaging mode after flicker is detected. FIG. 7 is a diagram for explaining the control of the charge accumulation time T and the signal gain G under illumination where the flicker frequency component is 100 [Hz] (illumination at a commercial frequency of 50 [Hz]). A set value of the charge accumulation time T of the area sensor 1 with respect to L, (b) is a set value of the signal gain G of the gain adjusting means 3 with respect to the subject illuminance L. FIG. 8 is a diagram for explaining the control of the charge accumulation time T and the signal gain G under illumination where the flicker frequency component is 120 [Hz] (illumination at a commercial frequency of 60 [Hz]). A set value of the charge accumulation time T of the area sensor 1 with respect to the subject illuminance L, and (b) is a set value of the signal gain G of the gain adjusting means 3 with respect to the subject illuminance L.
[0077]
In the imaging mode under illumination that causes flicker, as shown in FIG. 7A and FIG. 8A, the charge accumulation time T can be controlled only with a discontinuous value with respect to the subject illuminance L. Within the range of subject illuminance L in which the charge accumulation time T is set, discontinuous exposure control is performed by continuously changing the value of the signal gain G as shown in FIGS. 7B and 8B. Complement and hold the video signal level constant. By controlling the charge accumulation time T and the signal gain G as shown in FIGS. 7 and 8, it is possible to obtain a constant level video signal without any discontinuity at any brightness of the subject.
[0078]
A list of combinations of set values of the charge accumulation time T and the signal gain G under illumination that causes flicker is provided in advance in the computing means 5 as an LUT 5h. FIG. 9 is a structural diagram of the LUT 5h, where (a) shows the configuration of the LUT 5h under illumination at a commercial frequency of 50 [Hz], and (b) shows the configuration of the LUT 5h under illumination at a commercial frequency of 60 [Hz]. The control means 5b refers to the LUT 5h according to the comparison result between the integrated value of the video signal from the signal level detection means 5i (the integrated value by the integrating means 6) and the reference value range, and the charge accumulation time T and signal gain G according to the LUT 5h. Set.
[0079]
For example, when the flicker detection unit 5a detects a flicker frequency component of 100 [Hz], if the initial reference address of the LUT 5h is n = 4, the control unit 5b detects the flicker and the address n = 4, the charge accumulation time T of the area sensor 1 is set to 1/100 [s], and the signal gain G of the gain adjusting means 3 is set to 5 (maximum value). In this initial setting, if the integrated value of the video signal is larger than the reference value range, the control means 5b decrements the reference address n (n = 3), refers to the address n = 3 of the LUT 5h, and gain adjustment means 3 Is changed to 4. Even in this setting, if the integrated value of the video signal is larger than the reference value range, the control means 5b further decrements the reference address n (n = 2), refers to the address n = 2 of the LUT 5h, and adjusts the gain. The signal gain G of the means 3 is changed to 3. In the above initial setting, if the integrated value of the video signal is smaller than the reference value range, the control means 5b increments the reference address n (n = 5), refers to the address n = 5 of the LUT 5h, and gain The signal gain G of the adjusting means 3 is changed to 2 (minimum value), and the charge accumulation time T of the area sensor 1 is changed to 2/100 [s]. As described above, by setting the set values of the charge accumulation time T and the signal gain G in FIGS. 7 and 8 as the LUT 5h in the arithmetic means 5 as shown in FIG. 9, the exposure control and the signal gain control can be easily performed. Become.
[0080]
As described above, according to the first embodiment, the charge accumulation of all the PDs on the same line is started at the same time, the charge accumulation is sequentially started for each line, and the charges accumulated in all the PDs on the same line are added simultaneously. When the flicker is detected from the added video signal for each line, and the flicker is detected, the charge accumulation time is set to flicker. By setting a multiple of the period (flicker period), it is possible to detect flicker occurring in the frame in the imaging area sensor having different charge accumulation timing for each pixel, and to remove this flicker.
[0081]
The method of incrementing or decrementing the reference address of the LUT 5h according to the detection result of the video signal level by the signal level detection means 5i is an example of the video signal level control method, and the LUT 5h can be referred to by other methods. It is. In the first embodiment, in the flicker detection mode, the accumulated charges of all the PDs on the same line are added and read. However, the accumulated charges of a predetermined plurality of PDs on the same line are added. Even if read out, flicker can be detected. It is also possible to adopt a configuration in which an analog video signal (added video signal for each line) output from the gain adjusting unit 3 or the front signal processing unit 2 is input to the flicker detection unit 5a. The detection means 5c and the comparison means 5d can be realized by analog circuits. In these cases, it is necessary to provide an A / D converter in the flicker detection means 5a.
[0082]
Embodiment 2. FIG.
The imaging apparatus according to the second embodiment is obtained by changing the configuration of the calculation unit 5 in the imaging apparatus according to the first embodiment. FIG. 10 is a block diagram of the computing means 5 in the imaging apparatus according to Embodiment 2 of the present invention. In FIG. 10, the same components as those in FIG.
[0083]
As shown in FIG. 10, the calculation means 5 of the second embodiment includes flicker detection means 5j, control means 5b, LUT 5h, and signal level detection means 5i. The flicker detection means 5j includes specific frequency detection means 5c and 5k and a comparison means 5d.
[0084]
The specific frequency detector 5c detects a flicker frequency component (a frequency component of 100 [Hz] or 120 [Hz]) from the added video signal for each line, and the specific frequency detector 5k detects the above-mentioned video signal from the above video signal. A frequency component other than the flicker frequency component is detected. The specific frequency detection means 5k can be realized by BPF and integration means in the same manner as the specific frequency detection means 5c (see FIG. 3), for example.
[0085]
The comparator 5d includes a value of the flicker frequency component (first frequency component) detected by the specific frequency detection unit 5c and a frequency component (second frequency component) that is not the flicker frequency component detected by the specific frequency detection unit 5k. It is assumed that flicker is detected when the first frequency component is greater than the second frequency component by a predetermined value or more.
[0086]
As described above, according to the second embodiment, in addition to the specific frequency detection unit 5c that detects the flicker frequency component (first frequency component), the specific that detects the frequency component (second frequency component) that is not the flicker frequency component. The frequency detection means 5k is provided, and the value of each wave number component is compared in the comparator 5d. When the first frequency component is larger than the second frequency component by a predetermined value or more, flicker is detected. The detection means can be realized with a simple configuration.
[0087]
Embodiment 3 FIG.
The imaging apparatus according to the third embodiment is obtained by changing the configuration of the calculation unit 5 in the imaging apparatus according to the first embodiment. FIG. 11 is a configuration diagram of the calculation means 5 in the imaging apparatus according to Embodiment 3 of the present invention. In FIG. 11, the same components as those in FIG.
[0088]
As shown in FIG. 11, the computing means 5 of the third embodiment includes flicker detection means 5m, control means 5b, LUT 5h, and signal level detection means 5i. The flicker detection means 5m includes specific frequency detection means 5c and 5n, comparison means 5d and 5p, and a reference value setting means 5e.
[0089]
The specific frequency detector 5c detects a flicker frequency component of 100 [Hz] from the added video signal for each line, and the specific frequency detector 5n detects a frequency component of 120 [Hz] from the video signal. .
[0090]
The comparison means 5d compares the value of the 100 [Hz] flicker frequency component (first flicker frequency component) detected by the specific frequency detection means 5c with the reference value of the reference value setting means 5e, When the flicker frequency component is larger than the reference value, it is assumed that flicker having a flicker period of 1/100 [s] due to illumination with a commercial frequency of 50 [Hz] is detected. The comparison unit 5p compares the value of the 120 [Hz] flicker frequency component (second flicker frequency component) detected by the specific frequency detection unit 5n with the reference value of the reference value setting unit 5e, When the flicker frequency component of 1 is larger than the reference value, it is assumed that flicker having a flicker cycle of 1/120 [s] due to illumination with a commercial frequency of 60 [Hz] is detected.
[0091]
In the third embodiment, the LUT 5h is provided with a table for the commercial frequency 50 [Hz] in FIG. 9A and a table for the commercial frequency 60 [Hz] in FIG. 9B. When the flicker having a flicker cycle of 1/100 [s] is detected, the control means 5b refers to the table for the commercial frequency 50 [Hz] of the LUT 5h and the charge accumulation time of the area sensor 1 and the signal of the gain control means 3 When the gain is set and flicker with a flicker cycle of 1/100 [s] is detected, the charge accumulation time of the area sensor 1 and the signal of the gain control means 3 are referred to by referring to the table for the commercial frequency 50 [Hz] of the LUT 5h. Set the gain.
[0092]
As described above, according to the third embodiment, the specific frequency detecting means 5c that detects the flicker frequency component (first flicker frequency component) of 100 [Hz] and the flicker frequency component (second flicker) of 120 [Hz]. Specific frequency detection means 5n for detecting the frequency component), a comparator 5d for comparing the first flicker frequency component with the reference value, and a comparator 5p for comparing the second flicker frequency component with the reference value, When the first flicker frequency component is larger than the reference value, it is assumed that a flicker with a flicker cycle of 1/100 [s] is detected, and when the second flicker frequency component is larger than the reference value, the flicker cycle is 1/120 [s]. Flicker and quotient generated under illumination with a commercial frequency of 50 [Hz] with a simple configuration. It is possible to detect both the flicker occurring under the illumination of a frequency 60 [Hz], it is possible to determine flicker occurs due to any of the commercial frequency.
[0093]
Embodiment 4 FIG.
The computing means 5 of the first embodiment can be realized using a microcomputer or the like. The imaging apparatus according to the fourth embodiment described below is the same as the imaging apparatus according to the first embodiment, except that the calculation unit 5 is realized using a microcomputer. FIG. 12 is a block diagram of the calculation means 5 in the imaging apparatus according to Embodiment 4 of the present invention.
[0094]
As shown in FIG. 11, the computing means 5 by the microcomputer of the fourth embodiment has a CPU 5q and a ROM 5r. The CPU 5q corresponds to the flicker detection means 5a (excluding the reference value setting means 5e), the control means 5b, and the signal level detection means 5i in FIG. In the ROM 5r, the reference value by the reference value setting means 5e and the data of the LUT 5h are recorded. The ROM 5r stores programs of a flicker detection procedure by the flicker detection means 5a, a signal level detection procedure by the signal level detection means 5i, and a control procedure by the control means 5b.
[0095]
As described above, according to the fourth embodiment, the calculation means 5 can be realized with a simple configuration by realizing the calculation means 5 with a microcomputer.
[0096]
Embodiment 5 FIG.
Since the area sensor 1 of the first embodiment is composed of CMOS, it is also possible to incorporate a circuit such as the pre-signal processing means 2, the gain adjusting means 3, and the A / D converter 4 in the area sensor 1. Is possible. The imaging apparatus according to the fifth embodiment is obtained by incorporating the above circuit into the area sensor 1 in the imaging apparatus according to the first embodiment. FIG. 13 is a configuration diagram of the imaging apparatus according to the fifth embodiment of the present invention. FIG. 14 is a block diagram of the area sensor 11 of FIG. 13 and 14, the same reference numerals are given to the same components as those in FIG. 1 or FIG.
[0097]
As shown in FIG. 13, the imaging apparatus according to the fifth embodiment includes an area sensor 11, a calculation unit 5, an integration unit 6, and a signal processing unit 8. As shown in FIG. 14, the area sensor 11 includes a pixel array 11a, a vertical shift register 1q, a horizontal shift register 1r, a drive pulse generating unit 1t, a pre-signal processing unit 2, and a gain adjusting unit 3. , A / D converter 4, register file 11h, input terminal 11i, register value input terminal 11j, and output terminal 11k. The pixel array 11a includes PDs (1a, 1b, 1c, 1d,...), Amplifiers (1e, 1f, 1g, 1h,...), Reset circuits (1u, 1v, 1w, 1x,. ), Pixel selection transistors (1i, 1j, 1k, 1m,...), And column selection transistors (1n, 1p,...).
[0098]
The input terminal 11i is connected to the control means 5b (see FIG. 1) of the calculation means 5. The control means 5b sends the control signal to the input terminal 11i, thereby switching the operation mode of the area sensor 11 to the imaging mode or the flicker detection mode and setting the charge accumulation time.
[0099]
The output terminal 11i is connected to the integrating means 6, the signal processing means calculating means 8, and the flicker detecting means 5a (see FIG. 1) of the calculating means 4. The imaging signal output from the pixel array 11a is subjected to noise removal in the pre-signal processing means 2, amplified in the gain adjusting means 3, converted into a digital signal in the A / D converter 4, and integrated from the output terminal 11i, The signal is input to the signal processing means calculation means 8 and the flicker detection means 5a.
[0100]
The register file 11 h sets the signal gain value of the gain adjusting means 3 and supplies a reference voltage value to the A / D converter 4. The register setting of the register file 11h is input from the register value input terminal 11j, and the register value input terminal 11j is connected to the calculation means 5. When it is desired to change the signal gain of the gain adjusting means 3, the calculating means 5 outputs the signal gain value to the register value input terminal 11j, and changes the signal gain value by the register file 11h.
[0101]
【The invention's effect】
As described above, the imaging of the present invention apparatus Therefore, it is possible to easily detect flicker generated in the frame in the imaging area sensor having different charge accumulation timing for each photoelectric conversion element. This flicker can be removed There is an effect.
[0103]
Further, the claims of the present invention 1 or 2 According to the image pickup apparatus described in item 1, there is an effect that the flicker detection means can be realized with a simple configuration.
[0104]
Further, the claims of the present invention 3 According to the described imaging apparatus, it is possible to detect both flicker at a commercial frequency of 50 [Hz] and flicker at a commercial frequency of 60 [Hz] with a simple configuration, and which commercial frequency causes flicker. There is an effect that can be discriminated.
[0105]
Further, the claims of the present invention 4 According to the described imaging apparatus, there is an effect that the specific frequency detection unit can be realized with a simple configuration.
[0106]
Further, the claims of the present invention 5 According to the described image pickup apparatus, there are effects that flicker can be removed and the video signal level can be adjusted smoothly.
[0107]
Further, the claims of the present invention 6 According to the image pickup apparatus described above, it is easy to control the charge accumulation time and the signal gain in the first mode after the flicker is detected by making the charge accumulation time and the signal gain value free from flicker LUT. There is an effect of becoming.
[0108]
According to the image pickup device of the present invention, the charge accumulation in the first mode after the flicker is detected by making the charge accumulation time in which flicker does not occur and the gain value of the signal LUT. There is an effect that control of time and signal gain becomes easy.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an imaging apparatus according to Embodiment 1 of the present invention.
FIG. 2 is a configuration diagram of the area sensor of FIG. 1;
FIG. 3 is a configuration diagram of specific frequency detection means in FIG. 1;
4 is a waveform diagram of flicker frequency components included in an imaging signal by a certain column of PDs in the area sensor of FIG. 2;
FIG. 5 is a diagram for explaining the charge accumulation time of the area sensor of FIG. 2 when flicker occurs.
6 is a diagram for explaining the charge accumulation time of the area sensor of FIG. 2 when no flicker occurs.
7 is a diagram for describing control of charge accumulation time and signal gain under illumination with a flicker frequency component of 100 [Hz] (illumination at a commercial frequency of 50 [Hz]) in the imaging apparatus of FIG. 1;
FIG. 8 is a diagram for explaining control of charge accumulation time and signal gain under illumination with a flicker frequency component of 120 [Hz] (illumination at a commercial frequency of 60 [Hz]) in the imaging apparatus of FIG. 1;
FIG. 9 is a structural diagram of the LUT of FIG. 1;
FIG. 10 is a configuration diagram of computing means in the imaging apparatus according to Embodiment 2 of the present invention.
FIG. 11 is a configuration diagram of computing means in the imaging apparatus according to Embodiment 3 of the present invention.
FIG. 12 is a configuration diagram of calculation means in the imaging apparatus according to Embodiment 4 of the present invention.
FIG. 13 is a configuration diagram of an imaging apparatus according to Embodiment 5 of the present invention.
14 is a configuration diagram of the area sensor of FIG. 13;
FIG. 15 is a configuration diagram of a conventional imaging device including a CCD area sensor.
FIG. 16 is a principle diagram of a CCD area sensor.
FIG. 17 is a diagram for explaining the principle of generating flicker in a CCD area sensor.
FIG. 18 is a diagram illustrating a flicker suppression method in a CCD area sensor.
FIG. 19 is a configuration diagram of a conventional CMOS area sensor.
20 is a diagram for explaining scanning of the area sensor in FIG. 19;
FIG. 21 is a diagram for explaining the principle of causing flicker in the area sensor of FIG.
22 is a diagram showing a signal level for each line when flicker is generated in the area sensor of FIG. 19;
23 is a diagram showing a screen on which flicker is generated by the area sensor of FIG.
[Explanation of symbols]
1 area sensor, 1a, 1b, 1c, 1d photoelectric conversion element (photodiode), 1e, 1f, 1g, 1h amplifier, 1i, 1j, 1k, 1m, 1n, 1p transistor, 1q vertical shift register, 1r horizontal shift register , 1s output terminal, 1t drive pulse generating means, 1u, 1v, 1w, 1x reset circuit, 2 pre-signal processing means, 3 gain adjusting means, 4 A / D converter, 5 calculating means, 5a, 5i, 5m flicker detection Means, 5b control means, 5c, 5k, 5n specific frequency detection means, 5d, 5p comparison means, 5e reference value setting means, 5f BPF, 5g accumulation means, 5h LUT, 5q CPU, 5r ROM, 6 accumulation means, 7 outputs Terminal, 8 signal processing means, 11 area sensor, 11a pixel array, 11h register file, 1i input terminal, 11j register value input terminal, 11k output terminal.

Claims (6)

Resetting the photoelectric conversion elements individually and starting charge accumulation; reading out the charges accumulated in the photoelectric conversion elements individually; and outputting to the outside; driving the resetting means and the reading means; An imaging area having a drive means for controlling the charge accumulation start timing and readout timing of each photoelectric conversion element, and the charge accumulation timing at the time of imaging differs for each photoelectric conversion element, and the charge accumulation time of the photoelectric conversion element can be adjusted A sensor,
Flicker detection means for detecting flicker from the video signal;
Control means for controlling the driving means;
With
The driving means is
In the first mode, charge accumulation is started sequentially for each photoelectric conversion element, the accumulated charges are sequentially read out, and signals from the respective photoelectric conversion elements are sequentially output. In the second mode, the same line The charge accumulation of the plurality of photoelectric conversion elements (including all the photoelectric conversion elements in the same line) is started simultaneously, and the charge accumulation is sequentially started for each line, so that the charges accumulated in the plurality of photoelectric conversion elements are simultaneously There are two drive modes that add and read out, and sequentially output the added signal of each line,
The control means includes
When the imaging area sensor is operated in the second mode and flicker is detected, the charge accumulation time of the imaging area sensor is set to a multiple of the flicker period (including the flicker period), and the imaging area sensor In the first mode,
The flicker detection means is
Frequency detecting means for detecting a flicker frequency component from the video signal in the second mode;
Comparing means for comparing the signal level of the flicker frequency component with a preset reference value,
When the flicker frequency component is greater than the reference value, you characterized in that it is assumed that the detected flicker imaging device. Resetting the photoelectric conversion elements individually and starting charge accumulation; reading out the charges accumulated in the photoelectric conversion elements individually; and outputting to the outside; driving the resetting means and the reading means; An imaging area having a drive means for controlling the charge accumulation start timing and readout timing of each photoelectric conversion element, and the charge accumulation timing at the time of imaging differs for each photoelectric conversion element, and the charge accumulation time of the photoelectric conversion element can be adjusted A sensor,
Flicker detection means for detecting flicker from the video signal;
Control means for controlling the driving means;
With
The driving means is
In the first mode, charge accumulation is started sequentially for each photoelectric conversion element, the accumulated charges are sequentially read out, and signals from the respective photoelectric conversion elements are sequentially output. In the second mode, the same line The charge accumulation of the plurality of photoelectric conversion elements (including all the photoelectric conversion elements in the same line) is started simultaneously, and the charge accumulation is sequentially started for each line, so that the charges accumulated in the plurality of photoelectric conversion elements are simultaneously There are two drive modes that add and read out, and sequentially output the added signal of each line,
The control means includes
When the imaging area sensor is operated in the second mode and flicker is detected, the charge accumulation time of the imaging area sensor is set to a multiple of the flicker period (including the flicker period), and the imaging area sensor In the first mode,
The flicker detection means is
First frequency detecting means for detecting a first frequency component that is a flicker frequency component from the video signal in the second mode;
Second frequency detection means for detecting a second frequency component that is not a flicker frequency component from the imaging signal;
Comparing means for comparing the signal level of the first frequency component with the signal level of the second frequency component;
When the first frequency component is larger than a predetermined value than the second frequency component, you characterized in that it is assumed that the detected flicker imaging device. Resetting the photoelectric conversion elements individually and starting charge accumulation; reading out the charges accumulated in the photoelectric conversion elements individually; and outputting to the outside; driving the resetting means and the reading means; An imaging area having a drive means for controlling the charge accumulation start timing and readout timing of each photoelectric conversion element, and the charge accumulation timing at the time of imaging differs for each photoelectric conversion element, and the charge accumulation time of the photoelectric conversion element can be adjusted A sensor,
Flicker detection means for detecting flicker from the video signal;
Control means for controlling the driving means;
With
The driving means is
In the first mode, charge accumulation is started sequentially for each photoelectric conversion element, the accumulated charges are sequentially read out, and signals from the respective photoelectric conversion elements are sequentially output. In the second mode, the same line The charge accumulation of the plurality of photoelectric conversion elements (including all the photoelectric conversion elements in the same line) is started simultaneously, and the charge accumulation is sequentially started for each line, so that the charges accumulated in the plurality of photoelectric conversion elements are simultaneously There are two drive modes that add and read out, and sequentially output the added signal of each line,
The control means includes
When the imaging area sensor is operated in the second mode and flicker is detected, the charge accumulation time of the imaging area sensor is set to a multiple of the flicker period (including the flicker period), and the imaging area sensor In the first mode,
The flicker detection means is
First frequency detection means for detecting a first flicker frequency component from the video signal in the second mode;
Second frequency detection means for detecting a second flicker frequency component from the video signal;
First comparison means for comparing the signal level of the first flicker frequency component with a preset reference value;
Second comparison means for comparing the signal level of the second frequency component and the reference value;
When the first flicker frequency component is larger than the reference value, the first frequency flicker is detected, and when the second flicker-frequency component is larger than the reference value, the second frequency flicker is detected. it characterized in that it is assumed that the detected imaging device. The frequency detection means includes
A bandpass filter that passes only flicker frequency components;
The imaging apparatus according to any one of claims 1 to 3, characterized in that it has an integrating means for integrating an output signal of the band-pass filter. Resetting the photoelectric conversion elements individually and starting charge accumulation; reading out the charges accumulated in the photoelectric conversion elements individually; and outputting to the outside; driving the resetting means and the reading means; and a driving means for controlling the start timing and the read timing of the charge accumulation of each photoelectric conversion element, an imaging charge storage timing for imaging varies from photoelectric conversion elements, What can be adjusted charge accumulation time of the photoelectric conversion element An area sensor,
Flicker detection means for detecting flicker from the video signal;
Control means for controlling the driving means;
With
The driving means is
In the first mode, charge accumulation is started sequentially for each photoelectric conversion element, the accumulated charges are sequentially read out, and signals from the respective photoelectric conversion elements are sequentially output. In the second mode, the same line The charge accumulation of the plurality of photoelectric conversion elements (including all the photoelectric conversion elements in the same line) is started simultaneously, and the charge accumulation is sequentially started for each line, so that the charges accumulated in the plurality of photoelectric conversion elements are simultaneously There are two drive modes that add and read out, and sequentially output the added signal of each line,
The control means includes
When the imaging area sensor is operated in the second mode and flicker is detected, the charge accumulation time of the imaging area sensor is set to a multiple of the flicker period (including the flicker period), and the imaging area sensor In the first mode,
Gain adjusting means for adjusting the gain of the video signal by the imaging area sensor;
Integrating means for integrating the gain-adjusted video signal;
Signal level determining means for determining whether or not the integrated value of the video signal is within a predetermined range;
In the imaging operation in the first mode when flicker is detected, the control means is configured to adjust the charge accumulation time and the signal gain of the gain adjusting means so that the integrated value of the video signal is within the predetermined range. you and controlling the imaging device. A lookup table listing the combinations of charge accumulation times and signal gains that can be set in the imaging operation in the first mode when flicker is detected;
Said control means, the imaging operation in the first mode when the flicker is detected, according to claim 5, with reference to the look-up table and controls the charge storage time and the signal gain Imaging device.

Images