JP3656045B2 - Packet stream generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for realizing a high-speed operation with a simple configuration in a packet stream generator that generates a packet stream in which packet data and gap data are continuous.
[0002]
[Prior art]
When testing a system that transmits packet data in an environment close to the actual movable environment, it is necessary to provide the system under test with a packet stream signal in which gap data of an arbitrary length is inserted between packet data of an arbitrary length .
[0003]
In order to generate such a packet stream signal, conventionally, a predetermined length of packet stream data formed by a plurality of arbitrary length packet data and a plurality of arbitrary length gap data is stored in advance in a memory, The packet stream data is read from the memory, serially converted, and given to the test target system.
[0004]
[Problems to be solved by the invention]
However, in the conventional method of reading a series of packet stream data stored in the memory in advance as described above, the length of the packet stream data is limited by the capacity of the memory, and in order to output the packet stream data over a long period of time. The memory capacity becomes enormous.
[0005]
Also, in order to change the output pattern of the packet stream data to be output, the packet stream data cannot be output in a new pattern until the packet stream data is rewritten to the memory, and the pattern switching wait time is increased. There was a problem that it was long for display.
[0006]
An object of the present invention is to solve this problem and provide a packet stream generator capable of generating packet stream data with a small memory capacity and switching the pattern at high speed.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a packet stream generator according to claim 1 of the present invention provides:
a packet data generation unit (21) for sequentially outputting a plurality of packet data having an arbitrary multiple of m bits (m is a plurality of constants) in an (m × n) bit width (n is a plurality of constants);
A packet length designating means (22) for designating the length of each packet data output from the packet data generating unit in units of m bits;
A gap data generator (23) that sequentially outputs a plurality of gap data having an arbitrary multiple of m bits to be inserted into gaps of packet data output by the packet data generator with an (m × n) bit width )When,
Gap length designating means (24) for designating the length of gap data output by the gap data generating unit in units of m bits;
2n memories (30 (1) to 30 (2N)) capable of independently writing and reading data in units of m bits;
Based on the packet length specified by the packet length specifying means and the gap length specified by the gap length specifying means, the packet data output from the packet data generation unit with an (m × n) bit width and the gap A write processing unit (25) for continuously and cyclically writing the gap data output with a (m × n) bit width from the data generation unit to the 2n memories in units of m bits;
Of the 2n memories, (m × n) bit width data composed of m bits of data written in the first to nth memories, respectively, and (n + 1) th to (2n) th data A process of alternately reading out (m × n) bit width data composed of m-bit data written in the memory is performed in parallel with the writing process by the write processing unit, and the packet data generation unit And a read processing unit (31) for outputting a packet stream in which the generated packet data and the gap data generated by the gap data generation unit are continuous without gaps with an (m × n) bit width.
[0008]
A packet stream generator according to claim 2 of the present invention is the packet stream generator according to claim 1,
The write processing unit
Based on the packet length specified by the packet length specifying means and the gap length specified by the gap length specifying means, the write start position and write end position of the packet data and gap data in the 2n memories are determined. A desired writing position detecting means (26);
Based on the write start position and write end position obtained by the write position detection means, the packet data and gap data are shifted in units of m bits, and the final m bit data and gap data of the packet data are changed. Shift processing means (27) for outputting to the 2n memories in a state where the leading m-bit data is continuous and the last m-bit data of the gap data and the leading m-bit data of the next packet data are continuous When,
It is characterized by being constituted by a write control means (28) for writing packet data and gap data shifted by the shift processing means to the 2n memories.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of a packet stream generator 20 to which the present invention is applied. In this embodiment, the length of packet data and gap data is arbitrarily specified in units of 8 bits (1 byte) (m = 8), and the output bit width (m × n) is N bytes (n = N). An example is shown.
[0010]
In FIG. 1, a packet data generating unit 21 converts packet data P having a packet length Lp (arbitrary length) designated in bytes from the packet length designation unit 22 into N bytes (N is a plurality, for example, 4, 8, 16, etc.). ) In order.
[0011]
The gap data generation unit 23 sequentially outputs gap data G having a gap length Lg (arbitrary length) designated in byte units from the gap length designation unit 24 in N-byte width.
[0012]
Note that the packet length designating unit 22 and the gap length designating unit 24 are connected to the packet data generating unit 21 according to preset stream pattern information (information representing the length and arrangement of packet data and gap data constituting the packet stream). The packet length Lp and the gap length Lg are sequentially specified for the gap data generating unit 23.
[0013]
The packet data P output from the packet data generator 21 and the gap data G output from the gap data generator 23 are input to the write processor 25 together with the packet length Lp and the gap length Lg.
[0014]
The writing processing unit 25 performs writing processing of the packet data P and the gap data G to the 2N memories 30 (1) to 30 (2N) based on the packet length Lp and the gap length Lg.
[0015]
The 2N memories 30 (1) to 30 (2N) are FIFO-type memories that can independently perform writing and reading of data in units of 1 byte and that can be read in the order of writing. Each has a plurality of (for example, a maximum of 32) areas capable of storing 1-byte data.
[0016]
The write processor 25 cyclically writes the packet data P (x) output from the packet data generator 21 into 2N memories 30 (1) to 30 (2N) one byte at a time starting from the first byte. The gap data G (x) output from the gap data generation unit 23 to be inserted after the packet data P (x) is stored in the memory 30 (i) in which the last one byte of the packet data P (x) is written. The next packet data P (x + 1) output from the packet data generator 21 to be inserted after the gap data G (x) is cyclically written byte by byte from the next memory 30 (i + 1). The process of cyclically writing one byte at a time from the memory 30 (j + 1) next to the memory 30 (j) in which the last one byte of G (x) has been written Carried out.
[0017]
In order to perform the writing process almost in real time, the writing processing unit 25 includes a writing position detecting unit 26, a shift processing unit 27, and a writing control unit 28.
[0018]
Based on the packet length Lp and the gap length Lg, the write position detection means 26 writes the write start position Ws for the 2N memories 30 (1) to 30 (2N) of the packet data P and the gap data G, The end position We is obtained.
[0019]
The shift processing means 27 performs a byte-by-byte shift process on the packet data P and the gap data G based on the write start position Ws and the write end position We obtained by the write position detection means 26, and the packet data P Are output to the memories 30 (1) to 30 (2N) with the last byte of the gap data G and the last byte of the gap data G and the first byte of the next packet data P being continuous.
[0020]
The write control means 28 writes the packet data P and the gap data G shifted by the shift processing means 27 to 2N memories 30 (1) to 30 (2N).
[0021]
The read processing unit 31 includes a read control unit 32 that performs data read control on 2N memories 30 (1) to 30 (2N), and a data selection unit 33 that selectively outputs one of two N-bit data. N bytes of data consisting of 1 byte of data written in the first to Nth memories 30 (1) to 30 (N) of 2N memories 30 (1) to 30 (2N), respectively. Data and N-byte data composed of 1-byte data written in the (N + 1) th to (2N) th memories 30 (N + 1) to 30 (2N), respectively, from the earliest writing time The data is alternately read in sequence, packet data P having an arbitrary byte length generated by the packet data generation unit 21 and gap data G having an arbitrary byte length generated by the gap data generation unit 23. There outputs the packet stream data S N bytes wide consecutive without gaps.
[0022]
The data reading process by the reading processing unit 31 is performed in parallel with the data writing process by the writing processing unit 25.
[0023]
Next, the operation of the packet stream generating apparatus 20 configured as described above will be described.
For example, when N = 4, packet data P (1), P (2) of packet length Lp = 11, Lp = 9, Lp = 8,... From the packet data generation unit 21 as shown in FIG. ), P (3),... Are sequentially output with a width of N bytes. As shown in FIG. 2B, the gap data G (1) with gap lengths Lg = 9, Lg = 11,. ), G (2),... Are output.
[0024]
In this case, the write position detection means 26 of the write processing unit 25 always sets the reference position number of the first byte of each byte data input with 4 (= N) byte width for the packet data to 1 and the gap data. Always sets the reference position number of the first byte of each byte data inputted with its 4 (= N) byte width to 5 (= N + 1) and 1 to 8 for the memories 30 (1) to 30 (8). A position number of (= 2N) is assigned to obtain a writing start position and a writing end position.
[0025]
That is, when the first four byte data p (1,1) to p (1,4) of the packet data P (1) are input, the reference position number 1 of the first byte data p (1,1) is inputted. Is the initial value of the write start position Ws1, and the write end position We1 of the byte data p (1,1) to p (1,4) is
We1 = Ws1 + (number of bytes of valid data in N bytes) -1
Calculate by When the calculation result exceeds 8, a value obtained by subtracting 8 from the calculation result is used.
[0026]
In this case, since the first four byte data p (1,1) to p (1,4) are all valid data, the write end position We1 is
We1 = 1 + 4−1 = 4
It becomes.
[0027]
The shift processing means 27 having received the write start position Ws1 = 1 and the write end position We1 = 4 receives the first byte data p (1,1) to p (1,4) of the packet data P (1). Since there is no difference between the write start position Ws1 and the reference position number 1, the four byte data p (1, 1) to p (1, 4) are not performed as shown in FIG. ) Are output to the first to fourth memories 30 (1) to 30 (4), respectively, and the write control means 28 starts from the first memory 30 (1) corresponding to the write start position Ws = 1. A write instruction is issued up to the fourth memory 30 (4) corresponding to the write end position We = 4.
[0028]
As a result, the first four byte data p (1,1) to p (1,4) of the packet data P (1) are stored in the first to fourth memories 30 as shown in FIG. (1) to the first area of the memory 30 (4), respectively.
[0029]
When the next four bytes p (1,5) to p (1,8) of the packet data P (1) are input, the writing position detecting means 26 has written the packet length Lp and the previous time. From the number of byte data, it is determined that the four byte data p (1,5) to p (1,8) are all valid data, and 1 is added to the previous write end position We1 = 4. A value of 5 (when the added result is 9, the value 1 obtained by subtracting 8 from the result is used) is set as the writing start position Ws2, and the writing end position We2 is set as
We2 = Ws2 + (number of valid data bytes 4) -1 = 8
Ask for.
[0030]
The shift processing means 27 having received the write start position Ws2 = 5 and the write end position We2 = 8, as shown in FIG. 4A, shows byte data p (1,5) to p (1,8 ) Is shifted downward by 4 bytes equal to the difference between the reference position number 1 and the write start position Ws2 = 5, and is output to the fifth to eighth memories 30 (5) to 30 (8), respectively. The write control means 28 writes data from the fifth memory 30 (5) corresponding to the write start position Ws2 = 5 to the eighth memory 30 (7) corresponding to the write end position We2 = 8. Give instructions.
[0031]
As a result, the four byte data p (1,5) to p (1,8) are stored in the fifth to eighth memories 30 (5) to 30 (8) as shown in FIG. Each is written in the first area.
[0032]
Further, when the remaining three byte data p (1, 9) to p (1, 11) of the packet data P (1) and invalid 1-byte dummy data dd are input, the writing position detecting means 26 The write start position Ws3 is obtained from the value obtained by adding 1 to the previous write end position We2 = 8. In this case, since the addition result is 9, the value 1 obtained by subtracting 8 from the addition result 9 is written. The start position Ws3 is set, and the write end position We3 is set as
We3 = Ws3 + (number of valid data bytes 3) -1 = 3
Ask for.
[0033]
The shift processing means 27 having received the write start position Ws3 = 1 and the write end position We3 = 3 does not perform the shift process because the reference position number 1 and the write start position Ws3 = 1 are equal. As in (a) of FIG. 5, the three byte data p (1,9) to p (1,11) and the dummy data dd are directly used as the first to fourth memories 30 (1) to 30 (4). ), The write control means 28 from the first memory 30 (1) corresponding to the write start position Ws2 = 1 to the third memory 30 (3) corresponding to the write end position We3 = 3. Is given a write instruction.
[0034]
As a result, the last three valid byte data p (1,9) to p (1,11) of the packet data P (1) are changed from the first to the third as shown in FIG. Writing to the second area of each of the memories 30 (1) to 30 (3) and invalid dummy data dd to the fourth memory 30 (4) is restricted.
[0035]
Next, when the first four byte data g (1,1) to g (1,4) of the gap data G (1) with the gap length Lg = 9 are input, the writing position detecting unit 26 A value 4 obtained by adding 1 to the write end position We3 = 3 is set as the write start position Ws4 of the byte data g (1,1) to g (1,4), and the write end position We4 is set to
We4 = Ws4 + (number of valid data bytes 4) -1 = 7
Calculated by
[0036]
The shift processing means 27 having received the write start position Ws4 = 4 and the write end position We4 = 7, as shown in FIG. 6A, shows byte data g (1,1) to g (1,4 ) Is shifted to the upper side by 1 byte equal to the difference between the reference position number 5 and the write start position Ws4 = 4, and the write control means 28 outputs the fourth to seventh memories 30 (4). A write instruction is given to .about.30 (7).
[0037]
As a result, the byte data g (1,1) to g (1,4) are stored in the second of the fourth to seventh memories 30 (1) to 30 (3) as shown in FIG. Each is written to an area.
[0038]
When the next valid four byte data g (1,5) to g (1,8) of the gap data G (1) are input, the writing position detecting means 26 detects the previous writing end position. A value 8 obtained by adding 1 to We4 = 7 is set as a write start position Ws5 of byte data g (1,5) to g (1,8), and a write end position We5 is set as follows.
We5 = Ws5 + (number of valid data bytes 4) -1
In this case, since the calculation result is 11, the write end position We5 is 3 (= 11−8).
[0039]
The shift processing means 27 having received the write start position Ws5 = 8 and the write end position We5 = 3, as shown in FIG. 7A, shows bytes g (1,5) to g (1,8). Are shifted downward by 3 bytes equal to the difference between the reference position number 5 and the write start position Ws4 = 8. At this time, the most significant byte data g (1,5) is output to the least significant memory 30 (8), and the remaining three byte data g (1,6) to g (1,8) are cyclic. Thus, it returns to the upper side and is output to the memories 30 (1) to 30 (3).
[0040]
The write control means 28 instructs the eighth memory 30 (8) and the first to third memories 30 (1) to 30 (3) to write data.
As a result, the byte data g (1,5) is written in the second area of the eighth memory 30 (8), and the other three byte data g (1,6) to g (1,8) are The data is written in the third areas of the first to third memories 30 (1) to 30 (3), respectively.
[0041]
When the last byte data g (1, 9) of the gap data G (1) and the 3-byte dummy data dd are input, the write position detecting means 26 sets the previous write end position We5 = 3. The value 4 obtained by adding 1 is set as the writing start position Ws6, and the writing end position We6 is set as follows.
We6 = Ws6 + (valid data byte number 1) -1 = 4
Calculated by
[0042]
The shift processing means 27 having received the write start position Ws6 = 4 and the write end position We4 = 4, as shown in FIG. 8A, includes byte data g (1, 9) and 3-byte dummy data. dd is shifted upward by 1 byte equal to the difference between the reference position number 5 and the write start position Ws6 = 4, and output to the fourth to seventh memories 30 (4) to 30 (7), The write control means 28 instructs to write data to the memory 30 (4) from the write start position Ws6 = 4 to the write end position We6 = 4.
[0043]
As a result, as shown in FIG. 8B, the last valid byte data g (1, 9) of the gap data G (1) is stored in the third area of the fourth memory 30 (4). The
[0044]
The above operation is similarly performed for the next packet data P (2), gap data G (2),..., And packet data P (1) is stored in the eight memories 30 (1) to 30 (8). ), Gap data G (1), packet data P (2), gap data G (2), packet data P (3),... It will be stored cyclically in the state.
[0045]
For example, as shown in FIG. 9, the read processing unit 31 starts from the time when data is stored in the third area of each of the memories 30 (1) to 30 (8), from the first to the fourth on the upper side. 4 bytes wide data s1 composed of each byte data p (1,1) to p (1,4) stored in the first area of the memories 30 (1) to 30 (4) is read out at the next timing. Is 4 bytes consisting of each byte data p (1,5) -p (1,8) stored in the first area of the fifth to eighth memories 30 (5) -30 (8). The width data s2 is read, and each byte data p (1,9) to p (1,11), g (1) stored in the second area of the memories 30 (1) to 30 (4) at the next timing. , 1), the process of reading the 4-byte wide data s3 is continuously performed.
[0046]
Therefore, as shown in FIG. 10, from the read processing unit 31, byte data and gap data of packet data P (1), P (2),... Of arbitrary byte length generated by the packet data generation unit 21. Packet data S having an N-byte width in which gap data G (1), G (2),... Of any byte length generated by the generation unit 23 continues without a gap is output.
[0047]
Note that the writing process of the writing processing unit 25 and the reading process of the reading processing unit 31 for the memories 30 (1) to 30 (8) are performed in parallel at substantially the same bit rate. Even when data is output, the number of areas in each of the memories 30 (1) to 30 (8) is small.
[0048]
In addition, when the stream pattern information is switched, the stream data of the new pattern can be immediately output after the data of the previous pattern remaining in each of the memories 30 (1) to 30 (8) is output. The waiting time for switching the stream pattern is remarkably shortened.
[0049]
In the above description, the writing of the dummy data dd to the memory is regulated. However, the overwriting process may be performed with the packet data or the gap data after the dummy data dd is written to the memory.
[0050]
In the packet stream generator 20 described above, a FIFO type memory is used as the 2N memories 30 (1) to 30 (2N). However, any memory capable of independently writing and reading data can be used. It does not have to be a FIFO type memory.
[0051]
In the above description, m = 8 bits (1 byte), that is, the length of packet data and gap data is specified in units of 1 byte, and the output data width is (m × n) is N bytes. However, if m is a constant plural such as m = 4, m = 16,... And the data width is a number represented by m × n (n is an arbitrary constant plural), the present invention is The same applies.
[0052]
【The invention's effect】
As described above, the packet stream generation apparatus according to the present invention converts 2n pieces of packet data and gap data based on the length of packet data and gap data respectively input with (m × n) bit width. It consists of m bytes of data written in the 1st to nth memories of 2n memories while performing the process of writing continuously and cyclically in m bits in the memory (m × n). ) Bit width data and (m × n) bit width data consisting of m bytes of data written in the (n + 1) th to (2n) th memory are alternately read out (m × n) bits A packet stream of width is output.
[0053]
Therefore, a long packet stream can be generated with a small capacity memory, and stream pattern switching can be performed at high speed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a diagram for explaining the operation of the embodiment. FIG. 3 is a diagram for explaining the operation of the embodiment. FIG. 5 is a diagram for explaining the operation of the embodiment. FIG. 6 is a diagram for explaining the operation of the embodiment. FIG. 7 is a diagram for explaining the operation of the embodiment. FIG. 8 is a diagram for explaining the operation of the embodiment. FIG. 9 is a diagram for explaining the operation of the embodiment. FIG. 10 is a diagram for explaining the operation of the embodiment.
DESCRIPTION OF SYMBOLS 20 ... Packet stream generation device, 21 ... Packet data generation part, 22 ... Packet length designation means, 23 ... Gap data generation part, 24 ... Gap length designation means, 25 ... Write processing part, 26 ... ... Write position detection means 27... Shift processing means 28... Write control means, 30 (1) to 30 (2N)... Memory 31. ...... Data selection means

Claims (2)

a packet data generation unit (21) for sequentially outputting a plurality of packet data having an arbitrary multiple of m bits (m is a plurality of constants) in an (m × n) bit width (n is a plurality of constants);
A packet length designating means (22) for designating the length of each packet data output from the packet data generating unit in units of m bits;
A gap data generator (23) that sequentially outputs a plurality of gap data having an arbitrary multiple of m bits to be inserted into gaps of packet data output by the packet data generator with an (m × n) bit width )When,
Gap length designating means (24) for designating the length of gap data output by the gap data generating unit in units of m bits;
2n memories (30 (1) to 30 (2N)) capable of independently writing and reading data in units of m bits;
Based on the packet length specified by the packet length specifying means and the gap length specified by the gap length specifying means, the packet data output from the packet data generation unit with an (m × n) bit width and the gap A write processing unit (25) for continuously and cyclically writing the gap data output with a (m × n) bit width from the data generation unit to the 2n memories in units of m bits;
Of the 2n memories, (m × n) bit width data composed of m bits of data written in the first to nth memories, respectively, and (n + 1) th to (2n) th data A process of alternately reading out (m × n) bit width data composed of m-bit data written in the memory is performed in parallel with the writing process by the write processing unit, and the packet data generation unit A packet stream generator comprising: a read processing unit (31) that outputs a packet stream in which the generated packet data and the gap data generated by the gap data generation unit are continuous with no gap (m × n) bit width. The write processing unit
Based on the packet length specified by the packet length specifying means and the gap length specified by the gap length specifying means, the write start position and write end position of the packet data and gap data in the 2n memories are determined. A desired writing position detecting means (26);
Based on the write start position and write end position obtained by the write position detection means, the packet data and gap data are shifted in units of m bits, and the final m bit data and gap data of the packet data are changed. Shift processing means (27) for outputting to the 2n memories in a state where the leading m-bit data is continuous and the last m-bit data of the gap data and the leading m-bit data of the next packet data are continuous When,
2. A packet stream generator according to claim 1, wherein said packet stream generator comprises: packet control data shifted by said shift processing means and write control means for writing gap data into said 2n memories.

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