JPS63298434A - Sequential memory circuit - Google Patents

Abstract

PURPOSE:To double the speed of a working cycle in the areas except the place near the 0-address data by using plural 2-port memories which performs the writing and reading jobs independently of each other and a register which detours the 0-address data to write the input data alternately to those memories and selecting data out of those memories and register respectively for output of them. CONSTITUTION:The memory circuits 4 and 5 are provided together with a register 3 which detours the 0-address data, a rite address clock generating circuit 8 which supplies a write clock to use both circuits 4 and 5 with switching and at the same time stops the supply of the write clock to those memory circuits while the write clock is supplied to the register 3, a selector 6 which selects and delivers the data of the register 3 and circuits 4 and 5, and a read address clock generating circuit 9 which supplies a selection signal to the selector 6. In such a constitution, the storing actions are carried out at a high speed with use of plural 2-port memories. At the same time, the data of the optional length can be written and read out within the capacity with addition of a 0-address register.

Description

[Detailed Description of the Invention] [Summary] In a sequential memory for a data buffer, there are multiple 2-port memories that perform writing and reading independently, and
A register that detours address data is provided, input data is written to memory alternately, and each data is selectively output from these registers and multiple memories, thereby doubling the operating cycle speed except for the vicinity of 0 address data. let

[Industrial application field]

The present invention relates to improvements in sequential memory circuits.

The present invention provides a sequential memory circuit that can be used as a data buffer or data storage device for speed conversion in a digital device that uses sequential data.

It is desired that such memory circuits be able to store large amounts of data at high speed.

[Conventional technology]

Conventionally, a circuit has been proposed in which a memory share method (memory switching method) is applied to sequential memory in order to increase the operating speed.

In the conventional memory sharing method, as shown in FIGS. 5a to 5e, multiple systems of memory are switched and used. Generally, two systems of memory sharing systems are used, and these systems can be roughly divided into two systems: simultaneous operation as shown in FIG. 5a, and alternate operation as shown in FIG. 5b.

In the case of simultaneous operation, input data is first taken into a buffer and then distributed to two memories.

The memories are even address memory A and odd address memory B.
It is divided into two parts. The first TOI period is a buffer acquisition cycle for distributing input data to two memories. The next Tll period is a memory write cycle, and input data is simultaneously written from the buffer to memory address 0 and address 1.

In the same manner, the buffer import cycle TOI is performed.

Memory write cycle T12 to addresses 2 and 3
Continued.

By using two memories and performing simultaneous operations in this way, data can be written faster than in the case of a single memory.

In the case of alternate operation, the memory is divided into two, an even address memory A and an odd address memory B, and input data is written to memory address θ after it is written to address 1, and then similarly to address 2, etc. Writing is performed alternately to address number 3.

In such alternating operation, the write period is the same as in the case of a single memory, and there is no improvement in the operating speed of the circuit.

Therefore, in order to improve this problem, a method was proposed in which memory writing is shifted by half a cycle and operated alternately, as shown in FIG. 5C. According to this method, the writing speed can be doubled.

[Problem that the invention seeks to solve]

In the case of the conventional simultaneous operation shown in FIG. 5a above, the period TOL TO which input data is taken into the buffer before being written to the memory is
2... is required. Therefore, it is not possible to double the memory write speed.

Although the alternating operation of FIG. 5c can double the operating speed, problems may occur depending on the number of data to be written.

FIG. 5d shows a case where the problem occurs when the number of data is odd. If there is an odd number of data and you try to store it in address addresses O to 2n, the last data will be written to address 2n of even address memory, and the next first data will be written to address 0 of even address memory. It will be done.

In the odd address memory, the 2nd-1st data and the 1st
A blank operation cycle portion shown by diagonal lines is generated between the number data. As a result, it is necessary to process blank areas when reading. Attempts to avoid this processing would increase the circuit scale, and there is a drawback that it would be difficult to operate writing and reading completely independently.

FIG. 5e shows writing without creating blank spaces. To do this, the write cycle for the final addresses 2n and 0 becomes half of the memory operation cycle. However, this is a physically impossible range and data cannot be written.

[Means for solving problems]

The above problems are solved as shown in the principle diagram of the present invention in FIG.
A plurality of memory circuits (4) (51, one register (3) for bypassing address O data, the memory circuit (4) (
5), a write address clock generation circuit (8) which supplies a write clock to be used by switching and stops the write clock to the memory circuit while supplying the write clock to the register (3); 3) and a memory circuit (41(5)) and a selector (6) that selects and outputs each data, and a read address clock generation circuit (9) that supplies a selection signal to the selector (6). Solved by sequential memory circuit.

[Effect]

According to the invention, the register 3 bypasses address 0 data to be written to one of the memory circuits 4.5 without writing it to the memory circuit.

Register 3 writes data at address 0, and this writing is performed using a one-pulse write clock generated by write address clock generation circuit 8.

The write address clock generation circuit 8 generates one register write clock of one pulse in response to a write reset signal obtained from the outside.

Write address clock generation circuit 8 stops the write clock to memory circuit 4.5 while this 0 address data write clock is being generated.

In reading, the read address clock generation circuit 9 generates a selection signal from a clock signal obtained from the outside, and supplies the selection signal to the 3-1 selector 6 according to the read address.
The selector 6 is switched in synchronization with an external clock to select and output each data in the 0 address register 3 and memory circuit 4.5.

A plurality of memory circuits are controlled in hardware by generating control signals in each address circuit.

The operating speed of the memory circuit is increased without any increase, and the addition of a 0 address register provides consistency in writing and reading even when the data length is variable.

〔Example〕

FIG. 2 is a block circuit diagram of an embodiment of the sequential memory of the present invention.

It is assumed that the input data consists of seven (odd number) data of 8m''G+w (m -0 to 6).The input data l is 0 address register 30, A memory 43, B memory 53.
written to. A write address clock generation circuit 8 is provided for writing to registers and memory.

The circuit 8 writes the write clock -CKA of the data register 41 and address register 42 of the A memory 43 and the data register 51 of the B memory 53 and the address register 52 from the write clock -CK and write reset l signal given from the outside. Clock CKB generates write address A for both address registers 42 and 52.

The operation of the circuit of FIG. 2 is shown in the time charts of FIGS. 3 and 4.

Input data A111Bll, Cral...Gra are given address numbers 0, 1.2,...6, and the end to the input data with address number 0 is changed to 0 address by (f) 0 register write clock - CKO. Written to register 3. The data of even numbers 2, 4, and 6 except for the 0 address are stored in the A memory via the data register 41 by the A memory write clock -CKA.

Similarly, odd numbered data 1.3.5.7 B-1Dts
sFm is stored in the B memory by the B memory write clock WCKB.

By providing the 0th address register 3, the data An+ that should originally be written in the A mesori as even number data.
is taken into register 3. This capture timing corresponds to the read reset signal WR given from the outside, and a pulse synchronized with the read clock is generated by l pulses.
While the address read pulse is being issued, the write clocks of memories A and B are stopped.

The writing time chart for the 0th address register is as shown in (k), and the data writing order for the register ASB is as shown in (1).

The circuit shown in FIG. 2 includes a read address clock generation circuit 9 and a 3→1 selector 6 in order to read and output written data.

The read address clock generation circuit 9 is externally supplied with a read clock RCK (2) and a read reset signal RR(n).

The read address clock generation circuit 9 supplies read clocks RCKA(p) and B to the address register 44 of the A memory 43.
Read clock RC to address register 54 of memory 53
B(Ql, read address RA to both registers 44 and 54)
(01, also send address register θ to selector 6, A
Selection signal (y
).

(tl) from memory, B memory, and O address selector
The data outputs of ~(V) are selected by the 3-1 selector in the memory order indicated by -), and the data outputs are regularly outputted to the output section of the 3→1 selector in the order of Am~GI11 as shown in (X). can get.

The selection signal (X) is synchronized with an external clock, and the three signals 0
, ASB selects each data of the O register, A memory, and B memory.

In this way, the external clock cycle ■ and the internal clock cycle ■ shown in the time charts of FIGS.
If the operation near address 0 is excluded, ■ becomes twice as fast as ■, and speeding up is possible.

〔Effect of the invention〕

As described above, according to the present invention, memory operation is speeded up by using a plurality of 2-boat memories, and by adding an O address register, it is possible to write and read data of arbitrary length within the capacity. Its effects are extremely large.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the present invention. FIG. 2 is a block circuit diagram of a sequential memory according to an embodiment of the present invention. FIG. 3 is a write time chart of a sequential memory circuit according to an embodiment of the present invention. A read time chart of a sequential memory circuit according to an embodiment of the present invention, FIG. 5a is a conventional simultaneous operation memory share method, and FIG.
Figure 5c shows the conventional memory share method with alternating operations; Figure 5c shows the conventional memory share method with alternating operations even in half cycles (odd data); Figure 5e shows the conventional memory share method with alternating operations that shifts half a cycle. (odd data). In the figure, 1 is input data, 2 is output data, 3 is a register, 4.5 is a memory circuit, 6 is a selector, 7 is an output register, 8 is a write address clock generation circuit, 9 is a read address clock generation circuit, 30 is 0 address register, 41.51 is data register, 42.52.44.54 is address register, 43 is A
Memory 53 is B memory. Figure 1 Block times of the nosequential memory according to an embodiment of the present invention Figure 2 Write time chart of the sequential memory circuit according to an embodiment of the present invention Conventional simultaneous operation memory sharing method % formula % Conventional Alternating operation memory sharing method Figure 5b

Claims (1)

[Claims] A plurality of memory circuits (4) (5), one register (3) for bypassing address 0 data, and the memory circuit (4) (5).
), and a write address clock generation circuit (8) that supplies a write clock for switching use of the register (3) and stops the write clock to the memory circuit when supplying the write clock to the register (3), and the register (3) , memory circuit (4) (5)
1. A sequential memory circuit comprising: a selector (6) for selecting and outputting each data; and a read address clock generating circuit (9) for supplying a selection signal to the selector (6).