JP3618283B2 - Burst receiving method and apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a burst receiving method and apparatus.
With the development of multimedia technology, optical communication using optical fibers is rapidly spreading. In particular, the mainstream, that is, the spread of optical communication on the station side has been mainly used so far, but from now on, the spread of optical communication in subscriber systems will be activated in order to realize FTTH (Fiber To The Home). The present invention describes a communication means between a station and a plurality of subscriber terminals, particularly a burst receiving apparatus that interfaces with each subscriber terminal in the station.
[0002]
[Prior art]
FIG. 25 is a diagram illustrating an example of the entire system to which the burst receiving apparatus is applied. In this figure, reference numeral 1 is a burst receiver, which receives an optical signal in the uplink transmission direction from the subscriber system to the station 2. The optical signal in the upstream transmission direction is transmitted via the optical transmission path and the star coupler 4.
[0003]
The subscriber system is composed of a plurality of subscriber terminals (# 1, # 2... #N) 5, and each subscriber terminal 5 has its own optical transmission signal in each predetermined time slot that does not conflict with each other. Are output to the burst receiver 1 in the station 2 in a burst form.
FIG. 26 is a diagram schematically showing the state of burst transmission. In this figure, the components given reference numerals 1, 2, 3 and 5 are as already described in FIG. An optical signal transmitted on the optical transmission line 3 toward the optical burst receiver 3 in the station 2 is shown as an OS (Optical Signal) in the figure, and is a light with # 1, # 2, and #N attached thereto. The signal OS is output from burst signal transmitters # 1, # 2 and #N in the subscriber terminal (5), respectively. The signal in the downlink transmission direction from the station 2 side to each subscriber terminal 5 is normally transmitted at the same time, and the distribution of transmission signals to each subscriber terminal 5 corresponds to each subscriber terminal. Is added to the transmission signal.
[0004]
The present invention relates to the burst transmission system as described above. As a typical example of such a burst transmission system, there is a PON (Passive Optical Network), and FIG. 25 also represents this PON. However, the present invention is not limited to such a burst receiving device (optical burst receiving device) in PON, but also a LAN (Local Area Network) or wireless communication to which a CSMA (Carrier Sense Multiple Access) method or a CD (Collision Detection) method is applied. The present invention can also be applied to a burst receiving device used in a network.
[0005]
Furthermore, the present invention is applied to a burst receiving apparatus that receives a packet or cell having a fixed burst length. The burst receiving apparatus includes a burst receiving unit for receiving a burst signal, and a burst receiving / synchronizing circuit for receiving an output burst signal output from the burst receiving unit and synchronizing the output burst signal in units of bits. It is a device basically composed of
[0006]
The above-described burst transmission system including such a burst receiver is required to perform operations specific to burst transmission. This becomes clearer when compared to a continuous transmission system. In this continuous transmission system, a retiming operation (re-establishing bit synchronization on the receiving side in the continuous transmission system) for received data continuously received from a transmission line is usually performed in a receiving unit incorporating a PLL or the like. Yes. This receiving unit is generally known as B / U MDL (Bipolar / Unipolar module) or optical MDL (module). As described above, the reception data continuously received can be easily retimed by the reception unit including the PLL or the like.
[0007]
However, in a burst transmission system that handles burst-like received data given intermittently from the transmission path, it is not as easy to perform retiming on the received data as in the case of the above-described continuous transmission. This is because, in the case of burst transmission, every time burst received data is input to the burst receiver, an optimum phase for punching out the burst received data must be detected within a very short time.
[0008]
Such high-speed detection of the optimum phase is difficult in the burst receiving unit composed of the B / UMDL, optical MDL, or the like, and is usually performed by the burst receiving / synchronizing circuit provided at the subsequent stage of the burst receiving unit. Is going. Then, by detecting the clock extraction data sequence (so-called preamble) added to the head of the burst main signal data forming the main part of the burst reception data by the burst reception / synchronization circuit, the above-mentioned re-reception for the burst reception data is performed. Timing is done.
[0009]
Now referring again to FIG.
(1) When the network in the figure is the above-described wireless communication network, the level of the signal in the uplink transmission direction (the radio packet or cell corresponding to the OS in the figure) at the input of the burst receiver 1 is It fluctuates depending on the distance of the wireless transmission path for each user terminal. on the other hand,
(2) When the network of this figure is a wired (fiber) communication network typified by optical communication, the level of an upstream transmission direction signal (such as an optical signal OS) at the input of the burst receiver 1 is It fluctuates depending on the length of the fiber length for each user terminal 5.
[0010]
In view of the characteristics inherent to such a burst transmission system, a burst receiving apparatus adapted to the inherent characteristics is generally employed.
FIG. 27 is a block diagram showing an example of a general burst receiving apparatus. The following description will be given by taking the case of the latter wired communication network, particularly the case of an optical communication network using fibers, as an example of the wireless and wired communication networks described above. Therefore, the general burst receiving apparatus 1 shown in this figure is an optical burst receiving apparatus.
[0011]
The burst receiving apparatus 1 receives burst received data from the optical transmission path at the burst receiving unit 10. The burst receiving unit 10 includes an optical / electrical converter (O / E), and its output is input to a burst receiving / synchronizing circuit 20 in the next stage to obtain target reproduction data.
The burst reception / synchronization circuit 20 will be described in more detail. The circuit 20 includes a sampling unit 21, an edge detection unit 22, an optimum phase search unit 23, a protection stage 24, and a selector 25, as shown.
[0012]
The sampling unit 21 receives the burst reception data output from the burst reception unit 10 and performs sampling. As described above, the burst reception data is composed of burst main signal data (for example, a 53-byte cell) and a clock extraction data sequence added to the head thereof. The sampling unit 21 first samples the head clock extraction data sequence. To do. This data string is normally alternating data of “1” and “0” bits, for example, 16 bits long. When taking bit synchronization, the change point of data from “1” to “0” and the change point of data from “0” to “1” are captured, and an almost intermediate phase between both change points is optimal for bit synchronization. Detect as phase. In other words, the phase of the master clock of the burst receiving apparatus 1 that is optimal for bit synchronization with the burst received data is detected. These data change points are data switching edges, and the edge detection unit 22 in FIG. 27 detects the edges.
[0013]
In order to detect the edge, the sampling unit 21 samples the clock extraction data string using, for example, a clock obtained by multiplying the bit rate of the alternating data of “1” and “0” bits by 8 as the master clock. Therefore, the edge detection unit 22 outputs eight types of edge detection results that are sampled by each of the multiplied clocks and that are out of phase with each other.
[0014]
The edge detection result is applied to the optimum phase search unit 23 shown in FIG. 27, where one clock for generating data change points (edges) of “1” → “0” and “0” → “1”, that is, the above-mentioned The clock with the optimal phase is extracted.
The search result by the optimum phase search unit 23 is not always reliable. This is because there is no guarantee that the data string for clock extraction always maintains the ideal duty of 100%, and the data string may contain noise.
[0015]
Therefore, in the protection stage 24 of FIG. 27, a more probable optimum phase search result is specified. Usually, when the same optimum phase search result appears twice in succession, this is regarded as a probable optimum phase.
Thus, the selector 25 in FIG. 27 outputs one sampling data designated by the protection stage 24 out of the eight types of sampling data that are output in parallel from the sampling unit 21, that is, sampling with bit synchronization. Select data. The main signal data in the sampling data is used as target reproduction data.
[0016]
[Problems to be solved by the invention]
The above description has been made on the assumption that the burst reception data provided from the burst receiver 10 to the burst reception / synchronization circuit 20 in FIG. 27 is an almost ideal signal.
However, in the case of burst transmission, it is extremely difficult to always obtain such ideal burst reception data. The format of one-cycle burst reception data input from the transmission path to the burst receiver 10 in FIG. 27 is generally “no signal” (guard) + “clock extraction data string” + “main signal data”. ing. The latter two data are as described above, but the first “no signal” (guard) is the nth (n = 1, 2, 3,...) Burst received data and the (n + 1) th burst. It is a space portion on the transmission line that is inserted so as not to cause a collision with received data. If there is no such space portion, in FIG. 26, for example, the subscriber terminal 5 that outputs the optical signal OS (# 1) is located far from the station 2, and the subscriber outputs the optical signal OS (# 2). When the terminal 5 is close to the station 2, the collision that occurs between both bursts cannot be avoided.
[0017]
When attention is paid to the burst receiver 10 of FIG. 27, there are the following two problems.
(1) The problem that noise may be included in a portion corresponding to the no signal (guard) in the burst reception data output from the receiving unit 10;
{Circle around (2)} Of the burst received data output from the receiving unit 10, there is a problem that the clock extraction data sequence may include a bit sequence that is out of duty 100%.
[0018]
The problem {circle around (1)} is considered to be caused by a threshold error in the “1” and “0” judging means in the burst receiver 10, and as a result, circuit noise is unavoidable from the receiver 10 itself. It will be sent out.
The above problem (2) is that, as shown in FIG. 26, if there is a large level fluctuation (reception light level strength) between the optical signal OS (# 1) and the next optical signal OS (# 2), The signal OS (# 2) is considered to be caused by a known phenomenon that “0” bit reproduction is not normally performed, and the data string for clock extraction is originally “1” “0” with a duty of 100%. Where the bit data should be alternating data, the duty is 120% or more or 80% or less. This is a duty outside the operable range in the burst reception / synchronization circuit 20.
[0019]
Regardless of the problems {circle around (1)} and {circle around (2)} described above, there is a problem that a malfunction occurs in the burst receiver 1 and normal reproduction data cannot be obtained.
Therefore, in view of the above problems, an object of the present invention is to provide a burst receiving method and apparatus capable of guaranteeing accurate operation.
In addition, it is an object of the present invention to provide a burst receiving method and apparatus capable of guaranteeing as accurate an operation as possible even if any possible failure in actual operation of burst transmission occurs due to the above problems. It is.
[0020]
[Means for Solving the Problems]
First, the situation that causes the above problems (1) and (2) will be described with reference to the drawings.
1A and 1B are signal pattern diagrams showing input and output signals of a burst receiver, wherein FIG. 1A is an ideal case and FIG. 1B is a practical case.
Referring to FIG. 1A, the column 1) is an input signal to the burst receiving unit 10, that is, optical burst reception data, and the column 2) is an output signal from the burst receiving unit 10, that is, optical / electrical conversion. This is the subsequent burst received data. Both are shown for one burst cycle (OS (# 1), OS (# 2)... OS (#N) in FIG. 26). As described above, one-cycle burst reception data includes “no signal” (guard), “clock extraction data”, and “main signal data” (original transmission information).
[0021]
Referring to FIG. 1 (B) in contrast to FIG. 1 (A), due to various characteristics inherent to the burst receiver 10, the output burst received data from the burst receiver 10 is not the same in actual operation. As shown in the column 2) of FIG. 4B, when there is no signal (space portion on the transmission line), noise NS (shown by right-down hatching) is included, and the clock extraction data string has an abnormal duty bit DB (left-down). Is highly likely to be included). If so, there is a possibility that an erroneous bit synchronization operation may be started due to the noise NS. Further, there is a possibility that accurate bit synchronization cannot be obtained due to the abnormal duty bit DB. Therefore, the present invention provides a receiving method described below.
[0022]
FIG. 2 is a flowchart showing the basic steps of the receiving method according to the present invention.
As shown in FIG. 27, a burst receiving apparatus to which this receiving method is applied is a bit receiver that receives burst received data from a transmission path and an output burst received data from the burst receiving unit 10 as input. And a burst reception / synchronization circuit 20 that outputs main signal data (see FIG. 1) included in the burst reception data as reproduction data.
[0023]
In FIG. 2, steps S1 and S2 are particularly characteristic of the present invention. Step S3 is not substantially different from the conventional one. Steps S1 and S2 are as follows.
Step S1: As an output from the burst receiving unit 10, in addition to the original output burst received data, a reception identification signal indicating that the level of the burst received data input to the burst receiving unit 10 exceeds a predetermined level Is output.
[0024]
Step S2: Until the reception identification signal is output, it is prohibited to input the output burst reception data from the burst receiving unit 10 to the burst reception / synchronization circuit 20.
Taking the signal pattern shown in FIG. 1 as an example, when the burst received data from the transmission line has a signal pattern in which no signal, a data sequence for clock extraction, and main signal data have one burst cycle, the burst receiving unit 10 While no signal pattern is being input, input of the output burst reception data to the burst reception / synchronization circuit 20 is prohibited due to the non-output of the reception identification signal. This is shown in FIG.
[0025]
FIG. 3 is a signal pattern diagram schematically showing the receiving method according to the present invention. The columns 1) and 2) in this figure are almost the same as those in FIG. The column 3) of this figure is the reception identification signal RD generated based on step S1 of FIG. The column 4) of this figure is a mask signal MK that inhibits the input of the output burst reception data to the burst reception / synchronization circuit 20 until the reception identification signal is generated based on step S2 of FIG.
[0026]
FIG. 4 is another signal pattern diagram schematically showing the receiving method according to the present invention.
As shown in FIGS. 1B and 3, the burst reception data from the transmission line has a signal pattern in which no signal, a clock extraction data string, and main signal data are one burst cycle. When there is a possibility that at least a part of the data sequence for clock extraction is abnormal data while the burst receiving unit 10 is inputting the data sequence for clock extraction following the signal pattern of no signal, 3 in FIG. ) And 4), after the reception identification signal RD starts to be output, the period (T) during which the abnormal data is masked, the mask burst signal MK is used to input the output burst reception data to the burst reception / synchronization circuit 20. Continue to ban.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 5 is a signal pattern diagram when the first possible failure occurs in burst transmission. The first failure is that, for example, most of the data sequence for clock extraction is lost when the burst signal is transmitted due to a failure of the burst signal transmission device (FIG. 26) (see column 1 in FIG. 5). It is an obstacle.
[0028]
If most of the data string for clock extraction becomes ALL “0” in this way, the burst receiving unit 10 causes noise during the period corresponding to ALL “0” as shown in the column 2) of FIG. NS will continue to be output. When such output burst reception data (noise NS) is input to the next-stage burst reception / synchronization circuit 20, a protection mode as indicated by a circle in FIG. That is, in the protection stage 24 of FIG. 27, it has been determined that the optimum phase search is performed by the optimum phase search unit 23 twice in succession, that is, the protection has been taken (see A), then Is a protection mode in which it is determined that protection cannot be obtained (see B).
[0029]
In this case, it is determined that the protection is obtained at A, but this determination is made not for the original clock extraction data string but for the noise NS as shown in the figure. Even if the received burst received data is bit-synchronized according to the protection certification, the reliability of the bit synchronization is very low. That is, there is a high possibility that correct retiming is not performed. As a result, so-called data corruption occurs. This is because a setup / hold margin for sampling data is obtained.
[0030]
On the other hand, the case of B occurs following the case of protection by A, but the search for the third optimum phase in the figure in the case of B is highly reliable. This is because this search is performed on the original data string for clock extraction that deviates from the noise NS. However, despite the high reliability, it is not finally adopted as the optimum phase. This is because the data sequence for clock extraction is short and the search cannot be performed twice in succession, and protection cannot be obtained.
[0031]
In the above case, the following inconveniences are brought about at the same time. In the above case, retiming fails after all. Then, an abnormality notification that the normal burst data could not be received is given to the maintenance personnel of the station 2. However, the true cause of the retiming failure is a failure of the burst signal transmission apparatus or a failure on the transmission path, and not just a burst reception error. It is inconvenient in the above case that the true cause cannot be correctly notified to the maintenance person.
[0032]
According to the present invention, even if the first failure described above occurs, the burst receiving apparatus can be operated as accurately as possible. This will be described with reference to FIG.
FIG. 6 is a signal pattern diagram illustrating the method of the present invention for dealing with the first failure shown in FIG. The columns 1) and 2) of this figure are the same as the columns 1) and 2) of FIG. 5, and the columns 3) and 4) of this figure are the same as 3) and 4) of FIG. Corresponds to the column.
[0033]
According to the present invention, until the reception identification signal RD is output (column 3 in FIG. 6), the mask signal MK exists as an inverted signal of the signal RD (column 4 in FIG. 6). Therefore, by this mask signal MK, not only when there is no burst reception data, but also during the period when the data string for clock extraction has been lost as ALL “0”, the burst reception unit 10 performs the burst reception / synchronization circuit. The input of the output burst reception data to 20 is prohibited.
[0034]
This avoids the above-described problem of erroneous bit synchronization with respect to the noise NS that appears during the ALL “0” period.
In addition, there is a possibility that the optimum phase can be searched at least once with respect to a slight remaining normal clock extraction data string (see the circles in the column 4 of FIG. 5). What should be noted here is that the portion marked with ○ is in the latter half of the original data sequence for clock extraction, and the bit pattern of alternating “1” and “0” is very stable. Then, the protection operation by the protection stage 24 described above is omitted in this case, and even if the search for the optimum phase is performed once, even if the above-described master clock is selected by the selector 25 with the optimum phase of 1, There is no problem in operation. In this case, the operation of the protection stage 23 is suspended by the mask signal MK that continues beyond the time of no signal. It can be easily determined whether or not the mask signal continues longer than when there is no signal. For example, in the PON described above, the system information on which time slot the station 2 should use for each subscriber terminal 5, that is, which subscriber terminal uses which time slot, is previously stored in each subscriber terminal. Giving. Therefore, the station 2 also knows at what timing in the time slot the data sequence for clock extraction starts. If this is utilized, it can be easily determined whether or not the mask signal MK continues for a long time from the start of the data sequence for clock extraction.
[0035]
FIG. 7 is a signal pattern diagram when a second failure that can be considered in burst transmission occurs. The columns 1) to 4) in the figure correspond to the columns 1) to 4) in FIG. 6, but are substantially the same as the columns 1) to 4) in FIG.
In the case of FIG. 5 (first failure case), it is a failure case in which most of the clock extraction data string is lost due to some failure and becomes ALL “0”. In FIG. This represents a case where the head of the column is not normal. As described above, the bit pattern of alternating “1” and “0” is unstable at the beginning of the clock extraction data string, and the duty is outside the range in which the burst reception / synchronization circuit 20 can normally perform the bit synchronization operation. (DB in column 2 of FIG. 7).
[0036]
Then, if the mask signal MK is disabled at the same time when the reception identification signal RD rises, the burst reception / synchronization circuit 20 starts a retiming operation at the abnormal duty bit DB.
In such a case, the optimum phase search may be performed within the period of the abnormal duty bit DB, and protection may be taken (first optimum phase search “a” in the column (4) in FIG. 7). And second optimum phase search “b”). Even if protection by such two searches is taken (A in the figure), it cannot be said that the protection has been taken accurately. After that, when the optimum phase search (see “C” in the figure) is performed on the original stable clock extraction data string, this is almost certainly an accurate search. However, since the search “b” immediately before that does not match the content of the search result, protection cannot be obtained (B in the figure), and the burst receiving apparatus 1 does not operate correctly. Therefore, according to the present invention, the problem is dealt with as shown in FIG.
[0037]
FIG. 8 is a signal pattern diagram illustrating the method of the present invention that addresses the second failure shown in FIG. The way of viewing this figure is exactly the same as that of FIG.
As shown in the column 4) in FIG. 8, according to the present invention, the timing of disabling the mask signal MK is slightly delayed from the rising edge of the reception identification signal RD. As a result, the abnormal duty bit DB can be sufficiently masked, and the burst reception / synchronization circuit 20 can execute the retiming operation using only the portion of the stable original data sequence for clock extraction. FIG. 8 shows a state where protection is obtained by matching the results of the two optimum phase searches “a” and “b”. The number of bits of the abnormal duty bit DB is generally about 5 bits.
[0038]
Further, comparing the rising edge of the reception identification signal RD shown in the column 3) of FIG. 7 with the rising edge of the signal RD in the column 3) of FIG. 8, in the latter case, the rising edge of the signal RD is the data string for clock extraction. It is shown that it is delayed by Δt from the head of. The reason for this is as follows.
Looking at the reception identification signal RD, there is no guarantee that the signal RD is always generated only at the beginning of the data string for clock extraction. Noise generated in the burst receiver 10 for some reason may be mistaken as a reception identification signal.
[0039]
Therefore, protection is provided when the reception identification signal RD is output, and the reception identification signal is made effective only when the reception identification signal RD is continuously output at least twice. The above-described Δt represents the delay required for this protection operation.
Further, regarding the reception identification signal RD, there is a problem of fluctuation of the rising edge of the signal RD itself. This will be described with reference to FIG.
[0040]
FIG. 9 is a signal pattern diagram for explaining a problem with the reception identification signal. It is assumed that the head of the data sequence for clock extraction is detected by the burst receiver 10 and the reception identification signal RD is output at d in FIG. After d, the mask signal MK is disabled by delaying the abnormal duty bit DB by a time d that can be masked. However, if this delay time is short, the abnormal duty bit DB that cannot be completely masked remains as shown in the column 4) of this figure, and the burst reception / synchronization circuit 20 cannot perform retiming normally. Therefore, the delay time requires a sufficient time to sufficiently mask the abnormal duty bit DB.
[0041]
On the other hand, when considering the rise of the reception identification signal RD itself, in reality, it does not always rise at time d in 3) of FIG. In other words, it has been found that the signal RD rises up to the time indicated by e in FIG. That is, the fluctuation of the rising edge of the reception identification signal RD. This fluctuation occurs with a width of 1 to 5 bits, for example.
[0042]
As a result, it is safest to determine the disabling timing of the mask signal MK given to the burst reception / synchronization circuit 20 from the worst time e. That is, it is desirable to disable the mask signal when the time e + the delay time has elapsed.
Then, referring to the column 4) in FIG. 9, the mask signal MK is disabled when the time t has passed after the end of DB. In this case, since the period of time t is already in the stable data sequence for clock extraction, the stable data sequence is discarded without being taken into the retiming operation.
[0043]
FIG. 10 is a signal pattern diagram for explaining the method of the present invention for solving the problem shown in FIG. The basic idea of this solution is to generate rising information indicating the rising time of the reception identification signal RD in the burst receiving unit 10 and shorten the period for masking abnormal data as the rising time is short. Is to do. The abnormal data here is, for example, the above-described abnormal duty bit DB.
[0044]
The rising information indicating the rising time in the above concept is illustrated as the rising information IR in the column 4) of FIG. 10, and the rising time in this example is 1 bit. That is, the reception identification signal RD represents that the rising edge is delayed by the time of one bit of the clock extraction data string. This is an example, and for example, it may take 10 bits to rise.
[0045]
In this way, by notifying the burst reception / synchronization circuit 20 of the rise time by the rise information IR, the circuit 20 shifts the output burst reception data by the minimum time corresponding to the rise time and then enters the retiming operation. In this case, the number of bits of the stable clock extraction data string that will be lost at this time can be minimized.
[0046]
There is a further problem with the reception identification signal RD. This will be described with reference to FIG.
FIG. 11 is a signal pattern diagram for explaining another problem relating to the reception identification signal. The reception identification signal RD generated in the burst receiving unit 10 is also a command to execute a retiming operation for the burst reception / synchronization circuit 20. Therefore, the disappearance of this command (RD) during the retiming operation leads to a malfunction of the burst receiver 1.
[0047]
Referring to the column 3) in FIG. 11, the reception identification signal RD disappears at time f, for example. Although the occurrence of such a case is low in probability, it will lead to a serious accident, so countermeasures are required. Referring to columns 3) and 4) in FIG. 11, the tail part of the clock extraction data sequence is lost after time f, and therefore the original main signal data is also lost.
[0048]
FIG. 12 is a signal pattern diagram for explaining the method of the present invention for solving the problem shown in FIG. The basic idea of this solution is that when the reception identification signal RD is output, the reception identification signal is latched so that the output of the reception identification signal RD is held for a certain period.
Referring to columns 3) and 4) in FIG. 12, signal RD ′ in column 4) is a reception identification signal generated by latching original reception identification signal RD in column 3). By this signal RD ′, the supply of data to the burst reception / synchronization circuit 20 is not interrupted as shown in the column 5) of FIG. The latched signal RD ′ is canceled by the reset RST shown in the column 4) of FIG. For example, in the above-described PON or the like, the reset signal RST is a necessary signal in the station 2, and thus this signal may be used to release the latch.
[0049]
FIG. 13 is a signal pattern diagram for explaining the third obstacle in the burst receiving apparatus and the method of the present invention for solving this. When an abnormal condition as shown in the column 2) of this figure occurs, the burst receiver 1 naturally becomes inoperable. Conventionally, an alarm that analyzes the cause of such an abnormal condition is issued. There was a problem that recovery was delayed.
[0050]
However, under the present invention, it is possible to issue an alarm that clarifies the cause of the abnormal state. In this method, the burst reception data from the transmission line has a signal pattern in which no signal, a clock extraction data string, and main signal data are one burst cycle, and the burst reception unit 10 receives the clock extraction data string. When the reception identification signal RD is not output in the phase that is expected to be performed, it indicates that the ALL “0” abnormality of the clock extraction data string or that a failure has occurred in the transmission of the clock extraction data string from the transmission side An alarm is sent out.
[0051]
W shown in the column 5) of FIG. 13 represents a phase, that is, a window where the clock extraction data string is predicted to arrive. As already described, for example, in the PON, since the station 2 has previously notified each subscriber terminal as system information as to which phase the clock signal should be transmitted from which subscriber terminal. The position of W is naturally recognized by the burst receiver 1 in the station 2.
[0052]
The fact that the reception identification signal RD is output only after leaving the range of the window W means that there is substantially no clock extraction data string in at least the window W, and the clock extraction data string is ALL “0”. It can be seen that the data string is not transmitted due to a failure on the transmission side. The column 4) in FIG. 13 shows an example that does not correspond to the above abnormal state. When the reception identification signal RD rises in the window W, at least the above-mentioned ALL “0” abnormality or transmission abnormality is present. Not applicable.
[0053]
FIG. 14 is a signal pattern diagram for explaining the fourth obstacle in the burst receiving apparatus and the method of the present invention for solving this. When an abnormal condition as shown in the column 2) of this figure occurs, the burst receiver 1 naturally becomes inoperable. Conventionally, an alarm that analyzes the cause of such an abnormal condition is issued. There was a problem that recovery was delayed.
[0054]
However, under the present invention, it is possible to issue an alarm that clarifies the cause of the abnormal state. In this method, the burst reception data from the transmission line has a signal pattern in which no signal, a clock extraction data string, and main signal data are one burst cycle, and the burst reception unit 10 receives the clock extraction data string. When the reception identification signal RD is output in the phase that is expected to be performed, but bit synchronization is not achieved in the burst reception / synchronization circuit 20, a data error has occurred in the data string for clock extraction. An alarm is sent.
[0055]
As shown in the column 5) of FIG. 14, it is assumed that the phase is predicted to receive the data sequence for clock extraction, that is, within the window W. In this window W, it is assumed that the reception identification signal RD rises (see column 3). In such a case, as shown in the column 2) of FIG. 3, when the optimum phase search is not protected and eventually the retiming in the burst reception / synchronization circuit 20 fails, the data string for clock extraction itself Appears, it is expected that there is a data error in the contents of this data string. Therefore, the alarm can be sent out.
[0056]
FIG. 15 is a signal pattern diagram of FIG. 14 when there is no abnormal state. In this case, as shown in the column 2) of the figure, the optimum phase search “a” and “b” are protected, and the retiming operation in the burst reception / synchronization circuit 20 is normally performed.
A burst receiving apparatus for implementing the above-described burst receiving method according to the present invention will be described below. This burst receiving apparatus is an embodiment based on the present invention.
[0057]
FIG. 16 is a block diagram showing an embodiment of a burst receiving apparatus according to the present invention. The basic configuration is burst reception data D from the transmission path. _in , And burst output data B output from the burst receiver 10 _out The main signal data contained in the received burst data is converted into the reproduced data D _out Is a burst receiving / synchronizing circuit 20 that outputs as a burst receiving device 1.
[0058]
Here, the constituent elements that characterize the present invention are burst received data B _out A reception identification signal generating means 31 for outputting a reception identification signal RD indicating that the level of the signal exceeds a predetermined level;
At least until the reception identification signal RD is output, the output burst reception data B from the burst receiving unit 10 _out Is mask means 32 for prohibiting the input to the burst reception / synchronization circuit 20.
[0059]
FIG. 17 is a circuit diagram showing a specific configuration example of the embodiment shown in FIG. In this figure, the mask detection means 32 in FIG. 16 includes, as an example, a reception identification signal protection unit 41, a reception identification signal optimization unit 42, a valid data string creation unit 43, and a rise time detection unit 44.
In FIG. 17, the alarm detection means 33 for sending out the alarm described above and the burst signal processing unit 45 are also shown.
[0060]
As described above, the mask means 32 includes the valid data string creation unit 43, which creates output burst reception data B from the burst reception unit 10. _out Is transferred to the burst reception / synchronization circuit 20 in accordance with the mask signal MK.
The reception identification signal protection unit 41 constituting the masking unit 32 outputs the reception identification signal as a valid reception identification signal only when the reception identification signal RD is continuously output at least twice. Further, this is supplied to the reception identification signal optimization unit 42 in the next stage.
[0061]
Further, as described above, the mask unit 32 includes the rise time detection unit 44 that detects and outputs the rise time of the reception identification signal RD output from the reception identification signal generation unit 31 and the reception identification signal optimization unit 42 described above. The reception identification signal optimization unit 42 outputs the reception identification signal RD output from the reception identification signal protection unit 41 by an amount corresponding to the rise time of the reception identification signal RD detected by the rise time detection unit 44. shift. The rise time of the reception identification signal RD is included in the rise information IR described above (see FIG. 10).
[0062]
As described above, the burst receiver 1 further includes the alarm detection unit 33, and the alarm detection unit 33 receives the data sequence for clock extraction added to the head of the main signal data at the burst reception / synchronization circuit 20. The arrival phase information P predicted to be transmitted, the bit synchronization incomplete information Q indicating that the bit synchronization by the data sequence for clock extraction has not been completed in the burst reception / synchronization circuit 20, and the reception identification signal RD is the reception identification signal. At least three pieces of information of reception identification presence / absence information R indicating whether or not it has been output from the generation means 31 are input, and the above-described alarm ALM for determining abnormal reception of the clock extraction data string and notifying the outside is transmitted. (See FIGS. 13 and 14).
[0063]
FIG. 18 is a diagram (part 1) illustrating a main part of the burst signal processing unit 45 illustrated in FIG.
FIG. 19 is the same drawing (No. 2).
FIG. 18 shows a PG decoder (Pulse Generator decoder) 51, and the master clock CLK in the burst receiver 1 already described. _m 17 and a decoder 62 for decoding the count value from the counter 61, and various decode outputs from the decoder 62 correspond to the corresponding blocks (blocks 41, 41 in FIG. 17). 42, 43..., Etc.) are supplied as respective timing signals U.
[0064]
FIG. 19 shows the retiming circuit 52. The retiming circuit 52 is composed of a D-FF 63, and the data input D thereof is the reproduction data D from the burst reception / synchronization circuit 20. _out Is applied to the master clock CLK. _m Is applied.
Reproduction data D _out Since some phase jitter remains in the _out Is input to the retiming circuit 52, and the master clock CLK is completely input. _m Playback data D synchronized with _out Get ′.
[0065]
FIG. 20 is a diagram illustrating a detailed example of the valid data string creation unit 43 illustrated in FIG. The valid data string creation unit 43 includes an AND circuit 64 having the output burst reception data from the burst reception unit 10 as a first input and the signal S obtained by delaying the output timing of the reception identification signal RD as a second input. Consists of including.
The signal S may be a mask signal MK from the reception identification signal optimization unit 42 shown in FIG. 17, or a signal obtained by performing predetermined processing on the reception identification signal RD as shown in FIG. But you can. The predetermined processing is processing by the shift register 66 that gives a delay to the RD and the D-FF that receives the output. The D-FF 65 receives a latch timing signal U1 which is one of various timing signals U from the PG decoder 51 (FIG. 18) at its enable input E, receives the output of the shift register 64 at its data input D, and resets it. Reset by the signal RST. This reset signal RST is as shown in the column 4) of FIG. 12, and is given as one of various timing signals U (FIG. 18).
[0066]
FIG. 21 is a diagram showing a detailed example of the reception identification signal optimization unit 42 shown in FIG. In this figure, the reception identification signal optimization unit 42 includes a shift register 71 and a selector 72.
The shift register 71 receives the reception identification signal RD that has passed through the reception identification signal protection unit 41, and outputs n types of signals RD that are phase-shifted bit by bit. Any one of these n types of signals RD is selected by the selector 72 in the next stage. Which one is selected is determined in accordance with the rising information IR from the rising time detector 44 (FIG. 17), and the selected one signal RD is applied to the valid data string generator 43 as the mask signal MK. The rise information IR is as described in the column 4) of FIG.
[0067]
FIG. 22 is a diagram showing a detailed example of the reception identification signal protection unit 41 shown in FIG. As shown in the figure, the protection unit 41 includes a D-FF group 73 and an AND circuit 74 that are connected in cascade.
The D-FF group 73 uses the reception identification signal RD as the master clock CLK. _m Shift to the output side in synchronization with. When the signal RD of logic “1” is output from all the FFs, the output from the AND circuit 74 becomes a protected reception identification signal RD. In this case, if two protection stages are sufficient, two FFs are sufficient.
[0068]
FIG. 23 is a diagram showing a specific example of the alarm detection means 33 shown in FIG. The means 33 is composed of an AND circuit 75 and a D-FF 76 as shown.
The AND circuit 75 receives information P, Q and R as inputs. These pieces of information are as described with reference to FIG. 17, and the output of the AND circuit 75 determined by these is applied to the data input D of the D-FF 76, while the enable input E is the various inputs shown in FIG. A latch timing signal U2 which is one of the timing signals U is input.
[0069]
When the conditions (P, Q, and R) described with reference to FIG. 13 or FIG. 14 are satisfied, an alarm ALM is transmitted and an abnormality in the data string for clock extraction is notified to the outside.
FIG. 24 is a diagram showing a specific example of the burst receiving unit 10 shown in FIG. Burst received data D received at the photodiode PD _in The (optical signal OS) is converted into an electrical signal and then processed by each of the circuit elements 81 to 88 shown. Reference numeral 81 is a preamplifier, 82 is a main amplifier, 83 is an output buffer, 84 is a peak detector, 85 is a DC feedback unit, 86 is a 1/2 divider, 87, 88-a1 and 88-an are main amplifiers, 87 -1 is an output buffer, 88 is a table, and 88-b1 and bn are output buffers.
[0070]
In these circuit elements, the optical signal received by the PD is converted into a current, sent to the preamplifier 81, and converted into a voltage signal in the preamplifier 81. From this voltage signal, a peak detection unit 84 detects a “1” level voltage, and a DC feedback unit 85 detects a “0” level voltage. Note that the voltage value of the level detection result varies for each burst reception (because the light level differs for each burst reception).
[0071]
In the ½ divider 86 that halves the difference between the voltage value of “1” level in the peak detection unit 84 and the voltage value of “0” level in the DC feedback unit 85, the final data is A threshold voltage to determine whether it should be “0” or “1” is created, and the threshold voltage is applied to the main amplifier 82 so that a data string of “0” and “1” is obtained from the voltage signal output from the preamplifier 81. Input from the two-divider 86. Although the output of the main amplifier 82 is a “0” or “1” data string, it is necessary to provide an interface operable by the valid data string creating unit 43. That is the output buffer 83.
[0072]
Looking at the reception identification signal RD, a voltage value, which is a detection result of the “1” level in the peak detection unit 84, is input to the main amplifier 87, and a threshold voltage whose voltage value indicates a predetermined constant level is voltage-controlled. An output buffer for inputting to the main amplifier 87 from the unit 89 and outputting a signal from the main amplifier 87 when the voltage value from the peak detecting unit 84 exceeds the threshold value, and to make an interface operable in the logic unit at the subsequent stage. A reception identification signal RD is output from 87-1.
[0073]
In addition, when a delay occurs until the reception identification signal is output depending on the reception level due to the MDL configuration, a plurality of threshold values corresponding to the delay amount are previously set from the voltage control unit 89 to the main amplifier (88-a1, 88). -An), and when the voltage value from the peak detector 84 exceeds the threshold value, a signal is output from the main amplifier (88-a1 to an). Based on this signal, the rising information IR is output by pulling a table 88 formed of, for example, a ROM. When the table 88 is drawn, output buffers (88-b1 to bn) are provided in order to provide an operable interface.
[0074]
【The invention's effect】
As described above in detail, according to the present invention, even if a nozzle inevitably generated due to its characteristics is generated from the burst receiving unit 10 itself, the burst receiving / synchronizing circuit 20 connected to the subsequent stage of the burst receiving unit 10 The bit synchronization can be achieved without being affected by the noise, and an accurate retiming operation of the burst receiving apparatus is guaranteed.
[Brief description of the drawings]
1A and 1B are signal pattern diagrams showing input and output signals of a burst receiving apparatus, wherein FIG. 1A is an ideal case and FIG. 1B is a practical case.
FIG. 2 is a flowchart showing basic steps of a receiving method according to the present invention.
FIG. 3 is a signal pattern diagram schematically showing a receiving method according to the present invention.
FIG. 4 is another signal pattern diagram schematically showing the receiving method according to the present invention.
FIG. 5 is a signal pattern diagram when a first failure that can be considered in burst transmission occurs.
6 is a signal pattern diagram illustrating a method of the present invention that addresses the first failure shown in FIG.
FIG. 7 is a signal pattern diagram when a second failure that can be considered in burst transmission occurs.
FIG. 8 is a signal pattern diagram illustrating a method of the present invention that addresses the second failure shown in FIG.
FIG. 9 is a signal pattern diagram for explaining a problem with a reception identification signal.
10 is a signal pattern diagram for explaining the method of the present invention for solving the problem shown in FIG. 9;
FIG. 11 is a signal pattern diagram for explaining another problem relating to the reception identification signal.
12 is a signal pattern diagram for explaining the method of the present invention for solving the problem shown in FIG.
FIG. 13 is a signal pattern diagram illustrating a third obstacle in the burst receiving apparatus and the method of the present invention for solving the third obstacle.
FIG. 14 is a signal pattern diagram illustrating a fourth obstacle in the burst receiving apparatus and the method of the present invention for solving the same.
15 is a signal pattern diagram of FIG. 14 in the case of not being in an abnormal state.
FIG. 16 is a block diagram showing an embodiment of a burst receiver according to the present invention.
17 is a circuit diagram showing a specific configuration example of the embodiment shown in FIG. 16;
18 is a diagram (No. 1) illustrating a relevant part of the burst signal processing unit 45 illustrated in FIG. 17;
FIG. 19 is a diagram (No. 2) illustrating a substantial part of the burst signal processing unit 45 illustrated in FIG. 17;
20 is a diagram illustrating a detailed example of a valid data string creation unit 43 illustrated in FIG.
FIG. 21 is a diagram illustrating a detailed example of a reception identification signal optimization unit 42 illustrated in FIG. 17;
22 is a diagram showing a detailed example of a reception identification signal protection unit 41 shown in FIG.
FIG. 23 is a diagram showing a specific example of alarm detection means 33 shown in FIG.
24 is a diagram illustrating a specific example of a burst receiving unit 10 illustrated in FIG.
FIG. 25 is a diagram illustrating an example of an entire system to which a burst receiving device is applied.
FIG. 26 is a diagram schematically showing a state of burst transmission.
FIG. 27 is a block diagram illustrating an example of a general burst receiving apparatus.
[Explanation of symbols]
1: Burst receiver.
2 ... Station
5 ... Subscriber terminal
10: Burst receiver
20 ... Burst reception / synchronization circuit
21 ... Sampling part
22 Edge detection unit
23 ... Optimal phase detector
24 ... Protection stage
25 ... Selector
31. Reception identification signal generating means
32. Mask means
33. Alarm detection means
41. Reception identification signal protection unit
42. Reception identification signal optimization unit
43 ... Valid data string creation section
44. Rise time detector
45 ... Burst signal processor
64 ... AND circuit
OS: Optical signal
NS ... Noise
DB: Abnormal duty bit
RD: Reception identification signal
MK ... Mask signal
IR ... rise information
RST ... Reset
W ... Window
B _out ... Output burst received data
D _in ... Burst received data
D _out ... reproduction data
CLK _m ... Master clock

Claims (9)

A burst receiver for inputting burst reception data from the transmission path;
In a burst receiver having a burst reception / synchronization circuit that outputs main signal data included in the burst reception data as reproduction data by taking bit synchronization with the output burst reception data from the burst reception unit as input,
(I) As an output from the burst receiving unit, in addition to the output burst received data, a reception identification signal indicating that the level of the burst received data input to the burst receiving unit exceeds a predetermined level A step of outputting
(Ii) a step of prohibiting input of output burst reception data from the burst reception unit to the burst reception / synchronization circuit at least until the reception identification signal is output. ,
In the step (i), when the reception identification signal is output, the reception identification signal is latched so as to hold the reception identification signal for a certain period, and
In the step (ii), when the burst reception data from the transmission path has a signal pattern in which no signal, a clock extraction data string, and the main signal data are one burst cycle, the burst reception unit During the input of the signal pattern, the step of prohibiting the input of the output burst reception data to the burst reception / synchronization circuit due to the non-output of the reception identification signal ;
While the burst receiving unit is inputting the clock extraction data sequence following the no-signal signal pattern, masking a part of the clock extraction data sequence after the reception identification signal starts outputting, burst reception method characterized by a step of subsequently prohibit input to the burst receiver / synchronization circuit of the output burst received data. Rising information indicating a rising time of the reception identification signal is generated in the burst receiving unit, and a period for masking a part of the data string for clock extraction is shortened according to the short rising time. Item 2. A burst receiving method according to Item 1. The burst receiving method according to claim 1, wherein protection is provided when the reception identification signal is output, and the reception identification signal is made effective only when the reception identification signal is output at least twice in succession. The burst reception data from the transmission line has a signal pattern in which no signal, a clock extraction data string, and the main signal data are one burst cycle, and the burst reception unit receives the clock extraction data string. When the received identification signal is not output in a phase that is expected to be
2. The burst reception method according to claim 1, wherein an alarm indicating that ALL “0” of the clock extraction data string is abnormal or that a failure has occurred in transmission of the clock extraction data string from the transmission side is transmitted. The burst reception data from the transmission line has a signal pattern in which no signal, a clock extraction data string, and the main signal data are one burst cycle, and the burst reception unit receives the clock extraction data string. If the bit synchronization is not achieved in the burst reception / synchronization circuit even though the reception identification signal is output in the phase that is expected to be, a data error has occurred in the data string for clock extraction. The burst receiving method according to claim 1, wherein an alarm is transmitted. A burst receiver for inputting burst reception data from the transmission path;
A burst receiving device having a burst receiving / synchronizing circuit that outputs main signal data included in the burst received data as reproduction data by taking bit synchronization with the output burst received data from the burst receiving unit as an input And a reception identification signal generating means for outputting a reception identification signal indicating that the level of the burst reception data exceeds a predetermined level, and
A burst receiving device comprising: masking means for prohibiting the input of the burst reception data from the burst reception unit to the burst reception / synchronization circuit until at least the reception identification signal is output;
The mask means has a signal pattern in which the burst reception data from the transmission line has no signal, a data sequence for clock extraction, and the main signal data as one burst cycle. While inputting a pattern, by not outputting the reception identification signal, prohibiting input of the output burst reception data to the burst reception / synchronization circuit,
The mask means is configured to input a part of the clock extraction data sequence after the reception identification signal starts outputting while the burst receiving unit is inputting the clock extraction data sequence following the no-signal signal pattern. Is also masked, and the input of the output burst received data to the burst receiving / synchronizing circuit is continuously prohibited , and
The mask means includes a reception identification signal protection unit that outputs the reception identification signal as a valid reception identification signal only when the reception identification signal is continuously output at least twice, and a reception identification signal optimization unit. A burst receiving apparatus , wherein the reception identification signal optimization unit shifts the received identification signal output from the reception identification signal protection unit and further latched into a mask signal . It said mask means comprises further comprises a valid data sequence creation unit,
The valid data sequence creation unit includes an AND circuit having the output burst reception data from the burst reception unit as a first input and a signal obtained by delaying the output timing of the reception identification signal by a predetermined time as a second input. 6. The burst receiving device according to 6 . It said mask means further makes a rise time detector which detects and outputs the rise time of the received identification signal output from the reception identification signal generating means,
The reception identification signal optimization unit shifts the reception identification signal output from the reception identification signal protection unit by an amount corresponding to a rise time of the reception identification signal detected by the rise time detection unit. 6. The burst receiving device according to 6 . Further comprising an alarm detection means,
The alarm detection means includes arrival phase information in which a clock extraction data sequence added to the head of the main signal data is predicted to arrive at the burst reception / synchronization circuit, and the clock in the burst reception / synchronization circuit. Input at least three pieces of information: bit synchronization incomplete information indicating that bit synchronization by the extraction data string is incomplete, and reception identification presence / absence information indicating whether or not the reception identification signal is output from the reception identification signal generating means 7. The burst receiving apparatus according to claim 6 , wherein an alarm for determining abnormal reception of the data string for clock extraction and sending an alarm for notification to the outside is sent.

Images