JP3615478B2 - Memory access arbitration method - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a memory access arbitration method in a digital copying machine or the like.
[0002]
[Prior art]
As an arbitration method for memory access requests from a plurality of memory access request sources (hereinafter referred to as clients), there are (1) an arbitration method using a fixed priority and (2) an arbitration method using a round robin method.
[0003]
The arbitration method using the fixed priority method and the arbitration method using the round robin method both give priority to the memory access request from the client having a high priority when the memory access request conflicts. In the arbitration method, the priority is fixed, but in the round-robin arbitration method, when a client is selected by arbitration, the priority of the client is moved to the lowest level, and accordingly, when the client is arbitrated. The two clients are different in that the priority of other clients that are lower than the priority is raised.
[0004]
In the case of a system in which there are a large number of clients and it is necessary to guarantee the data transfer rate such as image input from the scanner, image output to the LSU (laser scan unit), etc. In the arbitration method using the fixed priority method or the round robin method, there is a high risk that the data transfer rate cannot be guaranteed for a specific client.
[0005]
In other words, in the arbitration method using the fixed priority method, even if the priority order for a plurality of clients whose data transfer rates are to be guaranteed is set higher, one of the clients whose data transfer rates are to be guaranteed is internally set to FIFO or the like. In the case of having a buffer, until the buffer is filled with data, the memory access of other clients that should guarantee the data transfer rate may be hindered.
[0006]
In addition, in the arbitration method using the round robin method, if the bandwidth of the memory (capacity of the transfer rate possessed by the memory) is not very large with respect to the sum of the data transfer rates requested by the client that should guarantee the data transfer rate, When the priority of a client that does not need to guarantee the data transfer rate is raised to a higher priority, memory bandwidth is consumed, and sufficient memory bandwidth cannot be secured for the client that should guarantee the data transfer rate. There is.
[0007]
[Problems to be solved by the invention]
An object of the present invention is to provide a memory access arbitration method capable of guaranteeing a data transfer rate for a specific client that needs to guarantee the data transfer rate.
[0008]
[Means for Solving the Problems]
The memory access arbitration method according to the present invention is generated by each client and provided in each client when a memory access request from a plurality of clients that need to guarantee the data transfer rate competes. A step of tentatively determining the next transaction to be processed based on the remaining amount of the buffer indicating the data accumulation status in the data buffer, and whether or not the tentatively determined transaction can be processed in the next predetermined period Transaction processing contents , Processing contents of the preceding transaction And the elapsed time from the start of the preceding transaction processing If it is determined that the transaction that is tentatively determined and the tentatively determined transaction can be processed in the next predetermined period, the tentatively determined transaction is started from the next predetermined period. In the case where it is determined that processing is not possible in the next predetermined period, there is provided a step of tentatively determining the next transaction to be processed based on the remaining buffer capacity generated by each client in the next predetermined period It is characterized by.
[0011]
When memory access by each client is performed by burst access, the tentative determination of the next transaction to be processed is based on the buffer remaining amount after the buffer remaining amount generated by each client is corrected by the intra-burst transfer amount. It is done.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0013]
[1] Explanation of configuration of peripheral circuit of memory control circuit of digital copying machine
[0014]
FIG. 1 shows the configuration of a memory control circuit and its peripheral circuits of a digital copying machine.
[0015]
An image input / output I / F 2, HDD I / F 3, SDRAM 4, CPU 5 and image compression / decompression circuit 6 are connected to the memory control circuit 1.
[0016]
[2] Description of the configuration of the memory control circuit of the digital copying machine
[0017]
FIG. 2 shows the configuration of the memory control circuit 1.
[0018]
The memory control circuit 1 includes a plurality of interfaces (I / F) 11 to 18, an image processing circuit (RBUF) 19, an internal CODEC circuit (MXX) 20, and a plurality of DMA controllers (DMAC) 21 to 33.
[0019]
In this embodiment, a memory for storing image data input to an image input I / F (IDIN0) 15 from a scanner (not shown) in the SDRAM 4 by the DMA controller (DMAC 10) 21 and the SDRAM I / F (SDRAM IF) 14. A memory access request for outputting the access request and image data stored in the SDRAM 4 to the image output I / F (VDOUT0) 17 by the DMA controller (DMAC 20) 23 and the SDRAM I / F (SDRAM IF) 14 As an example, the arbitration operation of the memory control circuit 1 will be described.
[0020]
[3] Description of the configuration of the data buffer built in the image input I / F (IDIN0) 15 and its peripheral circuits
[0021]
FIG. 3 shows a configuration of a data buffer built in the image input I / F (IDIN0) 15 and its peripheral circuits.
[0022]
The image input I / F (IDIN0) 15 includes a data buffer 40, a selector 56, a store control signal generation unit 57, a load control signal and selection control signal generation unit 58, and an encoder 59.
[0023]
The data buffer 40 takes in the input image data IDIN [31: 0] in synchronization with the operation clock WCK of the image input I / F (IDIN0) 15, and in synchronization with the system clock SCK, the image data idData [31: 0]. Is output. It is assumed that the SDRAM I / F (SDRAMIF) 14 also operates in synchronization with the system clock SCK. The data buffer 40 includes 15-stage word buffer flag generators 41 to 55, operates as a 15-stage × 32-bit FIFO, and stores the number of word buffer flag generators in which data is latched (accumulated in the data buffer 40). Data amount) is output as the remaining buffer capacity idFlag [3: 0].
[0024]
The data buffer 40 is synchronized with the operation clock WCK during a period in which the image data write control signal IDACK to the data buffer generated in the image input I / F (IDIN0) 15 is asserted (“H” level). Capture image data IDIN. Which of the word buffer flag generation units 41 to 55 stores the image data IDIN is controlled by a store control signal st [14: 0] generated by the store control signal generation unit 57.
[0025]
The store control signal generation unit 57 includes a first counter 57a and a first decoder 57b. The first counter 57a performs an up-count operation every time the image data write control signal IDACK is asserted. The count value of the first counter 57a is 14 at the maximum, and when it exceeds 14, it returns to 0.
[0026]
The first decoder 57b decodes the count value of the first counter 57a and generates 15 decoded signals. The store control signal generation unit 57 calculates a logical product of the image data write control signal IDACK and these telecode signals, and generates a store control signal st [14: 0].
[0027]
Each of the word buffer flag generation units 41 to 55 latches the input image data IDIN when the store control signals st0 to st14 input thereto are “H”. When the word buffer flag generation units 41 to 55 latch data, they assert the data storage flags of flag0 to offlag14. When the word buffer flag generation units 41 to 55 read the latched data, they negate the data storage flags of flag0 to offlag14.
[0028]
The encoder 59 encodes the number of asserted flags among the data storage flags offlag0 to offlag14, and generates a buffer remaining amount flag idFlag [3: 0].
[0029]
The data buffer 40 outputs image data in synchronization with the system clock SCK while the data transfer acknowledge signal sdAck10 sent from the SDRAM I / F (SDRAMIF) 14 is asserted (“H”). Which of the word buffer flag generation units 41 to 55 outputs the image data is controlled by the load control signal ld [14: 0] generated by the selection control signal generation unit 58 and the selection control signal Select. The
[0030]
The load control signal and selection control signal generator 58 includes a second counter 58a and a second decoder 58b. The second counter 58a performs an up-count operation every time the data transfer acknowledge signal sdAck10 is asserted. The count value of the second counter 58a is 14 at maximum, and when it exceeds 14, it returns to 0.
[0031]
The second decoder 58b decodes the count value of the second counter 58a and generates 15 decoded signals. The load control signal and selection control signal generation unit 58 calculates a logical product of the data transfer acknowledge signal sdAck10 and these telecode signals, and generates a load control signal ld.
[0032]
Each of the word buffer flag generation units 41 to 55 reads out image data and negates the data storage flags of flag0 to offlag14 when the load control signals ld0 to ld14 input thereto are “H”.
[0033]
The load control signal and selection control signal generator 58 outputs the count value of the second counter 58a to the selector 56 as the selection control signal Select. The selector 56 selects the image data Do0 to Do14 read from the word buffer flag generation units 41 to 55 corresponding to the selection control signal Select, and outputs it as the data buffer output signal idData [31: 0].
[0034]
[4] Description of the configuration of the data buffer built in the image output I / F (VDOUT0) 17 and its peripheral circuits
[0035]
FIG. 4 shows the configuration of the data buffer built in the image output I / F (VDOUT0) 17 and its peripheral circuits.
[0036]
The image output I / F (VDOUT0) 17 includes a data buffer 60, a selector 76, a store control signal generation unit 77, an encoder 78, and a load control signal and selection control signal generation unit 79.
[0037]
The data buffer 60 takes in the output data sdData [31: 0] of the SDRAM I / F (SDRAMIF) 14 in synchronization with the system clock SCK and synchronizes with the operation clock RCK of the image output I / F (VDOUT0) 17. , Output image data ODOUT [31: 0]. It is assumed that the SDRAM I / F (SDRAMIF) 14 also operates in synchronization with the system clock SCK. The data buffer 60 has built-in 15-stage word buffer flag generators 61 to 75, operates as a 15-stage × 32-bit FIFO, and the number of word buffer flag generators in which data is not latched (in the data buffer 60). Free capacity) is output as the remaining buffer capacity odFlag [3: 0].
[0038]
The data buffer 60 outputs the output data sdData of the SDRAMIF 14 in synchronization with the system clock SCK while the data transfer acknowledge signal sdAck20 sent from the SDRAM I / F (SDRAMIF) 14 is asserted (“H” level). take in. Which of the word buffer flag generation units 61 to 75 stores the input image data sdData is controlled by a store control signal st [14: 0] generated by the store control signal generation unit 77.
[0039]
The store control signal generation unit 77 includes a first counter 77a and a first decoder 77b. The first counter 77a performs an up-count operation every time the data transfer acknowledge signal sdAck20 is asserted. The count value of the first counter 77a is 14 at maximum, and when it exceeds 14, it returns to 0.
[0040]
The first decoder 77b decodes the count value of the first counter 77a and generates 15 decoded signals. The store control signal generation unit 77 calculates a logical product of the data transfer acknowledge signal sdAck20 and these decoded signals, and generates a store control signal st [14: 0].
[0041]
Each of the word buffer flag generation units 61 to 75 latches the output data sdData of the SDRAMIF 14 when the store control signals st0 to st14 input thereto are “H”. When the word buffer flag generation units 61 to 75 latch the data, they assert the data storage flags iflag0 to ifflag14. Then, when the word buffer flag generation units 61 to 75 read the latched data, they negate the data storage flags ifflag0 to ifflag14.
[0042]
The encoder 78 encodes the number of negated flags among the data storage flags ifflag0 to ifflag14 to generate a buffer remaining amount flag odFlag [3: 0].
[0043]
The data buffer 60 synchronizes with the operation clock RCK of the image output IF 17 while the image data read control signal ODACK to the data buffer generated in the image output IF 17 is asserted (“H”). Output. Which of the word buffer flag generation units 61 to 75 outputs the image data is determined by the load control signal ld [14: 0] generated by the load control signal and selection control signal generation unit 79 and the selection control signal. Controlled by Select.
[0044]
The load control signal and selection control signal generation unit 79 includes a second counter 79a and a second decoder 79b. The second counter 79a performs an up-count operation every time the image data read control signal ODACK is asserted. The count value of the second counter 79a is a maximum of 14, and when it exceeds 14, it returns to 0.
[0045]
The second decoder 79b decodes the count value of the second counter 79a and generates 15 decoded signals. The load control signal and selection control signal generation unit 79 calculates the logical product of the image data read control signal ODACK and these telecode signals to generate the load control signal ld.
[0046]
Each of the word buffer flag generation units 61 to 75 reads out image data and negates the data storage flags ifflag0 to ifflag14 when the load control signals ld0 to ld14 input thereto are "H".
[0047]
The load control signal and selection control signal generation unit 79 outputs the count value of the second counter 79a to the selector 76 as the selection control signal Select. The selector 76 selects the image data Do0 to Do14 read from the word buffer flag generation units 61 to 75 corresponding to the selection control signal Select, and outputs it as the data buffer output signal ODOUT [31: 0].
[0048]
[5] Explanation of configuration of SDRAM I / F (SDRAMIF) 14
[0049]
FIG. 5 shows the configuration of the SDRAM I / F (SDRAMIF) 14.
[0050]
The SDRAM I / F (SDRAMIF) 14 has an I / F with each of the DMA controllers 21 to 33 and each of the I / Fs 11 to 13 and 15 to 18 in FIG. 2. Only the I / F of the controller (DMAC 10) 21, the DMA controller (DMAC 20) 23, the image input I / F (IDIN0) 15, the image output I / F (VDOUT0) 17 and the CPU I / F (CPUIF) 13 is illustrated. ing.
[0051]
In FIG. 5, a DMAC 10 I / F 81 indicates an I / F with a DMA controller (DMAC 10) 21 and an image input I / F (IDIN 0) 15, and a DMAC 20 I / F 82 is a DMA controller (DMAC 20) 23 and an image output I / F (VDOUT0) 17 indicates the I / F, and CPUIF I / F 83 indicates the I / F with the CPU I / F (CPUIF) 13.
[0052]
The SDRAM I / F (SDRAMIF) 14 includes an arbitration circuit 84, a transaction file 85, a command generation circuit 86, a strobe generation circuit 87, and the like in addition to the I / Fs 81, 82, and 83.
[0053]
The DMAC 10 I / F 81 sends a value obtained by subtracting the buffer remaining amount correction value (internal signal FlagAdj 10) from the buffer remaining amount flag idFlag from the image input I / F (IDIN 0) 15 to the arbitration circuit 84 as Flag 10. Further, the DMAC10 I / F 81 masks the input data idData (logical product for each bit) based on the data transfer acknowledge signal sdAck10 sent from the strobe generation circuit 87 to generate Data10. Then, the logical write for each bit of the data 10 and the output data DataCpu of the CPUIF I / F 83 is taken to generate the SDRAM write data WriteData.
[0054]
The DMAC 20 I / F 82 sends a value obtained by subtracting the buffer remaining amount correction value (internal signal FlagAdj 20) from the buffer remaining amount flag odFlag from the image output I / F (VDOUT 0) 17 to the arbitration circuit 84 as Flag 20.
[0055]
The CPUIF I / F 83 corresponds to SDRAM access from the CPU 5. The arbitration circuit 84 arbitrates transaction processing requests from each client. The transaction file 85 holds transaction processing contents assigned SDRAM access by the arbitration circuit 84 and counts the number of cycles after arbitration.
[0056]
The command generation circuit 86 issues a command to the SDRAM 4 based on the contents of the transaction file 85 and the number of cycles after arbitration. Strobe generation circuit 87 generates data transfer acknowledge signals sdAck 10 and 20 and controls the data bus of SDRAM 4.
[0057]
The main input / output signals of each part will be described below.
[0058]
(1) Input / output signals of the DMAC10 I / F81, the DMAC20 I / F82, and the CPUIF I / F83.
Dm10Req, dm20Req, cpuSdramReq: Transaction processing request to SDRAM4.
IdFlag: a flag indicating the remaining buffer capacity of the image input I / F (IDIN0).
OdFlag: a flag indicating the remaining buffer capacity of the image output I / F (VDOUT0).
CpuDir: a signal that indicates the direction (read / write) of data transfer.
Dm10Address, dm20Address: DMA address.
[0059]
SdDispatch10, sdDispatch20: Signals indicating that transaction processing has been accepted by the SDRAM I / F (SDRAMIF) 14. The DMAC 10 I / F 81 and the DMAC 20 I / F 82 transfer these signals sdDispatch 10 and sdDispatch 20 generated by the arbitration circuit 84 to the client as they are.
[0060]
SdAck10, sdAck20: Data transfer acknowledge signals from the SDRAM I / F (SDRAMIF) 14. The DMAC 10 I / F 81 and the DMAC 20 I / F 82 transfer these signals sdAck 10 and sdAck 20 sent from the strobe signal generation circuit 87 to each client as they are.
[0061]
(2) Output signal of arbitration circuit 84
Register: A control signal for registering the transaction processing assigned by the arbitration circuit 84 in the transaction file 85.
Client: A code indicating a client (DMA controller (DMAC 10) 21, DMA controller (DMAC 20) 23,..., CPU IF (CPUIF) 13) that is provisionally determined by the arbitration circuit 84 to have the highest priority at the present time.
[0062]
Bank, Row, Col: Address obtained by decomposing the address sent from the top priority client into a bank number, a row address, and a column address.
TransType: a code (READ, WRITE) indicating the transaction processing content of the top priority client.
SdDispatch10, sdDispatch20, sdDispatchCpu: Signals indicating that the transaction processing request by the corresponding client has been accepted by the arbitration circuit 84.
[0063]
(3) Output signal of transaction file 85
[0064]
FileState: A signal indicating whether the contents of the transaction file 85 are valid (VALID) or invalid (INVALID).
CTtransType: a code (READ, WRITE) indicating the transaction processing content currently registered.
CC client: a code representing the request source of the currently registered transaction process.
[0065]
CBank, CRow, CCol: addresses obtained by decomposing the target addresses of transaction processing currently registered into bank numbers, row addresses, and column addresses.
CycleCount: a signal indicating a counter value of a counter that counts the number of cycles since the transaction processing is registered in the transaction file 85.
[0066]
(4) Output signal of command generation circuit 86
ReadTrigger: A trigger signal for designating read data timing to the strobe generation circuit 87.
WriteTrigger: a trigger signal that specifies the timing of write data for the strobe generation circuit 87.
• / CS, / RAS, / CAS, / WE, BA, MA: SDRAM control signal.
[0067]
(5) Output signal of strobe generation circuit 87.
SdAck10, 20: Data transfer acknowledge signal.
SdData: read data from the SDRAM 4
MD: SDRAMIF data bus.
[0068]
[6] Explanation of access arbitration method
[0069]
Examples of accessing the SDRAM 4 include the following.
(1) Transaction processing request from each DMA controller 21-33
(2) Transaction processing request from CPU I / F (CPUIF) 13 (CPU access)
[0070]
The SDRAM I / F (SDRAMIF) 14 arbitrates these access requests according to the priority order, and gives an access right to the one with the highest priority order. The priority order is fixed for each client. The priority order is determined in advance as follows.
[0071]
DMAC10, DMAC11, DMAC20, DMAC21> CPU access>DMAC7> DMAC30, DMAC6> DMAC40, DMAC5>DMAC31>DMAC41>DMAC8> DMAC9
[0072]
Items separated by commas have the same priority.
[0073]
When access requests with the same priority compete, the SDRAM I / F (SDRAMIF) 14 performs arbitration based on the remaining buffer flag of the client. However, for a client that does not have a buffer, the remaining buffer capacity is regarded as a specific value.
[0074]
When a transaction processing request is subsequently generated from the transaction processing request source client currently being processed, arbitration is performed based on the buffer remaining amount minus the burst length (4 in this example). Even when the SDRAM I / F (SDRAMIF) 14 receives an access request, if the remaining buffer capacity of the requesting client does not reach the burst length, the SDRAM I / F (SDRAMIF) 14 excludes the access request from the arbitration target.
[0075]
The SDRAM I / F (SDRAMIF) 14 provisionally determines a transaction candidate to be processed next every cycle in accordance with the above procedure. Further, it is checked whether or not the tentatively determined transaction can be processed in the next cycle, and if it can be processed, the processing of the tentatively determined transaction is actually started from the next cycle (command issuance to the SDRAM 4).
[0076]
Whether the tentatively determined transaction can be processed in the next cycle is determined based on the processing content of the preceding transaction, the processing content of the tentatively determined transaction, and the elapsed time from the start of the preceding transaction processing.
[0077]
[7] Explanation of specific example of access arbitration method
[0078]
Hereinafter, based on FIG. 6, an arbitration method in the case where access requests conflict between two clients, the DMA controller (DMAC 10) 21 and the DMA controller (DMAC 20) 23, will be described in detail.
[0079]
[7-1] Explanation of block internal signals
[0080]
First, the block internal signals shown in FIG. 6 will be described.
[0081]
FlagAdj20: Buffer remaining amount flag correction value for correcting the buffer remaining amount flag odFlag. The initial value of the correction value is 0, and the burst length (4 in this example) is added every time the signal sdDispatch20 indicating that the transaction processing request from the DMA controller (DMAC 20) 23 has been accepted is added, and the data transfer acknowledge signal While sdAck20 is asserted, 1 is subtracted. However, the minimum value of FlagAdj20 is 0.
[0082]
FlagAdj10: Buffer remaining amount flag correction value for correcting the buffer remaining amount flag idFlag. The initial value of the correction value is 0, and the burst length (“4” in this example) is added each time the signal sdDispatch10 indicating that a transaction processing request from the DMA controller (DMAC10) 21 has been accepted is added, and data transfer is performed. During the period when the acknowledge signal sdAck10 is asserted, 1 is subtracted. However, the minimum value of FlagAdj10 is 0.
[0083]
RCclient: A signal obtained by latching the code CCclient indicating the currently registered transaction processing request source on condition that the signal ReadTrigger indicating the read data timing is asserted.
ReadTrigger_ssss: A signal obtained by delaying ReadTrigger by delaying four clocks of the system clock SCK.
[0084]
ReadAck: A one-shot signal with a width of 4 clock cycles that operates using ReadTrigger_sss as a trigger.
WriteAck: A one-shot signal with a width of 4 clock cycles that operates with WriteTrigger as a trigger.
[0085]
RRCclient: A signal obtained by latching RCclient on condition that ReadTrigger_sss is asserted.
WClient: A signal obtained by latching CCClient on condition that WriteTrigger is asserted.
[0086]
[7-2] Description of preconditions of the specific example of FIG.
[0087]
The preconditions of the specific example of FIG. 6 are as follows.
[0088]
(1) It is assumed that only the DMA controller (DMAC 10) 21 and the DMA controller (DMAC 20) 23 are clients that access the SDRAM 4.
[0089]
(2) The operation clock (WCK) of the image input I / F (IDIN0) 15, the operation clock of the image output I / F (VDOUT0) 17 and the system clock (SCK) are all the same clock (same frequency). .
[0090]
(3) The image input I / F (IDIN0) 15 writes data to the data buffer 40 at a rate of once every 3 clocks (IDACK is asserted), and the image output I / F (VOUT0) 17 is 1 every 2 clocks. It is assumed that data is read from the data buffer 60 (ODACK asserted) at the rate of times.
[0091]
(4) The transfer start address set in the DMA controller (DMAC 10) 21 is Am, and the transfer start address set in the DMA controller (DMAC 20) 23 is An. In both Am and An, the lower 4 bits are set to “0” so as to start from the burst boundary and bank # 0.
[0092]
(5) The DMA address (dm10Address, dm20Address) indicates an address in units of words. Therefore, the DMA address is incremented by burst length (4) every time arbitration is performed once.
[0093]
[7-3] Explanation of timing chart of FIG.
[0094]
At time T1, the DMA controller (DMAC 10) 21 and the DMA controller (DMAC 20) 23 are activated (dm10Req, dm20Req asserted). At time T1, the image input I / F (IDIN0) 15 is activated, and at time T4, the image output I / F (VOUT0) 17 is activated.
[0095]
At the start time T1 of the image input I / F (IDIN0) 15, since the data buffer 40 is empty, the buffer remaining amount flag idFlag is “0”. Further, at the start time T4 of the image output I / F (VDOUT0) 17, the data buffer 60 is empty, so the buffer remaining amount flag odFlag is “15”.
[0096]
The buffer remaining amount correction value FlagAdj10 is 0 at the activation time T1 of the image input I / F (IDIN0) 15, and the buffer remaining amount correction value FlagAdj20 is 0 at the activation time T4 of the image output I / F (VDOUT0) 17. It is. Therefore, Flag10 (idFlag-FlagAdj10) output from the DMAC10 I / F81 becomes 0 at the start time T1 of the image input I / F (IDIN0) 15, and Flag20 (odFlag-FlagAdj20) output from the DMAC20 I / F 82 is At the start time T4 of the image output I / F (VDOUT0) 17, it becomes 15.
[0097]
The arbitration circuit 84 tentatively determines the highest-priority client by referring to the flags Flag10 and Flag20 indicating the remaining amount of the data buffer among the clients that are asserting the request signals (dm10Req, dm20Req).
[0098]
Immediately after activation of the image input I / F (IDIN0) 15 and the image output I / F (VDOUT0) 17, Flag10: Flag20 = 0: 15, so that the DMA controller (DMAC20) 23 is provisionally determined as the highest priority client. Is done. That is, at the time T4, the signal Client output from the arbitration circuit 84 is a signal representing the DMAC 20 (indicated as “20” in FIG. 6).
[0099]
At time T4, since the signal FileState output from the transaction file 85 is in the “INVALID” state, the arbitration circuit 84 determines that a command can be issued to the SDRAM 4, asserts Register, and the contents of the arbitrated transaction Is registered in the transaction file 85.
[0100]
When registering the transaction contents in the transaction file 85, the DMA address (in this case, dm20Address = An) is decomposed into a bank address (Bank), a row address (Row), and a column address (Col). The bank address (Bank) is obtained by performing bank interleaving using a DMA address (in this case, dm20Address).
[0101]
In the following description, dm10Address and dm20Address are collectively referred to as dm # Address. The row address (Row) is decomposed and generated from dm # Address by a function of FC (dm # Address) = {dm # Address [12: 6], dm # Address [3: 2]}. The column address (Col) is decomposed and generated from dm # Address by a function of FR (dm # Address) = dm # Address [24:13].
[0102]
At time T4, the arbitration circuit 84 asserts a signal sdDispatch20 indicating that the transaction processing request from the DMA controller (DMAC 20) 23 has been accepted. The signal sdDispatch 20 is generated by the logical product of the signal Register delayed by one clock and the signal obtained by decoding the contents of the signal CCclient. During the period in which sdDispatch20 is asserted, the arbitration circuit 84 prohibits arbitration.
[0103]
At time T5, the arbitration circuit 84 adds 4 to the buffer remaining amount correction value FlagAdj20 based on the assertion of sdDispatch20.
[0104]
When sdDispatch 20 is negated (time T6), the arbitration circuit 84 resumes arbitration. At time T6, Flag10: Flag20 = 1: 11, so that the DMA controller (DMAC 20) 23 is temporarily determined again as the highest priority client.
[0105]
At time T6, since the signal FileState output from the transaction file 85 is in the “VALID” state, the arbitration circuit 84 determines whether or not a command can be issued to the SDRAM 4 in relation to the contents of the preceding transaction. To do. Since the preceding transaction content is “Read”, it is determined whether or not a command can be issued to the SDRAM 4 based on the read operation preceding operation pattern of FIG.
[0106]
In this example, since the following transaction content is also “Read” and the bank is not competing, it corresponds to the pattern of (1) in FIG. 7, and in order to register the newly provisionally determined transaction content, the preceding transaction is registered. After that, it is necessary to wait for the burst length BL (4 clocks in this example).
[0107]
If the preceding transaction content is “Write”, it is determined whether or not a command can be issued to the SDRAM 4 based on the write operation preceding operation pattern of FIG.
[0108]
7 and 8, BL is the burst length (4 in this example), Tarb is arbitration-command issue latency (2 in this example), Trcd is / RAS or / CAS delay (2 in this example), CL indicates / CAS latency (2 in this example), Trec indicates the bus recovery time (1 in this example), Tdal indicates the data input during [WRITE]-[ACT] issuance interval (3 in this example). ing.
[0109]
Even if the highest priority client is provisionally determined at time T6, it is necessary to wait for the burst length BL (4 clocks in this example) after the preceding transaction is registered, as described above. After waiting until a certain time T8, the newly provisionally determined transaction content is registered in the transaction file 85.
[0110]
Thereafter, the same operation is repeated.
[0111]
The operation from time T14 to time T19 will be described.
[0112]
The arbitration circuit 84 resumes arbitration at time T14. However, at time T14, Flag10 and Flag20 are both 3, which is smaller than the burst length (4), so arbitration is not performed. At time T15, Flag10: Flag20 = 4: 3, so the DMA controller (DMAC 10) 21 is provisionally determined as the highest priority client.
[0113]
At time T15, since the signal FileState output from the transaction file 85 is in the “VALID” state, the arbitration circuit 84 determines whether or not a command can be issued to the SDRAM 4 in relation to the contents of the preceding transaction. . Since the preceding transaction content is “Read”, it is determined whether or not a command can be issued to the SDRAM 4 based on the read operation preceding operation pattern of FIG.
[0114]
In this example, since the follow-up transaction content is “Write” and the bank is not competing, it corresponds to the pattern of (2) in FIG. 7, and in order to register a new transaction, CL + BL + Trec ( In this example, it is necessary to wait for 7 clocks). The time point 7 clocks after the time point T12 is T19. Accordingly, the transaction content provisionally determined at time T15 is not registered at the next time T16.
[0115]
The tentative determination of the highest priority client is performed every cycle until it is registered in the transaction file.
[0116]
At time points T16 and T17, Flag10: Flag20 = 4: 3, so the DMA controller (DMAC10) 21 is provisionally determined as the highest priority client. For the same reason as described above, the provisionally determined transaction content is Not registered. At time T18, Flag10: Flag20 = 5: 4, so the DMA controller (DMAC 10) 21 is provisionally determined as the highest priority client. Then, at the next time point T19, the transaction contents provisionally determined at the time point T18 are registered.
[0117]
The operation from time T25 to time T29 will be described.
[0118]
At time T25, the arbitration circuit 84 resumes arbitration, but at time T25, Flag10 and Flag20 are both 3, which is smaller than the burst length (4), so no arbitration is performed. At time T26, since Flag10: Flag20 = 3: 4, the DMA controller (DMAC 20) 23 is provisionally determined as the highest priority client. In this case, it corresponds to the pattern of (1) in FIG. 8, and in order to register a new transaction, it is necessary to wait for BL (4 clocks in this example) after the preceding transaction is registered. No new transaction is registered at time T27.
[0119]
At time T27, Flag10: Flag20 = 4: 4, which are equal to each other, a predetermined client, in this example, the DMA controller (DMAC 10) 21 is provisionally determined as the highest priority client. In this case, it corresponds to the pattern of (2) in FIG. 8, and in order to register a new transaction, it is necessary to wait for BL (4 in this example) clock after the preceding transaction is registered. No new transaction is registered at T28.
[0120]
At time T28, Flag10: Flag20 = 4: 5, so the DMA controller (DMAC 20) 23 is provisionally determined as the highest priority client. In this case, it corresponds to the pattern of (1) in FIG. 7, and a new transaction is registered at the next time point T29.
[0121]
The remaining buffer flag idFlag is decreased by 1 with a latency of 1 due to sdAck10, and increased by 1 with a latency of 4 due to IDACK. However, when both signals are asserted simultaneously, the buffer remaining amount flag idFlag does not change. Similarly, the buffer remaining amount flag odFlag decreases by 1 with a latency of 1 due to sdAck20, and increases by 1 with a latency of 4 by ODACK. However, when both signals are asserted at the same time, the buffer remaining amount flag odFlag does not change.
[0122]
dm10Address increases by 4 each time sdDispath10 is asserted. Similarly, dm20Address increases by 4 each time sdDispath20 is asserted.
[0123]
ReadCycler is asserted when Cyclecount = 3 and CTransanceType = "READ". WriteTrigger is asserted when Cyclecount = 3 and CTransityType = "WRITE".
[0124]
The strobe generation circuit 87 asserts the data transfer acknowledge signal sdAck20 to the client held in the RRC client when ReadAck is asserted. The strobe generation circuit 87 asserts a data transfer acknowledge signal sdAck10 to the client held in WClient when WriteAck is asserted.
[0125]
The data buffer 40 of the image input I / F (IDIN0) 15 outputs data to the SDRAM I / F (SDRAMIF) 14 when sdAck10 is asserted. The data buffer 60 of the image output I / F (VDOUT) 17 takes in the output data sdData of the SDRAM I / F (SDRAMIF) 14 when sdAck20 is asserted.
[0126]
The command generation circuit 86 issues an [ACT] command and a CRow as a row address to the SDRAM 4 in the cycle following the cycle count = 1. Further, the command generation circuit 86 issues [READA] / [ERIRA] commands (these commands are switched by CTTransType) and CCol as a column address to the SDRAM 4 in the next cycle after Cycle count = 3.
[0127]
According to the above embodiment, when a memory access request from a client that needs to guarantee the data transfer rate competes, arbitration is performed based on the remaining buffer capacity of the data buffers 40 and 60. Data can be transferred without interruption even to clients that need to guarantee the rate.
[0128]
In addition, as in the above embodiment, by combining the arbitration method based on the fixed priority method and the arbitration based on the remaining buffer capacity, prioritization can be performed for each client group divided into clusters. Access rights can be distributed among a plurality of clients in a cluster according to the data transfer rate requested by each client.
[0129]
Also, when memory access by each client is performed by burst access, the access right is arbitrated based on the remaining buffer amount after the remaining buffer amount generated by each client is corrected by the intra-burst transfer amount. Therefore, it is possible to conceal the memory access latency found in a memory such as an SDRAM and perform data transfer continuously.
[0130]
Further, the next transaction to be processed is provisionally determined, and whether or not the provisionally determined transaction can be processed in the next cycle is determined based on the number of cycles after arbitration, the provisionally determined transaction processing content, and the processing content of the preceding transaction. This makes it possible to improve the efficiency of memory access.
[0131]
【The invention's effect】
According to the present invention, a memory access arbitration method that can guarantee a data transfer rate for a specific client that needs to guarantee the data transfer rate is realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the configuration of a memory control circuit 1 and its peripheral circuits in a digital copying machine.
2 is a block diagram showing a configuration of a memory control circuit 1. FIG.
FIG. 3 is a block diagram showing the configuration of a data buffer built in the image input I / F (IDIN0) 15 and its peripheral circuits.
FIG. 4 is a block diagram showing the configuration of a data buffer built in the image output I / F (VDOUT0) 17 and its peripheral circuits.
FIG. 5 is a block diagram showing a configuration of an SDRAM I / F (SDRAMIF) 14;
FIG. 6 is a time chart for explaining an arbitration method when access requests compete between two clients of the DMA controller (DMAC 10) 21 and the DMA controller (DMAC 20) 23;
FIG. 7 is a time chart showing a read operation preceding operation pattern.
FIG. 8 is a time chart showing a write operation preceding operation pattern.
[Explanation of symbols]
1 Memory control circuit
4 SDRAM
5 CPU
14 SDRAM I / F (SDRAMIF)
15 Image input I / F (IDIN0)
17 Image output I / F (VDOUT0)
21 DMA controller (DMAC10)
23 DMA controller (DMAC20)
40, 60 data buffer

Claims (2)

When memory access requests from multiple clients that need to guarantee the data transfer rate compete, the status of data storage in the data buffer generated by each client and provided in each client every predetermined period Tentatively determining the next transaction to be processed based on the remaining buffer capacity indicating
A step of checking whether or not the tentatively determined transaction can be processed in the next predetermined period based on the tentatively determined transaction processing content , the processing content of the preceding transaction , and the elapsed time from the start of the preceding transaction processing; If it is determined that the determined transaction can be processed in the next predetermined period, processing of the provisionally determined transaction is started from the next predetermined period, and the provisionally determined transaction cannot be processed in the next predetermined period. If it is determined that, in the next predetermined period, a step of tentatively determining the next transaction to be processed based on the remaining buffer capacity generated by each client;
A memory access arbitration method comprising: When memory access by each client is performed by burst access, the provisional determination of the next transaction to be processed is based on the remaining buffer amount after the remaining buffer amount generated by each client is corrected by the intra-burst transfer amount. The memory access arbitration method according to claim 1, wherein

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