JP2011034214A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve parallel processing of low-priority memory access without lowering efficiency of high-priority memory access. <P>SOLUTION: This memory controller divides a memory access request, decides priority of the memory access requests, and distribute them to a high-priority command buffer 105 holding the high-priority memory access request and a low-priority command buffer 106 holding the low-priority memory access request. The memory controller compares the high-priority memory access request and the low-priority memory access request, determines execution order of memory commands, and performs control to select and execute the high-priority memory access request and the low-priority memory access request according to the execution order of the memory commands. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a memory control device, and more particularly to a technique suitable for use in access control for a memory access request.

  In recent years, as a configuration of a system LSI, a unified memory configuration in which a plurality of bus masters share one memory device as a main memory is often used, and a DRAM is generally used as the main memory. In such a system, access control with respect to a memory access request from each bus master greatly affects the performance of the system.

  When video data stored in DRAM is output to a liquid crystal display (LCD), repeated data read / write processing and data read processing for displaying images at a frame rate determined by the liquid crystal display circuit are executed in parallel. Is done. Therefore, if the data read / write processing of the video data processing circuit is delayed due to the memory access interruption from the CPU, the decompressed data read by the liquid crystal display circuit is lost, and normal video cannot be output to the LCD. In order to prevent such a failure of the system, it is necessary to control the memory access bandwidth of the video data processing circuit that requires real-time processing to guarantee the completion of the data reading / writing processing within a certain period.

  Conventionally, as a method for guaranteeing a bandwidth for an access request, a bus arbiter method is generally used in which the execution order and execution frequency of memory access requests from a plurality of bus masters are adjusted by a bus connecting each bus master and the memory control circuit. ing. That is, when memory accesses from a plurality of bus masters compete, sequential access is permitted in a round robin manner, or access is permitted with a fixed priority. As a result, the memory access frequency for each bus master can be made variable according to the priority.

Japanese Patent Laid-Open No. 7-319756

  However, the technique shown in the prior art has a problem that the memory access efficiency of the bus master having a high priority is lowered when switching the memory access permission. In the bus arbiter method, it is possible to preferentially guarantee memory access to a bus master having a high priority for a certain period of time, but memory access is permitted to a bus master having a low priority at a certain ratio. At this time, the timing for switching the memory access permission follows the procedure built in the bus arbiter such as the round robin method or the fixed priority method, and the continuity with the immediately preceding memory access is not considered. For this reason, a memory access request of a bus master having a low priority interrupts a memory access request of a bus master having a high priority at a timing determined by the bus arbiter. As a result, there is a possibility that the memory access efficiency is lowered, and further, the high-priority memory access bandwidth is not guaranteed.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to realize parallel processing of low-priority memory access without reducing the efficiency of high-priority memory access.

  A memory control device according to the present invention is a memory control device that receives a memory access request from a bus master and issues a memory command to a memory device, and a dividing unit that divides the memory access request from the bus master into memory command units; The determination means for determining the priority of the memory access request divided by the dividing means, the first holding means for holding the memory access request with the high priority determined by the determination means, and the determination means A second holding unit that holds a low-priority memory access request, a high-priority memory access request that is held in the first holding unit, and a priority level that is held in the second holding unit. Determining means for comparing a low memory access request and determining an execution order of memory commands; and the memory command According to the order of execution, characterized by comprising an execution means for selecting and executing the higher priority memory access request and said low priority memory access requested.

  According to the present invention, in shared memory access from a plurality of bus masters, it is possible to execute parallel processing of low priority memory access without reducing the efficiency of high priority memory access.

It is a block diagram which shows the structural example of the memory control circuit which concerns on embodiment of this invention. It is a figure which shows an example of the memory command information produced | generated. It is a flowchart which shows an example of the production | generation procedure of memory command information. It is a figure which shows the behavior of DRAM bus. It is a figure which shows the state of a high priority command buffer. It is a figure which shows the state of a low priority command buffer. It is a figure which shows the calculation method of a memory bus unused period. It is a figure which shows the calculation method of a memory bus use period. It is a figure which shows the behavior of DRAM bus.

(First embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating a configuration example of the memory control device 100 according to the present embodiment.
In FIG. 1, when a memory access is requested from the bus master 101 to the shared DRAM 111 which is a memory device, the request is transferred to the memory control device 100 via the bus 102. The memory access request received by the memory control device 100 is divided by the command dividing circuit 103 into memory command information having execution information in units of memory commands. The memory command information is distributed to high priority memory command information and low priority memory command information by the priority distribution circuit 104 based on the identifier of the bus master 101 that is the issuer. Then, the data is held in the high priority command buffer 105 serving as the first holding unit or the low priority command buffer 106 serving as the second holding unit.

  Memory command information input to each command buffer is sequentially transferred to the memory command control circuit 109 from the top memory command information. As for the memory command information, only one of the memory command information of the high priority command buffer 105 or the low priority command buffer 106 is selected by the selection circuit 108 at a certain transferable timing. The memory command comparison circuit 107 determines whether or not a low priority memory command can be inserted between high priority memory commands without reducing the efficiency of the memory bus. When a low priority memory command can be inserted, an input switching signal is output to the selection circuit 108 and the low priority memory command is transferred to the memory command control circuit 109.

Next, the details of the command dividing circuit 103 of this embodiment will be described with reference to FIGS.
A memory access request from the bus master 101 is constituted by a data transfer start address, a data transfer length, and a data transfer direction (read / write). The command division circuit 103 generates a series of memory command information necessary for executing a memory access request based on these pieces of information.

FIG. 2 is a diagram illustrating an example of the generated memory command information.
As shown in FIG. 2, the memory command information includes a command type (CMD), a chip select signal (CS), a bank select signal (BS), and a row address signal (ROW). Further, a column address signal (COL), a burst enable signal (BEN), and a bus master identifier (ID) are included.

  The command type (CMD) includes a precharge command (PRE) necessary for page control of the DRAM 111. Further, there are an active command (ACT) and a read command (READ) and a write command (WRITE) for data read / write control from the DRAM 111. CS, BS, ROW, and COL are indexes that specify the chip, bank, and page of the DRAM 111 that is the target of issuing memory commands. Some of these indicators may not be cared for by some commands. For example, COL information is not used when issuing a PRE command. Also, ROW information is not used when issuing READ or WRITE commands.

  BEN is an index indicating the effective range of data transfer. The DRAM 111 has a fixed data length to be transferred by issuing a single READ / WRITE command. For this reason, when the memory access request is longer than the data length that can be transferred by one READ / WRITE command, it is necessary to issue a plurality of READ / WRITE commands. Conversely, if the memory access request is smaller than the data length transferred by a single READ / WRITE command, a valid data range is specified using a data mask signal. BEN is used for data mask signal control when a READ / WRITE command is executed. The bus identifier ID is referred to by the priority distribution circuit and used for the priority distribution of the divided memory access requests.

FIG. 3 is a flowchart illustrating an example of a procedure for generating memory command information in the command dividing circuit 103.
In FIG. 3, when receiving a memory transfer request from the bus master, the command dividing circuit 103 first decodes the transfer start address into information corresponding to CS, BS, ROW, and COL in the DRAM 111 in step S301.

  Next, in step S302, a page control command is generated. In this step S302, based on the CS, BS, ROW, and COL generated in step S301, it is determined whether a PRE or ACT command is required depending on the open / close status of the corresponding DRAM 111 page. To do. Then, a precharge command (PRE) for returning the page to the closed state once and an active command (ACT) for opening the page corresponding to the ROW are generated as memory command information.

  If the CS or BS to be accessed is not open, only memory command information for issuing an active command (ACT) for opening the page corresponding to the ROW is generated. On the other hand, when the page corresponding to the ROW is already open in the CS and BS to be accessed, no memory command information is generated because it is not necessary to issue a page control command.

  Next, in step S303, the number of READ (read) / WRITE (write) commands issued is determined according to the access request data length, and memory command information corresponding to the number of issued times is generated. Then, the process ends. For example, if the memory access request data length is 32 bytes and the data transfer length per READ / WRITE command issue of the DRAM 111 is 16 bytes, the number of issuances is 32/16 = 2 and two READ or WRITE command issuances are issued. Necessary. In this case, the BEN indicating the valid data transfer beat length is 4 for any READ / WRITE command. As another example, if the memory access request data length is 12 and the data transfer length per read / write command issued by the DRAM 111 is 16 bytes, 12/16 = 0.75, and one READ or WRITE command is issued. publish. Here, since the beat length of valid data transfer is only the first three beats, 3 is set in BEN.

  Next, the priority distribution circuit 104 will be described. The priority distribution circuit 104 distributes the memory command to the high priority command buffer 105 and the low priority command buffer 106 based on the priority information included in the divided memory command. When there are a plurality of bus masters as in the present embodiment, bus master identification information (identifier) can be used as priority information. By storing information on the bus master to be prioritized in the priority distribution circuit 104 in advance, it becomes possible to distribute memory requests from the bus master having a high priority to the high priority command buffer. In addition, when there is one bus master, unlike the present embodiment, it is possible to implement a priority distribution circuit by giving access priority identification information to a memory access request.

  Next, the relationship between each command buffer, the selection circuit 108, and the memory command control circuit 109 will be described. The high priority command buffer 105 and the low priority command buffer 106 hold the memory access request generated by the command dividing circuit 103 in units of memory command information. The memory command held in each of them obtains a control signal from the selection circuit 108 and is sequentially transferred to the memory command control circuit 109 from the memory command information at the head of the buffer. After the memory command information held at the head of the buffer is executed, the second and subsequent memory command information shifts by one stage toward the buffer head position. Memory command information at the head of each buffer is alternatively sent to the memory command control circuit 109 by the selection circuit 108.

  The memory command control circuit 109 converts the received memory command information into a memory command of the DRAM 111 and executes it. Further, the memory command control circuit 109 controls the issue interval of memory commands issued based on various timing constraints of the DRAM 111. For example, the memory command control circuit 109 performs timing control so that an interval from issuing an ACT command to issuing a READ / WRITE command for the same page of the CS and BS is issued after three cycles.

  FIG. 4 is a diagram showing the behavior of the DRAM bus 110 between the selection circuit 108 and the memory command control circuit 109 when the high priority command buffer 105 is in the state shown in FIG. In FIG. 5, the right end is the head position of the buffer. In the present embodiment, it is assumed that the memory command control circuit 109 can receive up to two memory command information from the selection circuit 108. The minimum cycle from the reception of the memory command information to the execution of the memory command to the DRAM bus 110 is defined as one cycle. The DRAM bus 110 is assumed to be a DDR type DRAM 111, and the operation mode is CasLatency of 2 cycles and BurstLength of 4 beats.

  In FIG. 4, signals (memory command information, memory command input Ready) indicate data transfer between the selection circuit 108 and the memory command control circuit 109. The memory command information is transferred from the selection circuit 108 to the memory command control circuit 109, and the memory command input Ready is transferred from the memory command control circuit 109 to the selection circuit 108. The selection circuit 108 extracts the top memory command information of the command buffer every cycle and transfers it to the memory command control circuit 109 while the memory command input Ready signal is asserted. The memory command control circuit 109 deasserts the memory command input Ready signal when the received memory command information becomes two or more.

  Three signals (Command, Address, and Data) in the lower part of FIG. 4 indicate data transfer on the DRAM bus 110. At time T2 in FIG. 4, the first READ command in the high priority command buffer 105 shown in FIG. 5 is executed. Subsequently, at time T3, the second PRE command (actually shifted to the beginning of the buffer at time T2) is executed. Further, when the ACT command is issued, a 2-cycle wait is inserted in the memory command control circuit 109 to satisfy the timing parameter tRP of the DRAM 111, and the ACT command is issued at time T6.

  Further, when a WRITE command located at the fourth position in the high priority command buffer 105 shown in FIG. 5 is issued, a one-cycle wait is inserted to satisfy the timing parameter tRCD of the DRAM 111. At time T8, the WRITE command is executed. Furthermore, when the last READ command is issued, a 4-cycle wait is inserted to satisfy the timing parameter tWTR of the DRAM 111, and the READ command is executed at time T13.

  Next, details of the memory command comparison circuit 107 of this embodiment will be described. The memory command comparison circuit 107 calculates a memory bus unused period when executing a high priority memory command, and determines whether or not a low priority memory command can be issued during the calculated period. When possible, the control signal output to the selection circuit 108 is switched. FIG. 7 is a diagram illustrating a method of calculating a memory bus unused period when executing a high priority memory command. The unused period of the memory bus is calculated for each of the command bus and the data bus between two consecutive high priority memory commands.

  FIG. 8 is a diagram illustrating a method of calculating a memory bus usage period when a low priority memory command is executed. Each time the high priority command buffer 105 is updated, the memory command comparison circuit 107 calculates a memory bus unused period between the first memory command in the command buffer and the second memory command following the command command. Then, the command bus use period and the data bus use period of the memory command held at the head of the low priority command buffer 106 are compared. If the unused period of the memory bus when executing the high priority memory command is equal to or greater than the usage period of the low priority memory command execution, the low priority memory command is changed to the head of the high priority memory command. It is determined that it can be issued following the memory command. Then, an input switching signal to the selection circuit 108 is asserted.

  FIG. 9 shows the behavior of the order of commands on the DRAM bus 110 when the high priority command buffer 105 is in the state shown in FIG. 5 and the low priority command buffer 106 is in the state shown in FIG. FIG. Here, timing constraints are tRP = 3 cycles, tRCD = 2 cycles, CasLatency = 2 cycles, BurstLength = 4 beats, and tWTR = 3 cycles.

  First, when the READ command of the high priority command buffer 105 comes to the top, the memory command comparison circuit 107 starts with two memory commands from the top of the high priority command buffer 105 and the top memory command of the low priority command buffer 106. Compare Then, it is determined whether or not a low priority memory command can be executed. In the example shown in FIG. 7, the two memory commands from the top of the high priority command buffer 105 are RD-PRE (diff. Bank), and the unused period of the command bus and data bus is zero. Further, in the example shown in FIG. 8, since the memory command information at the head of the low priority command buffer 106 is READ, a command bus usage period of one cycle or more is required for execution, and therefore it is impossible to issue a command. To be judged.

  Next, PRE-ACT of the high priority command buffer 105 and READ of the low priority command buffer 106 are compared. The untrial period of the command bus when executing a high-priority PRE-ACT command is (tRP-1) = (3-1) = 2 cycles, and a command can be issued. Further, the data bus untrial period is (tRP + tRCD-1) = (3 + 2-1) = 4 cycles, and the data bus use period necessary for executing the low-priority READ is (CL + BL / 2-1) = (2 + 4 + 4 / 2-1) = 3 cycles, which satisfies the condition. Therefore, it is determined that a low priority READ can be issued following a high priority PRE command. In this case, the memory command comparison circuit 107 inputs to the selection circuit 108 so that the READ command of the low priority command buffer 106 is transferred to the memory command control circuit 109 following the PRE command of the high priority command buffer 105. Outputs a switching signal.

  Next, the ACT-WRITE in the high priority command buffer 105 and the low priority ACT are compared. The command bus unused period when executing high-priority ACT-WRITE is (tRCD-1) = 1 cycle, which satisfies one cycle of command bus use necessary for issuing a low-priority ACT command. Therefore, also in this case, the low priority ACT is transferred to the memory command control circuit 109 following the high priority ACT command. Furthermore, WRITE-READ in the high priority command buffer 105 is compared with WRITE with low priority. When the high-priority WRITE-READ is executed, the unused period of the command bus is 4 cycles, and the unused period of the data bus is also 4 cycles. On the other hand, when the low-priority WRITE is executed, the command bus usage period is 1 cycle, and the data bus usage period is 2 cycles, which satisfies the condition. Therefore, the low priority WRITE is transferred to the memory command control circuit 109 following the high priority WRITE.

  As described above, the memory command control circuit 109 is read in the order of READ, PRE, READ (low priority), ACT, ACT (low priority), WRITE, WRITE (low priority), and READ, as shown in FIG. Memory command is transferred. As a result, as shown in FIGS. 4 and 9, the low priority memory command is executed at a timing that does not hinder the execution of the high priority memory command. Further, the input switching ready signal in FIG. 9 is synchronized with the memory command input ready signal input from the memory command control circuit 109 to the selection circuit 108. When the input switching ready signal is deasserted, the memory command comparison circuit 107 keeps asserting and holding the input switching signal at the same value.

(Other embodiments)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

DESCRIPTION OF SYMBOLS 101 Bus master, 103 Command division circuit, 104 Priority distribution circuit, 105 High priority command buffer, 106 Low priority command buffer, 107 Memory command comparison circuit, 108 Selection circuit, 109 Memory command control circuit, 110 DRAM bus, 111 DRAM

Claims (5)

A memory control device that issues a memory command to a memory device in response to a memory access request from a bus master,
Dividing means for dividing a memory access request from the bus master into memory command units;
Determining means for determining the priority of the memory access request divided by the dividing means;
First holding means for holding a memory access request having a high priority determined by the determining means;
Second holding means for holding a low-priority memory access request determined by the determining means;
The memory access request having a high priority held in the first holding unit and the memory access request having a low priority held in the second holding unit are compared to determine the execution order of the memory commands. A determination means;
A memory control apparatus comprising: an execution unit that selects and executes the memory access request having a high priority and the memory access request having a low priority according to an execution order of the memory commands.   The memory control device according to claim 1, wherein the memory device is a DRAM.   The dividing unit divides the memory access request for each access of the memory device, and generates a read or write command as many times as necessary to finish the memory access of the data transfer of the memory device. The memory control device according to claim 1.   The determining means includes a calculating means for calculating an unused period of the memory bus due to timing constraints of the memory device when executing a memory command of the memory access request having a high priority, and the memory command having the low priority is the And a means for determining which memory command is to be issued according to a result of determination by the determination means. 2. The memory control device according to 1.   2. The memory control according to claim 1, wherein the determination unit determines the priority of the memory access request based on bus master identification information or access priority identification information included in the memory access request from the bus master. apparatus.

Images