JP3568213B2 - Digital signal processor - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a digital signal processing device, and more particularly, to a dequantization circuit that decodes quantized data by dequantizing the data.
[0002]
[Prior art]
In recent years, it has been required to reduce the capacity of a recording medium and reduce the size of a transmission path by compressing a digital signal.
[0003]
For this purpose, a method has been proposed in which sampled data is grouped by an appropriate number into individual units, and quantization is performed for each unit.
In this method, quantization is performed by assigning the number of quantization bits (hereinafter, referred to as a word length code) and the magnitude of a normalized value (hereinafter, referred to as a scale factor value) to each unit, and performing quantization. For data (hereinafter referred to as sample data). That is, in general quantization, quantization is performed with a fixed word length. However, in this method, usually, quantization is performed with a variable word length smaller than the fixed word length, so that the entire data amount can be compressed. Further, in this method, since a word length code and a scale factor value are assigned to each unit, an increase in the data is smaller than a decrease in the total data amount due to quantization with a variable word length.
[0004]
Then, in the inverse quantization in this method, data B obtained by inversely quantizing the sample data A is obtained from the sample data A and the word length code WL and the scale factor value SF of the unit corresponding to the sample data A, for example, by the formula (1) Is calculated by the following calculation. That is, by performing the operation shown in the expression (1) in the inverse quantization circuit, the compressed data can be expanded and decoded.
[0005]
B = A · SF · F (WL) (1)
(However, F (WL) is a function of the word length code WL)
Also, in this method, an appropriate number of units are grouped together to form one group, and writing and reading (or transmission / reception to / from a transmission path) to / from a recording medium are performed by serially transferring the group. Has become.
[0006]
FIG. 3 shows an array of serial data of one group. In FIG. 3, the transfer direction of the serial data is rightward. That is, the serial data read from the recording medium (or sent from the transmission path) is input to the inverse quantization circuit sequentially rightward from the first bit with the leftmost bit shown in FIG. It shall be.
[0007]
One group of serial data is arranged, for example, from the top in the order of a word length code, a scale factor code, and sample data. Here, one group is composed of n units, each word length code corresponding to each unit is composed of m bits, and each scale factor code corresponding to each unit is composed of e bits. The scale factor code is converted by the decoder provided in the inverse quantization circuit to become the scale factor value.
[0008]
FIG. 4 shows an example of the correspondence between each unit and each sample of the sample data.
In this example, from the first sample of the sample data to the a-th sample (1 to a) corresponds to unit 1, and from the a + 1-th sample to the b-th sample (a + 1 to b) of the sample data, the unit 1 2 is supported. The units (c to N) from the c-th sample to the last (N-th) sample of the sample data correspond to the unit n.
[0009]
Here, the number of bits of each sample of the sample data is defined by the word length code of the corresponding unit (1 to n). That is, the number of bits of each word length code and each scale factor code are defined uniformly (m bits, e bits), but the number of bits of each sample of sample data is not uniform. Therefore, the data length (k bytes) of the entire group is not uniform.
[0010]
Quantization and inverse quantization by such methods can be used for compression processing of data such as sound and images.
For example, when using for audio signal processing, first, digital audio data obtained by A / D conversion of an audio signal on a time axis is cut out with an appropriate time window. Each digital audio data clipped in the time window corresponds to the one group of data. Then, the cut-out digital audio data is transformed on the frequency axis by an appropriate orthogonal transform (such as a discrete Fourier transform (DFT), a discrete cosine transform (DCT), or an improved discrete cosine transform (MDCT)). The signal is decomposed into a plurality of signal components having an appropriate frequency width.
[0011]
The plurality of signal components are determined based on the critical bandwidth (called the critical band, the higher the bandwidth, the wider the bandwidth) based on the human perception of noise and the frequency analysis capability (frequency resolution). Put together in a determined band.
[0012]
Then, each signal component is quantized using the word length code and the scale factor value, and written (or transmitted) to a recording medium (optical disk, magneto-optical disk, magnetic tape, etc.) as a serial data string as shown in FIG. Relocation to the road). In the inverse quantization, as described above, data obtained by inversely quantizing the sample data (that is, the signal components) is obtained from the sample data, the word length code corresponding to the sample data, and the scale factor value. It is.
[0013]
[Problems to be solved by the invention]
By the way, in the above-mentioned method, in the inverse quantization, when there is an error in any one bit of one group, it is determined whether the erroneous bit is in the word length code, the scale factor code, or the sample data. Error processing was performed on the entire group.
[0014]
However, since error processing is performed on one entire group, there is a problem that the utilization rate of valid data (error-free data) is reduced. That is, in order to uniformly perform error processing on valid data having bits other than the erroneous bit (in other words, to "discard" the valid data together with the erroneous data). , Valid data could not be fully utilized.
[0015]
Furthermore, error processing cannot completely restore data, and after all, it only makes the erroneous data inconspicuous when viewing the entire inverse quantization. Therefore, when the utilization rate of the effective data is low, there is a problem that the accuracy of the inverse quantization is reduced.
[0016]
In the above method, as a pre-process of inverse quantization, an error flag is set for each set obtained by dividing one group by an appropriate number of bits. This error flag is for detecting whether any bit of the corresponding set has an error. Then, the data string of the error flag is serially transferred together with the data string of one group, and is input to the inverse quantization circuit.
[0017]
A buffer RAM is provided in the inverse quantization circuit, and the serially transferred data of one group and the data of the error flag are temporarily stored in the buffer RAM. Then, error flag data is read from the buffer RAM as needed, and error processing is performed based on the read error flag. Therefore, when the number of accesses to the buffer RAM increases, the processing speed of the inverse quantization decreases.
[0018]
Therefore, it has been considered that an error flag processing register is provided separately from the buffer RAM, and all data of one group of error flags stored in the buffer RAM is transferred to the error flag processing register at a time. In this case, error flag data is read from the error flag processing register as necessary, and error processing is performed based on the read error flag.
[0019]
In this case, since the access speed of the error flag processing register is much higher than that of the buffer RAM, the processing speed of the inverse quantization does not decrease. However, when the data amount of the error flag is large (that is, when the number of bits in one group or one set is large), the circuit scale of the error flag processing register and a circuit for extracting a desired error flag from the error flag processing register And the width of the data bus connecting the buffer RAM and the error flag processing register increases. Therefore, there is a problem that the circuit scale of the entire inverse quantization circuit is increased and high integration is hindered.
[0020]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the first invention is to improve the efficiency of inverse quantization by increasing the utilization rate of effective data in error processing. A signal processing device is provided. It is another object of the present invention to provide a digital signal processing apparatus capable of increasing the processing speed without increasing the circuit scale when performing error processing in the inverse quantization processing.
[0021]
[Means for Solving the Problems]
In the first invention, the sampled data is grouped by an appropriate number into each unit, the data is quantized in each unit, and then the units are grouped by an appropriate number into each group. In a digital signal processing apparatus that performs inverse quantization on a unit basis for each group, if an error occurs in any bit in one group, error processing is performed only on quantized data affected by the error. That is the gist.
[0022]
According to a second aspect of the present invention, the sampled data is grouped by an appropriate number into each unit, and the data is quantized in each unit. Digital signal processing that sets an error flag to detect whether any bit in the set contains an error for each set obtained by appropriately dividing data of two groups, and performs inverse quantization on a unit basis for each group. A buffer RAM for storing error flag data corresponding to one group, and an error flag process for reading and storing a predetermined number of data at a time from the error flag data stored in the buffer RAM. The gist is that a register is provided.
[0023]
[Action]
Therefore, according to the first aspect, quantized data that is not affected by an error is used for inverse quantization as it is, so that the utilization rate of effective data can be increased and the accuracy of inverse quantization can be increased.
[0024]
Further, according to the second aspect, an error flag corresponding to the data width of the error flag processing register can be fetched by a single access to the buffer RAM, so that the number of accesses to the buffer RAM is reduced and the processing speed is improved. Can be done.
[0025]
【Example】
An embodiment of the present invention will be described below with reference to FIGS.
In the digital signal processed in this embodiment, detailed description of the same configuration as the conventional example shown in FIGS. 3 and 4 will be omitted.
[0026]
One group of quantized serial data as shown in FIG. 3 is read from a recording medium (or sent from a transmission path) and input to a pre-processing circuit (not shown) for inverse quantization.
[0027]
Note that a data string of basic data required for inverse quantization is added before the data string of one group. The basic data is data indicating the number of units of the word length code and the scale factor code when the number of units of the word length code and the scale factor code is smaller than the number of units of the sample data.
[0028]
For example, the number of units of the word length code and the scale factor code is set to p, and the number of units of the sample data is set to r more than p (p <r). Then, for the units 1 to p of the sample data, inverse quantization is performed based on the corresponding units 1 to p of the word length code and the scale factor code, and for the units p + 1 to r of the sample data, the word length code and the scale factor code Inverse quantization is performed on the basis of the unit p.
[0029]
That is, the unit of the sample data is grouped by an appropriate number into a large unit, and a word length code and a scale factor code are assigned to the large unit and inverse quantization is performed (in other words, the unit of the sample data is "Coarse" inverse quantization is performed for p + 1 to r). Therefore, since the data length of the entire group is shorter than that of the method described in the conventional example, the compression can be improved.
[0030]
For example, when used for processing an audio signal, the importance of a high-frequency signal is lower than that of a low / mid-frequency signal, so that a "coarse" inverse quantization ( And quantization), the data can be compressed without impairing the hearing.
[0031]
In the pre-processing circuit for inverse quantization, an error flag is set for each set obtained by dividing the basic data and the subsequent data of one group by an appropriate number of bits. This error flag is for detecting whether any bit of the corresponding set has an error. Then, the data sequence of the error flag is serially transferred following the basic data and the data sequence of one group subsequent thereto, and is input to the inverse quantization circuit 11.
[0032]
For example, if the data length of the basic data and the data length of one group are s bits and the number of bits in one set is t bits, an error flag is set every t bits from the first bit of the data of one group. , The total number of error flags is s / t. Since one data of the error flag is represented by one bit, the data length of the error flag is s / t bits.
[0033]
FIG. 1 shows a block circuit diagram of the inverse quantization circuit 11 of the present embodiment.
A buffer RAM 12 is provided in the inverse quantization circuit 11, and the serially transferred basic data, one group of data, and error flag data (see FIG. 2) are temporarily stored in the buffer RAM 12.
[0034]
The error flag data is sequentially read from the buffer RAM 12 by a predetermined number of data, and the read error flag data is transferred to and stored in the error flag processing register 13.
[0035]
Here, the data width of the error flag processing register 13 is equal to the number of data of the error flag read from the buffer RAM 12 at one time. For example, if the error flag data read out from the buffer RAM 12 at one time is 8 bits, the data width of the error flag processing register 13 is also 8 bits. In the present embodiment, the data width of the error flag processing register 13 is equal to the number of data of the error flag read from the buffer RAM 12 at one time, but it is not always necessary to make them equal.
[0036]
The error detection circuit 14 sequentially reads the error flag data stored in the error flag processing register 13 and detects whether the error flag data indicates an error of any bit of the corresponding set. I do.
[0037]
If the error detection circuit 14 detects that the data of the error flag indicates an error, the error type determination circuit 15 sets the basic data, the word length code, the scale factor code and the set corresponding to the error flag data. It is determined where the sample data is included.
[0038]
On the other hand, the basic data and one group of data stored in the buffer RAM 12 are transferred to the inverse quantization operation circuit 15.
Based on the basic data, the inverse quantization operation circuit 15 converts the data B obtained by inversely quantizing the sample data A from the sample data A and the word length code WL and the scale factor value SF corresponding to the sample data A according to the above equation ( It is determined by the calculation shown in 1). That is, by performing the operation shown in Expression (1) in the inverse quantization operation circuit 15, the compressed data can be expanded and decoded. Then, the inversely quantized data is transferred to the complementary processing circuit 17.
[0039]
The basic data error processing circuit 18, the word length code error processing circuit 19, the unit factor code error processing circuit 20, and the sample data error processing circuit 21 perform error processing on the complement processing circuit 17 based on the determination result of the error type determination circuit 15. Instructions.
[0040]
When the error type determination circuit 15 determines that the set corresponding to the error flag data indicating the error is included in the basic data, the basic data error processing circuit 18 performs error processing on the entire group. To the complementary processing circuit 17.
[0041]
When the error type determination circuit 15 determines that the set corresponding to the data of the error flag indicating the error is included in the word length code, the word length code error processing circuit 19 outputs the word length code unit having the error. Thereafter, it instructs the complementary processing circuit 17 to perform error processing on all corresponding sample data. For example, if any bit in the word length code unit 2 has an error, error processing is performed on all sample data (samples a + 1 to N) corresponding to the word length code units 2 to n ( (See FIG. 4).
[0042]
When the error type determination circuit 15 determines that the set corresponding to the data of the error flag indicating the error is included in the scale factor code, the scale factor code error processing circuit 20 sets the unit of the erroneous scale factor code. Is instructed to perform the error processing only on the sample data corresponding to. For example, if any bit in the scale factor code unit 2 has an error, error processing is performed only on the sample data (samples a + 1 to b) corresponding to the scale factor code unit 2 (FIG. 4). reference).
[0043]
If the error type determination circuit 15 determines that the set corresponding to the data of the error flag indicating the error is included in the sample data, the sample data error processing circuit 20 performs processing on one sample of the erroneous sample data. Only the error processing is instructed to the complementary processing circuit 17. For example, if there is an error in any bit of the sample c of the sample data, error processing is performed only on the sample c (see FIG. 4).
[0044]
The complementary processing circuit 17 performs error processing on the dequantized data according to the instructions of the error processing circuits 18 to 21, and outputs the error-processed data as output data of the inverse quantization circuit 11.
[0045]
Here, the error processing includes interpolation, pre-value holding, zero-level conversion, and the like. Here, an appropriate processing may be selected in consideration of the entire data processing of a plurality of groups. Note that the interpolation is a process of replacing erroneous data with an intermediate value of data before and after the error or a process of replacing an erroneous data with an intermediate value of equivalent data of the preceding and following groups. Retaining the previous value is a process of replacing erroneous data with the value of the previous data or a process of replacing the erroneous data with an equivalent data value in the previous group. Zeroing is a process of replacing all bits of erroneous data with “0”.
[0046]
As described above, in the present embodiment, the error flag processing register 13 is provided separately from the buffer RAM 12, and only a part of the error flag data is read from the buffer RAM 12 at a time. Here, the number of data of the error flag read at one time from the buffer RAM 12 (that is, the data width of the error flag processing register 13) depends on the improvement of the processing speed of the inverse quantization circuit 11 and the improvement of the inverse quantization circuit 11. It is determined at the time of circuit design from a trade-off relationship with an increase in the circuit scale (that is, the circuit scale of the error flag processing register 13 and the width of the data bus connecting the buffer RAM 12 and the error flag processing register 13).
[0047]
That is, if the number of data of the error flag read from the buffer RAM 12 at one time is increased, the number of accesses to the buffer RAM 12 is reduced and the processing speed is improved, but the improvement is saturated to some extent. On the other hand, when the circuit size of the error flag processing register 13 is increased, the width of the data bus connecting the buffer RAM 12 and the error flag processing register 13 is also increased, and the circuit size of the inverse quantization circuit 11 is increased. Therefore, the number of data of the error flag read at once from the buffer RAM 12 is set to an optimum value according to a trade-off relationship between the two.
[0048]
As a result, in this embodiment, the processing speed can be increased without increasing the circuit size of the inverse quantization circuit 11.
In this embodiment, when the error flag data indicates an error, the set corresponding to the error flag data is the basic data and one group (word length code, scale factor code, sample data). Is determined, and error processing is performed based on the result of the determination.
[0049]
Looking at the degree of error, it can be said that the error of the sample data is smaller than that of the scale factor code. In addition, it can be said that the error of the scale factor code is smaller than the error of the word length code. Furthermore, it can be said that the error degree of the word length code is smaller than that of the basic data.
[0050]
In this embodiment, the sample data sample not affected by the error is used as it is, and the error processing is performed only on the sample data sample affected by the error. That is, in the present embodiment, the unit of sample data for which error processing is performed is changed according to the degree of error, thereby increasing the utilization rate of valid data.
[0051]
As a result, in this embodiment, the accuracy of the inverse quantization can be increased.
Note that the present invention is not limited to the above embodiment. For example, error processing may be performed on only one group of data without basic data.
[0052]
Further, the error flag processing register 13 is provided and implemented only. The error type determination circuit 15 and each of the error processing circuits 18 to 21 are omitted, and the error processing is performed on the entire group as in the conventional example. It may be performed.
[0053]
Further, the error type determination circuit 15 and the error processing circuits 18 to 21 may be provided and implemented, and the error flag processing register 13 may be omitted. In addition, the number of units in one group may be changed for each group, and the number of bits in each set may be changed for each set.
[0054]
【The invention's effect】
As described in detail above, according to the first invention, there is an excellent effect that the accuracy of inverse quantization can be increased by increasing the utilization rate of valid data in error processing. Further, according to the second aspect, when performing error processing in the inverse quantization processing, there is an excellent effect that the processing speed can be increased without increasing the circuit scale.
[Brief description of the drawings]
FIG. 1 is a block circuit diagram of an embodiment embodying the present invention.
FIG. 2 is an explanatory diagram for explaining an array of basic data, one group of data, and error flag data serially transferred to a buffer RAM 12;
FIG. 3 is an explanatory diagram for explaining an array of serial data of one group.
FIG. 4 is an explanatory diagram for explaining a correspondence relationship between each unit and sample data.
[Explanation of symbols]
12 Buffer RAM
13 Error Flag Processing Register 14 Error Detection Circuit 15 Error Type Determination Circuit 16 Inverse Quantization Operation Circuit 17 Complementary Processing Circuit 18 Basic Data Error Processing Circuit 19 Word Length Code Error Processing Circuit 20 Scale Factor Code Error Processing Circuit 21 Sample Data Error Processing circuit

Claims (7)

The sampled data is grouped by the appropriate number into each unit, and a word length code, which is the number of quantization bits, and a scale factor value, which is the size of the normalized value, are assigned to each unit. Quantization is performed, and an appropriate number of units are grouped together into groups,
For each set obtained by appropriately dividing a group of data consisting of sample data that is quantized data, a scale factor code obtained by code-converting the scale factor value, and the word length code, one of the sets Set an error flag to detect if the bit is incorrect,
In a digital signal processing device that performs inverse quantization on a unit basis for each group,
An error detection circuit for detecting whether the error flag indicates an error in any bit of the corresponding set,
When the error detection circuit detects that the error flag indicates an error, it determines where the set corresponding to the error flag is included in the word length code, the scale factor code, and the sample data. An error type determination circuit;
A dequantization operation circuit for calculating data obtained by dequantizing the sample data from the sample data and a word length code and a scale factor value corresponding to the sample data,
A data complement processing circuit that performs error processing on the inversely quantized data obtained by the inverse quantization operation circuit and outputs the result;
Based on the determination of where the set corresponding to the error flag indicating the error is included in the error type determination circuit, the data itself in which the error occurred and the data different from this data, and the influence of the error An error processing circuit for instructing a complementary processing circuit to perform error processing only on the quantized data received. The error processing circuit, when the error type determination circuit determines that the set corresponding to the error flag indicating the error is included in the word length code, all of the units corresponding to the unit of the word length code after the error 2. The digital signal processing apparatus according to claim 1, wherein an instruction is given to a complementary processing circuit to perform error processing on the sample data. The error processing circuit, When the error type determination circuit determines that the set corresponding to the error flag indicating the error is included in the scale factor code, the error processing is performed only on the sample data corresponding to the unit of the erroneous scale factor code. 2. The digital signal processing apparatus according to claim 1, wherein a command is sent to a complementary processing circuit. The error processing circuit, When the error type determination circuit determines that the set corresponding to the error flag indicating the error is included in the sample data, the complement processing circuit performs error processing on only one sample of the erroneous sample data. 2. The digital signal processing device according to claim 1, wherein the instruction is issued. 5. The error processing according to claim 1, wherein the error processing is processing of replacing erroneous data with an intermediate value of data before and after the error, or replacing error data with an intermediate value of equivalent data of the preceding and following groups. 6. The digital signal processing device according to any one of the above . The error processing is any one of claims 1 to 4, characterized in that the process replaces the erroneous data on the value of the previous data, or a process of replacing the value of the equivalent data in the previous group 2. The digital signal processing device according to claim 1. The digital signal processing device according to claim 1 , wherein the error processing is processing of replacing all bits of erroneous data with “0”.

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